1f38b0dd6STero Kristo /* 2f38b0dd6STero Kristo * OMAP DPLL clock support 3f38b0dd6STero Kristo * 4f38b0dd6STero Kristo * Copyright (C) 2013 Texas Instruments, Inc. 5f38b0dd6STero Kristo * 6f38b0dd6STero Kristo * Tero Kristo <t-kristo@ti.com> 7f38b0dd6STero Kristo * 8f38b0dd6STero Kristo * This program is free software; you can redistribute it and/or modify 9f38b0dd6STero Kristo * it under the terms of the GNU General Public License version 2 as 10f38b0dd6STero Kristo * published by the Free Software Foundation. 11f38b0dd6STero Kristo * 12f38b0dd6STero Kristo * This program is distributed "as is" WITHOUT ANY WARRANTY of any 13f38b0dd6STero Kristo * kind, whether express or implied; without even the implied warranty 14f38b0dd6STero Kristo * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15f38b0dd6STero Kristo * GNU General Public License for more details. 16f38b0dd6STero Kristo */ 17f38b0dd6STero Kristo 181b29e601SStephen Boyd #include <linux/clk.h> 19f38b0dd6STero Kristo #include <linux/clk-provider.h> 20f38b0dd6STero Kristo #include <linux/slab.h> 21f38b0dd6STero Kristo #include <linux/err.h> 22f38b0dd6STero Kristo #include <linux/of.h> 23f38b0dd6STero Kristo #include <linux/of_address.h> 24f38b0dd6STero Kristo #include <linux/clk/ti.h> 25ed405a23STero Kristo #include "clock.h" 26f38b0dd6STero Kristo 27f38b0dd6STero Kristo #undef pr_fmt 28f38b0dd6STero Kristo #define pr_fmt(fmt) "%s: " fmt, __func__ 29f38b0dd6STero Kristo 30f38b0dd6STero Kristo #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \ 31f38b0dd6STero Kristo defined(CONFIG_SOC_DRA7XX) 32f38b0dd6STero Kristo static const struct clk_ops dpll_m4xen_ck_ops = { 33f38b0dd6STero Kristo .enable = &omap3_noncore_dpll_enable, 34f38b0dd6STero Kristo .disable = &omap3_noncore_dpll_disable, 35f38b0dd6STero Kristo .recalc_rate = &omap4_dpll_regm4xen_recalc, 36f38b0dd6STero Kristo .round_rate = &omap4_dpll_regm4xen_round_rate, 37f38b0dd6STero Kristo .set_rate = &omap3_noncore_dpll_set_rate, 382e1a7b01STero Kristo .set_parent = &omap3_noncore_dpll_set_parent, 392e1a7b01STero Kristo .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent, 402e1a7b01STero Kristo .determine_rate = &omap4_dpll_regm4xen_determine_rate, 41f38b0dd6STero Kristo .get_parent = &omap2_init_dpll_parent, 42d6e7bbc1SRuss Dill .save_context = &omap3_core_dpll_save_context, 43d6e7bbc1SRuss Dill .restore_context = &omap3_core_dpll_restore_context, 44f38b0dd6STero Kristo }; 45aa76fcf4STero Kristo #else 46aa76fcf4STero Kristo static const struct clk_ops dpll_m4xen_ck_ops = {}; 47f38b0dd6STero Kristo #endif 48f38b0dd6STero Kristo 49aa76fcf4STero Kristo #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) || \ 50aa76fcf4STero Kristo defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX) || \ 51aa76fcf4STero Kristo defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX) 52f38b0dd6STero Kristo static const struct clk_ops dpll_core_ck_ops = { 53f38b0dd6STero Kristo .recalc_rate = &omap3_dpll_recalc, 54f38b0dd6STero Kristo .get_parent = &omap2_init_dpll_parent, 55f38b0dd6STero Kristo }; 56f38b0dd6STero Kristo 57f38b0dd6STero Kristo static const struct clk_ops dpll_ck_ops = { 58f38b0dd6STero Kristo .enable = &omap3_noncore_dpll_enable, 59f38b0dd6STero Kristo .disable = &omap3_noncore_dpll_disable, 60f38b0dd6STero Kristo .recalc_rate = &omap3_dpll_recalc, 61f38b0dd6STero Kristo .round_rate = &omap2_dpll_round_rate, 62f38b0dd6STero Kristo .set_rate = &omap3_noncore_dpll_set_rate, 632e1a7b01STero Kristo .set_parent = &omap3_noncore_dpll_set_parent, 642e1a7b01STero Kristo .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent, 652e1a7b01STero Kristo .determine_rate = &omap3_noncore_dpll_determine_rate, 66f38b0dd6STero Kristo .get_parent = &omap2_init_dpll_parent, 67d6e7bbc1SRuss Dill .save_context = &omap3_noncore_dpll_save_context, 68d6e7bbc1SRuss Dill .restore_context = &omap3_noncore_dpll_restore_context, 69f38b0dd6STero Kristo }; 70f38b0dd6STero Kristo 71f38b0dd6STero Kristo static const struct clk_ops dpll_no_gate_ck_ops = { 72f38b0dd6STero Kristo .recalc_rate = &omap3_dpll_recalc, 73f38b0dd6STero Kristo .get_parent = &omap2_init_dpll_parent, 74f38b0dd6STero Kristo .round_rate = &omap2_dpll_round_rate, 75f38b0dd6STero Kristo .set_rate = &omap3_noncore_dpll_set_rate, 762e1a7b01STero Kristo .set_parent = &omap3_noncore_dpll_set_parent, 772e1a7b01STero Kristo .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent, 782e1a7b01STero Kristo .determine_rate = &omap3_noncore_dpll_determine_rate, 79d6e7bbc1SRuss Dill .save_context = &omap3_noncore_dpll_save_context, 80d6e7bbc1SRuss Dill .restore_context = &omap3_noncore_dpll_restore_context 81f38b0dd6STero Kristo }; 82aa76fcf4STero Kristo #else 83aa76fcf4STero Kristo static const struct clk_ops dpll_core_ck_ops = {}; 84aa76fcf4STero Kristo static const struct clk_ops dpll_ck_ops = {}; 85aa76fcf4STero Kristo static const struct clk_ops dpll_no_gate_ck_ops = {}; 86aa76fcf4STero Kristo const struct clk_hw_omap_ops clkhwops_omap3_dpll = {}; 87aa76fcf4STero Kristo #endif 88aa76fcf4STero Kristo 89aa76fcf4STero Kristo #ifdef CONFIG_ARCH_OMAP2 90aa76fcf4STero Kristo static const struct clk_ops omap2_dpll_core_ck_ops = { 91aa76fcf4STero Kristo .get_parent = &omap2_init_dpll_parent, 92aa76fcf4STero Kristo .recalc_rate = &omap2_dpllcore_recalc, 93aa76fcf4STero Kristo .round_rate = &omap2_dpll_round_rate, 94aa76fcf4STero Kristo .set_rate = &omap2_reprogram_dpllcore, 95aa76fcf4STero Kristo }; 96aa76fcf4STero Kristo #else 97aa76fcf4STero Kristo static const struct clk_ops omap2_dpll_core_ck_ops = {}; 98aa76fcf4STero Kristo #endif 99aa76fcf4STero Kristo 100aa76fcf4STero Kristo #ifdef CONFIG_ARCH_OMAP3 101aa76fcf4STero Kristo static const struct clk_ops omap3_dpll_core_ck_ops = { 102aa76fcf4STero Kristo .get_parent = &omap2_init_dpll_parent, 103aa76fcf4STero Kristo .recalc_rate = &omap3_dpll_recalc, 104aa76fcf4STero Kristo .round_rate = &omap2_dpll_round_rate, 105aa76fcf4STero Kristo }; 106aa76fcf4STero Kristo #else 107aa76fcf4STero Kristo static const struct clk_ops omap3_dpll_core_ck_ops = {}; 108aa76fcf4STero Kristo #endif 109f38b0dd6STero Kristo 110f38b0dd6STero Kristo #ifdef CONFIG_ARCH_OMAP3 111f38b0dd6STero Kristo static const struct clk_ops omap3_dpll_ck_ops = { 112f38b0dd6STero Kristo .enable = &omap3_noncore_dpll_enable, 113f38b0dd6STero Kristo .disable = &omap3_noncore_dpll_disable, 114f38b0dd6STero Kristo .get_parent = &omap2_init_dpll_parent, 115f38b0dd6STero Kristo .recalc_rate = &omap3_dpll_recalc, 116f38b0dd6STero Kristo .set_rate = &omap3_noncore_dpll_set_rate, 1172e1a7b01STero Kristo .set_parent = &omap3_noncore_dpll_set_parent, 1182e1a7b01STero Kristo .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent, 1192e1a7b01STero Kristo .determine_rate = &omap3_noncore_dpll_determine_rate, 120f38b0dd6STero Kristo .round_rate = &omap2_dpll_round_rate, 121f38b0dd6STero Kristo }; 122f38b0dd6STero Kristo 123035cd485SRichard Watts static const struct clk_ops omap3_dpll5_ck_ops = { 124035cd485SRichard Watts .enable = &omap3_noncore_dpll_enable, 125035cd485SRichard Watts .disable = &omap3_noncore_dpll_disable, 126035cd485SRichard Watts .get_parent = &omap2_init_dpll_parent, 127035cd485SRichard Watts .recalc_rate = &omap3_dpll_recalc, 128035cd485SRichard Watts .set_rate = &omap3_dpll5_set_rate, 129035cd485SRichard Watts .set_parent = &omap3_noncore_dpll_set_parent, 130035cd485SRichard Watts .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent, 131035cd485SRichard Watts .determine_rate = &omap3_noncore_dpll_determine_rate, 132035cd485SRichard Watts .round_rate = &omap2_dpll_round_rate, 133035cd485SRichard Watts }; 134035cd485SRichard Watts 135f38b0dd6STero Kristo static const struct clk_ops omap3_dpll_per_ck_ops = { 136f38b0dd6STero Kristo .enable = &omap3_noncore_dpll_enable, 137f38b0dd6STero Kristo .disable = &omap3_noncore_dpll_disable, 138f38b0dd6STero Kristo .get_parent = &omap2_init_dpll_parent, 139f38b0dd6STero Kristo .recalc_rate = &omap3_dpll_recalc, 140f38b0dd6STero Kristo .set_rate = &omap3_dpll4_set_rate, 1412e1a7b01STero Kristo .set_parent = &omap3_noncore_dpll_set_parent, 1422e1a7b01STero Kristo .set_rate_and_parent = &omap3_dpll4_set_rate_and_parent, 1432e1a7b01STero Kristo .determine_rate = &omap3_noncore_dpll_determine_rate, 144f38b0dd6STero Kristo .round_rate = &omap2_dpll_round_rate, 145f38b0dd6STero Kristo }; 146f38b0dd6STero Kristo #endif 147f38b0dd6STero Kristo 148f38b0dd6STero Kristo static const struct clk_ops dpll_x2_ck_ops = { 149f38b0dd6STero Kristo .recalc_rate = &omap3_clkoutx2_recalc, 150f38b0dd6STero Kristo }; 151f38b0dd6STero Kristo 152f38b0dd6STero Kristo /** 153ed405a23STero Kristo * _register_dpll - low level registration of a DPLL clock 154*975b3eddSLee Jones * @user: pointer to the hardware clock definition for the clock 155f38b0dd6STero Kristo * @node: device node for the clock 156f38b0dd6STero Kristo * 157f38b0dd6STero Kristo * Finalizes DPLL registration process. In case a failure (clk-ref or 158f38b0dd6STero Kristo * clk-bypass is missing), the clock is added to retry list and 159f38b0dd6STero Kristo * the initialization is retried on later stage. 160f38b0dd6STero Kristo */ 161ffb009b2STero Kristo static void __init _register_dpll(void *user, 162f38b0dd6STero Kristo struct device_node *node) 163f38b0dd6STero Kristo { 164ffb009b2STero Kristo struct clk_hw *hw = user; 165f38b0dd6STero Kristo struct clk_hw_omap *clk_hw = to_clk_hw_omap(hw); 166f38b0dd6STero Kristo struct dpll_data *dd = clk_hw->dpll_data; 167f38b0dd6STero Kristo struct clk *clk; 168e0e04fc8SStephen Boyd const struct clk_init_data *init = hw->init; 169f38b0dd6STero Kristo 170b6f51284STero Kristo clk = of_clk_get(node, 0); 171b6f51284STero Kristo if (IS_ERR(clk)) { 172e665f029SRob Herring pr_debug("clk-ref missing for %pOFn, retry later\n", 173e665f029SRob Herring node); 174ed405a23STero Kristo if (!ti_clk_retry_init(node, hw, _register_dpll)) 175f38b0dd6STero Kristo return; 176f38b0dd6STero Kristo 177f38b0dd6STero Kristo goto cleanup; 178f38b0dd6STero Kristo } 179f38b0dd6STero Kristo 180b6f51284STero Kristo dd->clk_ref = __clk_get_hw(clk); 181b6f51284STero Kristo 182b6f51284STero Kristo clk = of_clk_get(node, 1); 183b6f51284STero Kristo 184b6f51284STero Kristo if (IS_ERR(clk)) { 185e665f029SRob Herring pr_debug("clk-bypass missing for %pOFn, retry later\n", 186e665f029SRob Herring node); 187b6f51284STero Kristo if (!ti_clk_retry_init(node, hw, _register_dpll)) 188b6f51284STero Kristo return; 189b6f51284STero Kristo 190b6f51284STero Kristo goto cleanup; 191b6f51284STero Kristo } 192b6f51284STero Kristo 193b6f51284STero Kristo dd->clk_bypass = __clk_get_hw(clk); 194b6f51284STero Kristo 195f38b0dd6STero Kristo /* register the clock */ 196ead47825STero Kristo clk = ti_clk_register_omap_hw(NULL, &clk_hw->hw, node->name); 197f38b0dd6STero Kristo 198f38b0dd6STero Kristo if (!IS_ERR(clk)) { 199f38b0dd6STero Kristo of_clk_add_provider(node, of_clk_src_simple_get, clk); 200e0e04fc8SStephen Boyd kfree(init->parent_names); 201e0e04fc8SStephen Boyd kfree(init); 202f38b0dd6STero Kristo return; 203f38b0dd6STero Kristo } 204f38b0dd6STero Kristo 205f38b0dd6STero Kristo cleanup: 206f38b0dd6STero Kristo kfree(clk_hw->dpll_data); 207e0e04fc8SStephen Boyd kfree(init->parent_names); 208e0e04fc8SStephen Boyd kfree(init); 209f38b0dd6STero Kristo kfree(clk_hw); 210f38b0dd6STero Kristo } 211f38b0dd6STero Kristo 212f38b0dd6STero Kristo #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \ 2134332ec1aSRoger Quadros defined(CONFIG_SOC_DRA7XX) || defined(CONFIG_SOC_AM33XX) || \ 2144332ec1aSRoger Quadros defined(CONFIG_SOC_AM43XX) 215f38b0dd6STero Kristo /** 216ed405a23STero Kristo * _register_dpll_x2 - Registers a DPLLx2 clock 217f38b0dd6STero Kristo * @node: device node for this clock 218f38b0dd6STero Kristo * @ops: clk_ops for this clock 219f38b0dd6STero Kristo * @hw_ops: clk_hw_ops for this clock 220f38b0dd6STero Kristo * 221f38b0dd6STero Kristo * Initializes a DPLL x 2 clock from device tree data. 222f38b0dd6STero Kristo */ 223ed405a23STero Kristo static void _register_dpll_x2(struct device_node *node, 224f38b0dd6STero Kristo const struct clk_ops *ops, 225f38b0dd6STero Kristo const struct clk_hw_omap_ops *hw_ops) 226f38b0dd6STero Kristo { 227f38b0dd6STero Kristo struct clk *clk; 228f38b0dd6STero Kristo struct clk_init_data init = { NULL }; 229f38b0dd6STero Kristo struct clk_hw_omap *clk_hw; 230f38b0dd6STero Kristo const char *name = node->name; 231f38b0dd6STero Kristo const char *parent_name; 232f38b0dd6STero Kristo 233f38b0dd6STero Kristo parent_name = of_clk_get_parent_name(node, 0); 234f38b0dd6STero Kristo if (!parent_name) { 235e665f029SRob Herring pr_err("%pOFn must have parent\n", node); 236f38b0dd6STero Kristo return; 237f38b0dd6STero Kristo } 238f38b0dd6STero Kristo 239f38b0dd6STero Kristo clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL); 240f38b0dd6STero Kristo if (!clk_hw) 241f38b0dd6STero Kristo return; 242f38b0dd6STero Kristo 243f38b0dd6STero Kristo clk_hw->ops = hw_ops; 244f38b0dd6STero Kristo clk_hw->hw.init = &init; 245f38b0dd6STero Kristo 246f38b0dd6STero Kristo init.name = name; 247f38b0dd6STero Kristo init.ops = ops; 248f38b0dd6STero Kristo init.parent_names = &parent_name; 249f38b0dd6STero Kristo init.num_parents = 1; 250f38b0dd6STero Kristo 2512158a093SArnd Bergmann #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \ 2522158a093SArnd Bergmann defined(CONFIG_SOC_DRA7XX) 253473adbf4STero Kristo if (hw_ops == &clkhwops_omap4_dpllmx) { 2542158a093SArnd Bergmann int ret; 2552158a093SArnd Bergmann 256473adbf4STero Kristo /* Check if register defined, if not, drop hw-ops */ 257473adbf4STero Kristo ret = of_property_count_elems_of_size(node, "reg", 1); 258473adbf4STero Kristo if (ret <= 0) { 2592158a093SArnd Bergmann clk_hw->ops = NULL; 2606c0afb50STero Kristo } else if (ti_clk_get_reg_addr(node, 0, &clk_hw->clksel_reg)) { 261473adbf4STero Kristo kfree(clk_hw); 262473adbf4STero Kristo return; 263473adbf4STero Kristo } 264473adbf4STero Kristo } 2652158a093SArnd Bergmann #endif 266473adbf4STero Kristo 267f38b0dd6STero Kristo /* register the clock */ 268ead47825STero Kristo clk = ti_clk_register_omap_hw(NULL, &clk_hw->hw, name); 269f38b0dd6STero Kristo 270ead47825STero Kristo if (IS_ERR(clk)) 271f38b0dd6STero Kristo kfree(clk_hw); 272ead47825STero Kristo else 273f38b0dd6STero Kristo of_clk_add_provider(node, of_clk_src_simple_get, clk); 274f38b0dd6STero Kristo } 275f38b0dd6STero Kristo #endif 276f38b0dd6STero Kristo 277f38b0dd6STero Kristo /** 278f38b0dd6STero Kristo * of_ti_dpll_setup - Setup function for OMAP DPLL clocks 279f38b0dd6STero Kristo * @node: device node containing the DPLL info 280f38b0dd6STero Kristo * @ops: ops for the DPLL 281f38b0dd6STero Kristo * @ddt: DPLL data template to use 282f38b0dd6STero Kristo * 283f38b0dd6STero Kristo * Initializes a DPLL clock from device tree data. 284f38b0dd6STero Kristo */ 285f38b0dd6STero Kristo static void __init of_ti_dpll_setup(struct device_node *node, 286f38b0dd6STero Kristo const struct clk_ops *ops, 287a6fe3771STero Kristo const struct dpll_data *ddt) 288f38b0dd6STero Kristo { 289f38b0dd6STero Kristo struct clk_hw_omap *clk_hw = NULL; 290f38b0dd6STero Kristo struct clk_init_data *init = NULL; 291f38b0dd6STero Kristo const char **parent_names = NULL; 292f38b0dd6STero Kristo struct dpll_data *dd = NULL; 293f38b0dd6STero Kristo u8 dpll_mode = 0; 294f38b0dd6STero Kristo 29581b94f14SFuqian Huang dd = kmemdup(ddt, sizeof(*dd), GFP_KERNEL); 296f38b0dd6STero Kristo clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL); 297f38b0dd6STero Kristo init = kzalloc(sizeof(*init), GFP_KERNEL); 298f38b0dd6STero Kristo if (!dd || !clk_hw || !init) 299f38b0dd6STero Kristo goto cleanup; 300f38b0dd6STero Kristo 301f38b0dd6STero Kristo clk_hw->dpll_data = dd; 302f38b0dd6STero Kristo clk_hw->ops = &clkhwops_omap3_dpll; 303f38b0dd6STero Kristo clk_hw->hw.init = init; 304f38b0dd6STero Kristo 305f38b0dd6STero Kristo init->name = node->name; 306f38b0dd6STero Kristo init->ops = ops; 307f38b0dd6STero Kristo 308f38b0dd6STero Kristo init->num_parents = of_clk_get_parent_count(node); 309921bacfaSStephen Boyd if (!init->num_parents) { 310e665f029SRob Herring pr_err("%pOFn must have parent(s)\n", node); 311f38b0dd6STero Kristo goto cleanup; 312f38b0dd6STero Kristo } 313f38b0dd6STero Kristo 3146396bb22SKees Cook parent_names = kcalloc(init->num_parents, sizeof(char *), GFP_KERNEL); 315f38b0dd6STero Kristo if (!parent_names) 316f38b0dd6STero Kristo goto cleanup; 317f38b0dd6STero Kristo 3189da9e761SDinh Nguyen of_clk_parent_fill(node, parent_names, init->num_parents); 319f38b0dd6STero Kristo 320f38b0dd6STero Kristo init->parent_names = parent_names; 321f38b0dd6STero Kristo 3226c0afb50STero Kristo if (ti_clk_get_reg_addr(node, 0, &dd->control_reg)) 3236c0afb50STero Kristo goto cleanup; 324f38b0dd6STero Kristo 325aa76fcf4STero Kristo /* 326aa76fcf4STero Kristo * Special case for OMAP2 DPLL, register order is different due to 327aa76fcf4STero Kristo * missing idlest_reg, also clkhwops is different. Detected from 328aa76fcf4STero Kristo * missing idlest_mask. 329aa76fcf4STero Kristo */ 330aa76fcf4STero Kristo if (!dd->idlest_mask) { 3316c0afb50STero Kristo if (ti_clk_get_reg_addr(node, 1, &dd->mult_div1_reg)) 3326c0afb50STero Kristo goto cleanup; 333aa76fcf4STero Kristo #ifdef CONFIG_ARCH_OMAP2 334aa76fcf4STero Kristo clk_hw->ops = &clkhwops_omap2xxx_dpll; 335aa76fcf4STero Kristo omap2xxx_clkt_dpllcore_init(&clk_hw->hw); 336aa76fcf4STero Kristo #endif 337aa76fcf4STero Kristo } else { 3386c0afb50STero Kristo if (ti_clk_get_reg_addr(node, 1, &dd->idlest_reg)) 339aa76fcf4STero Kristo goto cleanup; 340aa76fcf4STero Kristo 3416c0afb50STero Kristo if (ti_clk_get_reg_addr(node, 2, &dd->mult_div1_reg)) 3426c0afb50STero Kristo goto cleanup; 343aa76fcf4STero Kristo } 344aa76fcf4STero Kristo 345a6fe3771STero Kristo if (dd->autoidle_mask) { 3466c0afb50STero Kristo if (ti_clk_get_reg_addr(node, 3, &dd->autoidle_reg)) 347f38b0dd6STero Kristo goto cleanup; 348f38b0dd6STero Kristo } 349f38b0dd6STero Kristo 350f38b0dd6STero Kristo if (of_property_read_bool(node, "ti,low-power-stop")) 351f38b0dd6STero Kristo dpll_mode |= 1 << DPLL_LOW_POWER_STOP; 352f38b0dd6STero Kristo 353f38b0dd6STero Kristo if (of_property_read_bool(node, "ti,low-power-bypass")) 354f38b0dd6STero Kristo dpll_mode |= 1 << DPLL_LOW_POWER_BYPASS; 355f38b0dd6STero Kristo 356f38b0dd6STero Kristo if (of_property_read_bool(node, "ti,lock")) 357f38b0dd6STero Kristo dpll_mode |= 1 << DPLL_LOCKED; 358f38b0dd6STero Kristo 359f38b0dd6STero Kristo if (dpll_mode) 360f38b0dd6STero Kristo dd->modes = dpll_mode; 361f38b0dd6STero Kristo 362ed405a23STero Kristo _register_dpll(&clk_hw->hw, node); 363f38b0dd6STero Kristo return; 364f38b0dd6STero Kristo 365f38b0dd6STero Kristo cleanup: 366f38b0dd6STero Kristo kfree(dd); 367f38b0dd6STero Kristo kfree(parent_names); 368f38b0dd6STero Kristo kfree(init); 369f38b0dd6STero Kristo kfree(clk_hw); 370f38b0dd6STero Kristo } 371f38b0dd6STero Kristo 372f38b0dd6STero Kristo #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \ 373f38b0dd6STero Kristo defined(CONFIG_SOC_DRA7XX) 374f38b0dd6STero Kristo static void __init of_ti_omap4_dpll_x2_setup(struct device_node *node) 375f38b0dd6STero Kristo { 376ed405a23STero Kristo _register_dpll_x2(node, &dpll_x2_ck_ops, &clkhwops_omap4_dpllmx); 377f38b0dd6STero Kristo } 378f38b0dd6STero Kristo CLK_OF_DECLARE(ti_omap4_dpll_x2_clock, "ti,omap4-dpll-x2-clock", 379f38b0dd6STero Kristo of_ti_omap4_dpll_x2_setup); 380f38b0dd6STero Kristo #endif 381f38b0dd6STero Kristo 3824332ec1aSRoger Quadros #if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX) 383f38b0dd6STero Kristo static void __init of_ti_am3_dpll_x2_setup(struct device_node *node) 384f38b0dd6STero Kristo { 385ed405a23STero Kristo _register_dpll_x2(node, &dpll_x2_ck_ops, NULL); 386f38b0dd6STero Kristo } 387f38b0dd6STero Kristo CLK_OF_DECLARE(ti_am3_dpll_x2_clock, "ti,am3-dpll-x2-clock", 388f38b0dd6STero Kristo of_ti_am3_dpll_x2_setup); 389f38b0dd6STero Kristo #endif 390f38b0dd6STero Kristo 391f38b0dd6STero Kristo #ifdef CONFIG_ARCH_OMAP3 392f38b0dd6STero Kristo static void __init of_ti_omap3_dpll_setup(struct device_node *node) 393f38b0dd6STero Kristo { 394f38b0dd6STero Kristo const struct dpll_data dd = { 395f38b0dd6STero Kristo .idlest_mask = 0x1, 396f38b0dd6STero Kristo .enable_mask = 0x7, 397f38b0dd6STero Kristo .autoidle_mask = 0x7, 398f38b0dd6STero Kristo .mult_mask = 0x7ff << 8, 399f38b0dd6STero Kristo .div1_mask = 0x7f, 400f38b0dd6STero Kristo .max_multiplier = 2047, 401f38b0dd6STero Kristo .max_divider = 128, 402f38b0dd6STero Kristo .min_divider = 1, 403f38b0dd6STero Kristo .freqsel_mask = 0xf0, 404f38b0dd6STero Kristo .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), 405f38b0dd6STero Kristo }; 406f38b0dd6STero Kristo 407035cd485SRichard Watts if ((of_machine_is_compatible("ti,omap3630") || 408035cd485SRichard Watts of_machine_is_compatible("ti,omap36xx")) && 40987ab1151SRob Herring of_node_name_eq(node, "dpll5_ck")) 410035cd485SRichard Watts of_ti_dpll_setup(node, &omap3_dpll5_ck_ops, &dd); 411035cd485SRichard Watts else 412a6fe3771STero Kristo of_ti_dpll_setup(node, &omap3_dpll_ck_ops, &dd); 413f38b0dd6STero Kristo } 414f38b0dd6STero Kristo CLK_OF_DECLARE(ti_omap3_dpll_clock, "ti,omap3-dpll-clock", 415f38b0dd6STero Kristo of_ti_omap3_dpll_setup); 416f38b0dd6STero Kristo 417f38b0dd6STero Kristo static void __init of_ti_omap3_core_dpll_setup(struct device_node *node) 418f38b0dd6STero Kristo { 419f38b0dd6STero Kristo const struct dpll_data dd = { 420f38b0dd6STero Kristo .idlest_mask = 0x1, 421f38b0dd6STero Kristo .enable_mask = 0x7, 422f38b0dd6STero Kristo .autoidle_mask = 0x7, 423f38b0dd6STero Kristo .mult_mask = 0x7ff << 16, 424f38b0dd6STero Kristo .div1_mask = 0x7f << 8, 425f38b0dd6STero Kristo .max_multiplier = 2047, 426f38b0dd6STero Kristo .max_divider = 128, 427f38b0dd6STero Kristo .min_divider = 1, 428f38b0dd6STero Kristo .freqsel_mask = 0xf0, 429f38b0dd6STero Kristo }; 430f38b0dd6STero Kristo 431a6fe3771STero Kristo of_ti_dpll_setup(node, &omap3_dpll_core_ck_ops, &dd); 432f38b0dd6STero Kristo } 433f38b0dd6STero Kristo CLK_OF_DECLARE(ti_omap3_core_dpll_clock, "ti,omap3-dpll-core-clock", 434f38b0dd6STero Kristo of_ti_omap3_core_dpll_setup); 435f38b0dd6STero Kristo 436f38b0dd6STero Kristo static void __init of_ti_omap3_per_dpll_setup(struct device_node *node) 437f38b0dd6STero Kristo { 438f38b0dd6STero Kristo const struct dpll_data dd = { 439f38b0dd6STero Kristo .idlest_mask = 0x1 << 1, 440f38b0dd6STero Kristo .enable_mask = 0x7 << 16, 441f38b0dd6STero Kristo .autoidle_mask = 0x7 << 3, 442f38b0dd6STero Kristo .mult_mask = 0x7ff << 8, 443f38b0dd6STero Kristo .div1_mask = 0x7f, 444f38b0dd6STero Kristo .max_multiplier = 2047, 445f38b0dd6STero Kristo .max_divider = 128, 446f38b0dd6STero Kristo .min_divider = 1, 447f38b0dd6STero Kristo .freqsel_mask = 0xf00000, 448f38b0dd6STero Kristo .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED), 449f38b0dd6STero Kristo }; 450f38b0dd6STero Kristo 451a6fe3771STero Kristo of_ti_dpll_setup(node, &omap3_dpll_per_ck_ops, &dd); 452f38b0dd6STero Kristo } 453f38b0dd6STero Kristo CLK_OF_DECLARE(ti_omap3_per_dpll_clock, "ti,omap3-dpll-per-clock", 454f38b0dd6STero Kristo of_ti_omap3_per_dpll_setup); 455f38b0dd6STero Kristo 456f38b0dd6STero Kristo static void __init of_ti_omap3_per_jtype_dpll_setup(struct device_node *node) 457f38b0dd6STero Kristo { 458f38b0dd6STero Kristo const struct dpll_data dd = { 459f38b0dd6STero Kristo .idlest_mask = 0x1 << 1, 460f38b0dd6STero Kristo .enable_mask = 0x7 << 16, 461f38b0dd6STero Kristo .autoidle_mask = 0x7 << 3, 462f38b0dd6STero Kristo .mult_mask = 0xfff << 8, 463f38b0dd6STero Kristo .div1_mask = 0x7f, 464f38b0dd6STero Kristo .max_multiplier = 4095, 465f38b0dd6STero Kristo .max_divider = 128, 466f38b0dd6STero Kristo .min_divider = 1, 467f38b0dd6STero Kristo .sddiv_mask = 0xff << 24, 468f38b0dd6STero Kristo .dco_mask = 0xe << 20, 469f38b0dd6STero Kristo .flags = DPLL_J_TYPE, 470f38b0dd6STero Kristo .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED), 471f38b0dd6STero Kristo }; 472f38b0dd6STero Kristo 473a6fe3771STero Kristo of_ti_dpll_setup(node, &omap3_dpll_per_ck_ops, &dd); 474f38b0dd6STero Kristo } 475f38b0dd6STero Kristo CLK_OF_DECLARE(ti_omap3_per_jtype_dpll_clock, "ti,omap3-dpll-per-j-type-clock", 476f38b0dd6STero Kristo of_ti_omap3_per_jtype_dpll_setup); 477f38b0dd6STero Kristo #endif 478f38b0dd6STero Kristo 479f38b0dd6STero Kristo static void __init of_ti_omap4_dpll_setup(struct device_node *node) 480f38b0dd6STero Kristo { 481f38b0dd6STero Kristo const struct dpll_data dd = { 482f38b0dd6STero Kristo .idlest_mask = 0x1, 483f38b0dd6STero Kristo .enable_mask = 0x7, 484f38b0dd6STero Kristo .autoidle_mask = 0x7, 485f38b0dd6STero Kristo .mult_mask = 0x7ff << 8, 486f38b0dd6STero Kristo .div1_mask = 0x7f, 487f38b0dd6STero Kristo .max_multiplier = 2047, 488f38b0dd6STero Kristo .max_divider = 128, 489f38b0dd6STero Kristo .min_divider = 1, 490f38b0dd6STero Kristo .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), 491f38b0dd6STero Kristo }; 492f38b0dd6STero Kristo 493a6fe3771STero Kristo of_ti_dpll_setup(node, &dpll_ck_ops, &dd); 494f38b0dd6STero Kristo } 495f38b0dd6STero Kristo CLK_OF_DECLARE(ti_omap4_dpll_clock, "ti,omap4-dpll-clock", 496f38b0dd6STero Kristo of_ti_omap4_dpll_setup); 497f38b0dd6STero Kristo 498b4be0189SNishanth Menon static void __init of_ti_omap5_mpu_dpll_setup(struct device_node *node) 499b4be0189SNishanth Menon { 500b4be0189SNishanth Menon const struct dpll_data dd = { 501b4be0189SNishanth Menon .idlest_mask = 0x1, 502b4be0189SNishanth Menon .enable_mask = 0x7, 503b4be0189SNishanth Menon .autoidle_mask = 0x7, 504b4be0189SNishanth Menon .mult_mask = 0x7ff << 8, 505b4be0189SNishanth Menon .div1_mask = 0x7f, 506b4be0189SNishanth Menon .max_multiplier = 2047, 507b4be0189SNishanth Menon .max_divider = 128, 508b4be0189SNishanth Menon .dcc_mask = BIT(22), 509b4be0189SNishanth Menon .dcc_rate = 1400000000, /* DCC beyond 1.4GHz */ 510b4be0189SNishanth Menon .min_divider = 1, 511b4be0189SNishanth Menon .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), 512b4be0189SNishanth Menon }; 513b4be0189SNishanth Menon 514b4be0189SNishanth Menon of_ti_dpll_setup(node, &dpll_ck_ops, &dd); 515b4be0189SNishanth Menon } 516b4be0189SNishanth Menon CLK_OF_DECLARE(of_ti_omap5_mpu_dpll_clock, "ti,omap5-mpu-dpll-clock", 517b4be0189SNishanth Menon of_ti_omap5_mpu_dpll_setup); 518b4be0189SNishanth Menon 519f38b0dd6STero Kristo static void __init of_ti_omap4_core_dpll_setup(struct device_node *node) 520f38b0dd6STero Kristo { 521f38b0dd6STero Kristo const struct dpll_data dd = { 522f38b0dd6STero Kristo .idlest_mask = 0x1, 523f38b0dd6STero Kristo .enable_mask = 0x7, 524f38b0dd6STero Kristo .autoidle_mask = 0x7, 525f38b0dd6STero Kristo .mult_mask = 0x7ff << 8, 526f38b0dd6STero Kristo .div1_mask = 0x7f, 527f38b0dd6STero Kristo .max_multiplier = 2047, 528f38b0dd6STero Kristo .max_divider = 128, 529f38b0dd6STero Kristo .min_divider = 1, 530f38b0dd6STero Kristo .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), 531f38b0dd6STero Kristo }; 532f38b0dd6STero Kristo 533a6fe3771STero Kristo of_ti_dpll_setup(node, &dpll_core_ck_ops, &dd); 534f38b0dd6STero Kristo } 535f38b0dd6STero Kristo CLK_OF_DECLARE(ti_omap4_core_dpll_clock, "ti,omap4-dpll-core-clock", 536f38b0dd6STero Kristo of_ti_omap4_core_dpll_setup); 537f38b0dd6STero Kristo 538f38b0dd6STero Kristo #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \ 539f38b0dd6STero Kristo defined(CONFIG_SOC_DRA7XX) 540f38b0dd6STero Kristo static void __init of_ti_omap4_m4xen_dpll_setup(struct device_node *node) 541f38b0dd6STero Kristo { 542f38b0dd6STero Kristo const struct dpll_data dd = { 543f38b0dd6STero Kristo .idlest_mask = 0x1, 544f38b0dd6STero Kristo .enable_mask = 0x7, 545f38b0dd6STero Kristo .autoidle_mask = 0x7, 546f38b0dd6STero Kristo .mult_mask = 0x7ff << 8, 547f38b0dd6STero Kristo .div1_mask = 0x7f, 548f38b0dd6STero Kristo .max_multiplier = 2047, 549f38b0dd6STero Kristo .max_divider = 128, 550f38b0dd6STero Kristo .min_divider = 1, 551f38b0dd6STero Kristo .m4xen_mask = 0x800, 552f38b0dd6STero Kristo .lpmode_mask = 1 << 10, 553f38b0dd6STero Kristo .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), 554f38b0dd6STero Kristo }; 555f38b0dd6STero Kristo 556a6fe3771STero Kristo of_ti_dpll_setup(node, &dpll_m4xen_ck_ops, &dd); 557f38b0dd6STero Kristo } 558f38b0dd6STero Kristo CLK_OF_DECLARE(ti_omap4_m4xen_dpll_clock, "ti,omap4-dpll-m4xen-clock", 559f38b0dd6STero Kristo of_ti_omap4_m4xen_dpll_setup); 560f38b0dd6STero Kristo 561f38b0dd6STero Kristo static void __init of_ti_omap4_jtype_dpll_setup(struct device_node *node) 562f38b0dd6STero Kristo { 563f38b0dd6STero Kristo const struct dpll_data dd = { 564f38b0dd6STero Kristo .idlest_mask = 0x1, 565f38b0dd6STero Kristo .enable_mask = 0x7, 566f38b0dd6STero Kristo .autoidle_mask = 0x7, 567f38b0dd6STero Kristo .mult_mask = 0xfff << 8, 568f38b0dd6STero Kristo .div1_mask = 0xff, 569f38b0dd6STero Kristo .max_multiplier = 4095, 570f38b0dd6STero Kristo .max_divider = 256, 571f38b0dd6STero Kristo .min_divider = 1, 572f38b0dd6STero Kristo .sddiv_mask = 0xff << 24, 573f38b0dd6STero Kristo .flags = DPLL_J_TYPE, 574f38b0dd6STero Kristo .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), 575f38b0dd6STero Kristo }; 576f38b0dd6STero Kristo 577a6fe3771STero Kristo of_ti_dpll_setup(node, &dpll_m4xen_ck_ops, &dd); 578f38b0dd6STero Kristo } 579f38b0dd6STero Kristo CLK_OF_DECLARE(ti_omap4_jtype_dpll_clock, "ti,omap4-dpll-j-type-clock", 580f38b0dd6STero Kristo of_ti_omap4_jtype_dpll_setup); 581f38b0dd6STero Kristo #endif 582f38b0dd6STero Kristo 583f38b0dd6STero Kristo static void __init of_ti_am3_no_gate_dpll_setup(struct device_node *node) 584f38b0dd6STero Kristo { 585f38b0dd6STero Kristo const struct dpll_data dd = { 586f38b0dd6STero Kristo .idlest_mask = 0x1, 587f38b0dd6STero Kristo .enable_mask = 0x7, 588f38b0dd6STero Kristo .mult_mask = 0x7ff << 8, 589f38b0dd6STero Kristo .div1_mask = 0x7f, 590f38b0dd6STero Kristo .max_multiplier = 2047, 591f38b0dd6STero Kristo .max_divider = 128, 592f38b0dd6STero Kristo .min_divider = 1, 5933db5ca27STero Kristo .max_rate = 1000000000, 594f38b0dd6STero Kristo .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), 595f38b0dd6STero Kristo }; 596f38b0dd6STero Kristo 597a6fe3771STero Kristo of_ti_dpll_setup(node, &dpll_no_gate_ck_ops, &dd); 598f38b0dd6STero Kristo } 599f38b0dd6STero Kristo CLK_OF_DECLARE(ti_am3_no_gate_dpll_clock, "ti,am3-dpll-no-gate-clock", 600f38b0dd6STero Kristo of_ti_am3_no_gate_dpll_setup); 601f38b0dd6STero Kristo 602f38b0dd6STero Kristo static void __init of_ti_am3_jtype_dpll_setup(struct device_node *node) 603f38b0dd6STero Kristo { 604f38b0dd6STero Kristo const struct dpll_data dd = { 605f38b0dd6STero Kristo .idlest_mask = 0x1, 606f38b0dd6STero Kristo .enable_mask = 0x7, 607f38b0dd6STero Kristo .mult_mask = 0x7ff << 8, 608f38b0dd6STero Kristo .div1_mask = 0x7f, 609f38b0dd6STero Kristo .max_multiplier = 4095, 610f38b0dd6STero Kristo .max_divider = 256, 611f38b0dd6STero Kristo .min_divider = 2, 612f38b0dd6STero Kristo .flags = DPLL_J_TYPE, 6133db5ca27STero Kristo .max_rate = 2000000000, 614f38b0dd6STero Kristo .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), 615f38b0dd6STero Kristo }; 616f38b0dd6STero Kristo 617a6fe3771STero Kristo of_ti_dpll_setup(node, &dpll_ck_ops, &dd); 618f38b0dd6STero Kristo } 619f38b0dd6STero Kristo CLK_OF_DECLARE(ti_am3_jtype_dpll_clock, "ti,am3-dpll-j-type-clock", 620f38b0dd6STero Kristo of_ti_am3_jtype_dpll_setup); 621f38b0dd6STero Kristo 622f38b0dd6STero Kristo static void __init of_ti_am3_no_gate_jtype_dpll_setup(struct device_node *node) 623f38b0dd6STero Kristo { 624f38b0dd6STero Kristo const struct dpll_data dd = { 625f38b0dd6STero Kristo .idlest_mask = 0x1, 626f38b0dd6STero Kristo .enable_mask = 0x7, 627f38b0dd6STero Kristo .mult_mask = 0x7ff << 8, 628f38b0dd6STero Kristo .div1_mask = 0x7f, 629f38b0dd6STero Kristo .max_multiplier = 2047, 630f38b0dd6STero Kristo .max_divider = 128, 631f38b0dd6STero Kristo .min_divider = 1, 6323db5ca27STero Kristo .max_rate = 2000000000, 633f38b0dd6STero Kristo .flags = DPLL_J_TYPE, 634f38b0dd6STero Kristo .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), 635f38b0dd6STero Kristo }; 636f38b0dd6STero Kristo 637a6fe3771STero Kristo of_ti_dpll_setup(node, &dpll_no_gate_ck_ops, &dd); 638f38b0dd6STero Kristo } 639f38b0dd6STero Kristo CLK_OF_DECLARE(ti_am3_no_gate_jtype_dpll_clock, 640f38b0dd6STero Kristo "ti,am3-dpll-no-gate-j-type-clock", 641f38b0dd6STero Kristo of_ti_am3_no_gate_jtype_dpll_setup); 642f38b0dd6STero Kristo 643f38b0dd6STero Kristo static void __init of_ti_am3_dpll_setup(struct device_node *node) 644f38b0dd6STero Kristo { 645f38b0dd6STero Kristo const struct dpll_data dd = { 646f38b0dd6STero Kristo .idlest_mask = 0x1, 647f38b0dd6STero Kristo .enable_mask = 0x7, 648f38b0dd6STero Kristo .mult_mask = 0x7ff << 8, 649f38b0dd6STero Kristo .div1_mask = 0x7f, 650f38b0dd6STero Kristo .max_multiplier = 2047, 651f38b0dd6STero Kristo .max_divider = 128, 652f38b0dd6STero Kristo .min_divider = 1, 6533db5ca27STero Kristo .max_rate = 1000000000, 654f38b0dd6STero Kristo .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), 655f38b0dd6STero Kristo }; 656f38b0dd6STero Kristo 657a6fe3771STero Kristo of_ti_dpll_setup(node, &dpll_ck_ops, &dd); 658f38b0dd6STero Kristo } 659f38b0dd6STero Kristo CLK_OF_DECLARE(ti_am3_dpll_clock, "ti,am3-dpll-clock", of_ti_am3_dpll_setup); 660f38b0dd6STero Kristo 661f38b0dd6STero Kristo static void __init of_ti_am3_core_dpll_setup(struct device_node *node) 662f38b0dd6STero Kristo { 663f38b0dd6STero Kristo const struct dpll_data dd = { 664f38b0dd6STero Kristo .idlest_mask = 0x1, 665f38b0dd6STero Kristo .enable_mask = 0x7, 666f38b0dd6STero Kristo .mult_mask = 0x7ff << 8, 667f38b0dd6STero Kristo .div1_mask = 0x7f, 668f38b0dd6STero Kristo .max_multiplier = 2047, 669f38b0dd6STero Kristo .max_divider = 128, 670f38b0dd6STero Kristo .min_divider = 1, 6713db5ca27STero Kristo .max_rate = 1000000000, 672f38b0dd6STero Kristo .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), 673f38b0dd6STero Kristo }; 674f38b0dd6STero Kristo 675a6fe3771STero Kristo of_ti_dpll_setup(node, &dpll_core_ck_ops, &dd); 676f38b0dd6STero Kristo } 677f38b0dd6STero Kristo CLK_OF_DECLARE(ti_am3_core_dpll_clock, "ti,am3-dpll-core-clock", 678f38b0dd6STero Kristo of_ti_am3_core_dpll_setup); 679aa76fcf4STero Kristo 680aa76fcf4STero Kristo static void __init of_ti_omap2_core_dpll_setup(struct device_node *node) 681aa76fcf4STero Kristo { 682aa76fcf4STero Kristo const struct dpll_data dd = { 683aa76fcf4STero Kristo .enable_mask = 0x3, 684aa76fcf4STero Kristo .mult_mask = 0x3ff << 12, 685aa76fcf4STero Kristo .div1_mask = 0xf << 8, 686aa76fcf4STero Kristo .max_divider = 16, 687aa76fcf4STero Kristo .min_divider = 1, 688aa76fcf4STero Kristo }; 689aa76fcf4STero Kristo 690aa76fcf4STero Kristo of_ti_dpll_setup(node, &omap2_dpll_core_ck_ops, &dd); 691aa76fcf4STero Kristo } 692aa76fcf4STero Kristo CLK_OF_DECLARE(ti_omap2_core_dpll_clock, "ti,omap2-dpll-core-clock", 693aa76fcf4STero Kristo of_ti_omap2_core_dpll_setup); 694