16b301a05SRhyland Klein /* 26b301a05SRhyland Klein * Copyright (c) 2012-2014 NVIDIA CORPORATION. All rights reserved. 36b301a05SRhyland Klein * 46b301a05SRhyland Klein * This program is free software; you can redistribute it and/or modify it 56b301a05SRhyland Klein * under the terms and conditions of the GNU General Public License, 66b301a05SRhyland Klein * version 2, as published by the Free Software Foundation. 76b301a05SRhyland Klein * 86b301a05SRhyland Klein * This program is distributed in the hope it will be useful, but WITHOUT 96b301a05SRhyland Klein * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 106b301a05SRhyland Klein * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 116b301a05SRhyland Klein * more details. 126b301a05SRhyland Klein * 136b301a05SRhyland Klein * You should have received a copy of the GNU General Public License 146b301a05SRhyland Klein * along with this program. If not, see <http://www.gnu.org/licenses/>. 156b301a05SRhyland Klein */ 166b301a05SRhyland Klein 176b301a05SRhyland Klein #include <linux/io.h> 186b301a05SRhyland Klein #include <linux/clk.h> 196b301a05SRhyland Klein #include <linux/clk-provider.h> 206b301a05SRhyland Klein #include <linux/clkdev.h> 216b301a05SRhyland Klein #include <linux/of.h> 226b301a05SRhyland Klein #include <linux/of_address.h> 236b301a05SRhyland Klein #include <linux/delay.h> 246b301a05SRhyland Klein #include <linux/export.h> 256b301a05SRhyland Klein #include <linux/clk/tegra.h> 266b301a05SRhyland Klein #include <dt-bindings/clock/tegra210-car.h> 2768d724ceSPeter De Schrijver #include <dt-bindings/reset/tegra210-car.h> 28e745f992SPeter De Schrijver #include <linux/iopoll.h> 296b301a05SRhyland Klein 306b301a05SRhyland Klein #include "clk.h" 316b301a05SRhyland Klein #include "clk-id.h" 326b301a05SRhyland Klein 336b301a05SRhyland Klein /* 346b301a05SRhyland Klein * TEGRA210_CAR_BANK_COUNT: the number of peripheral clock register 356b301a05SRhyland Klein * banks present in the Tegra210 CAR IP block. The banks are 366b301a05SRhyland Klein * identified by single letters, e.g.: L, H, U, V, W, X, Y. See 376b301a05SRhyland Klein * periph_regs[] in drivers/clk/tegra/clk.c 386b301a05SRhyland Klein */ 396b301a05SRhyland Klein #define TEGRA210_CAR_BANK_COUNT 7 406b301a05SRhyland Klein 416b301a05SRhyland Klein #define CLK_SOURCE_CSITE 0x1d4 426b301a05SRhyland Klein #define CLK_SOURCE_EMC 0x19c 43bc2e4d29SThierry Reding #define CLK_SOURCE_SOR1 0x410 446b301a05SRhyland Klein 456b301a05SRhyland Klein #define PLLC_BASE 0x80 466b301a05SRhyland Klein #define PLLC_OUT 0x84 476b301a05SRhyland Klein #define PLLC_MISC0 0x88 486b301a05SRhyland Klein #define PLLC_MISC1 0x8c 496b301a05SRhyland Klein #define PLLC_MISC2 0x5d0 506b301a05SRhyland Klein #define PLLC_MISC3 0x5d4 516b301a05SRhyland Klein 526b301a05SRhyland Klein #define PLLC2_BASE 0x4e8 536b301a05SRhyland Klein #define PLLC2_MISC0 0x4ec 546b301a05SRhyland Klein #define PLLC2_MISC1 0x4f0 556b301a05SRhyland Klein #define PLLC2_MISC2 0x4f4 566b301a05SRhyland Klein #define PLLC2_MISC3 0x4f8 576b301a05SRhyland Klein 586b301a05SRhyland Klein #define PLLC3_BASE 0x4fc 596b301a05SRhyland Klein #define PLLC3_MISC0 0x500 606b301a05SRhyland Klein #define PLLC3_MISC1 0x504 616b301a05SRhyland Klein #define PLLC3_MISC2 0x508 626b301a05SRhyland Klein #define PLLC3_MISC3 0x50c 636b301a05SRhyland Klein 646b301a05SRhyland Klein #define PLLM_BASE 0x90 656b301a05SRhyland Klein #define PLLM_MISC1 0x98 66474f2ba2SRhyland Klein #define PLLM_MISC2 0x9c 676b301a05SRhyland Klein #define PLLP_BASE 0xa0 686b301a05SRhyland Klein #define PLLP_MISC0 0xac 696b301a05SRhyland Klein #define PLLP_MISC1 0x680 706b301a05SRhyland Klein #define PLLA_BASE 0xb0 716b301a05SRhyland Klein #define PLLA_MISC0 0xbc 726b301a05SRhyland Klein #define PLLA_MISC1 0xb8 736b301a05SRhyland Klein #define PLLA_MISC2 0x5d8 746b301a05SRhyland Klein #define PLLD_BASE 0xd0 756b301a05SRhyland Klein #define PLLD_MISC0 0xdc 766b301a05SRhyland Klein #define PLLD_MISC1 0xd8 776b301a05SRhyland Klein #define PLLU_BASE 0xc0 786b301a05SRhyland Klein #define PLLU_OUTA 0xc4 796b301a05SRhyland Klein #define PLLU_MISC0 0xcc 806b301a05SRhyland Klein #define PLLU_MISC1 0xc8 816b301a05SRhyland Klein #define PLLX_BASE 0xe0 826b301a05SRhyland Klein #define PLLX_MISC0 0xe4 836b301a05SRhyland Klein #define PLLX_MISC1 0x510 846b301a05SRhyland Klein #define PLLX_MISC2 0x514 856b301a05SRhyland Klein #define PLLX_MISC3 0x518 866b301a05SRhyland Klein #define PLLX_MISC4 0x5f0 876b301a05SRhyland Klein #define PLLX_MISC5 0x5f4 886b301a05SRhyland Klein #define PLLE_BASE 0xe8 896b301a05SRhyland Klein #define PLLE_MISC0 0xec 906b301a05SRhyland Klein #define PLLD2_BASE 0x4b8 916b301a05SRhyland Klein #define PLLD2_MISC0 0x4bc 926b301a05SRhyland Klein #define PLLD2_MISC1 0x570 936b301a05SRhyland Klein #define PLLD2_MISC2 0x574 946b301a05SRhyland Klein #define PLLD2_MISC3 0x578 956b301a05SRhyland Klein #define PLLE_AUX 0x48c 966b301a05SRhyland Klein #define PLLRE_BASE 0x4c4 976b301a05SRhyland Klein #define PLLRE_MISC0 0x4c8 98926655f9SRhyland Klein #define PLLRE_OUT1 0x4cc 996b301a05SRhyland Klein #define PLLDP_BASE 0x590 1006b301a05SRhyland Klein #define PLLDP_MISC 0x594 1016b301a05SRhyland Klein 1026b301a05SRhyland Klein #define PLLC4_BASE 0x5a4 1036b301a05SRhyland Klein #define PLLC4_MISC0 0x5a8 1046b301a05SRhyland Klein #define PLLC4_OUT 0x5e4 1056b301a05SRhyland Klein #define PLLMB_BASE 0x5e8 106474f2ba2SRhyland Klein #define PLLMB_MISC1 0x5ec 1076b301a05SRhyland Klein #define PLLA1_BASE 0x6a4 1086b301a05SRhyland Klein #define PLLA1_MISC0 0x6a8 1096b301a05SRhyland Klein #define PLLA1_MISC1 0x6ac 1106b301a05SRhyland Klein #define PLLA1_MISC2 0x6b0 1116b301a05SRhyland Klein #define PLLA1_MISC3 0x6b4 1126b301a05SRhyland Klein 1136b301a05SRhyland Klein #define PLLU_IDDQ_BIT 31 1146b301a05SRhyland Klein #define PLLCX_IDDQ_BIT 27 1156b301a05SRhyland Klein #define PLLRE_IDDQ_BIT 24 1166b301a05SRhyland Klein #define PLLA_IDDQ_BIT 25 1176b301a05SRhyland Klein #define PLLD_IDDQ_BIT 20 1186b301a05SRhyland Klein #define PLLSS_IDDQ_BIT 18 1196b301a05SRhyland Klein #define PLLM_IDDQ_BIT 5 1206b301a05SRhyland Klein #define PLLMB_IDDQ_BIT 17 1216b301a05SRhyland Klein #define PLLXP_IDDQ_BIT 3 1226b301a05SRhyland Klein 1236b301a05SRhyland Klein #define PLLCX_RESET_BIT 30 1246b301a05SRhyland Klein 1256b301a05SRhyland Klein #define PLL_BASE_LOCK BIT(27) 1266b301a05SRhyland Klein #define PLLCX_BASE_LOCK BIT(26) 1276b301a05SRhyland Klein #define PLLE_MISC_LOCK BIT(11) 1286b301a05SRhyland Klein #define PLLRE_MISC_LOCK BIT(27) 1296b301a05SRhyland Klein 1306b301a05SRhyland Klein #define PLL_MISC_LOCK_ENABLE 18 1316b301a05SRhyland Klein #define PLLC_MISC_LOCK_ENABLE 24 1326b301a05SRhyland Klein #define PLLDU_MISC_LOCK_ENABLE 22 1336b301a05SRhyland Klein #define PLLU_MISC_LOCK_ENABLE 29 1346b301a05SRhyland Klein #define PLLE_MISC_LOCK_ENABLE 9 1356b301a05SRhyland Klein #define PLLRE_MISC_LOCK_ENABLE 30 1366b301a05SRhyland Klein #define PLLSS_MISC_LOCK_ENABLE 30 1376b301a05SRhyland Klein #define PLLP_MISC_LOCK_ENABLE 18 1386b301a05SRhyland Klein #define PLLM_MISC_LOCK_ENABLE 4 1396b301a05SRhyland Klein #define PLLMB_MISC_LOCK_ENABLE 16 1406b301a05SRhyland Klein #define PLLA_MISC_LOCK_ENABLE 28 1416b301a05SRhyland Klein #define PLLU_MISC_LOCK_ENABLE 29 1426b301a05SRhyland Klein #define PLLD_MISC_LOCK_ENABLE 18 1436b301a05SRhyland Klein 1446b301a05SRhyland Klein #define PLLA_SDM_DIN_MASK 0xffff 1456b301a05SRhyland Klein #define PLLA_SDM_EN_MASK BIT(26) 1466b301a05SRhyland Klein 1476b301a05SRhyland Klein #define PLLD_SDM_EN_MASK BIT(16) 1486b301a05SRhyland Klein 1496b301a05SRhyland Klein #define PLLD2_SDM_EN_MASK BIT(31) 150030999feSPeter De Schrijver #define PLLD2_SSC_EN_MASK 0 1516b301a05SRhyland Klein 1526b301a05SRhyland Klein #define PLLDP_SS_CFG 0x598 1536b301a05SRhyland Klein #define PLLDP_SDM_EN_MASK BIT(31) 1546b301a05SRhyland Klein #define PLLDP_SSC_EN_MASK BIT(30) 1556b301a05SRhyland Klein #define PLLDP_SS_CTRL1 0x59c 1566b301a05SRhyland Klein #define PLLDP_SS_CTRL2 0x5a0 1576b301a05SRhyland Klein 1586b301a05SRhyland Klein #define PMC_PLLM_WB0_OVERRIDE 0x1dc 1596b301a05SRhyland Klein #define PMC_PLLM_WB0_OVERRIDE_2 0x2b0 1606b301a05SRhyland Klein 161e745f992SPeter De Schrijver #define UTMIP_PLL_CFG2 0x488 162e745f992SPeter De Schrijver #define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xfff) << 6) 163e745f992SPeter De Schrijver #define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18) 164e745f992SPeter De Schrijver #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN BIT(0) 165e745f992SPeter De Schrijver #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERUP BIT(1) 166e745f992SPeter De Schrijver #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN BIT(2) 167e745f992SPeter De Schrijver #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERUP BIT(3) 168e745f992SPeter De Schrijver #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN BIT(4) 169e745f992SPeter De Schrijver #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERUP BIT(5) 170e745f992SPeter De Schrijver #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERDOWN BIT(24) 171e745f992SPeter De Schrijver #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERUP BIT(25) 172e745f992SPeter De Schrijver 173e745f992SPeter De Schrijver #define UTMIP_PLL_CFG1 0x484 174e745f992SPeter De Schrijver #define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27) 175e745f992SPeter De Schrijver #define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0) 176e745f992SPeter De Schrijver #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP BIT(17) 177e745f992SPeter De Schrijver #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN BIT(16) 178e745f992SPeter De Schrijver #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP BIT(15) 179e745f992SPeter De Schrijver #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN BIT(14) 180e745f992SPeter De Schrijver #define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN BIT(12) 181e745f992SPeter De Schrijver 1823358d2d9SAndrew Bresticker #define SATA_PLL_CFG0 0x490 1833358d2d9SAndrew Bresticker #define SATA_PLL_CFG0_PADPLL_RESET_SWCTL BIT(0) 1843358d2d9SAndrew Bresticker #define SATA_PLL_CFG0_PADPLL_USE_LOCKDET BIT(2) 18559af78d7SPeter De Schrijver #define SATA_PLL_CFG0_SATA_SEQ_IN_SWCTL BIT(4) 18659af78d7SPeter De Schrijver #define SATA_PLL_CFG0_SATA_SEQ_RESET_INPUT_VALUE BIT(5) 18759af78d7SPeter De Schrijver #define SATA_PLL_CFG0_SATA_SEQ_LANE_PD_INPUT_VALUE BIT(6) 18859af78d7SPeter De Schrijver #define SATA_PLL_CFG0_SATA_SEQ_PADPLL_PD_INPUT_VALUE BIT(7) 18959af78d7SPeter De Schrijver 1903358d2d9SAndrew Bresticker #define SATA_PLL_CFG0_PADPLL_SLEEP_IDDQ BIT(13) 1913358d2d9SAndrew Bresticker #define SATA_PLL_CFG0_SEQ_ENABLE BIT(24) 1923358d2d9SAndrew Bresticker 1933358d2d9SAndrew Bresticker #define XUSBIO_PLL_CFG0 0x51c 1943358d2d9SAndrew Bresticker #define XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL BIT(0) 1953358d2d9SAndrew Bresticker #define XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL BIT(2) 1963358d2d9SAndrew Bresticker #define XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET BIT(6) 1973358d2d9SAndrew Bresticker #define XUSBIO_PLL_CFG0_PADPLL_SLEEP_IDDQ BIT(13) 1983358d2d9SAndrew Bresticker #define XUSBIO_PLL_CFG0_SEQ_ENABLE BIT(24) 1993358d2d9SAndrew Bresticker 2006b301a05SRhyland Klein #define UTMIPLL_HW_PWRDN_CFG0 0x52c 2016b301a05SRhyland Klein #define UTMIPLL_HW_PWRDN_CFG0_UTMIPLL_LOCK BIT(31) 2026b301a05SRhyland Klein #define UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE BIT(25) 2036b301a05SRhyland Klein #define UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE BIT(24) 2046b301a05SRhyland Klein #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE BIT(7) 2056b301a05SRhyland Klein #define UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET BIT(6) 2066b301a05SRhyland Klein #define UTMIPLL_HW_PWRDN_CFG0_SEQ_RESET_INPUT_VALUE BIT(5) 2076b301a05SRhyland Klein #define UTMIPLL_HW_PWRDN_CFG0_SEQ_IN_SWCTL BIT(4) 2086b301a05SRhyland Klein #define UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL BIT(2) 2096b301a05SRhyland Klein #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE BIT(1) 2106b301a05SRhyland Klein #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL BIT(0) 2116b301a05SRhyland Klein 2126b301a05SRhyland Klein #define PLLU_HW_PWRDN_CFG0 0x530 2136b301a05SRhyland Klein #define PLLU_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE BIT(28) 2146b301a05SRhyland Klein #define PLLU_HW_PWRDN_CFG0_SEQ_ENABLE BIT(24) 2156b301a05SRhyland Klein #define PLLU_HW_PWRDN_CFG0_USE_SWITCH_DETECT BIT(7) 2166b301a05SRhyland Klein #define PLLU_HW_PWRDN_CFG0_USE_LOCKDET BIT(6) 2176b301a05SRhyland Klein #define PLLU_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL BIT(2) 2186b301a05SRhyland Klein #define PLLU_HW_PWRDN_CFG0_CLK_SWITCH_SWCTL BIT(0) 2196b301a05SRhyland Klein 2206b301a05SRhyland Klein #define XUSB_PLL_CFG0 0x534 2216b301a05SRhyland Klein #define XUSB_PLL_CFG0_UTMIPLL_LOCK_DLY 0x3ff 2226b301a05SRhyland Klein #define XUSB_PLL_CFG0_PLLU_LOCK_DLY_MASK (0x3ff << 14) 2236b301a05SRhyland Klein 2246b301a05SRhyland Klein #define SPARE_REG0 0x55c 2256b301a05SRhyland Klein #define CLK_M_DIVISOR_SHIFT 2 2266b301a05SRhyland Klein #define CLK_M_DIVISOR_MASK 0x3 2276b301a05SRhyland Klein 22868d724ceSPeter De Schrijver #define RST_DFLL_DVCO 0x2f4 22968d724ceSPeter De Schrijver #define DVFS_DFLL_RESET_SHIFT 0 23068d724ceSPeter De Schrijver 23168d724ceSPeter De Schrijver #define CLK_RST_CONTROLLER_RST_DEV_Y_SET 0x2a8 23268d724ceSPeter De Schrijver #define CLK_RST_CONTROLLER_RST_DEV_Y_CLR 0x2ac 23368d724ceSPeter De Schrijver 2346b301a05SRhyland Klein /* 2356b301a05SRhyland Klein * SDM fractional divisor is 16-bit 2's complement signed number within 2366b301a05SRhyland Klein * (-2^12 ... 2^12-1) range. Represented in PLL data structure as unsigned 2376b301a05SRhyland Klein * 16-bit value, with "0" divisor mapped to 0xFFFF. Data "0" is used to 2386b301a05SRhyland Klein * indicate that SDM is disabled. 2396b301a05SRhyland Klein * 2406b301a05SRhyland Klein * Effective ndiv value when SDM is enabled: ndiv + 1/2 + sdm_din/2^13 2416b301a05SRhyland Klein */ 2426b301a05SRhyland Klein #define PLL_SDM_COEFF BIT(13) 2436b301a05SRhyland Klein #define sdin_din_to_data(din) ((u16)((din) ? : 0xFFFFU)) 2446b301a05SRhyland Klein #define sdin_data_to_din(dat) (((dat) == 0xFFFFU) ? 0 : (s16)dat) 245a851ea2bSAlex Frid /* This macro returns ndiv effective scaled to SDM range */ 246a851ea2bSAlex Frid #define sdin_get_n_eff(cfg) ((cfg)->n * PLL_SDM_COEFF + ((cfg)->sdm_data ? \ 247a851ea2bSAlex Frid (PLL_SDM_COEFF/2 + sdin_data_to_din((cfg)->sdm_data)) : 0)) 2486b301a05SRhyland Klein 2496b301a05SRhyland Klein /* Tegra CPU clock and reset control regs */ 2506b301a05SRhyland Klein #define CLK_RST_CONTROLLER_CPU_CMPLX_STATUS 0x470 2516b301a05SRhyland Klein 2526b301a05SRhyland Klein #ifdef CONFIG_PM_SLEEP 2536b301a05SRhyland Klein static struct cpu_clk_suspend_context { 2546b301a05SRhyland Klein u32 clk_csite_src; 2556b301a05SRhyland Klein } tegra210_cpu_clk_sctx; 2566b301a05SRhyland Klein #endif 2576b301a05SRhyland Klein 2586b301a05SRhyland Klein static void __iomem *clk_base; 2596b301a05SRhyland Klein static void __iomem *pmc_base; 2606b301a05SRhyland Klein 2616b301a05SRhyland Klein static unsigned long osc_freq; 2626b301a05SRhyland Klein static unsigned long pll_ref_freq; 2636b301a05SRhyland Klein 2646b301a05SRhyland Klein static DEFINE_SPINLOCK(pll_d_lock); 2656b301a05SRhyland Klein static DEFINE_SPINLOCK(pll_e_lock); 2666b301a05SRhyland Klein static DEFINE_SPINLOCK(pll_re_lock); 2676b301a05SRhyland Klein static DEFINE_SPINLOCK(pll_u_lock); 268bc2e4d29SThierry Reding static DEFINE_SPINLOCK(sor1_lock); 2696b301a05SRhyland Klein static DEFINE_SPINLOCK(emc_lock); 2706b301a05SRhyland Klein 2716b301a05SRhyland Klein /* possible OSC frequencies in Hz */ 2726b301a05SRhyland Klein static unsigned long tegra210_input_freq[] = { 2736b301a05SRhyland Klein [5] = 38400000, 2746b301a05SRhyland Klein [8] = 12000000, 2756b301a05SRhyland Klein }; 2766b301a05SRhyland Klein 2776b301a05SRhyland Klein static const char *mux_pllmcp_clkm[] = { 2784f8d4440SJon Hunter "pll_m", "pll_c", "pll_p", "clk_m", "pll_m_ud", "pll_mb", "pll_mb", 2794f8d4440SJon Hunter "pll_p", 2806b301a05SRhyland Klein }; 2816b301a05SRhyland Klein #define mux_pllmcp_clkm_idx NULL 2826b301a05SRhyland Klein 2836b301a05SRhyland Klein #define PLL_ENABLE (1 << 30) 2846b301a05SRhyland Klein 2856b301a05SRhyland Klein #define PLLCX_MISC1_IDDQ (1 << 27) 2866b301a05SRhyland Klein #define PLLCX_MISC0_RESET (1 << 30) 2876b301a05SRhyland Klein 2886b301a05SRhyland Klein #define PLLCX_MISC0_DEFAULT_VALUE 0x40080000 2896b301a05SRhyland Klein #define PLLCX_MISC0_WRITE_MASK 0x400ffffb 2906b301a05SRhyland Klein #define PLLCX_MISC1_DEFAULT_VALUE 0x08000000 2916b301a05SRhyland Klein #define PLLCX_MISC1_WRITE_MASK 0x08003cff 2926b301a05SRhyland Klein #define PLLCX_MISC2_DEFAULT_VALUE 0x1f720f05 2936b301a05SRhyland Klein #define PLLCX_MISC2_WRITE_MASK 0xffffff17 2946b301a05SRhyland Klein #define PLLCX_MISC3_DEFAULT_VALUE 0x000000c4 2956b301a05SRhyland Klein #define PLLCX_MISC3_WRITE_MASK 0x00ffffff 2966b301a05SRhyland Klein 2976b301a05SRhyland Klein /* PLLA */ 2986b301a05SRhyland Klein #define PLLA_BASE_IDDQ (1 << 25) 2996b301a05SRhyland Klein #define PLLA_BASE_LOCK (1 << 27) 3006b301a05SRhyland Klein 3016b301a05SRhyland Klein #define PLLA_MISC0_LOCK_ENABLE (1 << 28) 3026b301a05SRhyland Klein #define PLLA_MISC0_LOCK_OVERRIDE (1 << 27) 3036b301a05SRhyland Klein 3046b301a05SRhyland Klein #define PLLA_MISC2_EN_SDM (1 << 26) 3056b301a05SRhyland Klein #define PLLA_MISC2_EN_DYNRAMP (1 << 25) 3066b301a05SRhyland Klein 3076b301a05SRhyland Klein #define PLLA_MISC0_DEFAULT_VALUE 0x12000020 3086b301a05SRhyland Klein #define PLLA_MISC0_WRITE_MASK 0x7fffffff 3096b301a05SRhyland Klein #define PLLA_MISC2_DEFAULT_VALUE 0x0 3106b301a05SRhyland Klein #define PLLA_MISC2_WRITE_MASK 0x06ffffff 3116b301a05SRhyland Klein 3126b301a05SRhyland Klein /* PLLD */ 3136b301a05SRhyland Klein #define PLLD_MISC0_EN_SDM (1 << 16) 3146b301a05SRhyland Klein #define PLLD_MISC0_LOCK_OVERRIDE (1 << 17) 3156b301a05SRhyland Klein #define PLLD_MISC0_LOCK_ENABLE (1 << 18) 3166b301a05SRhyland Klein #define PLLD_MISC0_IDDQ (1 << 20) 3176b301a05SRhyland Klein #define PLLD_MISC0_DSI_CLKENABLE (1 << 21) 3186b301a05SRhyland Klein 3196b301a05SRhyland Klein #define PLLD_MISC0_DEFAULT_VALUE 0x00140000 3206b301a05SRhyland Klein #define PLLD_MISC0_WRITE_MASK 0x3ff7ffff 3216b301a05SRhyland Klein #define PLLD_MISC1_DEFAULT_VALUE 0x20 3226b301a05SRhyland Klein #define PLLD_MISC1_WRITE_MASK 0x00ffffff 3236b301a05SRhyland Klein 3246b301a05SRhyland Klein /* PLLD2 and PLLDP and PLLC4 */ 3256b301a05SRhyland Klein #define PLLDSS_BASE_LOCK (1 << 27) 3266b301a05SRhyland Klein #define PLLDSS_BASE_LOCK_OVERRIDE (1 << 24) 3276b301a05SRhyland Klein #define PLLDSS_BASE_IDDQ (1 << 18) 3286b301a05SRhyland Klein #define PLLDSS_BASE_REF_SEL_SHIFT 25 3296b301a05SRhyland Klein #define PLLDSS_BASE_REF_SEL_MASK (0x3 << PLLDSS_BASE_REF_SEL_SHIFT) 3306b301a05SRhyland Klein 3316b301a05SRhyland Klein #define PLLDSS_MISC0_LOCK_ENABLE (1 << 30) 3326b301a05SRhyland Klein 3336b301a05SRhyland Klein #define PLLDSS_MISC1_CFG_EN_SDM (1 << 31) 3346b301a05SRhyland Klein #define PLLDSS_MISC1_CFG_EN_SSC (1 << 30) 3356b301a05SRhyland Klein 3366b301a05SRhyland Klein #define PLLD2_MISC0_DEFAULT_VALUE 0x40000020 3376b301a05SRhyland Klein #define PLLD2_MISC1_CFG_DEFAULT_VALUE 0x10000000 3386b301a05SRhyland Klein #define PLLD2_MISC2_CTRL1_DEFAULT_VALUE 0x0 3396b301a05SRhyland Klein #define PLLD2_MISC3_CTRL2_DEFAULT_VALUE 0x0 3406b301a05SRhyland Klein 3416b301a05SRhyland Klein #define PLLDP_MISC0_DEFAULT_VALUE 0x40000020 3426b301a05SRhyland Klein #define PLLDP_MISC1_CFG_DEFAULT_VALUE 0xc0000000 3436b301a05SRhyland Klein #define PLLDP_MISC2_CTRL1_DEFAULT_VALUE 0xf400f0da 3446b301a05SRhyland Klein #define PLLDP_MISC3_CTRL2_DEFAULT_VALUE 0x2004f400 3456b301a05SRhyland Klein 3466b301a05SRhyland Klein #define PLLDSS_MISC0_WRITE_MASK 0x47ffffff 3476b301a05SRhyland Klein #define PLLDSS_MISC1_CFG_WRITE_MASK 0xf8000000 3486b301a05SRhyland Klein #define PLLDSS_MISC2_CTRL1_WRITE_MASK 0xffffffff 3496b301a05SRhyland Klein #define PLLDSS_MISC3_CTRL2_WRITE_MASK 0xffffffff 3506b301a05SRhyland Klein 3516b301a05SRhyland Klein #define PLLC4_MISC0_DEFAULT_VALUE 0x40000000 3526b301a05SRhyland Klein 3536b301a05SRhyland Klein /* PLLRE */ 3546b301a05SRhyland Klein #define PLLRE_MISC0_LOCK_ENABLE (1 << 30) 3556b301a05SRhyland Klein #define PLLRE_MISC0_LOCK_OVERRIDE (1 << 29) 3566b301a05SRhyland Klein #define PLLRE_MISC0_LOCK (1 << 27) 3576b301a05SRhyland Klein #define PLLRE_MISC0_IDDQ (1 << 24) 3586b301a05SRhyland Klein 3596b301a05SRhyland Klein #define PLLRE_BASE_DEFAULT_VALUE 0x0 3606b301a05SRhyland Klein #define PLLRE_MISC0_DEFAULT_VALUE 0x41000000 3616b301a05SRhyland Klein 3626b301a05SRhyland Klein #define PLLRE_BASE_DEFAULT_MASK 0x1c000000 3636b301a05SRhyland Klein #define PLLRE_MISC0_WRITE_MASK 0x67ffffff 3646b301a05SRhyland Klein 3656b301a05SRhyland Klein /* PLLX */ 3666b301a05SRhyland Klein #define PLLX_USE_DYN_RAMP 1 3676b301a05SRhyland Klein #define PLLX_BASE_LOCK (1 << 27) 3686b301a05SRhyland Klein 3696b301a05SRhyland Klein #define PLLX_MISC0_FO_G_DISABLE (0x1 << 28) 3706b301a05SRhyland Klein #define PLLX_MISC0_LOCK_ENABLE (0x1 << 18) 3716b301a05SRhyland Klein 3726b301a05SRhyland Klein #define PLLX_MISC2_DYNRAMP_STEPB_SHIFT 24 3736b301a05SRhyland Klein #define PLLX_MISC2_DYNRAMP_STEPB_MASK (0xFF << PLLX_MISC2_DYNRAMP_STEPB_SHIFT) 3746b301a05SRhyland Klein #define PLLX_MISC2_DYNRAMP_STEPA_SHIFT 16 3756b301a05SRhyland Klein #define PLLX_MISC2_DYNRAMP_STEPA_MASK (0xFF << PLLX_MISC2_DYNRAMP_STEPA_SHIFT) 3766b301a05SRhyland Klein #define PLLX_MISC2_NDIV_NEW_SHIFT 8 3776b301a05SRhyland Klein #define PLLX_MISC2_NDIV_NEW_MASK (0xFF << PLLX_MISC2_NDIV_NEW_SHIFT) 3786b301a05SRhyland Klein #define PLLX_MISC2_LOCK_OVERRIDE (0x1 << 4) 3796b301a05SRhyland Klein #define PLLX_MISC2_DYNRAMP_DONE (0x1 << 2) 3806b301a05SRhyland Klein #define PLLX_MISC2_EN_DYNRAMP (0x1 << 0) 3816b301a05SRhyland Klein 3826b301a05SRhyland Klein #define PLLX_MISC3_IDDQ (0x1 << 3) 3836b301a05SRhyland Klein 3846b301a05SRhyland Klein #define PLLX_MISC0_DEFAULT_VALUE PLLX_MISC0_LOCK_ENABLE 3856b301a05SRhyland Klein #define PLLX_MISC0_WRITE_MASK 0x10c40000 3866b301a05SRhyland Klein #define PLLX_MISC1_DEFAULT_VALUE 0x20 3876b301a05SRhyland Klein #define PLLX_MISC1_WRITE_MASK 0x00ffffff 3886b301a05SRhyland Klein #define PLLX_MISC2_DEFAULT_VALUE 0x0 3896b301a05SRhyland Klein #define PLLX_MISC2_WRITE_MASK 0xffffff11 3906b301a05SRhyland Klein #define PLLX_MISC3_DEFAULT_VALUE PLLX_MISC3_IDDQ 3916b301a05SRhyland Klein #define PLLX_MISC3_WRITE_MASK 0x01ff0f0f 3926b301a05SRhyland Klein #define PLLX_MISC4_DEFAULT_VALUE 0x0 3936b301a05SRhyland Klein #define PLLX_MISC4_WRITE_MASK 0x8000ffff 3946b301a05SRhyland Klein #define PLLX_MISC5_DEFAULT_VALUE 0x0 3956b301a05SRhyland Klein #define PLLX_MISC5_WRITE_MASK 0x0000ffff 3966b301a05SRhyland Klein 3976b301a05SRhyland Klein #define PLLX_HW_CTRL_CFG 0x548 3986b301a05SRhyland Klein #define PLLX_HW_CTRL_CFG_SWCTRL (0x1 << 0) 3996b301a05SRhyland Klein 4006b301a05SRhyland Klein /* PLLMB */ 4016b301a05SRhyland Klein #define PLLMB_BASE_LOCK (1 << 27) 4026b301a05SRhyland Klein 403474f2ba2SRhyland Klein #define PLLMB_MISC1_LOCK_OVERRIDE (1 << 18) 404474f2ba2SRhyland Klein #define PLLMB_MISC1_IDDQ (1 << 17) 405474f2ba2SRhyland Klein #define PLLMB_MISC1_LOCK_ENABLE (1 << 16) 4066b301a05SRhyland Klein 407474f2ba2SRhyland Klein #define PLLMB_MISC1_DEFAULT_VALUE 0x00030000 408474f2ba2SRhyland Klein #define PLLMB_MISC1_WRITE_MASK 0x0007ffff 4096b301a05SRhyland Klein 4106b301a05SRhyland Klein /* PLLP */ 4116b301a05SRhyland Klein #define PLLP_BASE_OVERRIDE (1 << 28) 4126b301a05SRhyland Klein #define PLLP_BASE_LOCK (1 << 27) 4136b301a05SRhyland Klein 4146b301a05SRhyland Klein #define PLLP_MISC0_LOCK_ENABLE (1 << 18) 4156b301a05SRhyland Klein #define PLLP_MISC0_LOCK_OVERRIDE (1 << 17) 4166b301a05SRhyland Klein #define PLLP_MISC0_IDDQ (1 << 3) 4176b301a05SRhyland Klein 4186b301a05SRhyland Klein #define PLLP_MISC1_HSIO_EN_SHIFT 29 4196b301a05SRhyland Klein #define PLLP_MISC1_HSIO_EN (1 << PLLP_MISC1_HSIO_EN_SHIFT) 4206b301a05SRhyland Klein #define PLLP_MISC1_XUSB_EN_SHIFT 28 4216b301a05SRhyland Klein #define PLLP_MISC1_XUSB_EN (1 << PLLP_MISC1_XUSB_EN_SHIFT) 4226b301a05SRhyland Klein 4236b301a05SRhyland Klein #define PLLP_MISC0_DEFAULT_VALUE 0x00040008 4246b301a05SRhyland Klein #define PLLP_MISC1_DEFAULT_VALUE 0x0 4256b301a05SRhyland Klein 4266b301a05SRhyland Klein #define PLLP_MISC0_WRITE_MASK 0xdc6000f 4276b301a05SRhyland Klein #define PLLP_MISC1_WRITE_MASK 0x70ffffff 4286b301a05SRhyland Klein 4296b301a05SRhyland Klein /* PLLU */ 4306b301a05SRhyland Klein #define PLLU_BASE_LOCK (1 << 27) 4316b301a05SRhyland Klein #define PLLU_BASE_OVERRIDE (1 << 24) 4326b301a05SRhyland Klein #define PLLU_BASE_CLKENABLE_USB (1 << 21) 4336b301a05SRhyland Klein #define PLLU_BASE_CLKENABLE_HSIC (1 << 22) 4346b301a05SRhyland Klein #define PLLU_BASE_CLKENABLE_ICUSB (1 << 23) 4356b301a05SRhyland Klein #define PLLU_BASE_CLKENABLE_48M (1 << 25) 4366b301a05SRhyland Klein #define PLLU_BASE_CLKENABLE_ALL (PLLU_BASE_CLKENABLE_USB |\ 4376b301a05SRhyland Klein PLLU_BASE_CLKENABLE_HSIC |\ 4386b301a05SRhyland Klein PLLU_BASE_CLKENABLE_ICUSB |\ 4396b301a05SRhyland Klein PLLU_BASE_CLKENABLE_48M) 4406b301a05SRhyland Klein 4416b301a05SRhyland Klein #define PLLU_MISC0_IDDQ (1 << 31) 4426b301a05SRhyland Klein #define PLLU_MISC0_LOCK_ENABLE (1 << 29) 4436b301a05SRhyland Klein #define PLLU_MISC1_LOCK_OVERRIDE (1 << 0) 4446b301a05SRhyland Klein 4456b301a05SRhyland Klein #define PLLU_MISC0_DEFAULT_VALUE 0xa0000000 4466b301a05SRhyland Klein #define PLLU_MISC1_DEFAULT_VALUE 0x0 4476b301a05SRhyland Klein 4486b301a05SRhyland Klein #define PLLU_MISC0_WRITE_MASK 0xbfffffff 4496b301a05SRhyland Klein #define PLLU_MISC1_WRITE_MASK 0x00000007 4506b301a05SRhyland Klein 4513358d2d9SAndrew Bresticker void tegra210_xusb_pll_hw_control_enable(void) 4523358d2d9SAndrew Bresticker { 4533358d2d9SAndrew Bresticker u32 val; 4543358d2d9SAndrew Bresticker 4553358d2d9SAndrew Bresticker val = readl_relaxed(clk_base + XUSBIO_PLL_CFG0); 4563358d2d9SAndrew Bresticker val &= ~(XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL | 4573358d2d9SAndrew Bresticker XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL); 4583358d2d9SAndrew Bresticker val |= XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET | 4593358d2d9SAndrew Bresticker XUSBIO_PLL_CFG0_PADPLL_SLEEP_IDDQ; 4603358d2d9SAndrew Bresticker writel_relaxed(val, clk_base + XUSBIO_PLL_CFG0); 4613358d2d9SAndrew Bresticker } 4623358d2d9SAndrew Bresticker EXPORT_SYMBOL_GPL(tegra210_xusb_pll_hw_control_enable); 4633358d2d9SAndrew Bresticker 4643358d2d9SAndrew Bresticker void tegra210_xusb_pll_hw_sequence_start(void) 4653358d2d9SAndrew Bresticker { 4663358d2d9SAndrew Bresticker u32 val; 4673358d2d9SAndrew Bresticker 4683358d2d9SAndrew Bresticker val = readl_relaxed(clk_base + XUSBIO_PLL_CFG0); 4693358d2d9SAndrew Bresticker val |= XUSBIO_PLL_CFG0_SEQ_ENABLE; 4703358d2d9SAndrew Bresticker writel_relaxed(val, clk_base + XUSBIO_PLL_CFG0); 4713358d2d9SAndrew Bresticker } 4723358d2d9SAndrew Bresticker EXPORT_SYMBOL_GPL(tegra210_xusb_pll_hw_sequence_start); 4733358d2d9SAndrew Bresticker 4743358d2d9SAndrew Bresticker void tegra210_sata_pll_hw_control_enable(void) 4753358d2d9SAndrew Bresticker { 4763358d2d9SAndrew Bresticker u32 val; 4773358d2d9SAndrew Bresticker 4783358d2d9SAndrew Bresticker val = readl_relaxed(clk_base + SATA_PLL_CFG0); 4793358d2d9SAndrew Bresticker val &= ~SATA_PLL_CFG0_PADPLL_RESET_SWCTL; 4803358d2d9SAndrew Bresticker val |= SATA_PLL_CFG0_PADPLL_USE_LOCKDET | 4813358d2d9SAndrew Bresticker SATA_PLL_CFG0_PADPLL_SLEEP_IDDQ; 4823358d2d9SAndrew Bresticker writel_relaxed(val, clk_base + SATA_PLL_CFG0); 4833358d2d9SAndrew Bresticker } 4843358d2d9SAndrew Bresticker EXPORT_SYMBOL_GPL(tegra210_sata_pll_hw_control_enable); 4853358d2d9SAndrew Bresticker 4863358d2d9SAndrew Bresticker void tegra210_sata_pll_hw_sequence_start(void) 4873358d2d9SAndrew Bresticker { 4883358d2d9SAndrew Bresticker u32 val; 4893358d2d9SAndrew Bresticker 4903358d2d9SAndrew Bresticker val = readl_relaxed(clk_base + SATA_PLL_CFG0); 4913358d2d9SAndrew Bresticker val |= SATA_PLL_CFG0_SEQ_ENABLE; 4923358d2d9SAndrew Bresticker writel_relaxed(val, clk_base + SATA_PLL_CFG0); 4933358d2d9SAndrew Bresticker } 4943358d2d9SAndrew Bresticker EXPORT_SYMBOL_GPL(tegra210_sata_pll_hw_sequence_start); 4953358d2d9SAndrew Bresticker 49659af78d7SPeter De Schrijver void tegra210_set_sata_pll_seq_sw(bool state) 49759af78d7SPeter De Schrijver { 49859af78d7SPeter De Schrijver u32 val; 49959af78d7SPeter De Schrijver 50059af78d7SPeter De Schrijver val = readl_relaxed(clk_base + SATA_PLL_CFG0); 50159af78d7SPeter De Schrijver if (state) { 50259af78d7SPeter De Schrijver val |= SATA_PLL_CFG0_SATA_SEQ_IN_SWCTL; 50359af78d7SPeter De Schrijver val |= SATA_PLL_CFG0_SATA_SEQ_RESET_INPUT_VALUE; 50459af78d7SPeter De Schrijver val |= SATA_PLL_CFG0_SATA_SEQ_LANE_PD_INPUT_VALUE; 50559af78d7SPeter De Schrijver val |= SATA_PLL_CFG0_SATA_SEQ_PADPLL_PD_INPUT_VALUE; 50659af78d7SPeter De Schrijver } else { 50759af78d7SPeter De Schrijver val &= ~SATA_PLL_CFG0_SATA_SEQ_IN_SWCTL; 50859af78d7SPeter De Schrijver val &= ~SATA_PLL_CFG0_SATA_SEQ_RESET_INPUT_VALUE; 50959af78d7SPeter De Schrijver val &= ~SATA_PLL_CFG0_SATA_SEQ_LANE_PD_INPUT_VALUE; 51059af78d7SPeter De Schrijver val &= ~SATA_PLL_CFG0_SATA_SEQ_PADPLL_PD_INPUT_VALUE; 51159af78d7SPeter De Schrijver } 51259af78d7SPeter De Schrijver writel_relaxed(val, clk_base + SATA_PLL_CFG0); 51359af78d7SPeter De Schrijver } 51459af78d7SPeter De Schrijver EXPORT_SYMBOL_GPL(tegra210_set_sata_pll_seq_sw); 51559af78d7SPeter De Schrijver 5166b301a05SRhyland Klein static inline void _pll_misc_chk_default(void __iomem *base, 5176b301a05SRhyland Klein struct tegra_clk_pll_params *params, 5186b301a05SRhyland Klein u8 misc_num, u32 default_val, u32 mask) 5196b301a05SRhyland Klein { 5206b301a05SRhyland Klein u32 boot_val = readl_relaxed(base + params->ext_misc_reg[misc_num]); 5216b301a05SRhyland Klein 5226b301a05SRhyland Klein boot_val &= mask; 5236b301a05SRhyland Klein default_val &= mask; 5246b301a05SRhyland Klein if (boot_val != default_val) { 5256b301a05SRhyland Klein pr_warn("boot misc%d 0x%x: expected 0x%x\n", 5266b301a05SRhyland Klein misc_num, boot_val, default_val); 5276b301a05SRhyland Klein pr_warn(" (comparison mask = 0x%x)\n", mask); 5286b301a05SRhyland Klein params->defaults_set = false; 5296b301a05SRhyland Klein } 5306b301a05SRhyland Klein } 5316b301a05SRhyland Klein 5326b301a05SRhyland Klein /* 5336b301a05SRhyland Klein * PLLCX: PLLC, PLLC2, PLLC3, PLLA1 5346b301a05SRhyland Klein * Hybrid PLLs with dynamic ramp. Dynamic ramp is allowed for any transition 5356b301a05SRhyland Klein * that changes NDIV only, while PLL is already locked. 5366b301a05SRhyland Klein */ 5376b301a05SRhyland Klein static void pllcx_check_defaults(struct tegra_clk_pll_params *params) 5386b301a05SRhyland Klein { 5396b301a05SRhyland Klein u32 default_val; 5406b301a05SRhyland Klein 5416b301a05SRhyland Klein default_val = PLLCX_MISC0_DEFAULT_VALUE & (~PLLCX_MISC0_RESET); 5426b301a05SRhyland Klein _pll_misc_chk_default(clk_base, params, 0, default_val, 5436b301a05SRhyland Klein PLLCX_MISC0_WRITE_MASK); 5446b301a05SRhyland Klein 5456b301a05SRhyland Klein default_val = PLLCX_MISC1_DEFAULT_VALUE & (~PLLCX_MISC1_IDDQ); 5466b301a05SRhyland Klein _pll_misc_chk_default(clk_base, params, 1, default_val, 5476b301a05SRhyland Klein PLLCX_MISC1_WRITE_MASK); 5486b301a05SRhyland Klein 5496b301a05SRhyland Klein default_val = PLLCX_MISC2_DEFAULT_VALUE; 5506b301a05SRhyland Klein _pll_misc_chk_default(clk_base, params, 2, default_val, 5516b301a05SRhyland Klein PLLCX_MISC2_WRITE_MASK); 5526b301a05SRhyland Klein 5536b301a05SRhyland Klein default_val = PLLCX_MISC3_DEFAULT_VALUE; 5546b301a05SRhyland Klein _pll_misc_chk_default(clk_base, params, 3, default_val, 5556b301a05SRhyland Klein PLLCX_MISC3_WRITE_MASK); 5566b301a05SRhyland Klein } 5576b301a05SRhyland Klein 558fd360e20SJon Hunter static void tegra210_pllcx_set_defaults(const char *name, 559fd360e20SJon Hunter struct tegra_clk_pll *pllcx) 5606b301a05SRhyland Klein { 5616b301a05SRhyland Klein pllcx->params->defaults_set = true; 5626b301a05SRhyland Klein 5631116d5a7SJon Hunter if (readl_relaxed(clk_base + pllcx->params->base_reg) & PLL_ENABLE) { 5646b301a05SRhyland Klein /* PLL is ON: only check if defaults already set */ 5656b301a05SRhyland Klein pllcx_check_defaults(pllcx->params); 5661116d5a7SJon Hunter if (!pllcx->params->defaults_set) 5676b301a05SRhyland Klein pr_warn("%s already enabled. Postponing set full defaults\n", 5686b301a05SRhyland Klein name); 5696b301a05SRhyland Klein return; 5706b301a05SRhyland Klein } 5716b301a05SRhyland Klein 5726b301a05SRhyland Klein /* Defaults assert PLL reset, and set IDDQ */ 5736b301a05SRhyland Klein writel_relaxed(PLLCX_MISC0_DEFAULT_VALUE, 5746b301a05SRhyland Klein clk_base + pllcx->params->ext_misc_reg[0]); 5756b301a05SRhyland Klein writel_relaxed(PLLCX_MISC1_DEFAULT_VALUE, 5766b301a05SRhyland Klein clk_base + pllcx->params->ext_misc_reg[1]); 5776b301a05SRhyland Klein writel_relaxed(PLLCX_MISC2_DEFAULT_VALUE, 5786b301a05SRhyland Klein clk_base + pllcx->params->ext_misc_reg[2]); 5796b301a05SRhyland Klein writel_relaxed(PLLCX_MISC3_DEFAULT_VALUE, 5806b301a05SRhyland Klein clk_base + pllcx->params->ext_misc_reg[3]); 5816b301a05SRhyland Klein udelay(1); 5826b301a05SRhyland Klein } 5836b301a05SRhyland Klein 584fd360e20SJon Hunter static void _pllc_set_defaults(struct tegra_clk_pll *pllcx) 5856b301a05SRhyland Klein { 5866b301a05SRhyland Klein tegra210_pllcx_set_defaults("PLL_C", pllcx); 5876b301a05SRhyland Klein } 5886b301a05SRhyland Klein 589fd360e20SJon Hunter static void _pllc2_set_defaults(struct tegra_clk_pll *pllcx) 5906b301a05SRhyland Klein { 5916b301a05SRhyland Klein tegra210_pllcx_set_defaults("PLL_C2", pllcx); 5926b301a05SRhyland Klein } 5936b301a05SRhyland Klein 594fd360e20SJon Hunter static void _pllc3_set_defaults(struct tegra_clk_pll *pllcx) 5956b301a05SRhyland Klein { 5966b301a05SRhyland Klein tegra210_pllcx_set_defaults("PLL_C3", pllcx); 5976b301a05SRhyland Klein } 5986b301a05SRhyland Klein 599fd360e20SJon Hunter static void _plla1_set_defaults(struct tegra_clk_pll *pllcx) 6006b301a05SRhyland Klein { 6016b301a05SRhyland Klein tegra210_pllcx_set_defaults("PLL_A1", pllcx); 6026b301a05SRhyland Klein } 6036b301a05SRhyland Klein 6046b301a05SRhyland Klein /* 6056b301a05SRhyland Klein * PLLA 6066b301a05SRhyland Klein * PLL with dynamic ramp and fractional SDM. Dynamic ramp is not used. 6076b301a05SRhyland Klein * Fractional SDM is allowed to provide exact audio rates. 6086b301a05SRhyland Klein */ 609fd360e20SJon Hunter static void tegra210_plla_set_defaults(struct tegra_clk_pll *plla) 6106b301a05SRhyland Klein { 6116b301a05SRhyland Klein u32 mask; 6126b301a05SRhyland Klein u32 val = readl_relaxed(clk_base + plla->params->base_reg); 6136b301a05SRhyland Klein 6146b301a05SRhyland Klein plla->params->defaults_set = true; 6156b301a05SRhyland Klein 6166b301a05SRhyland Klein if (val & PLL_ENABLE) { 6176b301a05SRhyland Klein /* 6186b301a05SRhyland Klein * PLL is ON: check if defaults already set, then set those 6196b301a05SRhyland Klein * that can be updated in flight. 6206b301a05SRhyland Klein */ 6216b301a05SRhyland Klein if (val & PLLA_BASE_IDDQ) { 6226b301a05SRhyland Klein pr_warn("PLL_A boot enabled with IDDQ set\n"); 6236b301a05SRhyland Klein plla->params->defaults_set = false; 6246b301a05SRhyland Klein } 6256b301a05SRhyland Klein 6266b301a05SRhyland Klein pr_warn("PLL_A already enabled. Postponing set full defaults\n"); 6276b301a05SRhyland Klein 6286b301a05SRhyland Klein val = PLLA_MISC0_DEFAULT_VALUE; /* ignore lock enable */ 6296b301a05SRhyland Klein mask = PLLA_MISC0_LOCK_ENABLE | PLLA_MISC0_LOCK_OVERRIDE; 6306b301a05SRhyland Klein _pll_misc_chk_default(clk_base, plla->params, 0, val, 6316b301a05SRhyland Klein ~mask & PLLA_MISC0_WRITE_MASK); 6326b301a05SRhyland Klein 6336b301a05SRhyland Klein val = PLLA_MISC2_DEFAULT_VALUE; /* ignore all but control bit */ 6346b301a05SRhyland Klein _pll_misc_chk_default(clk_base, plla->params, 2, val, 6356b301a05SRhyland Klein PLLA_MISC2_EN_DYNRAMP); 6366b301a05SRhyland Klein 6376b301a05SRhyland Klein /* Enable lock detect */ 6386b301a05SRhyland Klein val = readl_relaxed(clk_base + plla->params->ext_misc_reg[0]); 6396b301a05SRhyland Klein val &= ~mask; 6406b301a05SRhyland Klein val |= PLLA_MISC0_DEFAULT_VALUE & mask; 6416b301a05SRhyland Klein writel_relaxed(val, clk_base + plla->params->ext_misc_reg[0]); 6426b301a05SRhyland Klein udelay(1); 6436b301a05SRhyland Klein 6446b301a05SRhyland Klein return; 6456b301a05SRhyland Klein } 6466b301a05SRhyland Klein 6476b301a05SRhyland Klein /* set IDDQ, enable lock detect, disable dynamic ramp and SDM */ 6486b301a05SRhyland Klein val |= PLLA_BASE_IDDQ; 6496b301a05SRhyland Klein writel_relaxed(val, clk_base + plla->params->base_reg); 6506b301a05SRhyland Klein writel_relaxed(PLLA_MISC0_DEFAULT_VALUE, 6516b301a05SRhyland Klein clk_base + plla->params->ext_misc_reg[0]); 6526b301a05SRhyland Klein writel_relaxed(PLLA_MISC2_DEFAULT_VALUE, 6536b301a05SRhyland Klein clk_base + plla->params->ext_misc_reg[2]); 6546b301a05SRhyland Klein udelay(1); 6556b301a05SRhyland Klein } 6566b301a05SRhyland Klein 6576b301a05SRhyland Klein /* 6586b301a05SRhyland Klein * PLLD 6596b301a05SRhyland Klein * PLL with fractional SDM. 6606b301a05SRhyland Klein */ 661fd360e20SJon Hunter static void tegra210_plld_set_defaults(struct tegra_clk_pll *plld) 6626b301a05SRhyland Klein { 6636b301a05SRhyland Klein u32 val; 6646b301a05SRhyland Klein u32 mask = 0xffff; 6656b301a05SRhyland Klein 6666b301a05SRhyland Klein plld->params->defaults_set = true; 6676b301a05SRhyland Klein 6686b301a05SRhyland Klein if (readl_relaxed(clk_base + plld->params->base_reg) & 6696b301a05SRhyland Klein PLL_ENABLE) { 6706b301a05SRhyland Klein 6716b301a05SRhyland Klein /* 6726b301a05SRhyland Klein * PLL is ON: check if defaults already set, then set those 6736b301a05SRhyland Klein * that can be updated in flight. 6746b301a05SRhyland Klein */ 6756b301a05SRhyland Klein val = PLLD_MISC1_DEFAULT_VALUE; 6766b301a05SRhyland Klein _pll_misc_chk_default(clk_base, plld->params, 1, 6776b301a05SRhyland Klein val, PLLD_MISC1_WRITE_MASK); 6786b301a05SRhyland Klein 6796b301a05SRhyland Klein /* ignore lock, DSI and SDM controls, make sure IDDQ not set */ 6806b301a05SRhyland Klein val = PLLD_MISC0_DEFAULT_VALUE & (~PLLD_MISC0_IDDQ); 6816b301a05SRhyland Klein mask |= PLLD_MISC0_DSI_CLKENABLE | PLLD_MISC0_LOCK_ENABLE | 6826b301a05SRhyland Klein PLLD_MISC0_LOCK_OVERRIDE | PLLD_MISC0_EN_SDM; 6836b301a05SRhyland Klein _pll_misc_chk_default(clk_base, plld->params, 0, val, 6846b301a05SRhyland Klein ~mask & PLLD_MISC0_WRITE_MASK); 6856b301a05SRhyland Klein 6868dce89a1SPeter De Schrijver if (!plld->params->defaults_set) 6878dce89a1SPeter De Schrijver pr_warn("PLL_D already enabled. Postponing set full defaults\n"); 6888dce89a1SPeter De Schrijver 6896b301a05SRhyland Klein /* Enable lock detect */ 6906b301a05SRhyland Klein mask = PLLD_MISC0_LOCK_ENABLE | PLLD_MISC0_LOCK_OVERRIDE; 6916b301a05SRhyland Klein val = readl_relaxed(clk_base + plld->params->ext_misc_reg[0]); 6926b301a05SRhyland Klein val &= ~mask; 6936b301a05SRhyland Klein val |= PLLD_MISC0_DEFAULT_VALUE & mask; 6946b301a05SRhyland Klein writel_relaxed(val, clk_base + plld->params->ext_misc_reg[0]); 6956b301a05SRhyland Klein udelay(1); 6966b301a05SRhyland Klein 6976b301a05SRhyland Klein return; 6986b301a05SRhyland Klein } 6996b301a05SRhyland Klein 7006b301a05SRhyland Klein val = readl_relaxed(clk_base + plld->params->ext_misc_reg[0]); 7016b301a05SRhyland Klein val &= PLLD_MISC0_DSI_CLKENABLE; 7026b301a05SRhyland Klein val |= PLLD_MISC0_DEFAULT_VALUE; 7036b301a05SRhyland Klein /* set IDDQ, enable lock detect, disable SDM */ 7046b301a05SRhyland Klein writel_relaxed(val, clk_base + plld->params->ext_misc_reg[0]); 7056b301a05SRhyland Klein writel_relaxed(PLLD_MISC1_DEFAULT_VALUE, clk_base + 7066b301a05SRhyland Klein plld->params->ext_misc_reg[1]); 7076b301a05SRhyland Klein udelay(1); 7086b301a05SRhyland Klein } 7096b301a05SRhyland Klein 7106b301a05SRhyland Klein /* 7116b301a05SRhyland Klein * PLLD2, PLLDP 7126b301a05SRhyland Klein * PLL with fractional SDM and Spread Spectrum (SDM is a must if SSC is used). 7136b301a05SRhyland Klein */ 7146b301a05SRhyland Klein static void plldss_defaults(const char *pll_name, struct tegra_clk_pll *plldss, 7156b301a05SRhyland Klein u32 misc0_val, u32 misc1_val, u32 misc2_val, u32 misc3_val) 7166b301a05SRhyland Klein { 7176b301a05SRhyland Klein u32 default_val; 7186b301a05SRhyland Klein u32 val = readl_relaxed(clk_base + plldss->params->base_reg); 7196b301a05SRhyland Klein 7206b301a05SRhyland Klein plldss->params->defaults_set = true; 7216b301a05SRhyland Klein 7226b301a05SRhyland Klein if (val & PLL_ENABLE) { 7236b301a05SRhyland Klein 7246b301a05SRhyland Klein /* 7256b301a05SRhyland Klein * PLL is ON: check if defaults already set, then set those 7266b301a05SRhyland Klein * that can be updated in flight. 7276b301a05SRhyland Klein */ 7286b301a05SRhyland Klein if (val & PLLDSS_BASE_IDDQ) { 7296b301a05SRhyland Klein pr_warn("plldss boot enabled with IDDQ set\n"); 7306b301a05SRhyland Klein plldss->params->defaults_set = false; 7316b301a05SRhyland Klein } 7326b301a05SRhyland Klein 7336b301a05SRhyland Klein /* ignore lock enable */ 7346b301a05SRhyland Klein default_val = misc0_val; 7356b301a05SRhyland Klein _pll_misc_chk_default(clk_base, plldss->params, 0, default_val, 7366b301a05SRhyland Klein PLLDSS_MISC0_WRITE_MASK & 7376b301a05SRhyland Klein (~PLLDSS_MISC0_LOCK_ENABLE)); 7386b301a05SRhyland Klein 7396b301a05SRhyland Klein /* 7406b301a05SRhyland Klein * If SSC is used, check all settings, otherwise just confirm 7416b301a05SRhyland Klein * that SSC is not used on boot as well. Do nothing when using 7426b301a05SRhyland Klein * this function for PLLC4 that has only MISC0. 7436b301a05SRhyland Klein */ 7446b301a05SRhyland Klein if (plldss->params->ssc_ctrl_en_mask) { 7456b301a05SRhyland Klein default_val = misc1_val; 7466b301a05SRhyland Klein _pll_misc_chk_default(clk_base, plldss->params, 1, 7476b301a05SRhyland Klein default_val, PLLDSS_MISC1_CFG_WRITE_MASK); 7486b301a05SRhyland Klein default_val = misc2_val; 7496b301a05SRhyland Klein _pll_misc_chk_default(clk_base, plldss->params, 2, 7506b301a05SRhyland Klein default_val, PLLDSS_MISC2_CTRL1_WRITE_MASK); 7516b301a05SRhyland Klein default_val = misc3_val; 7526b301a05SRhyland Klein _pll_misc_chk_default(clk_base, plldss->params, 3, 7536b301a05SRhyland Klein default_val, PLLDSS_MISC3_CTRL2_WRITE_MASK); 7546b301a05SRhyland Klein } else if (plldss->params->ext_misc_reg[1]) { 7556b301a05SRhyland Klein default_val = misc1_val; 7566b301a05SRhyland Klein _pll_misc_chk_default(clk_base, plldss->params, 1, 7576b301a05SRhyland Klein default_val, PLLDSS_MISC1_CFG_WRITE_MASK & 7586b301a05SRhyland Klein (~PLLDSS_MISC1_CFG_EN_SDM)); 7596b301a05SRhyland Klein } 7606b301a05SRhyland Klein 7611934ffd0SPeter De Schrijver if (!plldss->params->defaults_set) 7621934ffd0SPeter De Schrijver pr_warn("%s already enabled. Postponing set full defaults\n", 7631934ffd0SPeter De Schrijver pll_name); 7641934ffd0SPeter De Schrijver 7656b301a05SRhyland Klein /* Enable lock detect */ 7666b301a05SRhyland Klein if (val & PLLDSS_BASE_LOCK_OVERRIDE) { 7676b301a05SRhyland Klein val &= ~PLLDSS_BASE_LOCK_OVERRIDE; 7686b301a05SRhyland Klein writel_relaxed(val, clk_base + 7696b301a05SRhyland Klein plldss->params->base_reg); 7706b301a05SRhyland Klein } 7716b301a05SRhyland Klein 7726b301a05SRhyland Klein val = readl_relaxed(clk_base + plldss->params->ext_misc_reg[0]); 7736b301a05SRhyland Klein val &= ~PLLDSS_MISC0_LOCK_ENABLE; 7746b301a05SRhyland Klein val |= misc0_val & PLLDSS_MISC0_LOCK_ENABLE; 7756b301a05SRhyland Klein writel_relaxed(val, clk_base + plldss->params->ext_misc_reg[0]); 7766b301a05SRhyland Klein udelay(1); 7776b301a05SRhyland Klein 7786b301a05SRhyland Klein return; 7796b301a05SRhyland Klein } 7806b301a05SRhyland Klein 7816b301a05SRhyland Klein /* set IDDQ, enable lock detect, configure SDM/SSC */ 7826b301a05SRhyland Klein val |= PLLDSS_BASE_IDDQ; 7836b301a05SRhyland Klein val &= ~PLLDSS_BASE_LOCK_OVERRIDE; 7846b301a05SRhyland Klein writel_relaxed(val, clk_base + plldss->params->base_reg); 7856b301a05SRhyland Klein 7866b301a05SRhyland Klein /* When using this function for PLLC4 exit here */ 7876b301a05SRhyland Klein if (!plldss->params->ext_misc_reg[1]) { 7886b301a05SRhyland Klein writel_relaxed(misc0_val, clk_base + 7896b301a05SRhyland Klein plldss->params->ext_misc_reg[0]); 7906b301a05SRhyland Klein udelay(1); 7916b301a05SRhyland Klein return; 7926b301a05SRhyland Klein } 7936b301a05SRhyland Klein 7946b301a05SRhyland Klein writel_relaxed(misc0_val, clk_base + 7956b301a05SRhyland Klein plldss->params->ext_misc_reg[0]); 7966b301a05SRhyland Klein /* if SSC used set by 1st enable */ 7976b301a05SRhyland Klein writel_relaxed(misc1_val & (~PLLDSS_MISC1_CFG_EN_SSC), 7986b301a05SRhyland Klein clk_base + plldss->params->ext_misc_reg[1]); 7996b301a05SRhyland Klein writel_relaxed(misc2_val, clk_base + plldss->params->ext_misc_reg[2]); 8006b301a05SRhyland Klein writel_relaxed(misc3_val, clk_base + plldss->params->ext_misc_reg[3]); 8016b301a05SRhyland Klein udelay(1); 8026b301a05SRhyland Klein } 8036b301a05SRhyland Klein 804fd360e20SJon Hunter static void tegra210_plld2_set_defaults(struct tegra_clk_pll *plld2) 8056b301a05SRhyland Klein { 8066b301a05SRhyland Klein plldss_defaults("PLL_D2", plld2, PLLD2_MISC0_DEFAULT_VALUE, 8076b301a05SRhyland Klein PLLD2_MISC1_CFG_DEFAULT_VALUE, 8086b301a05SRhyland Klein PLLD2_MISC2_CTRL1_DEFAULT_VALUE, 8096b301a05SRhyland Klein PLLD2_MISC3_CTRL2_DEFAULT_VALUE); 8106b301a05SRhyland Klein } 8116b301a05SRhyland Klein 812fd360e20SJon Hunter static void tegra210_plldp_set_defaults(struct tegra_clk_pll *plldp) 8136b301a05SRhyland Klein { 8146b301a05SRhyland Klein plldss_defaults("PLL_DP", plldp, PLLDP_MISC0_DEFAULT_VALUE, 8156b301a05SRhyland Klein PLLDP_MISC1_CFG_DEFAULT_VALUE, 8166b301a05SRhyland Klein PLLDP_MISC2_CTRL1_DEFAULT_VALUE, 8176b301a05SRhyland Klein PLLDP_MISC3_CTRL2_DEFAULT_VALUE); 8186b301a05SRhyland Klein } 8196b301a05SRhyland Klein 8206b301a05SRhyland Klein /* 8216b301a05SRhyland Klein * PLLC4 8226b301a05SRhyland Klein * Base and misc0 layout is the same as PLLD2/PLLDP, but no SDM/SSC support. 8236b301a05SRhyland Klein * VCO is exposed to the clock tree via fixed 1/3 and 1/5 dividers. 8246b301a05SRhyland Klein */ 825fd360e20SJon Hunter static void tegra210_pllc4_set_defaults(struct tegra_clk_pll *pllc4) 8266b301a05SRhyland Klein { 8276b301a05SRhyland Klein plldss_defaults("PLL_C4", pllc4, PLLC4_MISC0_DEFAULT_VALUE, 0, 0, 0); 8286b301a05SRhyland Klein } 8296b301a05SRhyland Klein 8306b301a05SRhyland Klein /* 8316b301a05SRhyland Klein * PLLRE 8326b301a05SRhyland Klein * VCO is exposed to the clock tree directly along with post-divider output 8336b301a05SRhyland Klein */ 834fd360e20SJon Hunter static void tegra210_pllre_set_defaults(struct tegra_clk_pll *pllre) 8356b301a05SRhyland Klein { 8366b301a05SRhyland Klein u32 mask; 8376b301a05SRhyland Klein u32 val = readl_relaxed(clk_base + pllre->params->base_reg); 8386b301a05SRhyland Klein 8396b301a05SRhyland Klein pllre->params->defaults_set = true; 8406b301a05SRhyland Klein 8416b301a05SRhyland Klein if (val & PLL_ENABLE) { 8426b301a05SRhyland Klein pr_warn("PLL_RE already enabled. Postponing set full defaults\n"); 8436b301a05SRhyland Klein 8446b301a05SRhyland Klein /* 8456b301a05SRhyland Klein * PLL is ON: check if defaults already set, then set those 8466b301a05SRhyland Klein * that can be updated in flight. 8476b301a05SRhyland Klein */ 8486b301a05SRhyland Klein val &= PLLRE_BASE_DEFAULT_MASK; 8496b301a05SRhyland Klein if (val != PLLRE_BASE_DEFAULT_VALUE) { 8506b301a05SRhyland Klein pr_warn("pllre boot base 0x%x : expected 0x%x\n", 8516b301a05SRhyland Klein val, PLLRE_BASE_DEFAULT_VALUE); 8526b301a05SRhyland Klein pr_warn("(comparison mask = 0x%x)\n", 8536b301a05SRhyland Klein PLLRE_BASE_DEFAULT_MASK); 8546b301a05SRhyland Klein pllre->params->defaults_set = false; 8556b301a05SRhyland Klein } 8566b301a05SRhyland Klein 8576b301a05SRhyland Klein /* Ignore lock enable */ 8586b301a05SRhyland Klein val = PLLRE_MISC0_DEFAULT_VALUE & (~PLLRE_MISC0_IDDQ); 8596b301a05SRhyland Klein mask = PLLRE_MISC0_LOCK_ENABLE | PLLRE_MISC0_LOCK_OVERRIDE; 8606b301a05SRhyland Klein _pll_misc_chk_default(clk_base, pllre->params, 0, val, 8616b301a05SRhyland Klein ~mask & PLLRE_MISC0_WRITE_MASK); 8626b301a05SRhyland Klein 8636b301a05SRhyland Klein /* Enable lock detect */ 8646b301a05SRhyland Klein val = readl_relaxed(clk_base + pllre->params->ext_misc_reg[0]); 8656b301a05SRhyland Klein val &= ~mask; 8666b301a05SRhyland Klein val |= PLLRE_MISC0_DEFAULT_VALUE & mask; 8676b301a05SRhyland Klein writel_relaxed(val, clk_base + pllre->params->ext_misc_reg[0]); 8686b301a05SRhyland Klein udelay(1); 8696b301a05SRhyland Klein 8706b301a05SRhyland Klein return; 8716b301a05SRhyland Klein } 8726b301a05SRhyland Klein 8736b301a05SRhyland Klein /* set IDDQ, enable lock detect */ 8746b301a05SRhyland Klein val &= ~PLLRE_BASE_DEFAULT_MASK; 8756b301a05SRhyland Klein val |= PLLRE_BASE_DEFAULT_VALUE & PLLRE_BASE_DEFAULT_MASK; 8766b301a05SRhyland Klein writel_relaxed(val, clk_base + pllre->params->base_reg); 8776b301a05SRhyland Klein writel_relaxed(PLLRE_MISC0_DEFAULT_VALUE, 8786b301a05SRhyland Klein clk_base + pllre->params->ext_misc_reg[0]); 8796b301a05SRhyland Klein udelay(1); 8806b301a05SRhyland Klein } 8816b301a05SRhyland Klein 8826b301a05SRhyland Klein static void pllx_get_dyn_steps(struct clk_hw *hw, u32 *step_a, u32 *step_b) 8836b301a05SRhyland Klein { 8846b301a05SRhyland Klein unsigned long input_rate; 8856b301a05SRhyland Klein 8866b301a05SRhyland Klein /* cf rate */ 8873dad5c5fSRhyland Klein if (!IS_ERR_OR_NULL(hw->clk)) 8883dad5c5fSRhyland Klein input_rate = clk_hw_get_rate(clk_hw_get_parent(hw)); 8893dad5c5fSRhyland Klein else 8906b301a05SRhyland Klein input_rate = 38400000; 8913dad5c5fSRhyland Klein 8923dad5c5fSRhyland Klein input_rate /= tegra_pll_get_fixed_mdiv(hw, input_rate); 8936b301a05SRhyland Klein 8946b301a05SRhyland Klein switch (input_rate) { 8956b301a05SRhyland Klein case 12000000: 8966b301a05SRhyland Klein case 12800000: 8976b301a05SRhyland Klein case 13000000: 8986b301a05SRhyland Klein *step_a = 0x2B; 8996b301a05SRhyland Klein *step_b = 0x0B; 9006b301a05SRhyland Klein return; 9016b301a05SRhyland Klein case 19200000: 9026b301a05SRhyland Klein *step_a = 0x12; 9036b301a05SRhyland Klein *step_b = 0x08; 9046b301a05SRhyland Klein return; 9056b301a05SRhyland Klein case 38400000: 9066b301a05SRhyland Klein *step_a = 0x04; 9076b301a05SRhyland Klein *step_b = 0x05; 9086b301a05SRhyland Klein return; 9096b301a05SRhyland Klein default: 9106b301a05SRhyland Klein pr_err("%s: Unexpected reference rate %lu\n", 9116b301a05SRhyland Klein __func__, input_rate); 9126b301a05SRhyland Klein BUG(); 9136b301a05SRhyland Klein } 9146b301a05SRhyland Klein } 9156b301a05SRhyland Klein 9166b301a05SRhyland Klein static void pllx_check_defaults(struct tegra_clk_pll *pll) 9176b301a05SRhyland Klein { 9186b301a05SRhyland Klein u32 default_val; 9196b301a05SRhyland Klein 9206b301a05SRhyland Klein default_val = PLLX_MISC0_DEFAULT_VALUE; 9216b301a05SRhyland Klein /* ignore lock enable */ 9226b301a05SRhyland Klein _pll_misc_chk_default(clk_base, pll->params, 0, default_val, 9236b301a05SRhyland Klein PLLX_MISC0_WRITE_MASK & (~PLLX_MISC0_LOCK_ENABLE)); 9246b301a05SRhyland Klein 9256b301a05SRhyland Klein default_val = PLLX_MISC1_DEFAULT_VALUE; 9266b301a05SRhyland Klein _pll_misc_chk_default(clk_base, pll->params, 1, default_val, 9276b301a05SRhyland Klein PLLX_MISC1_WRITE_MASK); 9286b301a05SRhyland Klein 9296b301a05SRhyland Klein /* ignore all but control bit */ 9306b301a05SRhyland Klein default_val = PLLX_MISC2_DEFAULT_VALUE; 9316b301a05SRhyland Klein _pll_misc_chk_default(clk_base, pll->params, 2, 9326b301a05SRhyland Klein default_val, PLLX_MISC2_EN_DYNRAMP); 9336b301a05SRhyland Klein 9346b301a05SRhyland Klein default_val = PLLX_MISC3_DEFAULT_VALUE & (~PLLX_MISC3_IDDQ); 9356b301a05SRhyland Klein _pll_misc_chk_default(clk_base, pll->params, 3, default_val, 9366b301a05SRhyland Klein PLLX_MISC3_WRITE_MASK); 9376b301a05SRhyland Klein 9386b301a05SRhyland Klein default_val = PLLX_MISC4_DEFAULT_VALUE; 9396b301a05SRhyland Klein _pll_misc_chk_default(clk_base, pll->params, 4, default_val, 9406b301a05SRhyland Klein PLLX_MISC4_WRITE_MASK); 9416b301a05SRhyland Klein 9426b301a05SRhyland Klein default_val = PLLX_MISC5_DEFAULT_VALUE; 9436b301a05SRhyland Klein _pll_misc_chk_default(clk_base, pll->params, 5, default_val, 9446b301a05SRhyland Klein PLLX_MISC5_WRITE_MASK); 9456b301a05SRhyland Klein } 9466b301a05SRhyland Klein 947fd360e20SJon Hunter static void tegra210_pllx_set_defaults(struct tegra_clk_pll *pllx) 9486b301a05SRhyland Klein { 9496b301a05SRhyland Klein u32 val; 9506b301a05SRhyland Klein u32 step_a, step_b; 9516b301a05SRhyland Klein 9526b301a05SRhyland Klein pllx->params->defaults_set = true; 9536b301a05SRhyland Klein 9546b301a05SRhyland Klein /* Get ready dyn ramp state machine settings */ 9556b301a05SRhyland Klein pllx_get_dyn_steps(&pllx->hw, &step_a, &step_b); 9566b301a05SRhyland Klein val = PLLX_MISC2_DEFAULT_VALUE & (~PLLX_MISC2_DYNRAMP_STEPA_MASK) & 9576b301a05SRhyland Klein (~PLLX_MISC2_DYNRAMP_STEPB_MASK); 9586b301a05SRhyland Klein val |= step_a << PLLX_MISC2_DYNRAMP_STEPA_SHIFT; 9596b301a05SRhyland Klein val |= step_b << PLLX_MISC2_DYNRAMP_STEPB_SHIFT; 9606b301a05SRhyland Klein 9616b301a05SRhyland Klein if (readl_relaxed(clk_base + pllx->params->base_reg) & PLL_ENABLE) { 9626b301a05SRhyland Klein 9636b301a05SRhyland Klein /* 9646b301a05SRhyland Klein * PLL is ON: check if defaults already set, then set those 9656b301a05SRhyland Klein * that can be updated in flight. 9666b301a05SRhyland Klein */ 9676b301a05SRhyland Klein pllx_check_defaults(pllx); 9686b301a05SRhyland Klein 9698dce89a1SPeter De Schrijver if (!pllx->params->defaults_set) 9708dce89a1SPeter De Schrijver pr_warn("PLL_X already enabled. Postponing set full defaults\n"); 9716b301a05SRhyland Klein /* Configure dyn ramp, disable lock override */ 9726b301a05SRhyland Klein writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]); 9736b301a05SRhyland Klein 9746b301a05SRhyland Klein /* Enable lock detect */ 9756b301a05SRhyland Klein val = readl_relaxed(clk_base + pllx->params->ext_misc_reg[0]); 9766b301a05SRhyland Klein val &= ~PLLX_MISC0_LOCK_ENABLE; 9776b301a05SRhyland Klein val |= PLLX_MISC0_DEFAULT_VALUE & PLLX_MISC0_LOCK_ENABLE; 9786b301a05SRhyland Klein writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[0]); 9796b301a05SRhyland Klein udelay(1); 9806b301a05SRhyland Klein 9816b301a05SRhyland Klein return; 9826b301a05SRhyland Klein } 9836b301a05SRhyland Klein 9846b301a05SRhyland Klein /* Enable lock detect and CPU output */ 9856b301a05SRhyland Klein writel_relaxed(PLLX_MISC0_DEFAULT_VALUE, clk_base + 9866b301a05SRhyland Klein pllx->params->ext_misc_reg[0]); 9876b301a05SRhyland Klein 9886b301a05SRhyland Klein /* Setup */ 9896b301a05SRhyland Klein writel_relaxed(PLLX_MISC1_DEFAULT_VALUE, clk_base + 9906b301a05SRhyland Klein pllx->params->ext_misc_reg[1]); 9916b301a05SRhyland Klein 9926b301a05SRhyland Klein /* Configure dyn ramp state machine, disable lock override */ 9936b301a05SRhyland Klein writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]); 9946b301a05SRhyland Klein 9956b301a05SRhyland Klein /* Set IDDQ */ 9966b301a05SRhyland Klein writel_relaxed(PLLX_MISC3_DEFAULT_VALUE, clk_base + 9976b301a05SRhyland Klein pllx->params->ext_misc_reg[3]); 9986b301a05SRhyland Klein 9996b301a05SRhyland Klein /* Disable SDM */ 10006b301a05SRhyland Klein writel_relaxed(PLLX_MISC4_DEFAULT_VALUE, clk_base + 10016b301a05SRhyland Klein pllx->params->ext_misc_reg[4]); 10026b301a05SRhyland Klein writel_relaxed(PLLX_MISC5_DEFAULT_VALUE, clk_base + 10036b301a05SRhyland Klein pllx->params->ext_misc_reg[5]); 10046b301a05SRhyland Klein udelay(1); 10056b301a05SRhyland Klein } 10066b301a05SRhyland Klein 10076b301a05SRhyland Klein /* PLLMB */ 1008fd360e20SJon Hunter static void tegra210_pllmb_set_defaults(struct tegra_clk_pll *pllmb) 10096b301a05SRhyland Klein { 10106b301a05SRhyland Klein u32 mask, val = readl_relaxed(clk_base + pllmb->params->base_reg); 10116b301a05SRhyland Klein 10126b301a05SRhyland Klein pllmb->params->defaults_set = true; 10136b301a05SRhyland Klein 10146b301a05SRhyland Klein if (val & PLL_ENABLE) { 10156b301a05SRhyland Klein 10166b301a05SRhyland Klein /* 10176b301a05SRhyland Klein * PLL is ON: check if defaults already set, then set those 10186b301a05SRhyland Klein * that can be updated in flight. 10196b301a05SRhyland Klein */ 1020474f2ba2SRhyland Klein val = PLLMB_MISC1_DEFAULT_VALUE & (~PLLMB_MISC1_IDDQ); 1021474f2ba2SRhyland Klein mask = PLLMB_MISC1_LOCK_ENABLE | PLLMB_MISC1_LOCK_OVERRIDE; 10226b301a05SRhyland Klein _pll_misc_chk_default(clk_base, pllmb->params, 0, val, 1023474f2ba2SRhyland Klein ~mask & PLLMB_MISC1_WRITE_MASK); 10246b301a05SRhyland Klein 10258dce89a1SPeter De Schrijver if (!pllmb->params->defaults_set) 10268dce89a1SPeter De Schrijver pr_warn("PLL_MB already enabled. Postponing set full defaults\n"); 10276b301a05SRhyland Klein /* Enable lock detect */ 10286b301a05SRhyland Klein val = readl_relaxed(clk_base + pllmb->params->ext_misc_reg[0]); 10296b301a05SRhyland Klein val &= ~mask; 1030474f2ba2SRhyland Klein val |= PLLMB_MISC1_DEFAULT_VALUE & mask; 10316b301a05SRhyland Klein writel_relaxed(val, clk_base + pllmb->params->ext_misc_reg[0]); 10326b301a05SRhyland Klein udelay(1); 10336b301a05SRhyland Klein 10346b301a05SRhyland Klein return; 10356b301a05SRhyland Klein } 10366b301a05SRhyland Klein 10376b301a05SRhyland Klein /* set IDDQ, enable lock detect */ 1038474f2ba2SRhyland Klein writel_relaxed(PLLMB_MISC1_DEFAULT_VALUE, 10396b301a05SRhyland Klein clk_base + pllmb->params->ext_misc_reg[0]); 10406b301a05SRhyland Klein udelay(1); 10416b301a05SRhyland Klein } 10426b301a05SRhyland Klein 10436b301a05SRhyland Klein /* 10446b301a05SRhyland Klein * PLLP 10456b301a05SRhyland Klein * VCO is exposed to the clock tree directly along with post-divider output. 10466b301a05SRhyland Klein * Both VCO and post-divider output rates are fixed at 408MHz and 204MHz, 10476b301a05SRhyland Klein * respectively. 10486b301a05SRhyland Klein */ 10496b301a05SRhyland Klein static void pllp_check_defaults(struct tegra_clk_pll *pll, bool enabled) 10506b301a05SRhyland Klein { 10516b301a05SRhyland Klein u32 val, mask; 10526b301a05SRhyland Klein 10536b301a05SRhyland Klein /* Ignore lock enable (will be set), make sure not in IDDQ if enabled */ 10546b301a05SRhyland Klein val = PLLP_MISC0_DEFAULT_VALUE & (~PLLP_MISC0_IDDQ); 10556b301a05SRhyland Klein mask = PLLP_MISC0_LOCK_ENABLE | PLLP_MISC0_LOCK_OVERRIDE; 10566b301a05SRhyland Klein if (!enabled) 10576b301a05SRhyland Klein mask |= PLLP_MISC0_IDDQ; 10586b301a05SRhyland Klein _pll_misc_chk_default(clk_base, pll->params, 0, val, 10596b301a05SRhyland Klein ~mask & PLLP_MISC0_WRITE_MASK); 10606b301a05SRhyland Klein 10616b301a05SRhyland Klein /* Ignore branch controls */ 10626b301a05SRhyland Klein val = PLLP_MISC1_DEFAULT_VALUE; 10636b301a05SRhyland Klein mask = PLLP_MISC1_HSIO_EN | PLLP_MISC1_XUSB_EN; 10646b301a05SRhyland Klein _pll_misc_chk_default(clk_base, pll->params, 1, val, 10656b301a05SRhyland Klein ~mask & PLLP_MISC1_WRITE_MASK); 10666b301a05SRhyland Klein } 10676b301a05SRhyland Klein 1068fd360e20SJon Hunter static void tegra210_pllp_set_defaults(struct tegra_clk_pll *pllp) 10696b301a05SRhyland Klein { 10706b301a05SRhyland Klein u32 mask; 10716b301a05SRhyland Klein u32 val = readl_relaxed(clk_base + pllp->params->base_reg); 10726b301a05SRhyland Klein 10736b301a05SRhyland Klein pllp->params->defaults_set = true; 10746b301a05SRhyland Klein 10756b301a05SRhyland Klein if (val & PLL_ENABLE) { 10766b301a05SRhyland Klein 10776b301a05SRhyland Klein /* 10786b301a05SRhyland Klein * PLL is ON: check if defaults already set, then set those 10796b301a05SRhyland Klein * that can be updated in flight. 10806b301a05SRhyland Klein */ 10816b301a05SRhyland Klein pllp_check_defaults(pllp, true); 10828dce89a1SPeter De Schrijver if (!pllp->params->defaults_set) 10838dce89a1SPeter De Schrijver pr_warn("PLL_P already enabled. Postponing set full defaults\n"); 10846b301a05SRhyland Klein 10856b301a05SRhyland Klein /* Enable lock detect */ 10866b301a05SRhyland Klein val = readl_relaxed(clk_base + pllp->params->ext_misc_reg[0]); 10876b301a05SRhyland Klein mask = PLLP_MISC0_LOCK_ENABLE | PLLP_MISC0_LOCK_OVERRIDE; 10886b301a05SRhyland Klein val &= ~mask; 10896b301a05SRhyland Klein val |= PLLP_MISC0_DEFAULT_VALUE & mask; 10906b301a05SRhyland Klein writel_relaxed(val, clk_base + pllp->params->ext_misc_reg[0]); 10916b301a05SRhyland Klein udelay(1); 10926b301a05SRhyland Klein 10936b301a05SRhyland Klein return; 10946b301a05SRhyland Klein } 10956b301a05SRhyland Klein 10966b301a05SRhyland Klein /* set IDDQ, enable lock detect */ 10976b301a05SRhyland Klein writel_relaxed(PLLP_MISC0_DEFAULT_VALUE, 10986b301a05SRhyland Klein clk_base + pllp->params->ext_misc_reg[0]); 10996b301a05SRhyland Klein 11006b301a05SRhyland Klein /* Preserve branch control */ 11016b301a05SRhyland Klein val = readl_relaxed(clk_base + pllp->params->ext_misc_reg[1]); 11026b301a05SRhyland Klein mask = PLLP_MISC1_HSIO_EN | PLLP_MISC1_XUSB_EN; 11036b301a05SRhyland Klein val &= mask; 11046b301a05SRhyland Klein val |= ~mask & PLLP_MISC1_DEFAULT_VALUE; 11056b301a05SRhyland Klein writel_relaxed(val, clk_base + pllp->params->ext_misc_reg[1]); 11066b301a05SRhyland Klein udelay(1); 11076b301a05SRhyland Klein } 11086b301a05SRhyland Klein 11096b301a05SRhyland Klein /* 11106b301a05SRhyland Klein * PLLU 11116b301a05SRhyland Klein * VCO is exposed to the clock tree directly along with post-divider output. 11126b301a05SRhyland Klein * Both VCO and post-divider output rates are fixed at 480MHz and 240MHz, 11136b301a05SRhyland Klein * respectively. 11146b301a05SRhyland Klein */ 1115e745f992SPeter De Schrijver static void pllu_check_defaults(struct tegra_clk_pll_params *params, 1116e745f992SPeter De Schrijver bool hw_control) 11176b301a05SRhyland Klein { 11186b301a05SRhyland Klein u32 val, mask; 11196b301a05SRhyland Klein 11206b301a05SRhyland Klein /* Ignore lock enable (will be set) and IDDQ if under h/w control */ 11216b301a05SRhyland Klein val = PLLU_MISC0_DEFAULT_VALUE & (~PLLU_MISC0_IDDQ); 11226b301a05SRhyland Klein mask = PLLU_MISC0_LOCK_ENABLE | (hw_control ? PLLU_MISC0_IDDQ : 0); 1123e745f992SPeter De Schrijver _pll_misc_chk_default(clk_base, params, 0, val, 11246b301a05SRhyland Klein ~mask & PLLU_MISC0_WRITE_MASK); 11256b301a05SRhyland Klein 11266b301a05SRhyland Klein val = PLLU_MISC1_DEFAULT_VALUE; 11276b301a05SRhyland Klein mask = PLLU_MISC1_LOCK_OVERRIDE; 1128e745f992SPeter De Schrijver _pll_misc_chk_default(clk_base, params, 1, val, 11296b301a05SRhyland Klein ~mask & PLLU_MISC1_WRITE_MASK); 11306b301a05SRhyland Klein } 11316b301a05SRhyland Klein 1132e745f992SPeter De Schrijver static void tegra210_pllu_set_defaults(struct tegra_clk_pll_params *pllu) 11336b301a05SRhyland Klein { 1134e745f992SPeter De Schrijver u32 val = readl_relaxed(clk_base + pllu->base_reg); 11356b301a05SRhyland Klein 1136e745f992SPeter De Schrijver pllu->defaults_set = true; 11376b301a05SRhyland Klein 11386b301a05SRhyland Klein if (val & PLL_ENABLE) { 11396b301a05SRhyland Klein 11406b301a05SRhyland Klein /* 11416b301a05SRhyland Klein * PLL is ON: check if defaults already set, then set those 11426b301a05SRhyland Klein * that can be updated in flight. 11436b301a05SRhyland Klein */ 11446b301a05SRhyland Klein pllu_check_defaults(pllu, false); 1145e745f992SPeter De Schrijver if (!pllu->defaults_set) 11468dce89a1SPeter De Schrijver pr_warn("PLL_U already enabled. Postponing set full defaults\n"); 11476b301a05SRhyland Klein 11486b301a05SRhyland Klein /* Enable lock detect */ 1149e745f992SPeter De Schrijver val = readl_relaxed(clk_base + pllu->ext_misc_reg[0]); 11506b301a05SRhyland Klein val &= ~PLLU_MISC0_LOCK_ENABLE; 11516b301a05SRhyland Klein val |= PLLU_MISC0_DEFAULT_VALUE & PLLU_MISC0_LOCK_ENABLE; 1152e745f992SPeter De Schrijver writel_relaxed(val, clk_base + pllu->ext_misc_reg[0]); 11536b301a05SRhyland Klein 1154e745f992SPeter De Schrijver val = readl_relaxed(clk_base + pllu->ext_misc_reg[1]); 11556b301a05SRhyland Klein val &= ~PLLU_MISC1_LOCK_OVERRIDE; 11566b301a05SRhyland Klein val |= PLLU_MISC1_DEFAULT_VALUE & PLLU_MISC1_LOCK_OVERRIDE; 1157e745f992SPeter De Schrijver writel_relaxed(val, clk_base + pllu->ext_misc_reg[1]); 11586b301a05SRhyland Klein udelay(1); 11596b301a05SRhyland Klein 11606b301a05SRhyland Klein return; 11616b301a05SRhyland Klein } 11626b301a05SRhyland Klein 11636b301a05SRhyland Klein /* set IDDQ, enable lock detect */ 11646b301a05SRhyland Klein writel_relaxed(PLLU_MISC0_DEFAULT_VALUE, 1165e745f992SPeter De Schrijver clk_base + pllu->ext_misc_reg[0]); 11666b301a05SRhyland Klein writel_relaxed(PLLU_MISC1_DEFAULT_VALUE, 1167e745f992SPeter De Schrijver clk_base + pllu->ext_misc_reg[1]); 11686b301a05SRhyland Klein udelay(1); 11696b301a05SRhyland Klein } 11706b301a05SRhyland Klein 11716b301a05SRhyland Klein #define mask(w) ((1 << (w)) - 1) 11726b301a05SRhyland Klein #define divm_mask(p) mask(p->params->div_nmp->divm_width) 11736b301a05SRhyland Klein #define divn_mask(p) mask(p->params->div_nmp->divn_width) 11746b301a05SRhyland Klein #define divp_mask(p) (p->params->flags & TEGRA_PLLU ? PLLU_POST_DIVP_MASK :\ 11756b301a05SRhyland Klein mask(p->params->div_nmp->divp_width)) 11766b301a05SRhyland Klein 11776b301a05SRhyland Klein #define divm_shift(p) ((p)->params->div_nmp->divm_shift) 11786b301a05SRhyland Klein #define divn_shift(p) ((p)->params->div_nmp->divn_shift) 11796b301a05SRhyland Klein #define divp_shift(p) ((p)->params->div_nmp->divp_shift) 11806b301a05SRhyland Klein 11816b301a05SRhyland Klein #define divm_mask_shifted(p) (divm_mask(p) << divm_shift(p)) 11826b301a05SRhyland Klein #define divn_mask_shifted(p) (divn_mask(p) << divn_shift(p)) 11836b301a05SRhyland Klein #define divp_mask_shifted(p) (divp_mask(p) << divp_shift(p)) 11846b301a05SRhyland Klein 11856b301a05SRhyland Klein #define PLL_LOCKDET_DELAY 2 /* Lock detection safety delays */ 11866b301a05SRhyland Klein static int tegra210_wait_for_mask(struct tegra_clk_pll *pll, 11876b301a05SRhyland Klein u32 reg, u32 mask) 11886b301a05SRhyland Klein { 11896b301a05SRhyland Klein int i; 11906b301a05SRhyland Klein u32 val = 0; 11916b301a05SRhyland Klein 11926b301a05SRhyland Klein for (i = 0; i < pll->params->lock_delay / PLL_LOCKDET_DELAY + 1; i++) { 11936b301a05SRhyland Klein udelay(PLL_LOCKDET_DELAY); 11946b301a05SRhyland Klein val = readl_relaxed(clk_base + reg); 11956b301a05SRhyland Klein if ((val & mask) == mask) { 11966b301a05SRhyland Klein udelay(PLL_LOCKDET_DELAY); 11976b301a05SRhyland Klein return 0; 11986b301a05SRhyland Klein } 11996b301a05SRhyland Klein } 12006b301a05SRhyland Klein return -ETIMEDOUT; 12016b301a05SRhyland Klein } 12026b301a05SRhyland Klein 12036b301a05SRhyland Klein static int tegra210_pllx_dyn_ramp(struct tegra_clk_pll *pllx, 12046b301a05SRhyland Klein struct tegra_clk_pll_freq_table *cfg) 12056b301a05SRhyland Klein { 12066b301a05SRhyland Klein u32 val, base, ndiv_new_mask; 12076b301a05SRhyland Klein 12086b301a05SRhyland Klein ndiv_new_mask = (divn_mask(pllx) >> pllx->params->div_nmp->divn_shift) 12096b301a05SRhyland Klein << PLLX_MISC2_NDIV_NEW_SHIFT; 12106b301a05SRhyland Klein 12116b301a05SRhyland Klein val = readl_relaxed(clk_base + pllx->params->ext_misc_reg[2]); 12126b301a05SRhyland Klein val &= (~ndiv_new_mask); 12136b301a05SRhyland Klein val |= cfg->n << PLLX_MISC2_NDIV_NEW_SHIFT; 12146b301a05SRhyland Klein writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]); 12156b301a05SRhyland Klein udelay(1); 12166b301a05SRhyland Klein 12176b301a05SRhyland Klein val = readl_relaxed(clk_base + pllx->params->ext_misc_reg[2]); 12186b301a05SRhyland Klein val |= PLLX_MISC2_EN_DYNRAMP; 12196b301a05SRhyland Klein writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]); 12206b301a05SRhyland Klein udelay(1); 12216b301a05SRhyland Klein 12226b301a05SRhyland Klein tegra210_wait_for_mask(pllx, pllx->params->ext_misc_reg[2], 12236b301a05SRhyland Klein PLLX_MISC2_DYNRAMP_DONE); 12246b301a05SRhyland Klein 12256b301a05SRhyland Klein base = readl_relaxed(clk_base + pllx->params->base_reg) & 12266b301a05SRhyland Klein (~divn_mask_shifted(pllx)); 12276b301a05SRhyland Klein base |= cfg->n << pllx->params->div_nmp->divn_shift; 12286b301a05SRhyland Klein writel_relaxed(base, clk_base + pllx->params->base_reg); 12296b301a05SRhyland Klein udelay(1); 12306b301a05SRhyland Klein 12316b301a05SRhyland Klein val &= ~PLLX_MISC2_EN_DYNRAMP; 12326b301a05SRhyland Klein writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]); 12336b301a05SRhyland Klein udelay(1); 12346b301a05SRhyland Klein 12356b301a05SRhyland Klein pr_debug("%s: dynamic ramp to m = %u n = %u p = %u, Fout = %lu kHz\n", 12366b301a05SRhyland Klein __clk_get_name(pllx->hw.clk), cfg->m, cfg->n, cfg->p, 12376b301a05SRhyland Klein cfg->input_rate / cfg->m * cfg->n / 12386b301a05SRhyland Klein pllx->params->pdiv_tohw[cfg->p].pdiv / 1000); 12396b301a05SRhyland Klein 12406b301a05SRhyland Klein return 0; 12416b301a05SRhyland Klein } 12426b301a05SRhyland Klein 12436b301a05SRhyland Klein /* 12446b301a05SRhyland Klein * Common configuration for PLLs with fixed input divider policy: 12456b301a05SRhyland Klein * - always set fixed M-value based on the reference rate 12466b301a05SRhyland Klein * - always set P-value value 1:1 for output rates above VCO minimum, and 12476b301a05SRhyland Klein * choose minimum necessary P-value for output rates below VCO maximum 12486b301a05SRhyland Klein * - calculate N-value based on selected M and P 12496b301a05SRhyland Klein * - calculate SDM_DIN fractional part 12506b301a05SRhyland Klein */ 12516b301a05SRhyland Klein static int tegra210_pll_fixed_mdiv_cfg(struct clk_hw *hw, 12526b301a05SRhyland Klein struct tegra_clk_pll_freq_table *cfg, 12536b301a05SRhyland Klein unsigned long rate, unsigned long input_rate) 12546b301a05SRhyland Klein { 12556b301a05SRhyland Klein struct tegra_clk_pll *pll = to_clk_pll(hw); 12566b301a05SRhyland Klein struct tegra_clk_pll_params *params = pll->params; 12576b301a05SRhyland Klein int p; 12586b301a05SRhyland Klein unsigned long cf, p_rate; 12596b301a05SRhyland Klein u32 pdiv; 12606b301a05SRhyland Klein 12616b301a05SRhyland Klein if (!rate) 12626b301a05SRhyland Klein return -EINVAL; 12636b301a05SRhyland Klein 12646b301a05SRhyland Klein if (!(params->flags & TEGRA_PLL_VCO_OUT)) { 12656b301a05SRhyland Klein p = DIV_ROUND_UP(params->vco_min, rate); 12666b301a05SRhyland Klein p = params->round_p_to_pdiv(p, &pdiv); 12676b301a05SRhyland Klein } else { 12686b301a05SRhyland Klein p = rate >= params->vco_min ? 1 : -EINVAL; 12696b301a05SRhyland Klein } 12706b301a05SRhyland Klein 1271287980e4SArnd Bergmann if (p < 0) 12726b301a05SRhyland Klein return -EINVAL; 12736b301a05SRhyland Klein 12746b301a05SRhyland Klein cfg->m = tegra_pll_get_fixed_mdiv(hw, input_rate); 12756b301a05SRhyland Klein cfg->p = p; 12766b301a05SRhyland Klein 12776b301a05SRhyland Klein /* Store P as HW value, as that is what is expected */ 12786b301a05SRhyland Klein cfg->p = tegra_pll_p_div_to_hw(pll, cfg->p); 12796b301a05SRhyland Klein 12806b301a05SRhyland Klein p_rate = rate * p; 12816b301a05SRhyland Klein if (p_rate > params->vco_max) 12826b301a05SRhyland Klein p_rate = params->vco_max; 12836b301a05SRhyland Klein cf = input_rate / cfg->m; 12846b301a05SRhyland Klein cfg->n = p_rate / cf; 12856b301a05SRhyland Klein 12866b301a05SRhyland Klein cfg->sdm_data = 0; 1287ef6ed2b9SPeter De Schrijver cfg->output_rate = input_rate; 12886b301a05SRhyland Klein if (params->sdm_ctrl_reg) { 12896b301a05SRhyland Klein unsigned long rem = p_rate - cf * cfg->n; 12906b301a05SRhyland Klein /* If ssc is enabled SDM enabled as well, even for integer n */ 12916b301a05SRhyland Klein if (rem || params->ssc_ctrl_reg) { 12926b301a05SRhyland Klein u64 s = rem * PLL_SDM_COEFF; 12936b301a05SRhyland Klein 12946b301a05SRhyland Klein do_div(s, cf); 12956b301a05SRhyland Klein s -= PLL_SDM_COEFF / 2; 12966b301a05SRhyland Klein cfg->sdm_data = sdin_din_to_data(s); 12976b301a05SRhyland Klein } 1298a851ea2bSAlex Frid cfg->output_rate *= sdin_get_n_eff(cfg); 1299ef6ed2b9SPeter De Schrijver cfg->output_rate /= p * cfg->m * PLL_SDM_COEFF; 1300ef6ed2b9SPeter De Schrijver } else { 1301ef6ed2b9SPeter De Schrijver cfg->output_rate *= cfg->n; 1302ef6ed2b9SPeter De Schrijver cfg->output_rate /= p * cfg->m; 13036b301a05SRhyland Klein } 13046b301a05SRhyland Klein 13056b301a05SRhyland Klein cfg->input_rate = input_rate; 13066b301a05SRhyland Klein 13076b301a05SRhyland Klein return 0; 13086b301a05SRhyland Klein } 13096b301a05SRhyland Klein 13106b301a05SRhyland Klein /* 13116b301a05SRhyland Klein * clk_pll_set_gain - set gain to m, n to calculate correct VCO rate 13126b301a05SRhyland Klein * 13136b301a05SRhyland Klein * @cfg: struct tegra_clk_pll_freq_table * cfg 13146b301a05SRhyland Klein * 13156b301a05SRhyland Klein * For Normal mode: 13166b301a05SRhyland Klein * Fvco = Fref * NDIV / MDIV 13176b301a05SRhyland Klein * 13186b301a05SRhyland Klein * For fractional mode: 13196b301a05SRhyland Klein * Fvco = Fref * (NDIV + 0.5 + SDM_DIN / PLL_SDM_COEFF) / MDIV 13206b301a05SRhyland Klein */ 13216b301a05SRhyland Klein static void tegra210_clk_pll_set_gain(struct tegra_clk_pll_freq_table *cfg) 13226b301a05SRhyland Klein { 1323a851ea2bSAlex Frid cfg->n = sdin_get_n_eff(cfg); 13246b301a05SRhyland Klein cfg->m *= PLL_SDM_COEFF; 13256b301a05SRhyland Klein } 13266b301a05SRhyland Klein 1327fd360e20SJon Hunter static unsigned long 1328fd360e20SJon Hunter tegra210_clk_adjust_vco_min(struct tegra_clk_pll_params *params, 13296b301a05SRhyland Klein unsigned long parent_rate) 13306b301a05SRhyland Klein { 13316b301a05SRhyland Klein unsigned long vco_min = params->vco_min; 13326b301a05SRhyland Klein 13336b301a05SRhyland Klein params->vco_min += DIV_ROUND_UP(parent_rate, PLL_SDM_COEFF); 13346b301a05SRhyland Klein vco_min = min(vco_min, params->vco_min); 13356b301a05SRhyland Klein 13366b301a05SRhyland Klein return vco_min; 13376b301a05SRhyland Klein } 13386b301a05SRhyland Klein 13396b301a05SRhyland Klein static struct div_nmp pllx_nmp = { 13406b301a05SRhyland Klein .divm_shift = 0, 13416b301a05SRhyland Klein .divm_width = 8, 13426b301a05SRhyland Klein .divn_shift = 8, 13436b301a05SRhyland Klein .divn_width = 8, 13446b301a05SRhyland Klein .divp_shift = 20, 13456b301a05SRhyland Klein .divp_width = 5, 13466b301a05SRhyland Klein }; 13476b301a05SRhyland Klein /* 13486b301a05SRhyland Klein * PLL post divider maps - two types: quasi-linear and exponential 13496b301a05SRhyland Klein * post divider. 13506b301a05SRhyland Klein */ 13516b301a05SRhyland Klein #define PLL_QLIN_PDIV_MAX 16 13526b301a05SRhyland Klein static const struct pdiv_map pll_qlin_pdiv_to_hw[] = { 13536b301a05SRhyland Klein { .pdiv = 1, .hw_val = 0 }, 13546b301a05SRhyland Klein { .pdiv = 2, .hw_val = 1 }, 13556b301a05SRhyland Klein { .pdiv = 3, .hw_val = 2 }, 13566b301a05SRhyland Klein { .pdiv = 4, .hw_val = 3 }, 13576b301a05SRhyland Klein { .pdiv = 5, .hw_val = 4 }, 13586b301a05SRhyland Klein { .pdiv = 6, .hw_val = 5 }, 13596b301a05SRhyland Klein { .pdiv = 8, .hw_val = 6 }, 13606b301a05SRhyland Klein { .pdiv = 9, .hw_val = 7 }, 13616b301a05SRhyland Klein { .pdiv = 10, .hw_val = 8 }, 13626b301a05SRhyland Klein { .pdiv = 12, .hw_val = 9 }, 13636b301a05SRhyland Klein { .pdiv = 15, .hw_val = 10 }, 13646b301a05SRhyland Klein { .pdiv = 16, .hw_val = 11 }, 13656b301a05SRhyland Klein { .pdiv = 18, .hw_val = 12 }, 13666b301a05SRhyland Klein { .pdiv = 20, .hw_val = 13 }, 13676b301a05SRhyland Klein { .pdiv = 24, .hw_val = 14 }, 13686b301a05SRhyland Klein { .pdiv = 30, .hw_val = 15 }, 13696b301a05SRhyland Klein { .pdiv = 32, .hw_val = 16 }, 13706b301a05SRhyland Klein }; 13716b301a05SRhyland Klein 13726b301a05SRhyland Klein static u32 pll_qlin_p_to_pdiv(u32 p, u32 *pdiv) 13736b301a05SRhyland Klein { 13746b301a05SRhyland Klein int i; 13756b301a05SRhyland Klein 13766b301a05SRhyland Klein if (p) { 13776b301a05SRhyland Klein for (i = 0; i <= PLL_QLIN_PDIV_MAX; i++) { 13786b301a05SRhyland Klein if (p <= pll_qlin_pdiv_to_hw[i].pdiv) { 13796b301a05SRhyland Klein if (pdiv) 13806b301a05SRhyland Klein *pdiv = i; 13816b301a05SRhyland Klein return pll_qlin_pdiv_to_hw[i].pdiv; 13826b301a05SRhyland Klein } 13836b301a05SRhyland Klein } 13846b301a05SRhyland Klein } 13856b301a05SRhyland Klein 13866b301a05SRhyland Klein return -EINVAL; 13876b301a05SRhyland Klein } 13886b301a05SRhyland Klein 13896b301a05SRhyland Klein #define PLL_EXPO_PDIV_MAX 7 13906b301a05SRhyland Klein static const struct pdiv_map pll_expo_pdiv_to_hw[] = { 13916b301a05SRhyland Klein { .pdiv = 1, .hw_val = 0 }, 13926b301a05SRhyland Klein { .pdiv = 2, .hw_val = 1 }, 13936b301a05SRhyland Klein { .pdiv = 4, .hw_val = 2 }, 13946b301a05SRhyland Klein { .pdiv = 8, .hw_val = 3 }, 13956b301a05SRhyland Klein { .pdiv = 16, .hw_val = 4 }, 13966b301a05SRhyland Klein { .pdiv = 32, .hw_val = 5 }, 13976b301a05SRhyland Klein { .pdiv = 64, .hw_val = 6 }, 13986b301a05SRhyland Klein { .pdiv = 128, .hw_val = 7 }, 13996b301a05SRhyland Klein }; 14006b301a05SRhyland Klein 14016b301a05SRhyland Klein static u32 pll_expo_p_to_pdiv(u32 p, u32 *pdiv) 14026b301a05SRhyland Klein { 14036b301a05SRhyland Klein if (p) { 14046b301a05SRhyland Klein u32 i = fls(p); 14056b301a05SRhyland Klein 14066b301a05SRhyland Klein if (i == ffs(p)) 14076b301a05SRhyland Klein i--; 14086b301a05SRhyland Klein 14096b301a05SRhyland Klein if (i <= PLL_EXPO_PDIV_MAX) { 14106b301a05SRhyland Klein if (pdiv) 14116b301a05SRhyland Klein *pdiv = i; 14126b301a05SRhyland Klein return 1 << i; 14136b301a05SRhyland Klein } 14146b301a05SRhyland Klein } 14156b301a05SRhyland Klein return -EINVAL; 14166b301a05SRhyland Klein } 14176b301a05SRhyland Klein 14186b301a05SRhyland Klein static struct tegra_clk_pll_freq_table pll_x_freq_table[] = { 14196b301a05SRhyland Klein /* 1 GHz */ 1420eddb65e7SThierry Reding { 12000000, 1000000000, 166, 1, 2, 0 }, /* actual: 996.0 MHz */ 1421eddb65e7SThierry Reding { 13000000, 1000000000, 153, 1, 2, 0 }, /* actual: 994.0 MHz */ 1422eddb65e7SThierry Reding { 38400000, 1000000000, 156, 3, 2, 0 }, /* actual: 998.4 MHz */ 14236b301a05SRhyland Klein { 0, 0, 0, 0, 0, 0 }, 14246b301a05SRhyland Klein }; 14256b301a05SRhyland Klein 14266b301a05SRhyland Klein static struct tegra_clk_pll_params pll_x_params = { 14276b301a05SRhyland Klein .input_min = 12000000, 14286b301a05SRhyland Klein .input_max = 800000000, 14296b301a05SRhyland Klein .cf_min = 12000000, 14306b301a05SRhyland Klein .cf_max = 38400000, 14316b301a05SRhyland Klein .vco_min = 1350000000, 14326b301a05SRhyland Klein .vco_max = 3000000000UL, 14336b301a05SRhyland Klein .base_reg = PLLX_BASE, 14346b301a05SRhyland Klein .misc_reg = PLLX_MISC0, 14356b301a05SRhyland Klein .lock_mask = PLL_BASE_LOCK, 14366b301a05SRhyland Klein .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 14376b301a05SRhyland Klein .lock_delay = 300, 14386b301a05SRhyland Klein .ext_misc_reg[0] = PLLX_MISC0, 14396b301a05SRhyland Klein .ext_misc_reg[1] = PLLX_MISC1, 14406b301a05SRhyland Klein .ext_misc_reg[2] = PLLX_MISC2, 14416b301a05SRhyland Klein .ext_misc_reg[3] = PLLX_MISC3, 14426b301a05SRhyland Klein .ext_misc_reg[4] = PLLX_MISC4, 14436b301a05SRhyland Klein .ext_misc_reg[5] = PLLX_MISC5, 14446b301a05SRhyland Klein .iddq_reg = PLLX_MISC3, 14456b301a05SRhyland Klein .iddq_bit_idx = PLLXP_IDDQ_BIT, 14466b301a05SRhyland Klein .max_p = PLL_QLIN_PDIV_MAX, 14476b301a05SRhyland Klein .mdiv_default = 2, 14486b301a05SRhyland Klein .dyn_ramp_reg = PLLX_MISC2, 14496b301a05SRhyland Klein .stepa_shift = 16, 14506b301a05SRhyland Klein .stepb_shift = 24, 14516b301a05SRhyland Klein .round_p_to_pdiv = pll_qlin_p_to_pdiv, 14526b301a05SRhyland Klein .pdiv_tohw = pll_qlin_pdiv_to_hw, 14536b301a05SRhyland Klein .div_nmp = &pllx_nmp, 14546b301a05SRhyland Klein .freq_table = pll_x_freq_table, 14556b301a05SRhyland Klein .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE, 14566b301a05SRhyland Klein .dyn_ramp = tegra210_pllx_dyn_ramp, 14576b301a05SRhyland Klein .set_defaults = tegra210_pllx_set_defaults, 14586b301a05SRhyland Klein .calc_rate = tegra210_pll_fixed_mdiv_cfg, 14596b301a05SRhyland Klein }; 14606b301a05SRhyland Klein 14616b301a05SRhyland Klein static struct div_nmp pllc_nmp = { 14626b301a05SRhyland Klein .divm_shift = 0, 14636b301a05SRhyland Klein .divm_width = 8, 14646b301a05SRhyland Klein .divn_shift = 10, 14656b301a05SRhyland Klein .divn_width = 8, 14666b301a05SRhyland Klein .divp_shift = 20, 14676b301a05SRhyland Klein .divp_width = 5, 14686b301a05SRhyland Klein }; 14696b301a05SRhyland Klein 14706b301a05SRhyland Klein static struct tegra_clk_pll_freq_table pll_cx_freq_table[] = { 1471eddb65e7SThierry Reding { 12000000, 510000000, 85, 1, 2, 0 }, 1472eddb65e7SThierry Reding { 13000000, 510000000, 78, 1, 2, 0 }, /* actual: 507.0 MHz */ 1473eddb65e7SThierry Reding { 38400000, 510000000, 79, 3, 2, 0 }, /* actual: 505.6 MHz */ 14746b301a05SRhyland Klein { 0, 0, 0, 0, 0, 0 }, 14756b301a05SRhyland Klein }; 14766b301a05SRhyland Klein 14776b301a05SRhyland Klein static struct tegra_clk_pll_params pll_c_params = { 14786b301a05SRhyland Klein .input_min = 12000000, 14796b301a05SRhyland Klein .input_max = 700000000, 14806b301a05SRhyland Klein .cf_min = 12000000, 14816b301a05SRhyland Klein .cf_max = 50000000, 14826b301a05SRhyland Klein .vco_min = 600000000, 14836b301a05SRhyland Klein .vco_max = 1200000000, 14846b301a05SRhyland Klein .base_reg = PLLC_BASE, 14856b301a05SRhyland Klein .misc_reg = PLLC_MISC0, 14866b301a05SRhyland Klein .lock_mask = PLL_BASE_LOCK, 14876b301a05SRhyland Klein .lock_delay = 300, 14886b301a05SRhyland Klein .iddq_reg = PLLC_MISC1, 14896b301a05SRhyland Klein .iddq_bit_idx = PLLCX_IDDQ_BIT, 14906b301a05SRhyland Klein .reset_reg = PLLC_MISC0, 14916b301a05SRhyland Klein .reset_bit_idx = PLLCX_RESET_BIT, 14926b301a05SRhyland Klein .max_p = PLL_QLIN_PDIV_MAX, 14936b301a05SRhyland Klein .ext_misc_reg[0] = PLLC_MISC0, 14946b301a05SRhyland Klein .ext_misc_reg[1] = PLLC_MISC1, 14956b301a05SRhyland Klein .ext_misc_reg[2] = PLLC_MISC2, 14966b301a05SRhyland Klein .ext_misc_reg[3] = PLLC_MISC3, 14976b301a05SRhyland Klein .round_p_to_pdiv = pll_qlin_p_to_pdiv, 14986b301a05SRhyland Klein .pdiv_tohw = pll_qlin_pdiv_to_hw, 14996b301a05SRhyland Klein .mdiv_default = 3, 15006b301a05SRhyland Klein .div_nmp = &pllc_nmp, 15016b301a05SRhyland Klein .freq_table = pll_cx_freq_table, 150214050118SRhyland Klein .flags = TEGRA_PLL_USE_LOCK, 15036b301a05SRhyland Klein .set_defaults = _pllc_set_defaults, 15046b301a05SRhyland Klein .calc_rate = tegra210_pll_fixed_mdiv_cfg, 15056b301a05SRhyland Klein }; 15066b301a05SRhyland Klein 15076b301a05SRhyland Klein static struct div_nmp pllcx_nmp = { 15086b301a05SRhyland Klein .divm_shift = 0, 15096b301a05SRhyland Klein .divm_width = 8, 15106b301a05SRhyland Klein .divn_shift = 10, 15116b301a05SRhyland Klein .divn_width = 8, 15126b301a05SRhyland Klein .divp_shift = 20, 15136b301a05SRhyland Klein .divp_width = 5, 15146b301a05SRhyland Klein }; 15156b301a05SRhyland Klein 15166b301a05SRhyland Klein static struct tegra_clk_pll_params pll_c2_params = { 15176b301a05SRhyland Klein .input_min = 12000000, 15186b301a05SRhyland Klein .input_max = 700000000, 15196b301a05SRhyland Klein .cf_min = 12000000, 15206b301a05SRhyland Klein .cf_max = 50000000, 15216b301a05SRhyland Klein .vco_min = 600000000, 15226b301a05SRhyland Klein .vco_max = 1200000000, 15236b301a05SRhyland Klein .base_reg = PLLC2_BASE, 15246b301a05SRhyland Klein .misc_reg = PLLC2_MISC0, 15256b301a05SRhyland Klein .iddq_reg = PLLC2_MISC1, 15266b301a05SRhyland Klein .iddq_bit_idx = PLLCX_IDDQ_BIT, 15276b301a05SRhyland Klein .reset_reg = PLLC2_MISC0, 15286b301a05SRhyland Klein .reset_bit_idx = PLLCX_RESET_BIT, 15296b301a05SRhyland Klein .lock_mask = PLLCX_BASE_LOCK, 15306b301a05SRhyland Klein .lock_delay = 300, 15316b301a05SRhyland Klein .round_p_to_pdiv = pll_qlin_p_to_pdiv, 15326b301a05SRhyland Klein .pdiv_tohw = pll_qlin_pdiv_to_hw, 15336b301a05SRhyland Klein .mdiv_default = 3, 15346b301a05SRhyland Klein .div_nmp = &pllcx_nmp, 15356b301a05SRhyland Klein .max_p = PLL_QLIN_PDIV_MAX, 15366b301a05SRhyland Klein .ext_misc_reg[0] = PLLC2_MISC0, 15376b301a05SRhyland Klein .ext_misc_reg[1] = PLLC2_MISC1, 15386b301a05SRhyland Klein .ext_misc_reg[2] = PLLC2_MISC2, 15396b301a05SRhyland Klein .ext_misc_reg[3] = PLLC2_MISC3, 15406b301a05SRhyland Klein .freq_table = pll_cx_freq_table, 154114050118SRhyland Klein .flags = TEGRA_PLL_USE_LOCK, 15426b301a05SRhyland Klein .set_defaults = _pllc2_set_defaults, 15436b301a05SRhyland Klein .calc_rate = tegra210_pll_fixed_mdiv_cfg, 15446b301a05SRhyland Klein }; 15456b301a05SRhyland Klein 15466b301a05SRhyland Klein static struct tegra_clk_pll_params pll_c3_params = { 15476b301a05SRhyland Klein .input_min = 12000000, 15486b301a05SRhyland Klein .input_max = 700000000, 15496b301a05SRhyland Klein .cf_min = 12000000, 15506b301a05SRhyland Klein .cf_max = 50000000, 15516b301a05SRhyland Klein .vco_min = 600000000, 15526b301a05SRhyland Klein .vco_max = 1200000000, 15536b301a05SRhyland Klein .base_reg = PLLC3_BASE, 15546b301a05SRhyland Klein .misc_reg = PLLC3_MISC0, 15556b301a05SRhyland Klein .lock_mask = PLLCX_BASE_LOCK, 15566b301a05SRhyland Klein .lock_delay = 300, 15576b301a05SRhyland Klein .iddq_reg = PLLC3_MISC1, 15586b301a05SRhyland Klein .iddq_bit_idx = PLLCX_IDDQ_BIT, 15596b301a05SRhyland Klein .reset_reg = PLLC3_MISC0, 15606b301a05SRhyland Klein .reset_bit_idx = PLLCX_RESET_BIT, 15616b301a05SRhyland Klein .round_p_to_pdiv = pll_qlin_p_to_pdiv, 15626b301a05SRhyland Klein .pdiv_tohw = pll_qlin_pdiv_to_hw, 15636b301a05SRhyland Klein .mdiv_default = 3, 15646b301a05SRhyland Klein .div_nmp = &pllcx_nmp, 15656b301a05SRhyland Klein .max_p = PLL_QLIN_PDIV_MAX, 15666b301a05SRhyland Klein .ext_misc_reg[0] = PLLC3_MISC0, 15676b301a05SRhyland Klein .ext_misc_reg[1] = PLLC3_MISC1, 15686b301a05SRhyland Klein .ext_misc_reg[2] = PLLC3_MISC2, 15696b301a05SRhyland Klein .ext_misc_reg[3] = PLLC3_MISC3, 15706b301a05SRhyland Klein .freq_table = pll_cx_freq_table, 157114050118SRhyland Klein .flags = TEGRA_PLL_USE_LOCK, 15726b301a05SRhyland Klein .set_defaults = _pllc3_set_defaults, 15736b301a05SRhyland Klein .calc_rate = tegra210_pll_fixed_mdiv_cfg, 15746b301a05SRhyland Klein }; 15756b301a05SRhyland Klein 15766b301a05SRhyland Klein static struct div_nmp pllss_nmp = { 15776b301a05SRhyland Klein .divm_shift = 0, 15786b301a05SRhyland Klein .divm_width = 8, 15796b301a05SRhyland Klein .divn_shift = 8, 15806b301a05SRhyland Klein .divn_width = 8, 15816b301a05SRhyland Klein .divp_shift = 19, 15826b301a05SRhyland Klein .divp_width = 5, 15836b301a05SRhyland Klein }; 15846b301a05SRhyland Klein 15856b301a05SRhyland Klein static struct tegra_clk_pll_freq_table pll_c4_vco_freq_table[] = { 1586eddb65e7SThierry Reding { 12000000, 600000000, 50, 1, 1, 0 }, 1587eddb65e7SThierry Reding { 13000000, 600000000, 46, 1, 1, 0 }, /* actual: 598.0 MHz */ 1588eddb65e7SThierry Reding { 38400000, 600000000, 62, 4, 1, 0 }, /* actual: 595.2 MHz */ 15896b301a05SRhyland Klein { 0, 0, 0, 0, 0, 0 }, 15906b301a05SRhyland Klein }; 15916b301a05SRhyland Klein 15926b301a05SRhyland Klein static const struct clk_div_table pll_vco_post_div_table[] = { 15936b301a05SRhyland Klein { .val = 0, .div = 1 }, 15946b301a05SRhyland Klein { .val = 1, .div = 2 }, 15956b301a05SRhyland Klein { .val = 2, .div = 3 }, 15966b301a05SRhyland Klein { .val = 3, .div = 4 }, 15976b301a05SRhyland Klein { .val = 4, .div = 5 }, 15986b301a05SRhyland Klein { .val = 5, .div = 6 }, 15996b301a05SRhyland Klein { .val = 6, .div = 8 }, 16006b301a05SRhyland Klein { .val = 7, .div = 10 }, 16016b301a05SRhyland Klein { .val = 8, .div = 12 }, 16026b301a05SRhyland Klein { .val = 9, .div = 16 }, 16036b301a05SRhyland Klein { .val = 10, .div = 12 }, 16046b301a05SRhyland Klein { .val = 11, .div = 16 }, 16056b301a05SRhyland Klein { .val = 12, .div = 20 }, 16066b301a05SRhyland Klein { .val = 13, .div = 24 }, 16076b301a05SRhyland Klein { .val = 14, .div = 32 }, 16086b301a05SRhyland Klein { .val = 0, .div = 0 }, 16096b301a05SRhyland Klein }; 16106b301a05SRhyland Klein 16116b301a05SRhyland Klein static struct tegra_clk_pll_params pll_c4_vco_params = { 16126b301a05SRhyland Klein .input_min = 9600000, 16136b301a05SRhyland Klein .input_max = 800000000, 16146b301a05SRhyland Klein .cf_min = 9600000, 16156b301a05SRhyland Klein .cf_max = 19200000, 16166b301a05SRhyland Klein .vco_min = 500000000, 16176b301a05SRhyland Klein .vco_max = 1080000000, 16186b301a05SRhyland Klein .base_reg = PLLC4_BASE, 16196b301a05SRhyland Klein .misc_reg = PLLC4_MISC0, 16206b301a05SRhyland Klein .lock_mask = PLL_BASE_LOCK, 16216b301a05SRhyland Klein .lock_delay = 300, 16226b301a05SRhyland Klein .max_p = PLL_QLIN_PDIV_MAX, 16236b301a05SRhyland Klein .ext_misc_reg[0] = PLLC4_MISC0, 16246b301a05SRhyland Klein .iddq_reg = PLLC4_BASE, 16256b301a05SRhyland Klein .iddq_bit_idx = PLLSS_IDDQ_BIT, 16266b301a05SRhyland Klein .round_p_to_pdiv = pll_qlin_p_to_pdiv, 16276b301a05SRhyland Klein .pdiv_tohw = pll_qlin_pdiv_to_hw, 16286b301a05SRhyland Klein .mdiv_default = 3, 16296b301a05SRhyland Klein .div_nmp = &pllss_nmp, 16306b301a05SRhyland Klein .freq_table = pll_c4_vco_freq_table, 16316b301a05SRhyland Klein .set_defaults = tegra210_pllc4_set_defaults, 163214050118SRhyland Klein .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_VCO_OUT, 16336b301a05SRhyland Klein .calc_rate = tegra210_pll_fixed_mdiv_cfg, 16346b301a05SRhyland Klein }; 16356b301a05SRhyland Klein 16366b301a05SRhyland Klein static struct tegra_clk_pll_freq_table pll_m_freq_table[] = { 1637eddb65e7SThierry Reding { 12000000, 800000000, 66, 1, 1, 0 }, /* actual: 792.0 MHz */ 1638eddb65e7SThierry Reding { 13000000, 800000000, 61, 1, 1, 0 }, /* actual: 793.0 MHz */ 1639eddb65e7SThierry Reding { 38400000, 297600000, 93, 4, 3, 0 }, 1640eddb65e7SThierry Reding { 38400000, 400000000, 125, 4, 3, 0 }, 1641eddb65e7SThierry Reding { 38400000, 532800000, 111, 4, 2, 0 }, 1642eddb65e7SThierry Reding { 38400000, 665600000, 104, 3, 2, 0 }, 1643eddb65e7SThierry Reding { 38400000, 800000000, 125, 3, 2, 0 }, 1644eddb65e7SThierry Reding { 38400000, 931200000, 97, 4, 1, 0 }, 1645eddb65e7SThierry Reding { 38400000, 1065600000, 111, 4, 1, 0 }, 1646eddb65e7SThierry Reding { 38400000, 1200000000, 125, 4, 1, 0 }, 1647eddb65e7SThierry Reding { 38400000, 1331200000, 104, 3, 1, 0 }, 1648eddb65e7SThierry Reding { 38400000, 1459200000, 76, 2, 1, 0 }, 1649eddb65e7SThierry Reding { 38400000, 1600000000, 125, 3, 1, 0 }, 16506b301a05SRhyland Klein { 0, 0, 0, 0, 0, 0 }, 16516b301a05SRhyland Klein }; 16526b301a05SRhyland Klein 16536b301a05SRhyland Klein static struct div_nmp pllm_nmp = { 16546b301a05SRhyland Klein .divm_shift = 0, 16556b301a05SRhyland Klein .divm_width = 8, 16566b301a05SRhyland Klein .override_divm_shift = 0, 16576b301a05SRhyland Klein .divn_shift = 8, 16586b301a05SRhyland Klein .divn_width = 8, 16596b301a05SRhyland Klein .override_divn_shift = 8, 16606b301a05SRhyland Klein .divp_shift = 20, 16616b301a05SRhyland Klein .divp_width = 5, 16626b301a05SRhyland Klein .override_divp_shift = 27, 16636b301a05SRhyland Klein }; 16646b301a05SRhyland Klein 16656b301a05SRhyland Klein static struct tegra_clk_pll_params pll_m_params = { 16666b301a05SRhyland Klein .input_min = 9600000, 16676b301a05SRhyland Klein .input_max = 500000000, 16686b301a05SRhyland Klein .cf_min = 9600000, 16696b301a05SRhyland Klein .cf_max = 19200000, 16706b301a05SRhyland Klein .vco_min = 800000000, 16716b301a05SRhyland Klein .vco_max = 1866000000, 16726b301a05SRhyland Klein .base_reg = PLLM_BASE, 1673474f2ba2SRhyland Klein .misc_reg = PLLM_MISC2, 16746b301a05SRhyland Klein .lock_mask = PLL_BASE_LOCK, 16756b301a05SRhyland Klein .lock_enable_bit_idx = PLLM_MISC_LOCK_ENABLE, 16766b301a05SRhyland Klein .lock_delay = 300, 1677474f2ba2SRhyland Klein .iddq_reg = PLLM_MISC2, 16786b301a05SRhyland Klein .iddq_bit_idx = PLLM_IDDQ_BIT, 16796b301a05SRhyland Klein .max_p = PLL_QLIN_PDIV_MAX, 1680474f2ba2SRhyland Klein .ext_misc_reg[0] = PLLM_MISC2, 1681d9e65791SJon Hunter .ext_misc_reg[1] = PLLM_MISC1, 16826b301a05SRhyland Klein .round_p_to_pdiv = pll_qlin_p_to_pdiv, 16836b301a05SRhyland Klein .pdiv_tohw = pll_qlin_pdiv_to_hw, 16846b301a05SRhyland Klein .div_nmp = &pllm_nmp, 16856b301a05SRhyland Klein .pmc_divnm_reg = PMC_PLLM_WB0_OVERRIDE, 16866b301a05SRhyland Klein .pmc_divp_reg = PMC_PLLM_WB0_OVERRIDE_2, 16876b301a05SRhyland Klein .freq_table = pll_m_freq_table, 16886b301a05SRhyland Klein .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE, 16896b301a05SRhyland Klein .calc_rate = tegra210_pll_fixed_mdiv_cfg, 16906b301a05SRhyland Klein }; 16916b301a05SRhyland Klein 16926b301a05SRhyland Klein static struct tegra_clk_pll_params pll_mb_params = { 16936b301a05SRhyland Klein .input_min = 9600000, 16946b301a05SRhyland Klein .input_max = 500000000, 16956b301a05SRhyland Klein .cf_min = 9600000, 16966b301a05SRhyland Klein .cf_max = 19200000, 16976b301a05SRhyland Klein .vco_min = 800000000, 16986b301a05SRhyland Klein .vco_max = 1866000000, 16996b301a05SRhyland Klein .base_reg = PLLMB_BASE, 1700474f2ba2SRhyland Klein .misc_reg = PLLMB_MISC1, 17016b301a05SRhyland Klein .lock_mask = PLL_BASE_LOCK, 17026b301a05SRhyland Klein .lock_delay = 300, 1703474f2ba2SRhyland Klein .iddq_reg = PLLMB_MISC1, 17046b301a05SRhyland Klein .iddq_bit_idx = PLLMB_IDDQ_BIT, 17056b301a05SRhyland Klein .max_p = PLL_QLIN_PDIV_MAX, 1706474f2ba2SRhyland Klein .ext_misc_reg[0] = PLLMB_MISC1, 17076b301a05SRhyland Klein .round_p_to_pdiv = pll_qlin_p_to_pdiv, 17086b301a05SRhyland Klein .pdiv_tohw = pll_qlin_pdiv_to_hw, 17096b301a05SRhyland Klein .div_nmp = &pllm_nmp, 17106b301a05SRhyland Klein .freq_table = pll_m_freq_table, 171114050118SRhyland Klein .flags = TEGRA_PLL_USE_LOCK, 17126b301a05SRhyland Klein .set_defaults = tegra210_pllmb_set_defaults, 17136b301a05SRhyland Klein .calc_rate = tegra210_pll_fixed_mdiv_cfg, 17146b301a05SRhyland Klein }; 17156b301a05SRhyland Klein 17166b301a05SRhyland Klein 17176b301a05SRhyland Klein static struct tegra_clk_pll_freq_table pll_e_freq_table[] = { 17186b301a05SRhyland Klein /* PLLE special case: use cpcon field to store cml divider value */ 17196b301a05SRhyland Klein { 672000000, 100000000, 125, 42, 0, 13 }, 17206b301a05SRhyland Klein { 624000000, 100000000, 125, 39, 0, 13 }, 17216b301a05SRhyland Klein { 336000000, 100000000, 125, 21, 0, 13 }, 17226b301a05SRhyland Klein { 312000000, 100000000, 200, 26, 0, 14 }, 17236b301a05SRhyland Klein { 38400000, 100000000, 125, 2, 0, 14 }, 17246b301a05SRhyland Klein { 12000000, 100000000, 200, 1, 0, 14 }, 17256b301a05SRhyland Klein { 0, 0, 0, 0, 0, 0 }, 17266b301a05SRhyland Klein }; 17276b301a05SRhyland Klein 17286b301a05SRhyland Klein static struct div_nmp plle_nmp = { 17296b301a05SRhyland Klein .divm_shift = 0, 17306b301a05SRhyland Klein .divm_width = 8, 17316b301a05SRhyland Klein .divn_shift = 8, 17326b301a05SRhyland Klein .divn_width = 8, 17336b301a05SRhyland Klein .divp_shift = 24, 17346b301a05SRhyland Klein .divp_width = 5, 17356b301a05SRhyland Klein }; 17366b301a05SRhyland Klein 17376b301a05SRhyland Klein static struct tegra_clk_pll_params pll_e_params = { 17386b301a05SRhyland Klein .input_min = 12000000, 17396b301a05SRhyland Klein .input_max = 800000000, 17406b301a05SRhyland Klein .cf_min = 12000000, 17416b301a05SRhyland Klein .cf_max = 38400000, 17426b301a05SRhyland Klein .vco_min = 1600000000, 17436b301a05SRhyland Klein .vco_max = 2500000000U, 17446b301a05SRhyland Klein .base_reg = PLLE_BASE, 17456b301a05SRhyland Klein .misc_reg = PLLE_MISC0, 17466b301a05SRhyland Klein .aux_reg = PLLE_AUX, 17476b301a05SRhyland Klein .lock_mask = PLLE_MISC_LOCK, 17486b301a05SRhyland Klein .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE, 17496b301a05SRhyland Klein .lock_delay = 300, 17506b301a05SRhyland Klein .div_nmp = &plle_nmp, 17516b301a05SRhyland Klein .freq_table = pll_e_freq_table, 17526b301a05SRhyland Klein .flags = TEGRA_PLL_FIXED | TEGRA_PLL_LOCK_MISC | TEGRA_PLL_USE_LOCK | 17536b301a05SRhyland Klein TEGRA_PLL_HAS_LOCK_ENABLE, 17546b301a05SRhyland Klein .fixed_rate = 100000000, 17556b301a05SRhyland Klein .calc_rate = tegra210_pll_fixed_mdiv_cfg, 17566b301a05SRhyland Klein }; 17576b301a05SRhyland Klein 17586b301a05SRhyland Klein static struct tegra_clk_pll_freq_table pll_re_vco_freq_table[] = { 1759eddb65e7SThierry Reding { 12000000, 672000000, 56, 1, 1, 0 }, 1760eddb65e7SThierry Reding { 13000000, 672000000, 51, 1, 1, 0 }, /* actual: 663.0 MHz */ 1761eddb65e7SThierry Reding { 38400000, 672000000, 70, 4, 1, 0 }, 17626b301a05SRhyland Klein { 0, 0, 0, 0, 0, 0 }, 17636b301a05SRhyland Klein }; 17646b301a05SRhyland Klein 17656b301a05SRhyland Klein static struct div_nmp pllre_nmp = { 17666b301a05SRhyland Klein .divm_shift = 0, 17676b301a05SRhyland Klein .divm_width = 8, 17686b301a05SRhyland Klein .divn_shift = 8, 17696b301a05SRhyland Klein .divn_width = 8, 17706b301a05SRhyland Klein .divp_shift = 16, 17716b301a05SRhyland Klein .divp_width = 5, 17726b301a05SRhyland Klein }; 17736b301a05SRhyland Klein 17746b301a05SRhyland Klein static struct tegra_clk_pll_params pll_re_vco_params = { 17756b301a05SRhyland Klein .input_min = 9600000, 17766b301a05SRhyland Klein .input_max = 800000000, 17776b301a05SRhyland Klein .cf_min = 9600000, 17786b301a05SRhyland Klein .cf_max = 19200000, 17796b301a05SRhyland Klein .vco_min = 350000000, 17806b301a05SRhyland Klein .vco_max = 700000000, 17816b301a05SRhyland Klein .base_reg = PLLRE_BASE, 17826b301a05SRhyland Klein .misc_reg = PLLRE_MISC0, 17836b301a05SRhyland Klein .lock_mask = PLLRE_MISC_LOCK, 17846b301a05SRhyland Klein .lock_delay = 300, 17856b301a05SRhyland Klein .max_p = PLL_QLIN_PDIV_MAX, 17866b301a05SRhyland Klein .ext_misc_reg[0] = PLLRE_MISC0, 17876b301a05SRhyland Klein .iddq_reg = PLLRE_MISC0, 17886b301a05SRhyland Klein .iddq_bit_idx = PLLRE_IDDQ_BIT, 17896b301a05SRhyland Klein .round_p_to_pdiv = pll_qlin_p_to_pdiv, 17906b301a05SRhyland Klein .pdiv_tohw = pll_qlin_pdiv_to_hw, 17916b301a05SRhyland Klein .div_nmp = &pllre_nmp, 17926b301a05SRhyland Klein .freq_table = pll_re_vco_freq_table, 179314050118SRhyland Klein .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_LOCK_MISC | TEGRA_PLL_VCO_OUT, 17946b301a05SRhyland Klein .set_defaults = tegra210_pllre_set_defaults, 17956b301a05SRhyland Klein .calc_rate = tegra210_pll_fixed_mdiv_cfg, 17966b301a05SRhyland Klein }; 17976b301a05SRhyland Klein 17986b301a05SRhyland Klein static struct div_nmp pllp_nmp = { 17996b301a05SRhyland Klein .divm_shift = 0, 18006b301a05SRhyland Klein .divm_width = 8, 18016b301a05SRhyland Klein .divn_shift = 10, 18026b301a05SRhyland Klein .divn_width = 8, 18036b301a05SRhyland Klein .divp_shift = 20, 18046b301a05SRhyland Klein .divp_width = 5, 18056b301a05SRhyland Klein }; 18066b301a05SRhyland Klein 18076b301a05SRhyland Klein static struct tegra_clk_pll_freq_table pll_p_freq_table[] = { 1808eddb65e7SThierry Reding { 12000000, 408000000, 34, 1, 1, 0 }, 1809eddb65e7SThierry Reding { 38400000, 408000000, 85, 8, 1, 0 }, /* cf = 4.8MHz, allowed exception */ 18106b301a05SRhyland Klein { 0, 0, 0, 0, 0, 0 }, 18116b301a05SRhyland Klein }; 18126b301a05SRhyland Klein 18136b301a05SRhyland Klein static struct tegra_clk_pll_params pll_p_params = { 18146b301a05SRhyland Klein .input_min = 9600000, 18156b301a05SRhyland Klein .input_max = 800000000, 18166b301a05SRhyland Klein .cf_min = 9600000, 18176b301a05SRhyland Klein .cf_max = 19200000, 18186b301a05SRhyland Klein .vco_min = 350000000, 18196b301a05SRhyland Klein .vco_max = 700000000, 18206b301a05SRhyland Klein .base_reg = PLLP_BASE, 18216b301a05SRhyland Klein .misc_reg = PLLP_MISC0, 18226b301a05SRhyland Klein .lock_mask = PLL_BASE_LOCK, 18236b301a05SRhyland Klein .lock_delay = 300, 18246b301a05SRhyland Klein .iddq_reg = PLLP_MISC0, 18256b301a05SRhyland Klein .iddq_bit_idx = PLLXP_IDDQ_BIT, 18266b301a05SRhyland Klein .ext_misc_reg[0] = PLLP_MISC0, 18276b301a05SRhyland Klein .ext_misc_reg[1] = PLLP_MISC1, 18286b301a05SRhyland Klein .div_nmp = &pllp_nmp, 18296b301a05SRhyland Klein .freq_table = pll_p_freq_table, 18306b301a05SRhyland Klein .fixed_rate = 408000000, 183114050118SRhyland Klein .flags = TEGRA_PLL_FIXED | TEGRA_PLL_USE_LOCK | TEGRA_PLL_VCO_OUT, 18326b301a05SRhyland Klein .set_defaults = tegra210_pllp_set_defaults, 18336b301a05SRhyland Klein .calc_rate = tegra210_pll_fixed_mdiv_cfg, 18346b301a05SRhyland Klein }; 18356b301a05SRhyland Klein 18366b301a05SRhyland Klein static struct tegra_clk_pll_params pll_a1_params = { 18376b301a05SRhyland Klein .input_min = 12000000, 18386b301a05SRhyland Klein .input_max = 700000000, 18396b301a05SRhyland Klein .cf_min = 12000000, 18406b301a05SRhyland Klein .cf_max = 50000000, 18416b301a05SRhyland Klein .vco_min = 600000000, 18426b301a05SRhyland Klein .vco_max = 1200000000, 18436b301a05SRhyland Klein .base_reg = PLLA1_BASE, 18446b301a05SRhyland Klein .misc_reg = PLLA1_MISC0, 18456b301a05SRhyland Klein .lock_mask = PLLCX_BASE_LOCK, 18466b301a05SRhyland Klein .lock_delay = 300, 18479326947fSPeter De Schrijver .iddq_reg = PLLA1_MISC1, 18486b301a05SRhyland Klein .iddq_bit_idx = PLLCX_IDDQ_BIT, 18496b301a05SRhyland Klein .reset_reg = PLLA1_MISC0, 18506b301a05SRhyland Klein .reset_bit_idx = PLLCX_RESET_BIT, 18516b301a05SRhyland Klein .round_p_to_pdiv = pll_qlin_p_to_pdiv, 18526b301a05SRhyland Klein .pdiv_tohw = pll_qlin_pdiv_to_hw, 18536b301a05SRhyland Klein .div_nmp = &pllc_nmp, 18546b301a05SRhyland Klein .ext_misc_reg[0] = PLLA1_MISC0, 18556b301a05SRhyland Klein .ext_misc_reg[1] = PLLA1_MISC1, 18566b301a05SRhyland Klein .ext_misc_reg[2] = PLLA1_MISC2, 18576b301a05SRhyland Klein .ext_misc_reg[3] = PLLA1_MISC3, 18586b301a05SRhyland Klein .freq_table = pll_cx_freq_table, 185914050118SRhyland Klein .flags = TEGRA_PLL_USE_LOCK, 18606b301a05SRhyland Klein .set_defaults = _plla1_set_defaults, 18616b301a05SRhyland Klein .calc_rate = tegra210_pll_fixed_mdiv_cfg, 18626b301a05SRhyland Klein }; 18636b301a05SRhyland Klein 18646b301a05SRhyland Klein static struct div_nmp plla_nmp = { 18656b301a05SRhyland Klein .divm_shift = 0, 18666b301a05SRhyland Klein .divm_width = 8, 18676b301a05SRhyland Klein .divn_shift = 8, 18686b301a05SRhyland Klein .divn_width = 8, 18696b301a05SRhyland Klein .divp_shift = 20, 18706b301a05SRhyland Klein .divp_width = 5, 18716b301a05SRhyland Klein }; 18726b301a05SRhyland Klein 18736b301a05SRhyland Klein static struct tegra_clk_pll_freq_table pll_a_freq_table[] = { 1874eddb65e7SThierry Reding { 12000000, 282240000, 47, 1, 2, 1, 0xf148 }, /* actual: 282240234 */ 1875eddb65e7SThierry Reding { 12000000, 368640000, 61, 1, 2, 1, 0xfe15 }, /* actual: 368640381 */ 1876eddb65e7SThierry Reding { 12000000, 240000000, 60, 1, 3, 1, 0 }, 1877eddb65e7SThierry Reding { 13000000, 282240000, 43, 1, 2, 1, 0xfd7d }, /* actual: 282239807 */ 1878eddb65e7SThierry Reding { 13000000, 368640000, 56, 1, 2, 1, 0x06d8 }, /* actual: 368640137 */ 1879eddb65e7SThierry Reding { 13000000, 240000000, 55, 1, 3, 1, 0 }, /* actual: 238.3 MHz */ 1880eddb65e7SThierry Reding { 38400000, 282240000, 44, 3, 2, 1, 0xf333 }, /* actual: 282239844 */ 1881eddb65e7SThierry Reding { 38400000, 368640000, 57, 3, 2, 1, 0x0333 }, /* actual: 368639844 */ 18826b301a05SRhyland Klein { 38400000, 240000000, 75, 3, 3, 1, 0 }, 18836b301a05SRhyland Klein { 0, 0, 0, 0, 0, 0, 0 }, 18846b301a05SRhyland Klein }; 18856b301a05SRhyland Klein 18866b301a05SRhyland Klein static struct tegra_clk_pll_params pll_a_params = { 18876b301a05SRhyland Klein .input_min = 12000000, 18886b301a05SRhyland Klein .input_max = 800000000, 18896b301a05SRhyland Klein .cf_min = 12000000, 18906b301a05SRhyland Klein .cf_max = 19200000, 18916b301a05SRhyland Klein .vco_min = 500000000, 18926b301a05SRhyland Klein .vco_max = 1000000000, 18936b301a05SRhyland Klein .base_reg = PLLA_BASE, 18946b301a05SRhyland Klein .misc_reg = PLLA_MISC0, 18956b301a05SRhyland Klein .lock_mask = PLL_BASE_LOCK, 18966b301a05SRhyland Klein .lock_delay = 300, 18976b301a05SRhyland Klein .round_p_to_pdiv = pll_qlin_p_to_pdiv, 18986b301a05SRhyland Klein .pdiv_tohw = pll_qlin_pdiv_to_hw, 18996b301a05SRhyland Klein .iddq_reg = PLLA_BASE, 19006b301a05SRhyland Klein .iddq_bit_idx = PLLA_IDDQ_BIT, 19016b301a05SRhyland Klein .div_nmp = &plla_nmp, 19026b301a05SRhyland Klein .sdm_din_reg = PLLA_MISC1, 19036b301a05SRhyland Klein .sdm_din_mask = PLLA_SDM_DIN_MASK, 19046b301a05SRhyland Klein .sdm_ctrl_reg = PLLA_MISC2, 19056b301a05SRhyland Klein .sdm_ctrl_en_mask = PLLA_SDM_EN_MASK, 19066b301a05SRhyland Klein .ext_misc_reg[0] = PLLA_MISC0, 19076b301a05SRhyland Klein .ext_misc_reg[1] = PLLA_MISC1, 19086b301a05SRhyland Klein .ext_misc_reg[2] = PLLA_MISC2, 19096b301a05SRhyland Klein .freq_table = pll_a_freq_table, 191014050118SRhyland Klein .flags = TEGRA_PLL_USE_LOCK | TEGRA_MDIV_NEW, 19116b301a05SRhyland Klein .set_defaults = tegra210_plla_set_defaults, 19126b301a05SRhyland Klein .calc_rate = tegra210_pll_fixed_mdiv_cfg, 19136b301a05SRhyland Klein .set_gain = tegra210_clk_pll_set_gain, 19146b301a05SRhyland Klein .adjust_vco = tegra210_clk_adjust_vco_min, 19156b301a05SRhyland Klein }; 19166b301a05SRhyland Klein 19176b301a05SRhyland Klein static struct div_nmp plld_nmp = { 19186b301a05SRhyland Klein .divm_shift = 0, 19196b301a05SRhyland Klein .divm_width = 8, 19206b301a05SRhyland Klein .divn_shift = 11, 19216b301a05SRhyland Klein .divn_width = 8, 19226b301a05SRhyland Klein .divp_shift = 20, 19236b301a05SRhyland Klein .divp_width = 3, 19246b301a05SRhyland Klein }; 19256b301a05SRhyland Klein 19266b301a05SRhyland Klein static struct tegra_clk_pll_freq_table pll_d_freq_table[] = { 1927eddb65e7SThierry Reding { 12000000, 594000000, 99, 1, 2, 0, 0 }, 1928eddb65e7SThierry Reding { 13000000, 594000000, 91, 1, 2, 0, 0xfc4f }, /* actual: 594000183 */ 1929eddb65e7SThierry Reding { 38400000, 594000000, 30, 1, 2, 0, 0x0e00 }, 19306b301a05SRhyland Klein { 0, 0, 0, 0, 0, 0, 0 }, 19316b301a05SRhyland Klein }; 19326b301a05SRhyland Klein 19336b301a05SRhyland Klein static struct tegra_clk_pll_params pll_d_params = { 19346b301a05SRhyland Klein .input_min = 12000000, 19356b301a05SRhyland Klein .input_max = 800000000, 19366b301a05SRhyland Klein .cf_min = 12000000, 19376b301a05SRhyland Klein .cf_max = 38400000, 19386b301a05SRhyland Klein .vco_min = 750000000, 19396b301a05SRhyland Klein .vco_max = 1500000000, 19406b301a05SRhyland Klein .base_reg = PLLD_BASE, 19416b301a05SRhyland Klein .misc_reg = PLLD_MISC0, 19426b301a05SRhyland Klein .lock_mask = PLL_BASE_LOCK, 19436b301a05SRhyland Klein .lock_delay = 1000, 19446b301a05SRhyland Klein .iddq_reg = PLLD_MISC0, 19456b301a05SRhyland Klein .iddq_bit_idx = PLLD_IDDQ_BIT, 19466b301a05SRhyland Klein .round_p_to_pdiv = pll_expo_p_to_pdiv, 19476b301a05SRhyland Klein .pdiv_tohw = pll_expo_pdiv_to_hw, 19486b301a05SRhyland Klein .div_nmp = &plld_nmp, 19496b301a05SRhyland Klein .sdm_din_reg = PLLD_MISC0, 19506b301a05SRhyland Klein .sdm_din_mask = PLLA_SDM_DIN_MASK, 19516b301a05SRhyland Klein .sdm_ctrl_reg = PLLD_MISC0, 19526b301a05SRhyland Klein .sdm_ctrl_en_mask = PLLD_SDM_EN_MASK, 19536b301a05SRhyland Klein .ext_misc_reg[0] = PLLD_MISC0, 19546b301a05SRhyland Klein .ext_misc_reg[1] = PLLD_MISC1, 19556b301a05SRhyland Klein .freq_table = pll_d_freq_table, 195614050118SRhyland Klein .flags = TEGRA_PLL_USE_LOCK, 19576b301a05SRhyland Klein .mdiv_default = 1, 19586b301a05SRhyland Klein .set_defaults = tegra210_plld_set_defaults, 19596b301a05SRhyland Klein .calc_rate = tegra210_pll_fixed_mdiv_cfg, 19606b301a05SRhyland Klein .set_gain = tegra210_clk_pll_set_gain, 19616b301a05SRhyland Klein .adjust_vco = tegra210_clk_adjust_vco_min, 19626b301a05SRhyland Klein }; 19636b301a05SRhyland Klein 19646b301a05SRhyland Klein static struct tegra_clk_pll_freq_table tegra210_pll_d2_freq_table[] = { 1965eddb65e7SThierry Reding { 12000000, 594000000, 99, 1, 2, 0, 0xf000 }, 1966eddb65e7SThierry Reding { 13000000, 594000000, 91, 1, 2, 0, 0xfc4f }, /* actual: 594000183 */ 1967eddb65e7SThierry Reding { 38400000, 594000000, 30, 1, 2, 0, 0x0e00 }, 19686b301a05SRhyland Klein { 0, 0, 0, 0, 0, 0, 0 }, 19696b301a05SRhyland Klein }; 19706b301a05SRhyland Klein 19716b301a05SRhyland Klein /* s/w policy, always tegra_pll_ref */ 19726b301a05SRhyland Klein static struct tegra_clk_pll_params pll_d2_params = { 19736b301a05SRhyland Klein .input_min = 12000000, 19746b301a05SRhyland Klein .input_max = 800000000, 19756b301a05SRhyland Klein .cf_min = 12000000, 19766b301a05SRhyland Klein .cf_max = 38400000, 19776b301a05SRhyland Klein .vco_min = 750000000, 19786b301a05SRhyland Klein .vco_max = 1500000000, 19796b301a05SRhyland Klein .base_reg = PLLD2_BASE, 19806b301a05SRhyland Klein .misc_reg = PLLD2_MISC0, 19816b301a05SRhyland Klein .lock_mask = PLL_BASE_LOCK, 19826b301a05SRhyland Klein .lock_delay = 300, 19836b301a05SRhyland Klein .iddq_reg = PLLD2_BASE, 19846b301a05SRhyland Klein .iddq_bit_idx = PLLSS_IDDQ_BIT, 19856b301a05SRhyland Klein .sdm_din_reg = PLLD2_MISC3, 19866b301a05SRhyland Klein .sdm_din_mask = PLLA_SDM_DIN_MASK, 19876b301a05SRhyland Klein .sdm_ctrl_reg = PLLD2_MISC1, 19886b301a05SRhyland Klein .sdm_ctrl_en_mask = PLLD2_SDM_EN_MASK, 1989e2f71656SThierry Reding /* disable spread-spectrum for pll_d2 */ 1990e2f71656SThierry Reding .ssc_ctrl_reg = 0, 1991e2f71656SThierry Reding .ssc_ctrl_en_mask = 0, 19926b301a05SRhyland Klein .round_p_to_pdiv = pll_qlin_p_to_pdiv, 19936b301a05SRhyland Klein .pdiv_tohw = pll_qlin_pdiv_to_hw, 19946b301a05SRhyland Klein .div_nmp = &pllss_nmp, 19956b301a05SRhyland Klein .ext_misc_reg[0] = PLLD2_MISC0, 19966b301a05SRhyland Klein .ext_misc_reg[1] = PLLD2_MISC1, 19976b301a05SRhyland Klein .ext_misc_reg[2] = PLLD2_MISC2, 19986b301a05SRhyland Klein .ext_misc_reg[3] = PLLD2_MISC3, 19996b301a05SRhyland Klein .max_p = PLL_QLIN_PDIV_MAX, 20006b301a05SRhyland Klein .mdiv_default = 1, 20016b301a05SRhyland Klein .freq_table = tegra210_pll_d2_freq_table, 20026b301a05SRhyland Klein .set_defaults = tegra210_plld2_set_defaults, 200314050118SRhyland Klein .flags = TEGRA_PLL_USE_LOCK, 20046b301a05SRhyland Klein .calc_rate = tegra210_pll_fixed_mdiv_cfg, 20056b301a05SRhyland Klein .set_gain = tegra210_clk_pll_set_gain, 20066b301a05SRhyland Klein .adjust_vco = tegra210_clk_adjust_vco_min, 20076b301a05SRhyland Klein }; 20086b301a05SRhyland Klein 20096b301a05SRhyland Klein static struct tegra_clk_pll_freq_table pll_dp_freq_table[] = { 2010eddb65e7SThierry Reding { 12000000, 270000000, 90, 1, 4, 0, 0xf000 }, 2011eddb65e7SThierry Reding { 13000000, 270000000, 83, 1, 4, 0, 0xf000 }, /* actual: 269.8 MHz */ 2012eddb65e7SThierry Reding { 38400000, 270000000, 28, 1, 4, 0, 0xf400 }, 20136b301a05SRhyland Klein { 0, 0, 0, 0, 0, 0, 0 }, 20146b301a05SRhyland Klein }; 20156b301a05SRhyland Klein 20166b301a05SRhyland Klein static struct tegra_clk_pll_params pll_dp_params = { 20176b301a05SRhyland Klein .input_min = 12000000, 20186b301a05SRhyland Klein .input_max = 800000000, 20196b301a05SRhyland Klein .cf_min = 12000000, 20206b301a05SRhyland Klein .cf_max = 38400000, 20216b301a05SRhyland Klein .vco_min = 750000000, 20226b301a05SRhyland Klein .vco_max = 1500000000, 20236b301a05SRhyland Klein .base_reg = PLLDP_BASE, 20246b301a05SRhyland Klein .misc_reg = PLLDP_MISC, 20256b301a05SRhyland Klein .lock_mask = PLL_BASE_LOCK, 20266b301a05SRhyland Klein .lock_delay = 300, 20276b301a05SRhyland Klein .iddq_reg = PLLDP_BASE, 20286b301a05SRhyland Klein .iddq_bit_idx = PLLSS_IDDQ_BIT, 20296b301a05SRhyland Klein .sdm_din_reg = PLLDP_SS_CTRL2, 20306b301a05SRhyland Klein .sdm_din_mask = PLLA_SDM_DIN_MASK, 20316b301a05SRhyland Klein .sdm_ctrl_reg = PLLDP_SS_CFG, 20326b301a05SRhyland Klein .sdm_ctrl_en_mask = PLLDP_SDM_EN_MASK, 20336b301a05SRhyland Klein .ssc_ctrl_reg = PLLDP_SS_CFG, 20346b301a05SRhyland Klein .ssc_ctrl_en_mask = PLLDP_SSC_EN_MASK, 20356b301a05SRhyland Klein .round_p_to_pdiv = pll_qlin_p_to_pdiv, 20366b301a05SRhyland Klein .pdiv_tohw = pll_qlin_pdiv_to_hw, 20376b301a05SRhyland Klein .div_nmp = &pllss_nmp, 20386b301a05SRhyland Klein .ext_misc_reg[0] = PLLDP_MISC, 20396b301a05SRhyland Klein .ext_misc_reg[1] = PLLDP_SS_CFG, 20406b301a05SRhyland Klein .ext_misc_reg[2] = PLLDP_SS_CTRL1, 20416b301a05SRhyland Klein .ext_misc_reg[3] = PLLDP_SS_CTRL2, 20426b301a05SRhyland Klein .max_p = PLL_QLIN_PDIV_MAX, 20436b301a05SRhyland Klein .mdiv_default = 1, 20446b301a05SRhyland Klein .freq_table = pll_dp_freq_table, 20456b301a05SRhyland Klein .set_defaults = tegra210_plldp_set_defaults, 204614050118SRhyland Klein .flags = TEGRA_PLL_USE_LOCK, 20476b301a05SRhyland Klein .calc_rate = tegra210_pll_fixed_mdiv_cfg, 20486b301a05SRhyland Klein .set_gain = tegra210_clk_pll_set_gain, 20496b301a05SRhyland Klein .adjust_vco = tegra210_clk_adjust_vco_min, 20506b301a05SRhyland Klein }; 20516b301a05SRhyland Klein 20526b301a05SRhyland Klein static struct div_nmp pllu_nmp = { 20536b301a05SRhyland Klein .divm_shift = 0, 20546b301a05SRhyland Klein .divm_width = 8, 20556b301a05SRhyland Klein .divn_shift = 8, 20566b301a05SRhyland Klein .divn_width = 8, 20576b301a05SRhyland Klein .divp_shift = 16, 20586b301a05SRhyland Klein .divp_width = 5, 20596b301a05SRhyland Klein }; 20606b301a05SRhyland Klein 20616b301a05SRhyland Klein static struct tegra_clk_pll_freq_table pll_u_freq_table[] = { 2062e745f992SPeter De Schrijver { 12000000, 480000000, 40, 1, 0, 0 }, 2063e745f992SPeter De Schrijver { 13000000, 480000000, 36, 1, 0, 0 }, /* actual: 468.0 MHz */ 2064e745f992SPeter De Schrijver { 38400000, 480000000, 25, 2, 0, 0 }, 20656b301a05SRhyland Klein { 0, 0, 0, 0, 0, 0 }, 20666b301a05SRhyland Klein }; 20676b301a05SRhyland Klein 20686b301a05SRhyland Klein static struct tegra_clk_pll_params pll_u_vco_params = { 20696b301a05SRhyland Klein .input_min = 9600000, 20706b301a05SRhyland Klein .input_max = 800000000, 20716b301a05SRhyland Klein .cf_min = 9600000, 20726b301a05SRhyland Klein .cf_max = 19200000, 20736b301a05SRhyland Klein .vco_min = 350000000, 20746b301a05SRhyland Klein .vco_max = 700000000, 20756b301a05SRhyland Klein .base_reg = PLLU_BASE, 20766b301a05SRhyland Klein .misc_reg = PLLU_MISC0, 20776b301a05SRhyland Klein .lock_mask = PLL_BASE_LOCK, 20786b301a05SRhyland Klein .lock_delay = 1000, 20796b301a05SRhyland Klein .iddq_reg = PLLU_MISC0, 20806b301a05SRhyland Klein .iddq_bit_idx = PLLU_IDDQ_BIT, 20816b301a05SRhyland Klein .ext_misc_reg[0] = PLLU_MISC0, 20826b301a05SRhyland Klein .ext_misc_reg[1] = PLLU_MISC1, 20836b301a05SRhyland Klein .round_p_to_pdiv = pll_qlin_p_to_pdiv, 20846b301a05SRhyland Klein .pdiv_tohw = pll_qlin_pdiv_to_hw, 20856b301a05SRhyland Klein .div_nmp = &pllu_nmp, 20866b301a05SRhyland Klein .freq_table = pll_u_freq_table, 208714050118SRhyland Klein .flags = TEGRA_PLLU | TEGRA_PLL_USE_LOCK | TEGRA_PLL_VCO_OUT, 2088e745f992SPeter De Schrijver }; 2089e745f992SPeter De Schrijver 2090e745f992SPeter De Schrijver struct utmi_clk_param { 2091e745f992SPeter De Schrijver /* Oscillator Frequency in KHz */ 2092e745f992SPeter De Schrijver u32 osc_frequency; 2093e745f992SPeter De Schrijver /* UTMIP PLL Enable Delay Count */ 2094e745f992SPeter De Schrijver u8 enable_delay_count; 2095e745f992SPeter De Schrijver /* UTMIP PLL Stable count */ 2096e745f992SPeter De Schrijver u16 stable_count; 2097e745f992SPeter De Schrijver /* UTMIP PLL Active delay count */ 2098e745f992SPeter De Schrijver u8 active_delay_count; 2099e745f992SPeter De Schrijver /* UTMIP PLL Xtal frequency count */ 2100e745f992SPeter De Schrijver u16 xtal_freq_count; 2101e745f992SPeter De Schrijver }; 2102e745f992SPeter De Schrijver 2103e745f992SPeter De Schrijver static const struct utmi_clk_param utmi_parameters[] = { 2104e745f992SPeter De Schrijver { 2105e745f992SPeter De Schrijver .osc_frequency = 38400000, .enable_delay_count = 0x0, 2106e745f992SPeter De Schrijver .stable_count = 0x0, .active_delay_count = 0x6, 2107e745f992SPeter De Schrijver .xtal_freq_count = 0x80 2108e745f992SPeter De Schrijver }, { 2109e745f992SPeter De Schrijver .osc_frequency = 13000000, .enable_delay_count = 0x02, 2110e745f992SPeter De Schrijver .stable_count = 0x33, .active_delay_count = 0x05, 2111e745f992SPeter De Schrijver .xtal_freq_count = 0x7f 2112e745f992SPeter De Schrijver }, { 2113e745f992SPeter De Schrijver .osc_frequency = 19200000, .enable_delay_count = 0x03, 2114e745f992SPeter De Schrijver .stable_count = 0x4b, .active_delay_count = 0x06, 2115e745f992SPeter De Schrijver .xtal_freq_count = 0xbb 2116e745f992SPeter De Schrijver }, { 2117e745f992SPeter De Schrijver .osc_frequency = 12000000, .enable_delay_count = 0x02, 2118e745f992SPeter De Schrijver .stable_count = 0x2f, .active_delay_count = 0x08, 2119e745f992SPeter De Schrijver .xtal_freq_count = 0x76 2120e745f992SPeter De Schrijver }, { 2121e745f992SPeter De Schrijver .osc_frequency = 26000000, .enable_delay_count = 0x04, 2122e745f992SPeter De Schrijver .stable_count = 0x66, .active_delay_count = 0x09, 2123e745f992SPeter De Schrijver .xtal_freq_count = 0xfe 2124e745f992SPeter De Schrijver }, { 2125e745f992SPeter De Schrijver .osc_frequency = 16800000, .enable_delay_count = 0x03, 2126e745f992SPeter De Schrijver .stable_count = 0x41, .active_delay_count = 0x0a, 2127e745f992SPeter De Schrijver .xtal_freq_count = 0xa4 2128e745f992SPeter De Schrijver }, 21296b301a05SRhyland Klein }; 21306b301a05SRhyland Klein 21316b301a05SRhyland Klein static struct tegra_clk tegra210_clks[tegra_clk_max] __initdata = { 21326b301a05SRhyland Klein [tegra_clk_ispb] = { .dt_id = TEGRA210_CLK_ISPB, .present = true }, 21336b301a05SRhyland Klein [tegra_clk_rtc] = { .dt_id = TEGRA210_CLK_RTC, .present = true }, 21346b301a05SRhyland Klein [tegra_clk_timer] = { .dt_id = TEGRA210_CLK_TIMER, .present = true }, 21356b301a05SRhyland Klein [tegra_clk_uarta_8] = { .dt_id = TEGRA210_CLK_UARTA, .present = true }, 21366b301a05SRhyland Klein [tegra_clk_sdmmc2_9] = { .dt_id = TEGRA210_CLK_SDMMC2, .present = true }, 21376b301a05SRhyland Klein [tegra_clk_i2s1] = { .dt_id = TEGRA210_CLK_I2S1, .present = true }, 21386b301a05SRhyland Klein [tegra_clk_i2c1] = { .dt_id = TEGRA210_CLK_I2C1, .present = true }, 21396b301a05SRhyland Klein [tegra_clk_sdmmc1_9] = { .dt_id = TEGRA210_CLK_SDMMC1, .present = true }, 21406b301a05SRhyland Klein [tegra_clk_sdmmc4_9] = { .dt_id = TEGRA210_CLK_SDMMC4, .present = true }, 21416b301a05SRhyland Klein [tegra_clk_pwm] = { .dt_id = TEGRA210_CLK_PWM, .present = true }, 21426b301a05SRhyland Klein [tegra_clk_i2s2] = { .dt_id = TEGRA210_CLK_I2S2, .present = true }, 21436b301a05SRhyland Klein [tegra_clk_usbd] = { .dt_id = TEGRA210_CLK_USBD, .present = true }, 21446b301a05SRhyland Klein [tegra_clk_isp_9] = { .dt_id = TEGRA210_CLK_ISP, .present = true }, 21456b301a05SRhyland Klein [tegra_clk_disp2_8] = { .dt_id = TEGRA210_CLK_DISP2, .present = true }, 21466b301a05SRhyland Klein [tegra_clk_disp1_8] = { .dt_id = TEGRA210_CLK_DISP1, .present = true }, 21476b301a05SRhyland Klein [tegra_clk_host1x_9] = { .dt_id = TEGRA210_CLK_HOST1X, .present = true }, 21486b301a05SRhyland Klein [tegra_clk_i2s0] = { .dt_id = TEGRA210_CLK_I2S0, .present = true }, 21496b301a05SRhyland Klein [tegra_clk_apbdma] = { .dt_id = TEGRA210_CLK_APBDMA, .present = true }, 21506b301a05SRhyland Klein [tegra_clk_kfuse] = { .dt_id = TEGRA210_CLK_KFUSE, .present = true }, 21516b301a05SRhyland Klein [tegra_clk_sbc1_9] = { .dt_id = TEGRA210_CLK_SBC1, .present = true }, 21526b301a05SRhyland Klein [tegra_clk_sbc2_9] = { .dt_id = TEGRA210_CLK_SBC2, .present = true }, 21536b301a05SRhyland Klein [tegra_clk_sbc3_9] = { .dt_id = TEGRA210_CLK_SBC3, .present = true }, 21546b301a05SRhyland Klein [tegra_clk_i2c5] = { .dt_id = TEGRA210_CLK_I2C5, .present = true }, 21556b301a05SRhyland Klein [tegra_clk_csi] = { .dt_id = TEGRA210_CLK_CSI, .present = true }, 21566b301a05SRhyland Klein [tegra_clk_i2c2] = { .dt_id = TEGRA210_CLK_I2C2, .present = true }, 21576b301a05SRhyland Klein [tegra_clk_uartc_8] = { .dt_id = TEGRA210_CLK_UARTC, .present = true }, 21586b301a05SRhyland Klein [tegra_clk_mipi_cal] = { .dt_id = TEGRA210_CLK_MIPI_CAL, .present = true }, 21596b301a05SRhyland Klein [tegra_clk_emc] = { .dt_id = TEGRA210_CLK_EMC, .present = true }, 21606b301a05SRhyland Klein [tegra_clk_usb2] = { .dt_id = TEGRA210_CLK_USB2, .present = true }, 21616b301a05SRhyland Klein [tegra_clk_bsev] = { .dt_id = TEGRA210_CLK_BSEV, .present = true }, 21626b301a05SRhyland Klein [tegra_clk_uartd_8] = { .dt_id = TEGRA210_CLK_UARTD, .present = true }, 21636b301a05SRhyland Klein [tegra_clk_i2c3] = { .dt_id = TEGRA210_CLK_I2C3, .present = true }, 21646b301a05SRhyland Klein [tegra_clk_sbc4_9] = { .dt_id = TEGRA210_CLK_SBC4, .present = true }, 21656b301a05SRhyland Klein [tegra_clk_sdmmc3_9] = { .dt_id = TEGRA210_CLK_SDMMC3, .present = true }, 21666b301a05SRhyland Klein [tegra_clk_pcie] = { .dt_id = TEGRA210_CLK_PCIE, .present = true }, 21676b301a05SRhyland Klein [tegra_clk_owr_8] = { .dt_id = TEGRA210_CLK_OWR, .present = true }, 21686b301a05SRhyland Klein [tegra_clk_afi] = { .dt_id = TEGRA210_CLK_AFI, .present = true }, 21696b301a05SRhyland Klein [tegra_clk_csite_8] = { .dt_id = TEGRA210_CLK_CSITE, .present = true }, 21706b301a05SRhyland Klein [tegra_clk_soc_therm_8] = { .dt_id = TEGRA210_CLK_SOC_THERM, .present = true }, 21716b301a05SRhyland Klein [tegra_clk_dtv] = { .dt_id = TEGRA210_CLK_DTV, .present = true }, 21726b301a05SRhyland Klein [tegra_clk_i2cslow] = { .dt_id = TEGRA210_CLK_I2CSLOW, .present = true }, 21736b301a05SRhyland Klein [tegra_clk_tsec_8] = { .dt_id = TEGRA210_CLK_TSEC, .present = true }, 21746b301a05SRhyland Klein [tegra_clk_xusb_host] = { .dt_id = TEGRA210_CLK_XUSB_HOST, .present = true }, 21756b301a05SRhyland Klein [tegra_clk_csus] = { .dt_id = TEGRA210_CLK_CSUS, .present = true }, 21766b301a05SRhyland Klein [tegra_clk_mselect] = { .dt_id = TEGRA210_CLK_MSELECT, .present = true }, 21776b301a05SRhyland Klein [tegra_clk_tsensor] = { .dt_id = TEGRA210_CLK_TSENSOR, .present = true }, 21786b301a05SRhyland Klein [tegra_clk_i2s3] = { .dt_id = TEGRA210_CLK_I2S3, .present = true }, 21796b301a05SRhyland Klein [tegra_clk_i2s4] = { .dt_id = TEGRA210_CLK_I2S4, .present = true }, 21806b301a05SRhyland Klein [tegra_clk_i2c4] = { .dt_id = TEGRA210_CLK_I2C4, .present = true }, 21816b301a05SRhyland Klein [tegra_clk_d_audio] = { .dt_id = TEGRA210_CLK_D_AUDIO, .present = true }, 21826b301a05SRhyland Klein [tegra_clk_hda2codec_2x_8] = { .dt_id = TEGRA210_CLK_HDA2CODEC_2X, .present = true }, 21836b301a05SRhyland Klein [tegra_clk_spdif_2x] = { .dt_id = TEGRA210_CLK_SPDIF_2X, .present = true }, 21846b301a05SRhyland Klein [tegra_clk_actmon] = { .dt_id = TEGRA210_CLK_ACTMON, .present = true }, 21856b301a05SRhyland Klein [tegra_clk_extern1] = { .dt_id = TEGRA210_CLK_EXTERN1, .present = true }, 21866b301a05SRhyland Klein [tegra_clk_extern2] = { .dt_id = TEGRA210_CLK_EXTERN2, .present = true }, 21876b301a05SRhyland Klein [tegra_clk_extern3] = { .dt_id = TEGRA210_CLK_EXTERN3, .present = true }, 21886b301a05SRhyland Klein [tegra_clk_sata_oob_8] = { .dt_id = TEGRA210_CLK_SATA_OOB, .present = true }, 21896b301a05SRhyland Klein [tegra_clk_sata_8] = { .dt_id = TEGRA210_CLK_SATA, .present = true }, 21906b301a05SRhyland Klein [tegra_clk_hda_8] = { .dt_id = TEGRA210_CLK_HDA, .present = true }, 21916b301a05SRhyland Klein [tegra_clk_hda2hdmi] = { .dt_id = TEGRA210_CLK_HDA2HDMI, .present = true }, 21926b301a05SRhyland Klein [tegra_clk_cilab] = { .dt_id = TEGRA210_CLK_CILAB, .present = true }, 21936b301a05SRhyland Klein [tegra_clk_cilcd] = { .dt_id = TEGRA210_CLK_CILCD, .present = true }, 21946b301a05SRhyland Klein [tegra_clk_cile] = { .dt_id = TEGRA210_CLK_CILE, .present = true }, 21956b301a05SRhyland Klein [tegra_clk_dsialp] = { .dt_id = TEGRA210_CLK_DSIALP, .present = true }, 21966b301a05SRhyland Klein [tegra_clk_dsiblp] = { .dt_id = TEGRA210_CLK_DSIBLP, .present = true }, 21976b301a05SRhyland Klein [tegra_clk_entropy_8] = { .dt_id = TEGRA210_CLK_ENTROPY, .present = true }, 21986b301a05SRhyland Klein [tegra_clk_xusb_ss] = { .dt_id = TEGRA210_CLK_XUSB_SS, .present = true }, 21996b301a05SRhyland Klein [tegra_clk_i2c6] = { .dt_id = TEGRA210_CLK_I2C6, .present = true }, 22006b301a05SRhyland Klein [tegra_clk_vim2_clk] = { .dt_id = TEGRA210_CLK_VIM2_CLK, .present = true }, 22016b301a05SRhyland Klein [tegra_clk_clk72Mhz_8] = { .dt_id = TEGRA210_CLK_CLK72MHZ, .present = true }, 22026b301a05SRhyland Klein [tegra_clk_vic03_8] = { .dt_id = TEGRA210_CLK_VIC03, .present = true }, 22036b301a05SRhyland Klein [tegra_clk_dpaux] = { .dt_id = TEGRA210_CLK_DPAUX, .present = true }, 220498c4b366SThierry Reding [tegra_clk_dpaux1] = { .dt_id = TEGRA210_CLK_DPAUX1, .present = true }, 22056b301a05SRhyland Klein [tegra_clk_sor0] = { .dt_id = TEGRA210_CLK_SOR0, .present = true }, 22066b301a05SRhyland Klein [tegra_clk_sor0_lvds] = { .dt_id = TEGRA210_CLK_SOR0_LVDS, .present = true }, 2207e452b818SThierry Reding [tegra_clk_sor1] = { .dt_id = TEGRA210_CLK_SOR1, .present = true }, 2208e452b818SThierry Reding [tegra_clk_sor1_src] = { .dt_id = TEGRA210_CLK_SOR1_SRC, .present = true }, 22096b301a05SRhyland Klein [tegra_clk_gpu] = { .dt_id = TEGRA210_CLK_GPU, .present = true }, 22106b301a05SRhyland Klein [tegra_clk_pll_g_ref] = { .dt_id = TEGRA210_CLK_PLL_G_REF, .present = true, }, 22116b301a05SRhyland Klein [tegra_clk_uartb_8] = { .dt_id = TEGRA210_CLK_UARTB, .present = true }, 22126b301a05SRhyland Klein [tegra_clk_spdif_in_8] = { .dt_id = TEGRA210_CLK_SPDIF_IN, .present = true }, 22136b301a05SRhyland Klein [tegra_clk_spdif_out] = { .dt_id = TEGRA210_CLK_SPDIF_OUT, .present = true }, 22146b301a05SRhyland Klein [tegra_clk_vi_10] = { .dt_id = TEGRA210_CLK_VI, .present = true }, 22156b301a05SRhyland Klein [tegra_clk_vi_sensor_8] = { .dt_id = TEGRA210_CLK_VI_SENSOR, .present = true }, 22166b301a05SRhyland Klein [tegra_clk_fuse] = { .dt_id = TEGRA210_CLK_FUSE, .present = true }, 22176b301a05SRhyland Klein [tegra_clk_fuse_burn] = { .dt_id = TEGRA210_CLK_FUSE_BURN, .present = true }, 22186b301a05SRhyland Klein [tegra_clk_clk_32k] = { .dt_id = TEGRA210_CLK_CLK_32K, .present = true }, 22196b301a05SRhyland Klein [tegra_clk_clk_m] = { .dt_id = TEGRA210_CLK_CLK_M, .present = true }, 22206b301a05SRhyland Klein [tegra_clk_clk_m_div2] = { .dt_id = TEGRA210_CLK_CLK_M_DIV2, .present = true }, 22216b301a05SRhyland Klein [tegra_clk_clk_m_div4] = { .dt_id = TEGRA210_CLK_CLK_M_DIV4, .present = true }, 22226b301a05SRhyland Klein [tegra_clk_pll_ref] = { .dt_id = TEGRA210_CLK_PLL_REF, .present = true }, 22236b301a05SRhyland Klein [tegra_clk_pll_c] = { .dt_id = TEGRA210_CLK_PLL_C, .present = true }, 22246b301a05SRhyland Klein [tegra_clk_pll_c_out1] = { .dt_id = TEGRA210_CLK_PLL_C_OUT1, .present = true }, 22256b301a05SRhyland Klein [tegra_clk_pll_c2] = { .dt_id = TEGRA210_CLK_PLL_C2, .present = true }, 22266b301a05SRhyland Klein [tegra_clk_pll_c3] = { .dt_id = TEGRA210_CLK_PLL_C3, .present = true }, 22276b301a05SRhyland Klein [tegra_clk_pll_m] = { .dt_id = TEGRA210_CLK_PLL_M, .present = true }, 22286b301a05SRhyland Klein [tegra_clk_pll_p] = { .dt_id = TEGRA210_CLK_PLL_P, .present = true }, 22296b301a05SRhyland Klein [tegra_clk_pll_p_out1] = { .dt_id = TEGRA210_CLK_PLL_P_OUT1, .present = true }, 22306b301a05SRhyland Klein [tegra_clk_pll_p_out3] = { .dt_id = TEGRA210_CLK_PLL_P_OUT3, .present = true }, 22316b301a05SRhyland Klein [tegra_clk_pll_p_out4_cpu] = { .dt_id = TEGRA210_CLK_PLL_P_OUT4, .present = true }, 22326b301a05SRhyland Klein [tegra_clk_pll_p_out_hsio] = { .dt_id = TEGRA210_CLK_PLL_P_OUT_HSIO, .present = true }, 22336b301a05SRhyland Klein [tegra_clk_pll_p_out_xusb] = { .dt_id = TEGRA210_CLK_PLL_P_OUT_XUSB, .present = true }, 22346b301a05SRhyland Klein [tegra_clk_pll_p_out_cpu] = { .dt_id = TEGRA210_CLK_PLL_P_OUT_CPU, .present = true }, 22356b301a05SRhyland Klein [tegra_clk_pll_p_out_adsp] = { .dt_id = TEGRA210_CLK_PLL_P_OUT_ADSP, .present = true }, 22366b301a05SRhyland Klein [tegra_clk_pll_a] = { .dt_id = TEGRA210_CLK_PLL_A, .present = true }, 22376b301a05SRhyland Klein [tegra_clk_pll_a_out0] = { .dt_id = TEGRA210_CLK_PLL_A_OUT0, .present = true }, 22386b301a05SRhyland Klein [tegra_clk_pll_d] = { .dt_id = TEGRA210_CLK_PLL_D, .present = true }, 22396b301a05SRhyland Klein [tegra_clk_pll_d_out0] = { .dt_id = TEGRA210_CLK_PLL_D_OUT0, .present = true }, 22406b301a05SRhyland Klein [tegra_clk_pll_d2] = { .dt_id = TEGRA210_CLK_PLL_D2, .present = true }, 22416b301a05SRhyland Klein [tegra_clk_pll_d2_out0] = { .dt_id = TEGRA210_CLK_PLL_D2_OUT0, .present = true }, 22426b301a05SRhyland Klein [tegra_clk_pll_u] = { .dt_id = TEGRA210_CLK_PLL_U, .present = true }, 22436b301a05SRhyland Klein [tegra_clk_pll_u_out] = { .dt_id = TEGRA210_CLK_PLL_U_OUT, .present = true }, 22446b301a05SRhyland Klein [tegra_clk_pll_u_out1] = { .dt_id = TEGRA210_CLK_PLL_U_OUT1, .present = true }, 22456b301a05SRhyland Klein [tegra_clk_pll_u_out2] = { .dt_id = TEGRA210_CLK_PLL_U_OUT2, .present = true }, 22466b301a05SRhyland Klein [tegra_clk_pll_u_480m] = { .dt_id = TEGRA210_CLK_PLL_U_480M, .present = true }, 22476b301a05SRhyland Klein [tegra_clk_pll_u_60m] = { .dt_id = TEGRA210_CLK_PLL_U_60M, .present = true }, 22486b301a05SRhyland Klein [tegra_clk_pll_u_48m] = { .dt_id = TEGRA210_CLK_PLL_U_48M, .present = true }, 22496b301a05SRhyland Klein [tegra_clk_pll_x] = { .dt_id = TEGRA210_CLK_PLL_X, .present = true }, 22506b301a05SRhyland Klein [tegra_clk_pll_x_out0] = { .dt_id = TEGRA210_CLK_PLL_X_OUT0, .present = true }, 22516b301a05SRhyland Klein [tegra_clk_pll_re_vco] = { .dt_id = TEGRA210_CLK_PLL_RE_VCO, .present = true }, 22526b301a05SRhyland Klein [tegra_clk_pll_re_out] = { .dt_id = TEGRA210_CLK_PLL_RE_OUT, .present = true }, 22536b301a05SRhyland Klein [tegra_clk_spdif_in_sync] = { .dt_id = TEGRA210_CLK_SPDIF_IN_SYNC, .present = true }, 22546b301a05SRhyland Klein [tegra_clk_i2s0_sync] = { .dt_id = TEGRA210_CLK_I2S0_SYNC, .present = true }, 22556b301a05SRhyland Klein [tegra_clk_i2s1_sync] = { .dt_id = TEGRA210_CLK_I2S1_SYNC, .present = true }, 22566b301a05SRhyland Klein [tegra_clk_i2s2_sync] = { .dt_id = TEGRA210_CLK_I2S2_SYNC, .present = true }, 22576b301a05SRhyland Klein [tegra_clk_i2s3_sync] = { .dt_id = TEGRA210_CLK_I2S3_SYNC, .present = true }, 22586b301a05SRhyland Klein [tegra_clk_i2s4_sync] = { .dt_id = TEGRA210_CLK_I2S4_SYNC, .present = true }, 22596b301a05SRhyland Klein [tegra_clk_vimclk_sync] = { .dt_id = TEGRA210_CLK_VIMCLK_SYNC, .present = true }, 22606b301a05SRhyland Klein [tegra_clk_audio0] = { .dt_id = TEGRA210_CLK_AUDIO0, .present = true }, 22616b301a05SRhyland Klein [tegra_clk_audio1] = { .dt_id = TEGRA210_CLK_AUDIO1, .present = true }, 22626b301a05SRhyland Klein [tegra_clk_audio2] = { .dt_id = TEGRA210_CLK_AUDIO2, .present = true }, 22636b301a05SRhyland Klein [tegra_clk_audio3] = { .dt_id = TEGRA210_CLK_AUDIO3, .present = true }, 22646b301a05SRhyland Klein [tegra_clk_audio4] = { .dt_id = TEGRA210_CLK_AUDIO4, .present = true }, 22656b301a05SRhyland Klein [tegra_clk_spdif] = { .dt_id = TEGRA210_CLK_SPDIF, .present = true }, 22666b301a05SRhyland Klein [tegra_clk_clk_out_1] = { .dt_id = TEGRA210_CLK_CLK_OUT_1, .present = true }, 22676b301a05SRhyland Klein [tegra_clk_clk_out_2] = { .dt_id = TEGRA210_CLK_CLK_OUT_2, .present = true }, 22686b301a05SRhyland Klein [tegra_clk_clk_out_3] = { .dt_id = TEGRA210_CLK_CLK_OUT_3, .present = true }, 22696b301a05SRhyland Klein [tegra_clk_blink] = { .dt_id = TEGRA210_CLK_BLINK, .present = true }, 22706b301a05SRhyland Klein [tegra_clk_xusb_gate] = { .dt_id = TEGRA210_CLK_XUSB_GATE, .present = true }, 22716b301a05SRhyland Klein [tegra_clk_xusb_host_src_8] = { .dt_id = TEGRA210_CLK_XUSB_HOST_SRC, .present = true }, 22726b301a05SRhyland Klein [tegra_clk_xusb_falcon_src_8] = { .dt_id = TEGRA210_CLK_XUSB_FALCON_SRC, .present = true }, 22736b301a05SRhyland Klein [tegra_clk_xusb_fs_src] = { .dt_id = TEGRA210_CLK_XUSB_FS_SRC, .present = true }, 22746b301a05SRhyland Klein [tegra_clk_xusb_ss_src_8] = { .dt_id = TEGRA210_CLK_XUSB_SS_SRC, .present = true }, 22756b301a05SRhyland Klein [tegra_clk_xusb_ss_div2] = { .dt_id = TEGRA210_CLK_XUSB_SS_DIV2, .present = true }, 22766b301a05SRhyland Klein [tegra_clk_xusb_dev_src_8] = { .dt_id = TEGRA210_CLK_XUSB_DEV_SRC, .present = true }, 22776b301a05SRhyland Klein [tegra_clk_xusb_dev] = { .dt_id = TEGRA210_CLK_XUSB_DEV, .present = true }, 22786b301a05SRhyland Klein [tegra_clk_xusb_hs_src_4] = { .dt_id = TEGRA210_CLK_XUSB_HS_SRC, .present = true }, 22796b301a05SRhyland Klein [tegra_clk_xusb_ssp_src] = { .dt_id = TEGRA210_CLK_XUSB_SSP_SRC, .present = true }, 22806b301a05SRhyland Klein [tegra_clk_usb2_hsic_trk] = { .dt_id = TEGRA210_CLK_USB2_HSIC_TRK, .present = true }, 22816b301a05SRhyland Klein [tegra_clk_hsic_trk] = { .dt_id = TEGRA210_CLK_HSIC_TRK, .present = true }, 22826b301a05SRhyland Klein [tegra_clk_usb2_trk] = { .dt_id = TEGRA210_CLK_USB2_TRK, .present = true }, 22836b301a05SRhyland Klein [tegra_clk_sclk] = { .dt_id = TEGRA210_CLK_SCLK, .present = true }, 22846b301a05SRhyland Klein [tegra_clk_sclk_mux] = { .dt_id = TEGRA210_CLK_SCLK_MUX, .present = true }, 22856b301a05SRhyland Klein [tegra_clk_hclk] = { .dt_id = TEGRA210_CLK_HCLK, .present = true }, 22866b301a05SRhyland Klein [tegra_clk_pclk] = { .dt_id = TEGRA210_CLK_PCLK, .present = true }, 22876b301a05SRhyland Klein [tegra_clk_cclk_g] = { .dt_id = TEGRA210_CLK_CCLK_G, .present = true }, 22886b301a05SRhyland Klein [tegra_clk_cclk_lp] = { .dt_id = TEGRA210_CLK_CCLK_LP, .present = true }, 22896b301a05SRhyland Klein [tegra_clk_dfll_ref] = { .dt_id = TEGRA210_CLK_DFLL_REF, .present = true }, 22906b301a05SRhyland Klein [tegra_clk_dfll_soc] = { .dt_id = TEGRA210_CLK_DFLL_SOC, .present = true }, 22916b301a05SRhyland Klein [tegra_clk_vi_sensor2_8] = { .dt_id = TEGRA210_CLK_VI_SENSOR2, .present = true }, 22926b301a05SRhyland Klein [tegra_clk_pll_p_out5] = { .dt_id = TEGRA210_CLK_PLL_P_OUT5, .present = true }, 22936b301a05SRhyland Klein [tegra_clk_pll_c4] = { .dt_id = TEGRA210_CLK_PLL_C4, .present = true }, 22946b301a05SRhyland Klein [tegra_clk_pll_dp] = { .dt_id = TEGRA210_CLK_PLL_DP, .present = true }, 22956b301a05SRhyland Klein [tegra_clk_audio0_mux] = { .dt_id = TEGRA210_CLK_AUDIO0_MUX, .present = true }, 22966b301a05SRhyland Klein [tegra_clk_audio1_mux] = { .dt_id = TEGRA210_CLK_AUDIO1_MUX, .present = true }, 22976b301a05SRhyland Klein [tegra_clk_audio2_mux] = { .dt_id = TEGRA210_CLK_AUDIO2_MUX, .present = true }, 22986b301a05SRhyland Klein [tegra_clk_audio3_mux] = { .dt_id = TEGRA210_CLK_AUDIO3_MUX, .present = true }, 22996b301a05SRhyland Klein [tegra_clk_audio4_mux] = { .dt_id = TEGRA210_CLK_AUDIO4_MUX, .present = true }, 23006b301a05SRhyland Klein [tegra_clk_spdif_mux] = { .dt_id = TEGRA210_CLK_SPDIF_MUX, .present = true }, 23016b301a05SRhyland Klein [tegra_clk_clk_out_1_mux] = { .dt_id = TEGRA210_CLK_CLK_OUT_1_MUX, .present = true }, 23026b301a05SRhyland Klein [tegra_clk_clk_out_2_mux] = { .dt_id = TEGRA210_CLK_CLK_OUT_2_MUX, .present = true }, 23036b301a05SRhyland Klein [tegra_clk_clk_out_3_mux] = { .dt_id = TEGRA210_CLK_CLK_OUT_3_MUX, .present = true }, 23046b301a05SRhyland Klein [tegra_clk_maud] = { .dt_id = TEGRA210_CLK_MAUD, .present = true }, 23056b301a05SRhyland Klein [tegra_clk_mipibif] = { .dt_id = TEGRA210_CLK_MIPIBIF, .present = true }, 23066b301a05SRhyland Klein [tegra_clk_qspi] = { .dt_id = TEGRA210_CLK_QSPI, .present = true }, 23076b301a05SRhyland Klein [tegra_clk_sdmmc_legacy] = { .dt_id = TEGRA210_CLK_SDMMC_LEGACY, .present = true }, 23086b301a05SRhyland Klein [tegra_clk_tsecb] = { .dt_id = TEGRA210_CLK_TSECB, .present = true }, 23096b301a05SRhyland Klein [tegra_clk_uartape] = { .dt_id = TEGRA210_CLK_UARTAPE, .present = true }, 23106b301a05SRhyland Klein [tegra_clk_vi_i2c] = { .dt_id = TEGRA210_CLK_VI_I2C, .present = true }, 23116b301a05SRhyland Klein [tegra_clk_ape] = { .dt_id = TEGRA210_CLK_APE, .present = true }, 23126b301a05SRhyland Klein [tegra_clk_dbgapb] = { .dt_id = TEGRA210_CLK_DBGAPB, .present = true }, 23136b301a05SRhyland Klein [tegra_clk_nvdec] = { .dt_id = TEGRA210_CLK_NVDEC, .present = true }, 23146b301a05SRhyland Klein [tegra_clk_nvenc] = { .dt_id = TEGRA210_CLK_NVENC, .present = true }, 23156b301a05SRhyland Klein [tegra_clk_nvjpg] = { .dt_id = TEGRA210_CLK_NVJPG, .present = true }, 23166b301a05SRhyland Klein [tegra_clk_pll_c4_out0] = { .dt_id = TEGRA210_CLK_PLL_C4_OUT0, .present = true }, 23176b301a05SRhyland Klein [tegra_clk_pll_c4_out1] = { .dt_id = TEGRA210_CLK_PLL_C4_OUT1, .present = true }, 23186b301a05SRhyland Klein [tegra_clk_pll_c4_out2] = { .dt_id = TEGRA210_CLK_PLL_C4_OUT2, .present = true }, 23196b301a05SRhyland Klein [tegra_clk_pll_c4_out3] = { .dt_id = TEGRA210_CLK_PLL_C4_OUT3, .present = true }, 232029569941SJon Hunter [tegra_clk_apb2ape] = { .dt_id = TEGRA210_CLK_APB2APE, .present = true }, 23219326947fSPeter De Schrijver [tegra_clk_pll_a1] = { .dt_id = TEGRA210_CLK_PLL_A1, .present = true }, 232234ac2c27SPeter De Schrijver [tegra_clk_ispa] = { .dt_id = TEGRA210_CLK_ISPA, .present = true }, 2323bfa34832SPeter De Schrijver [tegra_clk_cec] = { .dt_id = TEGRA210_CLK_CEC, .present = true }, 23246cfc8bc9SPeter De Schrijver [tegra_clk_dmic1] = { .dt_id = TEGRA210_CLK_DMIC1, .present = true }, 23256cfc8bc9SPeter De Schrijver [tegra_clk_dmic2] = { .dt_id = TEGRA210_CLK_DMIC2, .present = true }, 23266cfc8bc9SPeter De Schrijver [tegra_clk_dmic3] = { .dt_id = TEGRA210_CLK_DMIC3, .present = true }, 2327319af797SPeter De Schrijver [tegra_clk_dmic1_sync_clk] = { .dt_id = TEGRA210_CLK_DMIC1_SYNC_CLK, .present = true }, 2328319af797SPeter De Schrijver [tegra_clk_dmic2_sync_clk] = { .dt_id = TEGRA210_CLK_DMIC2_SYNC_CLK, .present = true }, 2329319af797SPeter De Schrijver [tegra_clk_dmic3_sync_clk] = { .dt_id = TEGRA210_CLK_DMIC3_SYNC_CLK, .present = true }, 2330319af797SPeter De Schrijver [tegra_clk_dmic1_sync_clk_mux] = { .dt_id = TEGRA210_CLK_DMIC1_SYNC_CLK_MUX, .present = true }, 2331319af797SPeter De Schrijver [tegra_clk_dmic2_sync_clk_mux] = { .dt_id = TEGRA210_CLK_DMIC2_SYNC_CLK_MUX, .present = true }, 2332319af797SPeter De Schrijver [tegra_clk_dmic3_sync_clk_mux] = { .dt_id = TEGRA210_CLK_DMIC3_SYNC_CLK_MUX, .present = true }, 233388da44c5SPeter De Schrijver [tegra_clk_dp2] = { .dt_id = TEGRA210_CLK_DP2, .present = true }, 233488da44c5SPeter De Schrijver [tegra_clk_iqc1] = { .dt_id = TEGRA210_CLK_IQC1, .present = true }, 233588da44c5SPeter De Schrijver [tegra_clk_iqc2] = { .dt_id = TEGRA210_CLK_IQC2, .present = true }, 233688da44c5SPeter De Schrijver [tegra_clk_pll_a_out_adsp] = { .dt_id = TEGRA210_CLK_PLL_A_OUT_ADSP, .present = true }, 233788da44c5SPeter De Schrijver [tegra_clk_pll_a_out0_out_adsp] = { .dt_id = TEGRA210_CLK_PLL_A_OUT0_OUT_ADSP, .present = true }, 233888da44c5SPeter De Schrijver [tegra_clk_adsp] = { .dt_id = TEGRA210_CLK_ADSP, .present = true }, 233988da44c5SPeter De Schrijver [tegra_clk_adsp_neon] = { .dt_id = TEGRA210_CLK_ADSP_NEON, .present = true }, 23406b301a05SRhyland Klein }; 23416b301a05SRhyland Klein 23426b301a05SRhyland Klein static struct tegra_devclk devclks[] __initdata = { 23436b301a05SRhyland Klein { .con_id = "clk_m", .dt_id = TEGRA210_CLK_CLK_M }, 23446b301a05SRhyland Klein { .con_id = "pll_ref", .dt_id = TEGRA210_CLK_PLL_REF }, 23456b301a05SRhyland Klein { .con_id = "clk_32k", .dt_id = TEGRA210_CLK_CLK_32K }, 23466b301a05SRhyland Klein { .con_id = "clk_m_div2", .dt_id = TEGRA210_CLK_CLK_M_DIV2 }, 23476b301a05SRhyland Klein { .con_id = "clk_m_div4", .dt_id = TEGRA210_CLK_CLK_M_DIV4 }, 23486b301a05SRhyland Klein { .con_id = "pll_c", .dt_id = TEGRA210_CLK_PLL_C }, 23496b301a05SRhyland Klein { .con_id = "pll_c_out1", .dt_id = TEGRA210_CLK_PLL_C_OUT1 }, 23506b301a05SRhyland Klein { .con_id = "pll_c2", .dt_id = TEGRA210_CLK_PLL_C2 }, 23516b301a05SRhyland Klein { .con_id = "pll_c3", .dt_id = TEGRA210_CLK_PLL_C3 }, 23526b301a05SRhyland Klein { .con_id = "pll_p", .dt_id = TEGRA210_CLK_PLL_P }, 23536b301a05SRhyland Klein { .con_id = "pll_p_out1", .dt_id = TEGRA210_CLK_PLL_P_OUT1 }, 23546b301a05SRhyland Klein { .con_id = "pll_p_out2", .dt_id = TEGRA210_CLK_PLL_P_OUT2 }, 23556b301a05SRhyland Klein { .con_id = "pll_p_out3", .dt_id = TEGRA210_CLK_PLL_P_OUT3 }, 23566b301a05SRhyland Klein { .con_id = "pll_p_out4", .dt_id = TEGRA210_CLK_PLL_P_OUT4 }, 23576b301a05SRhyland Klein { .con_id = "pll_m", .dt_id = TEGRA210_CLK_PLL_M }, 23586b301a05SRhyland Klein { .con_id = "pll_x", .dt_id = TEGRA210_CLK_PLL_X }, 23596b301a05SRhyland Klein { .con_id = "pll_x_out0", .dt_id = TEGRA210_CLK_PLL_X_OUT0 }, 23606b301a05SRhyland Klein { .con_id = "pll_u", .dt_id = TEGRA210_CLK_PLL_U }, 23616b301a05SRhyland Klein { .con_id = "pll_u_out", .dt_id = TEGRA210_CLK_PLL_U_OUT }, 23626b301a05SRhyland Klein { .con_id = "pll_u_out1", .dt_id = TEGRA210_CLK_PLL_U_OUT1 }, 23636b301a05SRhyland Klein { .con_id = "pll_u_out2", .dt_id = TEGRA210_CLK_PLL_U_OUT2 }, 23646b301a05SRhyland Klein { .con_id = "pll_u_480M", .dt_id = TEGRA210_CLK_PLL_U_480M }, 23656b301a05SRhyland Klein { .con_id = "pll_u_60M", .dt_id = TEGRA210_CLK_PLL_U_60M }, 23666b301a05SRhyland Klein { .con_id = "pll_u_48M", .dt_id = TEGRA210_CLK_PLL_U_48M }, 23676b301a05SRhyland Klein { .con_id = "pll_d", .dt_id = TEGRA210_CLK_PLL_D }, 23686b301a05SRhyland Klein { .con_id = "pll_d_out0", .dt_id = TEGRA210_CLK_PLL_D_OUT0 }, 23696b301a05SRhyland Klein { .con_id = "pll_d2", .dt_id = TEGRA210_CLK_PLL_D2 }, 23706b301a05SRhyland Klein { .con_id = "pll_d2_out0", .dt_id = TEGRA210_CLK_PLL_D2_OUT0 }, 23716b301a05SRhyland Klein { .con_id = "pll_a", .dt_id = TEGRA210_CLK_PLL_A }, 23726b301a05SRhyland Klein { .con_id = "pll_a_out0", .dt_id = TEGRA210_CLK_PLL_A_OUT0 }, 23736b301a05SRhyland Klein { .con_id = "pll_re_vco", .dt_id = TEGRA210_CLK_PLL_RE_VCO }, 23746b301a05SRhyland Klein { .con_id = "pll_re_out", .dt_id = TEGRA210_CLK_PLL_RE_OUT }, 23756b301a05SRhyland Klein { .con_id = "spdif_in_sync", .dt_id = TEGRA210_CLK_SPDIF_IN_SYNC }, 23766b301a05SRhyland Klein { .con_id = "i2s0_sync", .dt_id = TEGRA210_CLK_I2S0_SYNC }, 23776b301a05SRhyland Klein { .con_id = "i2s1_sync", .dt_id = TEGRA210_CLK_I2S1_SYNC }, 23786b301a05SRhyland Klein { .con_id = "i2s2_sync", .dt_id = TEGRA210_CLK_I2S2_SYNC }, 23796b301a05SRhyland Klein { .con_id = "i2s3_sync", .dt_id = TEGRA210_CLK_I2S3_SYNC }, 23806b301a05SRhyland Klein { .con_id = "i2s4_sync", .dt_id = TEGRA210_CLK_I2S4_SYNC }, 23816b301a05SRhyland Klein { .con_id = "vimclk_sync", .dt_id = TEGRA210_CLK_VIMCLK_SYNC }, 23826b301a05SRhyland Klein { .con_id = "audio0", .dt_id = TEGRA210_CLK_AUDIO0 }, 23836b301a05SRhyland Klein { .con_id = "audio1", .dt_id = TEGRA210_CLK_AUDIO1 }, 23846b301a05SRhyland Klein { .con_id = "audio2", .dt_id = TEGRA210_CLK_AUDIO2 }, 23856b301a05SRhyland Klein { .con_id = "audio3", .dt_id = TEGRA210_CLK_AUDIO3 }, 23866b301a05SRhyland Klein { .con_id = "audio4", .dt_id = TEGRA210_CLK_AUDIO4 }, 23876b301a05SRhyland Klein { .con_id = "spdif", .dt_id = TEGRA210_CLK_SPDIF }, 23886b301a05SRhyland Klein { .con_id = "spdif_2x", .dt_id = TEGRA210_CLK_SPDIF_2X }, 23896b301a05SRhyland Klein { .con_id = "extern1", .dev_id = "clk_out_1", .dt_id = TEGRA210_CLK_EXTERN1 }, 23906b301a05SRhyland Klein { .con_id = "extern2", .dev_id = "clk_out_2", .dt_id = TEGRA210_CLK_EXTERN2 }, 23916b301a05SRhyland Klein { .con_id = "extern3", .dev_id = "clk_out_3", .dt_id = TEGRA210_CLK_EXTERN3 }, 23926b301a05SRhyland Klein { .con_id = "blink", .dt_id = TEGRA210_CLK_BLINK }, 23936b301a05SRhyland Klein { .con_id = "cclk_g", .dt_id = TEGRA210_CLK_CCLK_G }, 23946b301a05SRhyland Klein { .con_id = "cclk_lp", .dt_id = TEGRA210_CLK_CCLK_LP }, 23956b301a05SRhyland Klein { .con_id = "sclk", .dt_id = TEGRA210_CLK_SCLK }, 23966b301a05SRhyland Klein { .con_id = "hclk", .dt_id = TEGRA210_CLK_HCLK }, 23976b301a05SRhyland Klein { .con_id = "pclk", .dt_id = TEGRA210_CLK_PCLK }, 23986b301a05SRhyland Klein { .con_id = "fuse", .dt_id = TEGRA210_CLK_FUSE }, 23996b301a05SRhyland Klein { .dev_id = "rtc-tegra", .dt_id = TEGRA210_CLK_RTC }, 24006b301a05SRhyland Klein { .dev_id = "timer", .dt_id = TEGRA210_CLK_TIMER }, 24016b301a05SRhyland Klein { .con_id = "pll_c4_out0", .dt_id = TEGRA210_CLK_PLL_C4_OUT0 }, 24026b301a05SRhyland Klein { .con_id = "pll_c4_out1", .dt_id = TEGRA210_CLK_PLL_C4_OUT1 }, 24036b301a05SRhyland Klein { .con_id = "pll_c4_out2", .dt_id = TEGRA210_CLK_PLL_C4_OUT2 }, 24046b301a05SRhyland Klein { .con_id = "pll_c4_out3", .dt_id = TEGRA210_CLK_PLL_C4_OUT3 }, 24056b301a05SRhyland Klein { .con_id = "dpaux", .dt_id = TEGRA210_CLK_DPAUX }, 24066b301a05SRhyland Klein { .con_id = "sor0", .dt_id = TEGRA210_CLK_SOR0 }, 24076b301a05SRhyland Klein }; 24086b301a05SRhyland Klein 24096b301a05SRhyland Klein static struct tegra_audio_clk_info tegra210_audio_plls[] = { 24106b301a05SRhyland Klein { "pll_a", &pll_a_params, tegra_clk_pll_a, "pll_ref" }, 24116b301a05SRhyland Klein { "pll_a1", &pll_a1_params, tegra_clk_pll_a1, "pll_ref" }, 24126b301a05SRhyland Klein }; 24136b301a05SRhyland Klein 24146b301a05SRhyland Klein static struct clk **clks; 24156b301a05SRhyland Klein 241624c3ebefSPeter De Schrijver static const char * const aclk_parents[] = { 241724c3ebefSPeter De Schrijver "pll_a1", "pll_c", "pll_p", "pll_a_out0", "pll_c2", "pll_c3", 241824c3ebefSPeter De Schrijver "clk_m" 241924c3ebefSPeter De Schrijver }; 242024c3ebefSPeter De Schrijver 24213843832fSPeter De Schrijver void tegra210_put_utmipll_in_iddq(void) 24223843832fSPeter De Schrijver { 24233843832fSPeter De Schrijver u32 reg; 24243843832fSPeter De Schrijver 24253843832fSPeter De Schrijver reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); 24263843832fSPeter De Schrijver 24273843832fSPeter De Schrijver if (reg & UTMIPLL_HW_PWRDN_CFG0_UTMIPLL_LOCK) { 24283843832fSPeter De Schrijver pr_err("trying to assert IDDQ while UTMIPLL is locked\n"); 24293843832fSPeter De Schrijver return; 24303843832fSPeter De Schrijver } 24313843832fSPeter De Schrijver 24323843832fSPeter De Schrijver reg |= UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE; 24333843832fSPeter De Schrijver writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); 24343843832fSPeter De Schrijver } 24353843832fSPeter De Schrijver EXPORT_SYMBOL_GPL(tegra210_put_utmipll_in_iddq); 24363843832fSPeter De Schrijver 24373843832fSPeter De Schrijver void tegra210_put_utmipll_out_iddq(void) 24383843832fSPeter De Schrijver { 24393843832fSPeter De Schrijver u32 reg; 24403843832fSPeter De Schrijver 24413843832fSPeter De Schrijver reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); 24423843832fSPeter De Schrijver reg &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE; 24433843832fSPeter De Schrijver writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); 24443843832fSPeter De Schrijver } 24453843832fSPeter De Schrijver EXPORT_SYMBOL_GPL(tegra210_put_utmipll_out_iddq); 24463843832fSPeter De Schrijver 2447e745f992SPeter De Schrijver static void tegra210_utmi_param_configure(void) 2448e745f992SPeter De Schrijver { 2449e745f992SPeter De Schrijver u32 reg; 2450e745f992SPeter De Schrijver int i; 2451e745f992SPeter De Schrijver 2452e745f992SPeter De Schrijver for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) { 2453e745f992SPeter De Schrijver if (osc_freq == utmi_parameters[i].osc_frequency) 2454e745f992SPeter De Schrijver break; 2455e745f992SPeter De Schrijver } 2456e745f992SPeter De Schrijver 2457e745f992SPeter De Schrijver if (i >= ARRAY_SIZE(utmi_parameters)) { 2458e745f992SPeter De Schrijver pr_err("%s: Unexpected oscillator freq %lu\n", __func__, 2459e745f992SPeter De Schrijver osc_freq); 2460e745f992SPeter De Schrijver return; 2461e745f992SPeter De Schrijver } 2462e745f992SPeter De Schrijver 2463e745f992SPeter De Schrijver reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); 2464e745f992SPeter De Schrijver reg &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE; 2465e745f992SPeter De Schrijver writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); 2466e745f992SPeter De Schrijver 2467e745f992SPeter De Schrijver udelay(10); 2468e745f992SPeter De Schrijver 2469e745f992SPeter De Schrijver reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2); 2470e745f992SPeter De Schrijver 2471e745f992SPeter De Schrijver /* Program UTMIP PLL stable and active counts */ 2472e745f992SPeter De Schrijver /* [FIXME] arclk_rst.h says WRONG! This should be 1ms -> 0x50 Check! */ 2473e745f992SPeter De Schrijver reg &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0); 2474e745f992SPeter De Schrijver reg |= UTMIP_PLL_CFG2_STABLE_COUNT(utmi_parameters[i].stable_count); 2475e745f992SPeter De Schrijver 2476e745f992SPeter De Schrijver reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0); 2477e745f992SPeter De Schrijver reg |= 2478e745f992SPeter De Schrijver UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(utmi_parameters[i].active_delay_count); 2479e745f992SPeter De Schrijver writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2); 2480e745f992SPeter De Schrijver 2481e745f992SPeter De Schrijver /* Program UTMIP PLL delay and oscillator frequency counts */ 2482e745f992SPeter De Schrijver reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1); 2483e745f992SPeter De Schrijver 248471422dbbSAlex Frid reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0); 2485e745f992SPeter De Schrijver reg |= 2486e745f992SPeter De Schrijver UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(utmi_parameters[i].enable_delay_count); 2487e745f992SPeter De Schrijver 2488e745f992SPeter De Schrijver reg &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0); 2489e745f992SPeter De Schrijver reg |= 2490e745f992SPeter De Schrijver UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(utmi_parameters[i].xtal_freq_count); 2491e745f992SPeter De Schrijver 2492e745f992SPeter De Schrijver reg |= UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN; 2493e745f992SPeter De Schrijver writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1); 2494e745f992SPeter De Schrijver 2495e745f992SPeter De Schrijver /* Remove power downs from UTMIP PLL control bits */ 2496e745f992SPeter De Schrijver reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1); 2497e745f992SPeter De Schrijver reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN; 2498e745f992SPeter De Schrijver reg |= UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP; 2499e745f992SPeter De Schrijver writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1); 250071422dbbSAlex Frid 250171422dbbSAlex Frid udelay(20); 2502e745f992SPeter De Schrijver 2503e745f992SPeter De Schrijver /* Enable samplers for SNPS, XUSB_HOST, XUSB_DEV */ 2504e745f992SPeter De Schrijver reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2); 2505e745f992SPeter De Schrijver reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERUP; 2506e745f992SPeter De Schrijver reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERUP; 2507e745f992SPeter De Schrijver reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERUP; 2508e745f992SPeter De Schrijver reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN; 2509e745f992SPeter De Schrijver reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN; 2510e745f992SPeter De Schrijver reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERDOWN; 2511e745f992SPeter De Schrijver writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2); 2512e745f992SPeter De Schrijver 2513e745f992SPeter De Schrijver /* Setup HW control of UTMIPLL */ 2514e745f992SPeter De Schrijver reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1); 2515e745f992SPeter De Schrijver reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN; 2516e745f992SPeter De Schrijver reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP; 2517e745f992SPeter De Schrijver writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1); 2518e745f992SPeter De Schrijver 2519e745f992SPeter De Schrijver reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); 2520e745f992SPeter De Schrijver reg |= UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET; 2521e745f992SPeter De Schrijver reg &= ~UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL; 2522e745f992SPeter De Schrijver writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); 2523e745f992SPeter De Schrijver 2524e745f992SPeter De Schrijver udelay(1); 2525e745f992SPeter De Schrijver 2526e745f992SPeter De Schrijver reg = readl_relaxed(clk_base + XUSB_PLL_CFG0); 2527e745f992SPeter De Schrijver reg &= ~XUSB_PLL_CFG0_UTMIPLL_LOCK_DLY; 2528e745f992SPeter De Schrijver writel_relaxed(reg, clk_base + XUSB_PLL_CFG0); 2529e745f992SPeter De Schrijver 2530e745f992SPeter De Schrijver udelay(1); 2531e745f992SPeter De Schrijver 2532e745f992SPeter De Schrijver /* Enable HW control UTMIPLL */ 2533e745f992SPeter De Schrijver reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); 2534e745f992SPeter De Schrijver reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE; 2535e745f992SPeter De Schrijver writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); 2536e745f992SPeter De Schrijver } 2537e745f992SPeter De Schrijver 2538e745f992SPeter De Schrijver static int tegra210_enable_pllu(void) 2539e745f992SPeter De Schrijver { 2540e745f992SPeter De Schrijver struct tegra_clk_pll_freq_table *fentry; 2541e745f992SPeter De Schrijver struct tegra_clk_pll pllu; 2542e745f992SPeter De Schrijver u32 reg; 2543e745f992SPeter De Schrijver 2544e745f992SPeter De Schrijver for (fentry = pll_u_freq_table; fentry->input_rate; fentry++) { 2545e745f992SPeter De Schrijver if (fentry->input_rate == pll_ref_freq) 2546e745f992SPeter De Schrijver break; 2547e745f992SPeter De Schrijver } 2548e745f992SPeter De Schrijver 2549e745f992SPeter De Schrijver if (!fentry->input_rate) { 2550e745f992SPeter De Schrijver pr_err("Unknown PLL_U reference frequency %lu\n", pll_ref_freq); 2551e745f992SPeter De Schrijver return -EINVAL; 2552e745f992SPeter De Schrijver } 2553e745f992SPeter De Schrijver 2554e745f992SPeter De Schrijver /* clear IDDQ bit */ 2555e745f992SPeter De Schrijver pllu.params = &pll_u_vco_params; 2556e745f992SPeter De Schrijver reg = readl_relaxed(clk_base + pllu.params->ext_misc_reg[0]); 2557e745f992SPeter De Schrijver reg &= ~BIT(pllu.params->iddq_bit_idx); 2558e745f992SPeter De Schrijver writel_relaxed(reg, clk_base + pllu.params->ext_misc_reg[0]); 25597157c69aSAlex Frid udelay(5); 2560e745f992SPeter De Schrijver 2561e745f992SPeter De Schrijver reg = readl_relaxed(clk_base + PLLU_BASE); 2562e745f992SPeter De Schrijver reg &= ~GENMASK(20, 0); 2563e745f992SPeter De Schrijver reg |= fentry->m; 2564e745f992SPeter De Schrijver reg |= fentry->n << 8; 2565e745f992SPeter De Schrijver reg |= fentry->p << 16; 2566e745f992SPeter De Schrijver writel(reg, clk_base + PLLU_BASE); 25677157c69aSAlex Frid udelay(1); 2568e745f992SPeter De Schrijver reg |= PLL_ENABLE; 2569e745f992SPeter De Schrijver writel(reg, clk_base + PLLU_BASE); 2570e745f992SPeter De Schrijver 2571*22ef01a2SNicolin Chen readl_relaxed_poll_timeout_atomic(clk_base + PLLU_BASE, reg, 2572e745f992SPeter De Schrijver reg & PLL_BASE_LOCK, 2, 1000); 2573e745f992SPeter De Schrijver if (!(reg & PLL_BASE_LOCK)) { 2574e745f992SPeter De Schrijver pr_err("Timed out waiting for PLL_U to lock\n"); 2575e745f992SPeter De Schrijver return -ETIMEDOUT; 2576e745f992SPeter De Schrijver } 2577e745f992SPeter De Schrijver 2578e745f992SPeter De Schrijver return 0; 2579e745f992SPeter De Schrijver } 2580e745f992SPeter De Schrijver 2581e745f992SPeter De Schrijver static int tegra210_init_pllu(void) 2582e745f992SPeter De Schrijver { 2583e745f992SPeter De Schrijver u32 reg; 2584e745f992SPeter De Schrijver int err; 2585e745f992SPeter De Schrijver 2586e745f992SPeter De Schrijver tegra210_pllu_set_defaults(&pll_u_vco_params); 2587e745f992SPeter De Schrijver /* skip initialization when pllu is in hw controlled mode */ 2588e745f992SPeter De Schrijver reg = readl_relaxed(clk_base + PLLU_BASE); 2589e745f992SPeter De Schrijver if (reg & PLLU_BASE_OVERRIDE) { 2590e745f992SPeter De Schrijver if (!(reg & PLL_ENABLE)) { 2591e745f992SPeter De Schrijver err = tegra210_enable_pllu(); 2592e745f992SPeter De Schrijver if (err < 0) { 2593e745f992SPeter De Schrijver WARN_ON(1); 2594e745f992SPeter De Schrijver return err; 2595e745f992SPeter De Schrijver } 2596e745f992SPeter De Schrijver } 2597e745f992SPeter De Schrijver /* enable hw controlled mode */ 2598e745f992SPeter De Schrijver reg = readl_relaxed(clk_base + PLLU_BASE); 2599e745f992SPeter De Schrijver reg &= ~PLLU_BASE_OVERRIDE; 2600e745f992SPeter De Schrijver writel(reg, clk_base + PLLU_BASE); 2601e745f992SPeter De Schrijver 2602e745f992SPeter De Schrijver reg = readl_relaxed(clk_base + PLLU_HW_PWRDN_CFG0); 2603e745f992SPeter De Schrijver reg |= PLLU_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE | 2604e745f992SPeter De Schrijver PLLU_HW_PWRDN_CFG0_USE_SWITCH_DETECT | 2605e745f992SPeter De Schrijver PLLU_HW_PWRDN_CFG0_USE_LOCKDET; 2606e745f992SPeter De Schrijver reg &= ~(PLLU_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL | 2607e745f992SPeter De Schrijver PLLU_HW_PWRDN_CFG0_CLK_SWITCH_SWCTL); 2608e745f992SPeter De Schrijver writel_relaxed(reg, clk_base + PLLU_HW_PWRDN_CFG0); 2609e745f992SPeter De Schrijver 2610e745f992SPeter De Schrijver reg = readl_relaxed(clk_base + XUSB_PLL_CFG0); 2611e745f992SPeter De Schrijver reg &= ~XUSB_PLL_CFG0_PLLU_LOCK_DLY_MASK; 2612e745f992SPeter De Schrijver writel_relaxed(reg, clk_base + XUSB_PLL_CFG0); 2613e745f992SPeter De Schrijver udelay(1); 2614e745f992SPeter De Schrijver 2615e745f992SPeter De Schrijver reg = readl_relaxed(clk_base + PLLU_HW_PWRDN_CFG0); 2616e745f992SPeter De Schrijver reg |= PLLU_HW_PWRDN_CFG0_SEQ_ENABLE; 2617e745f992SPeter De Schrijver writel_relaxed(reg, clk_base + PLLU_HW_PWRDN_CFG0); 2618e745f992SPeter De Schrijver udelay(1); 2619e745f992SPeter De Schrijver 2620e745f992SPeter De Schrijver reg = readl_relaxed(clk_base + PLLU_BASE); 2621e745f992SPeter De Schrijver reg &= ~PLLU_BASE_CLKENABLE_USB; 2622e745f992SPeter De Schrijver writel_relaxed(reg, clk_base + PLLU_BASE); 2623e745f992SPeter De Schrijver } 2624e745f992SPeter De Schrijver 2625e745f992SPeter De Schrijver /* enable UTMIPLL hw control if not yet done by the bootloader */ 2626e745f992SPeter De Schrijver reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); 2627e745f992SPeter De Schrijver if (!(reg & UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE)) 2628e745f992SPeter De Schrijver tegra210_utmi_param_configure(); 2629e745f992SPeter De Schrijver 2630e745f992SPeter De Schrijver return 0; 2631e745f992SPeter De Schrijver } 2632e745f992SPeter De Schrijver 2633bc2e4d29SThierry Reding static const char * const sor1_out_parents[] = { 2634bc2e4d29SThierry Reding /* 2635bc2e4d29SThierry Reding * Bit 0 of the mux selects sor1_pad_clkout, irrespective of bit 1, so 2636bc2e4d29SThierry Reding * the sor1_pad_clkout parent appears twice in the list below. This is 2637bc2e4d29SThierry Reding * merely to support clk_get_parent() if firmware happened to set 2638bc2e4d29SThierry Reding * these bits to 0b11. While not an invalid setting, code should 2639bc2e4d29SThierry Reding * always set the bits to 0b01 to select sor1_pad_clkout. 2640bc2e4d29SThierry Reding */ 2641bc2e4d29SThierry Reding "sor_safe", "sor1_pad_clkout", "sor1", "sor1_pad_clkout", 2642bc2e4d29SThierry Reding }; 2643bc2e4d29SThierry Reding 2644bc2e4d29SThierry Reding static const char * const sor1_parents[] = { 2645bc2e4d29SThierry Reding "pll_p", "pll_d_out0", "pll_d2_out0", "clk_m", 2646bc2e4d29SThierry Reding }; 2647bc2e4d29SThierry Reding 2648bc2e4d29SThierry Reding static u32 sor1_parents_idx[] = { 0, 2, 5, 6 }; 2649bc2e4d29SThierry Reding 2650bc2e4d29SThierry Reding static struct tegra_periph_init_data tegra210_periph[] = { 2651bc2e4d29SThierry Reding TEGRA_INIT_DATA_TABLE("sor1", NULL, NULL, sor1_parents, 2652bc2e4d29SThierry Reding CLK_SOURCE_SOR1, 29, 0x7, 0, 0, 8, 1, 2653bc2e4d29SThierry Reding TEGRA_DIVIDER_ROUND_UP, 183, 0, tegra_clk_sor1, 2654bc2e4d29SThierry Reding sor1_parents_idx, 0, &sor1_lock), 2655bc2e4d29SThierry Reding }; 2656bc2e4d29SThierry Reding 26576b301a05SRhyland Klein static __init void tegra210_periph_clk_init(void __iomem *clk_base, 26586b301a05SRhyland Klein void __iomem *pmc_base) 26596b301a05SRhyland Klein { 26606b301a05SRhyland Klein struct clk *clk; 2661bc2e4d29SThierry Reding unsigned int i; 26626b301a05SRhyland Klein 26636b301a05SRhyland Klein /* xusb_ss_div2 */ 26646b301a05SRhyland Klein clk = clk_register_fixed_factor(NULL, "xusb_ss_div2", "xusb_ss_src", 0, 26656b301a05SRhyland Klein 1, 2); 26666b301a05SRhyland Klein clks[TEGRA210_CLK_XUSB_SS_DIV2] = clk; 26676b301a05SRhyland Klein 266874d3ba0bSThierry Reding clk = tegra_clk_register_periph_fixed("sor_safe", "pll_p", 0, clk_base, 266974d3ba0bSThierry Reding 1, 17, 222); 267074d3ba0bSThierry Reding clks[TEGRA210_CLK_SOR_SAFE] = clk; 267174d3ba0bSThierry Reding 26722e34c2acSThierry Reding clk = tegra_clk_register_periph_fixed("dpaux", "sor_safe", 0, clk_base, 2673eede7113SThierry Reding 1, 17, 181); 2674eede7113SThierry Reding clks[TEGRA210_CLK_DPAUX] = clk; 2675eede7113SThierry Reding 26762e34c2acSThierry Reding clk = tegra_clk_register_periph_fixed("dpaux1", "sor_safe", 0, clk_base, 2677eede7113SThierry Reding 1, 17, 207); 2678eede7113SThierry Reding clks[TEGRA210_CLK_DPAUX1] = clk; 2679eede7113SThierry Reding 2680bc2e4d29SThierry Reding clk = clk_register_mux_table(NULL, "sor1_out", sor1_out_parents, 2681bc2e4d29SThierry Reding ARRAY_SIZE(sor1_out_parents), 0, 2682bc2e4d29SThierry Reding clk_base + CLK_SOURCE_SOR1, 14, 0x3, 2683bc2e4d29SThierry Reding 0, NULL, &sor1_lock); 2684bc2e4d29SThierry Reding clks[TEGRA210_CLK_SOR1_OUT] = clk; 2685bc2e4d29SThierry Reding 26866b301a05SRhyland Klein /* pll_d_dsi_out */ 26876b301a05SRhyland Klein clk = clk_register_gate(NULL, "pll_d_dsi_out", "pll_d_out0", 0, 26886b301a05SRhyland Klein clk_base + PLLD_MISC0, 21, 0, &pll_d_lock); 26896b301a05SRhyland Klein clks[TEGRA210_CLK_PLL_D_DSI_OUT] = clk; 26906b301a05SRhyland Klein 26916b301a05SRhyland Klein /* dsia */ 26926b301a05SRhyland Klein clk = tegra_clk_register_periph_gate("dsia", "pll_d_dsi_out", 0, 26936b301a05SRhyland Klein clk_base, 0, 48, 26946b301a05SRhyland Klein periph_clk_enb_refcnt); 26956b301a05SRhyland Klein clks[TEGRA210_CLK_DSIA] = clk; 26966b301a05SRhyland Klein 26976b301a05SRhyland Klein /* dsib */ 26986b301a05SRhyland Klein clk = tegra_clk_register_periph_gate("dsib", "pll_d_dsi_out", 0, 26996b301a05SRhyland Klein clk_base, 0, 82, 27006b301a05SRhyland Klein periph_clk_enb_refcnt); 27016b301a05SRhyland Klein clks[TEGRA210_CLK_DSIB] = clk; 27026b301a05SRhyland Klein 27036b301a05SRhyland Klein /* emc mux */ 27046b301a05SRhyland Klein clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm, 27056b301a05SRhyland Klein ARRAY_SIZE(mux_pllmcp_clkm), 0, 27066b301a05SRhyland Klein clk_base + CLK_SOURCE_EMC, 27076b301a05SRhyland Klein 29, 3, 0, &emc_lock); 27086b301a05SRhyland Klein 27096b301a05SRhyland Klein clk = tegra_clk_register_mc("mc", "emc_mux", clk_base + CLK_SOURCE_EMC, 27106b301a05SRhyland Klein &emc_lock); 27116b301a05SRhyland Klein clks[TEGRA210_CLK_MC] = clk; 27126b301a05SRhyland Klein 27136b301a05SRhyland Klein /* cml0 */ 27146b301a05SRhyland Klein clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX, 27156b301a05SRhyland Klein 0, 0, &pll_e_lock); 27166b301a05SRhyland Klein clk_register_clkdev(clk, "cml0", NULL); 27176b301a05SRhyland Klein clks[TEGRA210_CLK_CML0] = clk; 27186b301a05SRhyland Klein 27196b301a05SRhyland Klein /* cml1 */ 27206b301a05SRhyland Klein clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX, 27216b301a05SRhyland Klein 1, 0, &pll_e_lock); 27226b301a05SRhyland Klein clk_register_clkdev(clk, "cml1", NULL); 27236b301a05SRhyland Klein clks[TEGRA210_CLK_CML1] = clk; 27246b301a05SRhyland Klein 272524c3ebefSPeter De Schrijver clk = tegra_clk_register_super_clk("aclk", aclk_parents, 272624c3ebefSPeter De Schrijver ARRAY_SIZE(aclk_parents), 0, clk_base + 0x6e0, 272724c3ebefSPeter De Schrijver 0, NULL); 272824c3ebefSPeter De Schrijver clks[TEGRA210_CLK_ACLK] = clk; 272924c3ebefSPeter De Schrijver 2730bc2e4d29SThierry Reding for (i = 0; i < ARRAY_SIZE(tegra210_periph); i++) { 2731bc2e4d29SThierry Reding struct tegra_periph_init_data *init = &tegra210_periph[i]; 2732bc2e4d29SThierry Reding struct clk **clkp; 2733bc2e4d29SThierry Reding 2734bc2e4d29SThierry Reding clkp = tegra_lookup_dt_id(init->clk_id, tegra210_clks); 2735bc2e4d29SThierry Reding if (!clkp) { 2736bc2e4d29SThierry Reding pr_warn("clock %u not found\n", init->clk_id); 2737bc2e4d29SThierry Reding continue; 2738bc2e4d29SThierry Reding } 2739bc2e4d29SThierry Reding 2740bc2e4d29SThierry Reding clk = tegra_clk_register_periph_data(clk_base, init); 2741bc2e4d29SThierry Reding *clkp = clk; 2742bc2e4d29SThierry Reding } 2743bc2e4d29SThierry Reding 27446b301a05SRhyland Klein tegra_periph_clk_init(clk_base, pmc_base, tegra210_clks, &pll_p_params); 27456b301a05SRhyland Klein } 27466b301a05SRhyland Klein 27476b301a05SRhyland Klein static void __init tegra210_pll_init(void __iomem *clk_base, 27486b301a05SRhyland Klein void __iomem *pmc) 27496b301a05SRhyland Klein { 27506b301a05SRhyland Klein struct clk *clk; 27516b301a05SRhyland Klein 27526b301a05SRhyland Klein /* PLLC */ 2753ac99afe5SAlex Frid clk = tegra_clk_register_pllc_tegra210("pll_c", "pll_ref", clk_base, 27546b301a05SRhyland Klein pmc, 0, &pll_c_params, NULL); 27556b301a05SRhyland Klein if (!WARN_ON(IS_ERR(clk))) 27566b301a05SRhyland Klein clk_register_clkdev(clk, "pll_c", NULL); 27576b301a05SRhyland Klein clks[TEGRA210_CLK_PLL_C] = clk; 27586b301a05SRhyland Klein 27596b301a05SRhyland Klein /* PLLC_OUT1 */ 27606b301a05SRhyland Klein clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c", 27616b301a05SRhyland Klein clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP, 27626b301a05SRhyland Klein 8, 8, 1, NULL); 27636b301a05SRhyland Klein clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div", 27646b301a05SRhyland Klein clk_base + PLLC_OUT, 1, 0, 27656b301a05SRhyland Klein CLK_SET_RATE_PARENT, 0, NULL); 27666b301a05SRhyland Klein clk_register_clkdev(clk, "pll_c_out1", NULL); 27676b301a05SRhyland Klein clks[TEGRA210_CLK_PLL_C_OUT1] = clk; 27686b301a05SRhyland Klein 27696b301a05SRhyland Klein /* PLLC_UD */ 27706b301a05SRhyland Klein clk = clk_register_fixed_factor(NULL, "pll_c_ud", "pll_c", 27716b301a05SRhyland Klein CLK_SET_RATE_PARENT, 1, 1); 27726b301a05SRhyland Klein clk_register_clkdev(clk, "pll_c_ud", NULL); 27736b301a05SRhyland Klein clks[TEGRA210_CLK_PLL_C_UD] = clk; 27746b301a05SRhyland Klein 27756b301a05SRhyland Klein /* PLLC2 */ 27766b301a05SRhyland Klein clk = tegra_clk_register_pllc_tegra210("pll_c2", "pll_ref", clk_base, 27776b301a05SRhyland Klein pmc, 0, &pll_c2_params, NULL); 27786b301a05SRhyland Klein clk_register_clkdev(clk, "pll_c2", NULL); 27796b301a05SRhyland Klein clks[TEGRA210_CLK_PLL_C2] = clk; 27806b301a05SRhyland Klein 27816b301a05SRhyland Klein /* PLLC3 */ 27826b301a05SRhyland Klein clk = tegra_clk_register_pllc_tegra210("pll_c3", "pll_ref", clk_base, 27836b301a05SRhyland Klein pmc, 0, &pll_c3_params, NULL); 27846b301a05SRhyland Klein clk_register_clkdev(clk, "pll_c3", NULL); 27856b301a05SRhyland Klein clks[TEGRA210_CLK_PLL_C3] = clk; 27866b301a05SRhyland Klein 27876b301a05SRhyland Klein /* PLLM */ 27886b301a05SRhyland Klein clk = tegra_clk_register_pllm("pll_m", "osc", clk_base, pmc, 27896b301a05SRhyland Klein CLK_SET_RATE_GATE, &pll_m_params, NULL); 27906b301a05SRhyland Klein clk_register_clkdev(clk, "pll_m", NULL); 27916b301a05SRhyland Klein clks[TEGRA210_CLK_PLL_M] = clk; 27926b301a05SRhyland Klein 27936b301a05SRhyland Klein /* PLLMB */ 27946b301a05SRhyland Klein clk = tegra_clk_register_pllmb("pll_mb", "osc", clk_base, pmc, 27956b301a05SRhyland Klein CLK_SET_RATE_GATE, &pll_mb_params, NULL); 27966b301a05SRhyland Klein clk_register_clkdev(clk, "pll_mb", NULL); 27976b301a05SRhyland Klein clks[TEGRA210_CLK_PLL_MB] = clk; 27986b301a05SRhyland Klein 27996b301a05SRhyland Klein /* PLLM_UD */ 28006b301a05SRhyland Klein clk = clk_register_fixed_factor(NULL, "pll_m_ud", "pll_m", 28016b301a05SRhyland Klein CLK_SET_RATE_PARENT, 1, 1); 28026b301a05SRhyland Klein clk_register_clkdev(clk, "pll_m_ud", NULL); 28036b301a05SRhyland Klein clks[TEGRA210_CLK_PLL_M_UD] = clk; 28046b301a05SRhyland Klein 28056b301a05SRhyland Klein /* PLLU_VCO */ 2806e745f992SPeter De Schrijver if (!tegra210_init_pllu()) { 2807e745f992SPeter De Schrijver clk = clk_register_fixed_rate(NULL, "pll_u_vco", "pll_ref", 0, 2808e745f992SPeter De Schrijver 480*1000*1000); 28096b301a05SRhyland Klein clk_register_clkdev(clk, "pll_u_vco", NULL); 28106b301a05SRhyland Klein clks[TEGRA210_CLK_PLL_U] = clk; 2811e745f992SPeter De Schrijver } 28126b301a05SRhyland Klein 28136b301a05SRhyland Klein /* PLLU_OUT */ 28146b301a05SRhyland Klein clk = clk_register_divider_table(NULL, "pll_u_out", "pll_u_vco", 0, 28156b301a05SRhyland Klein clk_base + PLLU_BASE, 16, 4, 0, 28166b301a05SRhyland Klein pll_vco_post_div_table, NULL); 28176b301a05SRhyland Klein clk_register_clkdev(clk, "pll_u_out", NULL); 28186b301a05SRhyland Klein clks[TEGRA210_CLK_PLL_U_OUT] = clk; 28196b301a05SRhyland Klein 28206b301a05SRhyland Klein /* PLLU_OUT1 */ 28216b301a05SRhyland Klein clk = tegra_clk_register_divider("pll_u_out1_div", "pll_u_out", 28226b301a05SRhyland Klein clk_base + PLLU_OUTA, 0, 28236b301a05SRhyland Klein TEGRA_DIVIDER_ROUND_UP, 28246b301a05SRhyland Klein 8, 8, 1, &pll_u_lock); 28256b301a05SRhyland Klein clk = tegra_clk_register_pll_out("pll_u_out1", "pll_u_out1_div", 28266b301a05SRhyland Klein clk_base + PLLU_OUTA, 1, 0, 28276b301a05SRhyland Klein CLK_SET_RATE_PARENT, 0, &pll_u_lock); 28286b301a05SRhyland Klein clk_register_clkdev(clk, "pll_u_out1", NULL); 28296b301a05SRhyland Klein clks[TEGRA210_CLK_PLL_U_OUT1] = clk; 28306b301a05SRhyland Klein 28316b301a05SRhyland Klein /* PLLU_OUT2 */ 28326b301a05SRhyland Klein clk = tegra_clk_register_divider("pll_u_out2_div", "pll_u_out", 28336b301a05SRhyland Klein clk_base + PLLU_OUTA, 0, 28346b301a05SRhyland Klein TEGRA_DIVIDER_ROUND_UP, 28356b301a05SRhyland Klein 24, 8, 1, &pll_u_lock); 28366b301a05SRhyland Klein clk = tegra_clk_register_pll_out("pll_u_out2", "pll_u_out2_div", 28376b301a05SRhyland Klein clk_base + PLLU_OUTA, 17, 16, 28386b301a05SRhyland Klein CLK_SET_RATE_PARENT, 0, &pll_u_lock); 28396b301a05SRhyland Klein clk_register_clkdev(clk, "pll_u_out2", NULL); 28406b301a05SRhyland Klein clks[TEGRA210_CLK_PLL_U_OUT2] = clk; 28416b301a05SRhyland Klein 28426b301a05SRhyland Klein /* PLLU_480M */ 28436b301a05SRhyland Klein clk = clk_register_gate(NULL, "pll_u_480M", "pll_u_vco", 28446b301a05SRhyland Klein CLK_SET_RATE_PARENT, clk_base + PLLU_BASE, 28456b301a05SRhyland Klein 22, 0, &pll_u_lock); 28466b301a05SRhyland Klein clk_register_clkdev(clk, "pll_u_480M", NULL); 28476b301a05SRhyland Klein clks[TEGRA210_CLK_PLL_U_480M] = clk; 28486b301a05SRhyland Klein 28496b301a05SRhyland Klein /* PLLU_60M */ 28506b301a05SRhyland Klein clk = clk_register_gate(NULL, "pll_u_60M", "pll_u_out2", 28516b301a05SRhyland Klein CLK_SET_RATE_PARENT, clk_base + PLLU_BASE, 28527157c69aSAlex Frid 23, 0, &pll_u_lock); 28536b301a05SRhyland Klein clk_register_clkdev(clk, "pll_u_60M", NULL); 28546b301a05SRhyland Klein clks[TEGRA210_CLK_PLL_U_60M] = clk; 28556b301a05SRhyland Klein 28566b301a05SRhyland Klein /* PLLU_48M */ 28576b301a05SRhyland Klein clk = clk_register_gate(NULL, "pll_u_48M", "pll_u_out1", 28586b301a05SRhyland Klein CLK_SET_RATE_PARENT, clk_base + PLLU_BASE, 28597157c69aSAlex Frid 25, 0, &pll_u_lock); 28606b301a05SRhyland Klein clk_register_clkdev(clk, "pll_u_48M", NULL); 28616b301a05SRhyland Klein clks[TEGRA210_CLK_PLL_U_48M] = clk; 28626b301a05SRhyland Klein 28636b301a05SRhyland Klein /* PLLD */ 28646b301a05SRhyland Klein clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc, 0, 28656b301a05SRhyland Klein &pll_d_params, &pll_d_lock); 28666b301a05SRhyland Klein clk_register_clkdev(clk, "pll_d", NULL); 28676b301a05SRhyland Klein clks[TEGRA210_CLK_PLL_D] = clk; 28686b301a05SRhyland Klein 28696b301a05SRhyland Klein /* PLLD_OUT0 */ 28706b301a05SRhyland Klein clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d", 28716b301a05SRhyland Klein CLK_SET_RATE_PARENT, 1, 2); 28726b301a05SRhyland Klein clk_register_clkdev(clk, "pll_d_out0", NULL); 28736b301a05SRhyland Klein clks[TEGRA210_CLK_PLL_D_OUT0] = clk; 28746b301a05SRhyland Klein 28756b301a05SRhyland Klein /* PLLRE */ 2876926655f9SRhyland Klein clk = tegra_clk_register_pllre_tegra210("pll_re_vco", "pll_ref", 2877926655f9SRhyland Klein clk_base, pmc, 0, 2878926655f9SRhyland Klein &pll_re_vco_params, 2879926655f9SRhyland Klein &pll_re_lock, pll_ref_freq); 28806b301a05SRhyland Klein clk_register_clkdev(clk, "pll_re_vco", NULL); 28816b301a05SRhyland Klein clks[TEGRA210_CLK_PLL_RE_VCO] = clk; 28826b301a05SRhyland Klein 28836b301a05SRhyland Klein clk = clk_register_divider_table(NULL, "pll_re_out", "pll_re_vco", 0, 28846b301a05SRhyland Klein clk_base + PLLRE_BASE, 16, 5, 0, 28856b301a05SRhyland Klein pll_vco_post_div_table, &pll_re_lock); 28866b301a05SRhyland Klein clk_register_clkdev(clk, "pll_re_out", NULL); 28876b301a05SRhyland Klein clks[TEGRA210_CLK_PLL_RE_OUT] = clk; 28886b301a05SRhyland Klein 2889926655f9SRhyland Klein clk = tegra_clk_register_divider("pll_re_out1_div", "pll_re_vco", 2890926655f9SRhyland Klein clk_base + PLLRE_OUT1, 0, 2891926655f9SRhyland Klein TEGRA_DIVIDER_ROUND_UP, 2892926655f9SRhyland Klein 8, 8, 1, NULL); 2893926655f9SRhyland Klein clk = tegra_clk_register_pll_out("pll_re_out1", "pll_re_out1_div", 2894926655f9SRhyland Klein clk_base + PLLRE_OUT1, 1, 0, 2895926655f9SRhyland Klein CLK_SET_RATE_PARENT, 0, NULL); 2896926655f9SRhyland Klein clks[TEGRA210_CLK_PLL_RE_OUT1] = clk; 2897926655f9SRhyland Klein 28986b301a05SRhyland Klein /* PLLE */ 28996b301a05SRhyland Klein clk = tegra_clk_register_plle_tegra210("pll_e", "pll_ref", 29006b301a05SRhyland Klein clk_base, 0, &pll_e_params, NULL); 29016b301a05SRhyland Klein clk_register_clkdev(clk, "pll_e", NULL); 29026b301a05SRhyland Klein clks[TEGRA210_CLK_PLL_E] = clk; 29036b301a05SRhyland Klein 29046b301a05SRhyland Klein /* PLLC4 */ 29056b301a05SRhyland Klein clk = tegra_clk_register_pllre("pll_c4_vco", "pll_ref", clk_base, pmc, 29066b301a05SRhyland Klein 0, &pll_c4_vco_params, NULL, pll_ref_freq); 29076b301a05SRhyland Klein clk_register_clkdev(clk, "pll_c4_vco", NULL); 29086b301a05SRhyland Klein clks[TEGRA210_CLK_PLL_C4] = clk; 29096b301a05SRhyland Klein 29106b301a05SRhyland Klein /* PLLC4_OUT0 */ 29116b301a05SRhyland Klein clk = clk_register_divider_table(NULL, "pll_c4_out0", "pll_c4_vco", 0, 29126b301a05SRhyland Klein clk_base + PLLC4_BASE, 19, 4, 0, 29136b301a05SRhyland Klein pll_vco_post_div_table, NULL); 29146b301a05SRhyland Klein clk_register_clkdev(clk, "pll_c4_out0", NULL); 29156b301a05SRhyland Klein clks[TEGRA210_CLK_PLL_C4_OUT0] = clk; 29166b301a05SRhyland Klein 29176b301a05SRhyland Klein /* PLLC4_OUT1 */ 29186b301a05SRhyland Klein clk = clk_register_fixed_factor(NULL, "pll_c4_out1", "pll_c4_vco", 29196b301a05SRhyland Klein CLK_SET_RATE_PARENT, 1, 3); 29206b301a05SRhyland Klein clk_register_clkdev(clk, "pll_c4_out1", NULL); 29216b301a05SRhyland Klein clks[TEGRA210_CLK_PLL_C4_OUT1] = clk; 29226b301a05SRhyland Klein 29236b301a05SRhyland Klein /* PLLC4_OUT2 */ 29246b301a05SRhyland Klein clk = clk_register_fixed_factor(NULL, "pll_c4_out2", "pll_c4_vco", 29256b301a05SRhyland Klein CLK_SET_RATE_PARENT, 1, 5); 29266b301a05SRhyland Klein clk_register_clkdev(clk, "pll_c4_out2", NULL); 29276b301a05SRhyland Klein clks[TEGRA210_CLK_PLL_C4_OUT2] = clk; 29286b301a05SRhyland Klein 29296b301a05SRhyland Klein /* PLLC4_OUT3 */ 29306b301a05SRhyland Klein clk = tegra_clk_register_divider("pll_c4_out3_div", "pll_c4_out0", 29316b301a05SRhyland Klein clk_base + PLLC4_OUT, 0, TEGRA_DIVIDER_ROUND_UP, 29326b301a05SRhyland Klein 8, 8, 1, NULL); 29336b301a05SRhyland Klein clk = tegra_clk_register_pll_out("pll_c4_out3", "pll_c4_out3_div", 29346b301a05SRhyland Klein clk_base + PLLC4_OUT, 1, 0, 29356b301a05SRhyland Klein CLK_SET_RATE_PARENT, 0, NULL); 29366b301a05SRhyland Klein clk_register_clkdev(clk, "pll_c4_out3", NULL); 29376b301a05SRhyland Klein clks[TEGRA210_CLK_PLL_C4_OUT3] = clk; 29386b301a05SRhyland Klein 29396b301a05SRhyland Klein /* PLLDP */ 29406b301a05SRhyland Klein clk = tegra_clk_register_pllss_tegra210("pll_dp", "pll_ref", clk_base, 29416b301a05SRhyland Klein 0, &pll_dp_params, NULL); 29426b301a05SRhyland Klein clk_register_clkdev(clk, "pll_dp", NULL); 29436b301a05SRhyland Klein clks[TEGRA210_CLK_PLL_DP] = clk; 29446b301a05SRhyland Klein 29456b301a05SRhyland Klein /* PLLD2 */ 29466b301a05SRhyland Klein clk = tegra_clk_register_pllss_tegra210("pll_d2", "pll_ref", clk_base, 29476b301a05SRhyland Klein 0, &pll_d2_params, NULL); 29486b301a05SRhyland Klein clk_register_clkdev(clk, "pll_d2", NULL); 29496b301a05SRhyland Klein clks[TEGRA210_CLK_PLL_D2] = clk; 29506b301a05SRhyland Klein 29516b301a05SRhyland Klein /* PLLD2_OUT0 */ 29526b301a05SRhyland Klein clk = clk_register_fixed_factor(NULL, "pll_d2_out0", "pll_d2", 29536b301a05SRhyland Klein CLK_SET_RATE_PARENT, 1, 1); 29546b301a05SRhyland Klein clk_register_clkdev(clk, "pll_d2_out0", NULL); 29556b301a05SRhyland Klein clks[TEGRA210_CLK_PLL_D2_OUT0] = clk; 29566b301a05SRhyland Klein 29576b301a05SRhyland Klein /* PLLP_OUT2 */ 29586b301a05SRhyland Klein clk = clk_register_fixed_factor(NULL, "pll_p_out2", "pll_p", 29596b301a05SRhyland Klein CLK_SET_RATE_PARENT, 1, 2); 29606b301a05SRhyland Klein clk_register_clkdev(clk, "pll_p_out2", NULL); 29616b301a05SRhyland Klein clks[TEGRA210_CLK_PLL_P_OUT2] = clk; 29626b301a05SRhyland Klein 29636b301a05SRhyland Klein } 29646b301a05SRhyland Klein 29656b301a05SRhyland Klein /* Tegra210 CPU clock and reset control functions */ 29666b301a05SRhyland Klein static void tegra210_wait_cpu_in_reset(u32 cpu) 29676b301a05SRhyland Klein { 29686b301a05SRhyland Klein unsigned int reg; 29696b301a05SRhyland Klein 29706b301a05SRhyland Klein do { 29716b301a05SRhyland Klein reg = readl(clk_base + CLK_RST_CONTROLLER_CPU_CMPLX_STATUS); 29726b301a05SRhyland Klein cpu_relax(); 29736b301a05SRhyland Klein } while (!(reg & (1 << cpu))); /* check CPU been reset or not */ 29746b301a05SRhyland Klein } 29756b301a05SRhyland Klein 29766b301a05SRhyland Klein static void tegra210_disable_cpu_clock(u32 cpu) 29776b301a05SRhyland Klein { 29786b301a05SRhyland Klein /* flow controller would take care in the power sequence. */ 29796b301a05SRhyland Klein } 29806b301a05SRhyland Klein 29816b301a05SRhyland Klein #ifdef CONFIG_PM_SLEEP 29826b301a05SRhyland Klein static void tegra210_cpu_clock_suspend(void) 29836b301a05SRhyland Klein { 29846b301a05SRhyland Klein /* switch coresite to clk_m, save off original source */ 29856b301a05SRhyland Klein tegra210_cpu_clk_sctx.clk_csite_src = 29866b301a05SRhyland Klein readl(clk_base + CLK_SOURCE_CSITE); 29876b301a05SRhyland Klein writel(3 << 30, clk_base + CLK_SOURCE_CSITE); 29886b301a05SRhyland Klein } 29896b301a05SRhyland Klein 29906b301a05SRhyland Klein static void tegra210_cpu_clock_resume(void) 29916b301a05SRhyland Klein { 29926b301a05SRhyland Klein writel(tegra210_cpu_clk_sctx.clk_csite_src, 29936b301a05SRhyland Klein clk_base + CLK_SOURCE_CSITE); 29946b301a05SRhyland Klein } 29956b301a05SRhyland Klein #endif 29966b301a05SRhyland Klein 29976b301a05SRhyland Klein static struct tegra_cpu_car_ops tegra210_cpu_car_ops = { 29986b301a05SRhyland Klein .wait_for_reset = tegra210_wait_cpu_in_reset, 29996b301a05SRhyland Klein .disable_clock = tegra210_disable_cpu_clock, 30006b301a05SRhyland Klein #ifdef CONFIG_PM_SLEEP 30016b301a05SRhyland Klein .suspend = tegra210_cpu_clock_suspend, 30026b301a05SRhyland Klein .resume = tegra210_cpu_clock_resume, 30036b301a05SRhyland Klein #endif 30046b301a05SRhyland Klein }; 30056b301a05SRhyland Klein 30066b301a05SRhyland Klein static const struct of_device_id pmc_match[] __initconst = { 30076b301a05SRhyland Klein { .compatible = "nvidia,tegra210-pmc" }, 30086b301a05SRhyland Klein { }, 30096b301a05SRhyland Klein }; 30106b301a05SRhyland Klein 30116b301a05SRhyland Klein static struct tegra_clk_init_table init_table[] __initdata = { 30126b301a05SRhyland Klein { TEGRA210_CLK_UARTA, TEGRA210_CLK_PLL_P, 408000000, 0 }, 30136b301a05SRhyland Klein { TEGRA210_CLK_UARTB, TEGRA210_CLK_PLL_P, 408000000, 0 }, 30146b301a05SRhyland Klein { TEGRA210_CLK_UARTC, TEGRA210_CLK_PLL_P, 408000000, 0 }, 30156b301a05SRhyland Klein { TEGRA210_CLK_UARTD, TEGRA210_CLK_PLL_P, 408000000, 0 }, 30166b301a05SRhyland Klein { TEGRA210_CLK_PLL_A, TEGRA210_CLK_CLK_MAX, 564480000, 1 }, 30176b301a05SRhyland Klein { TEGRA210_CLK_PLL_A_OUT0, TEGRA210_CLK_CLK_MAX, 11289600, 1 }, 30186b301a05SRhyland Klein { TEGRA210_CLK_EXTERN1, TEGRA210_CLK_PLL_A_OUT0, 0, 1 }, 30196b301a05SRhyland Klein { TEGRA210_CLK_CLK_OUT_1_MUX, TEGRA210_CLK_EXTERN1, 0, 1 }, 30206b301a05SRhyland Klein { TEGRA210_CLK_CLK_OUT_1, TEGRA210_CLK_CLK_MAX, 0, 1 }, 30216b301a05SRhyland Klein { TEGRA210_CLK_I2S0, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 }, 30226b301a05SRhyland Klein { TEGRA210_CLK_I2S1, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 }, 30236b301a05SRhyland Klein { TEGRA210_CLK_I2S2, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 }, 30246b301a05SRhyland Klein { TEGRA210_CLK_I2S3, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 }, 30256b301a05SRhyland Klein { TEGRA210_CLK_I2S4, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 }, 30266b301a05SRhyland Klein { TEGRA210_CLK_HOST1X, TEGRA210_CLK_PLL_P, 136000000, 1 }, 30276b301a05SRhyland Klein { TEGRA210_CLK_SCLK_MUX, TEGRA210_CLK_PLL_P, 0, 1 }, 30286b301a05SRhyland Klein { TEGRA210_CLK_SCLK, TEGRA210_CLK_CLK_MAX, 102000000, 1 }, 30296b301a05SRhyland Klein { TEGRA210_CLK_DFLL_SOC, TEGRA210_CLK_PLL_P, 51000000, 1 }, 30306b301a05SRhyland Klein { TEGRA210_CLK_DFLL_REF, TEGRA210_CLK_PLL_P, 51000000, 1 }, 30316b301a05SRhyland Klein { TEGRA210_CLK_SBC4, TEGRA210_CLK_PLL_P, 12000000, 1 }, 30326b301a05SRhyland Klein { TEGRA210_CLK_PLL_RE_VCO, TEGRA210_CLK_CLK_MAX, 672000000, 1 }, 30336b301a05SRhyland Klein { TEGRA210_CLK_XUSB_GATE, TEGRA210_CLK_CLK_MAX, 0, 1 }, 30346b301a05SRhyland Klein { TEGRA210_CLK_XUSB_SS_SRC, TEGRA210_CLK_PLL_U_480M, 120000000, 0 }, 30356b301a05SRhyland Klein { TEGRA210_CLK_XUSB_FS_SRC, TEGRA210_CLK_PLL_U_48M, 48000000, 0 }, 30366b301a05SRhyland Klein { TEGRA210_CLK_XUSB_HS_SRC, TEGRA210_CLK_XUSB_SS_SRC, 120000000, 0 }, 30376b301a05SRhyland Klein { TEGRA210_CLK_XUSB_SSP_SRC, TEGRA210_CLK_XUSB_SS_SRC, 120000000, 0 }, 30386b301a05SRhyland Klein { TEGRA210_CLK_XUSB_FALCON_SRC, TEGRA210_CLK_PLL_P_OUT_XUSB, 204000000, 0 }, 30396b301a05SRhyland Klein { TEGRA210_CLK_XUSB_HOST_SRC, TEGRA210_CLK_PLL_P_OUT_XUSB, 102000000, 0 }, 30406b301a05SRhyland Klein { TEGRA210_CLK_XUSB_DEV_SRC, TEGRA210_CLK_PLL_P_OUT_XUSB, 102000000, 0 }, 30416b301a05SRhyland Klein { TEGRA210_CLK_SATA, TEGRA210_CLK_PLL_P, 104000000, 0 }, 30426b301a05SRhyland Klein { TEGRA210_CLK_SATA_OOB, TEGRA210_CLK_PLL_P, 204000000, 0 }, 30436b301a05SRhyland Klein { TEGRA210_CLK_EMC, TEGRA210_CLK_CLK_MAX, 0, 1 }, 30446b301a05SRhyland Klein { TEGRA210_CLK_MSELECT, TEGRA210_CLK_CLK_MAX, 0, 1 }, 30456b301a05SRhyland Klein { TEGRA210_CLK_CSITE, TEGRA210_CLK_CLK_MAX, 0, 1 }, 3046bea1baa1SPeter De Schrijver /* TODO find a way to enable this on-demand */ 3047bea1baa1SPeter De Schrijver { TEGRA210_CLK_DBGAPB, TEGRA210_CLK_CLK_MAX, 0, 1 }, 30486b301a05SRhyland Klein { TEGRA210_CLK_TSENSOR, TEGRA210_CLK_CLK_M, 400000, 0 }, 30496b301a05SRhyland Klein { TEGRA210_CLK_I2C1, TEGRA210_CLK_PLL_P, 0, 0 }, 30506b301a05SRhyland Klein { TEGRA210_CLK_I2C2, TEGRA210_CLK_PLL_P, 0, 0 }, 30516b301a05SRhyland Klein { TEGRA210_CLK_I2C3, TEGRA210_CLK_PLL_P, 0, 0 }, 30526b301a05SRhyland Klein { TEGRA210_CLK_I2C4, TEGRA210_CLK_PLL_P, 0, 0 }, 30536b301a05SRhyland Klein { TEGRA210_CLK_I2C5, TEGRA210_CLK_PLL_P, 0, 0 }, 30546b301a05SRhyland Klein { TEGRA210_CLK_I2C6, TEGRA210_CLK_PLL_P, 0, 0 }, 30556b301a05SRhyland Klein { TEGRA210_CLK_PLL_DP, TEGRA210_CLK_CLK_MAX, 270000000, 0 }, 30566b301a05SRhyland Klein { TEGRA210_CLK_SOC_THERM, TEGRA210_CLK_PLL_P, 51000000, 0 }, 30576b301a05SRhyland Klein { TEGRA210_CLK_CCLK_G, TEGRA210_CLK_CLK_MAX, 0, 1 }, 3058e745f992SPeter De Schrijver { TEGRA210_CLK_PLL_U_OUT1, TEGRA210_CLK_CLK_MAX, 48000000, 1 }, 3059e745f992SPeter De Schrijver { TEGRA210_CLK_PLL_U_OUT2, TEGRA210_CLK_CLK_MAX, 60000000, 1 }, 30606b301a05SRhyland Klein /* This MUST be the last entry. */ 30616b301a05SRhyland Klein { TEGRA210_CLK_CLK_MAX, TEGRA210_CLK_CLK_MAX, 0, 0 }, 30626b301a05SRhyland Klein }; 30636b301a05SRhyland Klein 30646b301a05SRhyland Klein /** 30656b301a05SRhyland Klein * tegra210_clock_apply_init_table - initialize clocks on Tegra210 SoCs 30666b301a05SRhyland Klein * 30676b301a05SRhyland Klein * Program an initial clock rate and enable or disable clocks needed 30686b301a05SRhyland Klein * by the rest of the kernel, for Tegra210 SoCs. It is intended to be 30696b301a05SRhyland Klein * called by assigning a pointer to it to tegra_clk_apply_init_table - 30706b301a05SRhyland Klein * this will be called as an arch_initcall. No return value. 30716b301a05SRhyland Klein */ 30726b301a05SRhyland Klein static void __init tegra210_clock_apply_init_table(void) 30736b301a05SRhyland Klein { 30746b301a05SRhyland Klein tegra_init_from_table(init_table, clks, TEGRA210_CLK_CLK_MAX); 30756b301a05SRhyland Klein } 30766b301a05SRhyland Klein 30776b301a05SRhyland Klein /** 307868d724ceSPeter De Schrijver * tegra210_car_barrier - wait for pending writes to the CAR to complete 307968d724ceSPeter De Schrijver * 308068d724ceSPeter De Schrijver * Wait for any outstanding writes to the CAR MMIO space from this CPU 308168d724ceSPeter De Schrijver * to complete before continuing execution. No return value. 308268d724ceSPeter De Schrijver */ 308368d724ceSPeter De Schrijver static void tegra210_car_barrier(void) 308468d724ceSPeter De Schrijver { 308568d724ceSPeter De Schrijver readl_relaxed(clk_base + RST_DFLL_DVCO); 308668d724ceSPeter De Schrijver } 308768d724ceSPeter De Schrijver 308868d724ceSPeter De Schrijver /** 308968d724ceSPeter De Schrijver * tegra210_clock_assert_dfll_dvco_reset - assert the DFLL's DVCO reset 309068d724ceSPeter De Schrijver * 309168d724ceSPeter De Schrijver * Assert the reset line of the DFLL's DVCO. No return value. 309268d724ceSPeter De Schrijver */ 309368d724ceSPeter De Schrijver static void tegra210_clock_assert_dfll_dvco_reset(void) 309468d724ceSPeter De Schrijver { 309568d724ceSPeter De Schrijver u32 v; 309668d724ceSPeter De Schrijver 309768d724ceSPeter De Schrijver v = readl_relaxed(clk_base + RST_DFLL_DVCO); 309868d724ceSPeter De Schrijver v |= (1 << DVFS_DFLL_RESET_SHIFT); 309968d724ceSPeter De Schrijver writel_relaxed(v, clk_base + RST_DFLL_DVCO); 310068d724ceSPeter De Schrijver tegra210_car_barrier(); 310168d724ceSPeter De Schrijver } 310268d724ceSPeter De Schrijver 310368d724ceSPeter De Schrijver /** 310468d724ceSPeter De Schrijver * tegra210_clock_deassert_dfll_dvco_reset - deassert the DFLL's DVCO reset 310568d724ceSPeter De Schrijver * 310668d724ceSPeter De Schrijver * Deassert the reset line of the DFLL's DVCO, allowing the DVCO to 310768d724ceSPeter De Schrijver * operate. No return value. 310868d724ceSPeter De Schrijver */ 310968d724ceSPeter De Schrijver static void tegra210_clock_deassert_dfll_dvco_reset(void) 311068d724ceSPeter De Schrijver { 311168d724ceSPeter De Schrijver u32 v; 311268d724ceSPeter De Schrijver 311368d724ceSPeter De Schrijver v = readl_relaxed(clk_base + RST_DFLL_DVCO); 311468d724ceSPeter De Schrijver v &= ~(1 << DVFS_DFLL_RESET_SHIFT); 311568d724ceSPeter De Schrijver writel_relaxed(v, clk_base + RST_DFLL_DVCO); 311668d724ceSPeter De Schrijver tegra210_car_barrier(); 311768d724ceSPeter De Schrijver } 311868d724ceSPeter De Schrijver 311968d724ceSPeter De Schrijver static int tegra210_reset_assert(unsigned long id) 312068d724ceSPeter De Schrijver { 312168d724ceSPeter De Schrijver if (id == TEGRA210_RST_DFLL_DVCO) 312268d724ceSPeter De Schrijver tegra210_clock_assert_dfll_dvco_reset(); 312368d724ceSPeter De Schrijver else if (id == TEGRA210_RST_ADSP) 312468d724ceSPeter De Schrijver writel(GENMASK(26, 21) | BIT(7), 312568d724ceSPeter De Schrijver clk_base + CLK_RST_CONTROLLER_RST_DEV_Y_SET); 312668d724ceSPeter De Schrijver else 312768d724ceSPeter De Schrijver return -EINVAL; 312868d724ceSPeter De Schrijver 312968d724ceSPeter De Schrijver return 0; 313068d724ceSPeter De Schrijver } 313168d724ceSPeter De Schrijver 313268d724ceSPeter De Schrijver static int tegra210_reset_deassert(unsigned long id) 313368d724ceSPeter De Schrijver { 313468d724ceSPeter De Schrijver if (id == TEGRA210_RST_DFLL_DVCO) 313568d724ceSPeter De Schrijver tegra210_clock_deassert_dfll_dvco_reset(); 313668d724ceSPeter De Schrijver else if (id == TEGRA210_RST_ADSP) { 313768d724ceSPeter De Schrijver writel(BIT(21), clk_base + CLK_RST_CONTROLLER_RST_DEV_Y_CLR); 313868d724ceSPeter De Schrijver /* 313968d724ceSPeter De Schrijver * Considering adsp cpu clock (min: 12.5MHZ, max: 1GHz) 314068d724ceSPeter De Schrijver * a delay of 5us ensures that it's at least 314168d724ceSPeter De Schrijver * 6 * adsp_cpu_cycle_period long. 314268d724ceSPeter De Schrijver */ 314368d724ceSPeter De Schrijver udelay(5); 314468d724ceSPeter De Schrijver writel(GENMASK(26, 22) | BIT(7), 314568d724ceSPeter De Schrijver clk_base + CLK_RST_CONTROLLER_RST_DEV_Y_CLR); 314668d724ceSPeter De Schrijver } else 314768d724ceSPeter De Schrijver return -EINVAL; 314868d724ceSPeter De Schrijver 314968d724ceSPeter De Schrijver return 0; 315068d724ceSPeter De Schrijver } 315168d724ceSPeter De Schrijver 315268d724ceSPeter De Schrijver /** 31536b301a05SRhyland Klein * tegra210_clock_init - Tegra210-specific clock initialization 31546b301a05SRhyland Klein * @np: struct device_node * of the DT node for the SoC CAR IP block 31556b301a05SRhyland Klein * 31566b301a05SRhyland Klein * Register most SoC clocks for the Tegra210 system-on-chip. Intended 31576b301a05SRhyland Klein * to be called by the OF init code when a DT node with the 31586b301a05SRhyland Klein * "nvidia,tegra210-car" string is encountered, and declared with 31596b301a05SRhyland Klein * CLK_OF_DECLARE. No return value. 31606b301a05SRhyland Klein */ 31616b301a05SRhyland Klein static void __init tegra210_clock_init(struct device_node *np) 31626b301a05SRhyland Klein { 31636b301a05SRhyland Klein struct device_node *node; 31646b301a05SRhyland Klein u32 value, clk_m_div; 31656b301a05SRhyland Klein 31666b301a05SRhyland Klein clk_base = of_iomap(np, 0); 31676b301a05SRhyland Klein if (!clk_base) { 31686b301a05SRhyland Klein pr_err("ioremap tegra210 CAR failed\n"); 31696b301a05SRhyland Klein return; 31706b301a05SRhyland Klein } 31716b301a05SRhyland Klein 31726b301a05SRhyland Klein node = of_find_matching_node(NULL, pmc_match); 31736b301a05SRhyland Klein if (!node) { 31746b301a05SRhyland Klein pr_err("Failed to find pmc node\n"); 31756b301a05SRhyland Klein WARN_ON(1); 31766b301a05SRhyland Klein return; 31776b301a05SRhyland Klein } 31786b301a05SRhyland Klein 31796b301a05SRhyland Klein pmc_base = of_iomap(node, 0); 31806b301a05SRhyland Klein if (!pmc_base) { 31816b301a05SRhyland Klein pr_err("Can't map pmc registers\n"); 31826b301a05SRhyland Klein WARN_ON(1); 31836b301a05SRhyland Klein return; 31846b301a05SRhyland Klein } 31856b301a05SRhyland Klein 31866b301a05SRhyland Klein clks = tegra_clk_init(clk_base, TEGRA210_CLK_CLK_MAX, 31876b301a05SRhyland Klein TEGRA210_CAR_BANK_COUNT); 31886b301a05SRhyland Klein if (!clks) 31896b301a05SRhyland Klein return; 31906b301a05SRhyland Klein 31916b301a05SRhyland Klein value = clk_readl(clk_base + SPARE_REG0) >> CLK_M_DIVISOR_SHIFT; 31926b301a05SRhyland Klein clk_m_div = (value & CLK_M_DIVISOR_MASK) + 1; 31936b301a05SRhyland Klein 31946b301a05SRhyland Klein if (tegra_osc_clk_init(clk_base, tegra210_clks, tegra210_input_freq, 31956b301a05SRhyland Klein ARRAY_SIZE(tegra210_input_freq), clk_m_div, 31966b301a05SRhyland Klein &osc_freq, &pll_ref_freq) < 0) 31976b301a05SRhyland Klein return; 31986b301a05SRhyland Klein 31996b301a05SRhyland Klein tegra_fixed_clk_init(tegra210_clks); 32006b301a05SRhyland Klein tegra210_pll_init(clk_base, pmc_base); 32016b301a05SRhyland Klein tegra210_periph_clk_init(clk_base, pmc_base); 32026b301a05SRhyland Klein tegra_audio_clk_init(clk_base, pmc_base, tegra210_clks, 32036b301a05SRhyland Klein tegra210_audio_plls, 32046b301a05SRhyland Klein ARRAY_SIZE(tegra210_audio_plls)); 32056b301a05SRhyland Klein tegra_pmc_clk_init(pmc_base, tegra210_clks); 32066b301a05SRhyland Klein 32076b301a05SRhyland Klein /* For Tegra210, PLLD is the only source for DSIA & DSIB */ 32086b301a05SRhyland Klein value = clk_readl(clk_base + PLLD_BASE); 32096b301a05SRhyland Klein value &= ~BIT(25); 32106b301a05SRhyland Klein clk_writel(value, clk_base + PLLD_BASE); 32116b301a05SRhyland Klein 32126b301a05SRhyland Klein tegra_clk_apply_init_table = tegra210_clock_apply_init_table; 32136b301a05SRhyland Klein 32146b301a05SRhyland Klein tegra_super_clk_gen5_init(clk_base, pmc_base, tegra210_clks, 32156b301a05SRhyland Klein &pll_x_params); 321668d724ceSPeter De Schrijver tegra_init_special_resets(2, tegra210_reset_assert, 321768d724ceSPeter De Schrijver tegra210_reset_deassert); 321868d724ceSPeter De Schrijver 32196b301a05SRhyland Klein tegra_add_of_provider(np); 32206b301a05SRhyland Klein tegra_register_devclks(devclks, ARRAY_SIZE(devclks)); 32216b301a05SRhyland Klein 32226b301a05SRhyland Klein tegra_cpu_car_ops = &tegra210_cpu_car_ops; 32236b301a05SRhyland Klein } 32246b301a05SRhyland Klein CLK_OF_DECLARE(tegra210, "nvidia,tegra210-car", tegra210_clock_init); 3225