1*d0f11d14SIcenowy Zheng /* 2*d0f11d14SIcenowy Zheng * Copyright (c) 2016 Icenowy Zheng <icenowy@aosc.xyz> 3*d0f11d14SIcenowy Zheng * 4*d0f11d14SIcenowy Zheng * Based on ccu-sun8i-h3.h, which is: 5*d0f11d14SIcenowy Zheng * Copyright (c) 2016 Maxime Ripard <maxime.ripard@free-electrons.com> 6*d0f11d14SIcenowy Zheng * 7*d0f11d14SIcenowy Zheng * This program is free software; you can redistribute it and/or modify 8*d0f11d14SIcenowy Zheng * it under the terms of the GNU General Public License as published by 9*d0f11d14SIcenowy Zheng * the Free Software Foundation; either version 2 of the License, or 10*d0f11d14SIcenowy Zheng * (at your option) any later version. 11*d0f11d14SIcenowy Zheng * 12*d0f11d14SIcenowy Zheng * This program is distributed in the hope that it will be useful, 13*d0f11d14SIcenowy Zheng * but WITHOUT ANY WARRANTY; without even the implied warranty of 14*d0f11d14SIcenowy Zheng * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15*d0f11d14SIcenowy Zheng * GNU General Public License for more details. 16*d0f11d14SIcenowy Zheng */ 17*d0f11d14SIcenowy Zheng 18*d0f11d14SIcenowy Zheng #ifndef _CCU_SUN8I_H3_H_ 19*d0f11d14SIcenowy Zheng #define _CCU_SUN8I_H3_H_ 20*d0f11d14SIcenowy Zheng 21*d0f11d14SIcenowy Zheng #include <dt-bindings/clock/sun8i-v3s-ccu.h> 22*d0f11d14SIcenowy Zheng #include <dt-bindings/reset/sun8i-v3s-ccu.h> 23*d0f11d14SIcenowy Zheng 24*d0f11d14SIcenowy Zheng #define CLK_PLL_CPU 0 25*d0f11d14SIcenowy Zheng #define CLK_PLL_AUDIO_BASE 1 26*d0f11d14SIcenowy Zheng #define CLK_PLL_AUDIO 2 27*d0f11d14SIcenowy Zheng #define CLK_PLL_AUDIO_2X 3 28*d0f11d14SIcenowy Zheng #define CLK_PLL_AUDIO_4X 4 29*d0f11d14SIcenowy Zheng #define CLK_PLL_AUDIO_8X 5 30*d0f11d14SIcenowy Zheng #define CLK_PLL_VIDEO 6 31*d0f11d14SIcenowy Zheng #define CLK_PLL_VE 7 32*d0f11d14SIcenowy Zheng #define CLK_PLL_DDR 8 33*d0f11d14SIcenowy Zheng #define CLK_PLL_PERIPH0 9 34*d0f11d14SIcenowy Zheng #define CLK_PLL_PERIPH0_2X 10 35*d0f11d14SIcenowy Zheng #define CLK_PLL_ISP 11 36*d0f11d14SIcenowy Zheng #define CLK_PLL_PERIPH1 12 37*d0f11d14SIcenowy Zheng /* Reserve one number for not implemented and not used PLL_DDR1 */ 38*d0f11d14SIcenowy Zheng 39*d0f11d14SIcenowy Zheng /* The CPU clock is exported */ 40*d0f11d14SIcenowy Zheng 41*d0f11d14SIcenowy Zheng #define CLK_AXI 15 42*d0f11d14SIcenowy Zheng #define CLK_AHB1 16 43*d0f11d14SIcenowy Zheng #define CLK_APB1 17 44*d0f11d14SIcenowy Zheng #define CLK_APB2 18 45*d0f11d14SIcenowy Zheng #define CLK_AHB2 19 46*d0f11d14SIcenowy Zheng 47*d0f11d14SIcenowy Zheng /* All the bus gates are exported */ 48*d0f11d14SIcenowy Zheng 49*d0f11d14SIcenowy Zheng /* The first bunch of module clocks are exported */ 50*d0f11d14SIcenowy Zheng 51*d0f11d14SIcenowy Zheng #define CLK_DRAM 58 52*d0f11d14SIcenowy Zheng 53*d0f11d14SIcenowy Zheng /* All the DRAM gates are exported */ 54*d0f11d14SIcenowy Zheng 55*d0f11d14SIcenowy Zheng /* Some more module clocks are exported */ 56*d0f11d14SIcenowy Zheng 57*d0f11d14SIcenowy Zheng #define CLK_MBUS 72 58*d0f11d14SIcenowy Zheng 59*d0f11d14SIcenowy Zheng /* And the GPU module clock is exported */ 60*d0f11d14SIcenowy Zheng 61*d0f11d14SIcenowy Zheng #define CLK_NUMBER (CLK_MIPI_CSI + 1) 62*d0f11d14SIcenowy Zheng 63*d0f11d14SIcenowy Zheng #endif /* _CCU_SUN8I_H3_H_ */ 64