19c92ab61SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 2763c5bd0SIcenowy Zheng /* 3763c5bd0SIcenowy Zheng * Copyright (c) 2017 Icenowy Zheng <icenowy@aosc.io> 4763c5bd0SIcenowy Zheng */ 5763c5bd0SIcenowy Zheng 6763c5bd0SIcenowy Zheng #include <linux/clk.h> 7763c5bd0SIcenowy Zheng #include <linux/clk-provider.h> 8763c5bd0SIcenowy Zheng #include <linux/of_address.h> 9763c5bd0SIcenowy Zheng #include <linux/of_platform.h> 10763c5bd0SIcenowy Zheng #include <linux/platform_device.h> 11763c5bd0SIcenowy Zheng #include <linux/reset.h> 12763c5bd0SIcenowy Zheng 13763c5bd0SIcenowy Zheng #include "ccu_common.h" 14763c5bd0SIcenowy Zheng #include "ccu_div.h" 15763c5bd0SIcenowy Zheng #include "ccu_gate.h" 16763c5bd0SIcenowy Zheng #include "ccu_reset.h" 17763c5bd0SIcenowy Zheng 18763c5bd0SIcenowy Zheng #include "ccu-sun8i-de2.h" 19763c5bd0SIcenowy Zheng 20763c5bd0SIcenowy Zheng static SUNXI_CCU_GATE(bus_mixer0_clk, "bus-mixer0", "bus-de", 21763c5bd0SIcenowy Zheng 0x04, BIT(0), 0); 22763c5bd0SIcenowy Zheng static SUNXI_CCU_GATE(bus_mixer1_clk, "bus-mixer1", "bus-de", 23763c5bd0SIcenowy Zheng 0x04, BIT(1), 0); 24763c5bd0SIcenowy Zheng static SUNXI_CCU_GATE(bus_wb_clk, "bus-wb", "bus-de", 25763c5bd0SIcenowy Zheng 0x04, BIT(2), 0); 2656808da9SJernej Skrabec static SUNXI_CCU_GATE(bus_rot_clk, "bus-rot", "bus-de", 2756808da9SJernej Skrabec 0x04, BIT(3), 0); 28763c5bd0SIcenowy Zheng 29763c5bd0SIcenowy Zheng static SUNXI_CCU_GATE(mixer0_clk, "mixer0", "mixer0-div", 30763c5bd0SIcenowy Zheng 0x00, BIT(0), CLK_SET_RATE_PARENT); 31763c5bd0SIcenowy Zheng static SUNXI_CCU_GATE(mixer1_clk, "mixer1", "mixer1-div", 32763c5bd0SIcenowy Zheng 0x00, BIT(1), CLK_SET_RATE_PARENT); 33763c5bd0SIcenowy Zheng static SUNXI_CCU_GATE(wb_clk, "wb", "wb-div", 34763c5bd0SIcenowy Zheng 0x00, BIT(2), CLK_SET_RATE_PARENT); 3556808da9SJernej Skrabec static SUNXI_CCU_GATE(rot_clk, "rot", "rot-div", 3656808da9SJernej Skrabec 0x00, BIT(3), CLK_SET_RATE_PARENT); 37763c5bd0SIcenowy Zheng 38763c5bd0SIcenowy Zheng static SUNXI_CCU_M(mixer0_div_clk, "mixer0-div", "de", 0x0c, 0, 4, 39763c5bd0SIcenowy Zheng CLK_SET_RATE_PARENT); 4019368d99SIcenowy Zheng static SUNXI_CCU_M(mixer1_div_clk, "mixer1-div", "de", 0x0c, 4, 4, 4119368d99SIcenowy Zheng CLK_SET_RATE_PARENT); 42763c5bd0SIcenowy Zheng static SUNXI_CCU_M(wb_div_clk, "wb-div", "de", 0x0c, 8, 4, 43763c5bd0SIcenowy Zheng CLK_SET_RATE_PARENT); 4456808da9SJernej Skrabec static SUNXI_CCU_M(rot_div_clk, "rot-div", "de", 0x0c, 0x0c, 4, 4556808da9SJernej Skrabec CLK_SET_RATE_PARENT); 46763c5bd0SIcenowy Zheng 47553c7d5bSMaxime Ripard static SUNXI_CCU_M(mixer0_div_a83_clk, "mixer0-div", "pll-de", 0x0c, 0, 4, 48553c7d5bSMaxime Ripard CLK_SET_RATE_PARENT); 49553c7d5bSMaxime Ripard static SUNXI_CCU_M(mixer1_div_a83_clk, "mixer1-div", "pll-de", 0x0c, 4, 4, 50553c7d5bSMaxime Ripard CLK_SET_RATE_PARENT); 51553c7d5bSMaxime Ripard static SUNXI_CCU_M(wb_div_a83_clk, "wb-div", "pll-de", 0x0c, 8, 4, 52553c7d5bSMaxime Ripard CLK_SET_RATE_PARENT); 53553c7d5bSMaxime Ripard 54763c5bd0SIcenowy Zheng static struct ccu_common *sun8i_a83t_de2_clks[] = { 55763c5bd0SIcenowy Zheng &mixer0_clk.common, 56763c5bd0SIcenowy Zheng &mixer1_clk.common, 57763c5bd0SIcenowy Zheng &wb_clk.common, 58763c5bd0SIcenowy Zheng 59763c5bd0SIcenowy Zheng &bus_mixer0_clk.common, 60763c5bd0SIcenowy Zheng &bus_mixer1_clk.common, 61763c5bd0SIcenowy Zheng &bus_wb_clk.common, 62763c5bd0SIcenowy Zheng 63553c7d5bSMaxime Ripard &mixer0_div_a83_clk.common, 64553c7d5bSMaxime Ripard &mixer1_div_a83_clk.common, 65553c7d5bSMaxime Ripard &wb_div_a83_clk.common, 66763c5bd0SIcenowy Zheng }; 67763c5bd0SIcenowy Zheng 6819368d99SIcenowy Zheng static struct ccu_common *sun8i_h3_de2_clks[] = { 6919368d99SIcenowy Zheng &mixer0_clk.common, 7019368d99SIcenowy Zheng &mixer1_clk.common, 7119368d99SIcenowy Zheng &wb_clk.common, 7219368d99SIcenowy Zheng 7319368d99SIcenowy Zheng &bus_mixer0_clk.common, 7419368d99SIcenowy Zheng &bus_mixer1_clk.common, 7519368d99SIcenowy Zheng &bus_wb_clk.common, 7619368d99SIcenowy Zheng 7719368d99SIcenowy Zheng &mixer0_div_clk.common, 7819368d99SIcenowy Zheng &mixer1_div_clk.common, 7919368d99SIcenowy Zheng &wb_div_clk.common, 8019368d99SIcenowy Zheng }; 8119368d99SIcenowy Zheng 82763c5bd0SIcenowy Zheng static struct ccu_common *sun8i_v3s_de2_clks[] = { 83763c5bd0SIcenowy Zheng &mixer0_clk.common, 84763c5bd0SIcenowy Zheng &wb_clk.common, 85763c5bd0SIcenowy Zheng 86763c5bd0SIcenowy Zheng &bus_mixer0_clk.common, 87763c5bd0SIcenowy Zheng &bus_wb_clk.common, 88763c5bd0SIcenowy Zheng 89763c5bd0SIcenowy Zheng &mixer0_div_clk.common, 90763c5bd0SIcenowy Zheng &wb_div_clk.common, 91763c5bd0SIcenowy Zheng }; 92763c5bd0SIcenowy Zheng 93b4bbce66SJernej Skrabec static struct ccu_common *sun50i_a64_de2_clks[] = { 94b4bbce66SJernej Skrabec &mixer0_clk.common, 95b4bbce66SJernej Skrabec &mixer1_clk.common, 96b4bbce66SJernej Skrabec &wb_clk.common, 97b4bbce66SJernej Skrabec 98b4bbce66SJernej Skrabec &bus_mixer0_clk.common, 99b4bbce66SJernej Skrabec &bus_mixer1_clk.common, 100b4bbce66SJernej Skrabec &bus_wb_clk.common, 101b4bbce66SJernej Skrabec 102b4bbce66SJernej Skrabec &mixer0_div_clk.common, 103b4bbce66SJernej Skrabec &mixer1_div_clk.common, 104b4bbce66SJernej Skrabec &wb_div_clk.common, 105b4bbce66SJernej Skrabec 106b4bbce66SJernej Skrabec &bus_rot_clk.common, 107b4bbce66SJernej Skrabec &rot_clk.common, 108b4bbce66SJernej Skrabec &rot_div_clk.common, 109b4bbce66SJernej Skrabec }; 110b4bbce66SJernej Skrabec 111763c5bd0SIcenowy Zheng static struct clk_hw_onecell_data sun8i_a83t_de2_hw_clks = { 112763c5bd0SIcenowy Zheng .hws = { 113763c5bd0SIcenowy Zheng [CLK_MIXER0] = &mixer0_clk.common.hw, 114763c5bd0SIcenowy Zheng [CLK_MIXER1] = &mixer1_clk.common.hw, 115763c5bd0SIcenowy Zheng [CLK_WB] = &wb_clk.common.hw, 116763c5bd0SIcenowy Zheng 117763c5bd0SIcenowy Zheng [CLK_BUS_MIXER0] = &bus_mixer0_clk.common.hw, 118763c5bd0SIcenowy Zheng [CLK_BUS_MIXER1] = &bus_mixer1_clk.common.hw, 119763c5bd0SIcenowy Zheng [CLK_BUS_WB] = &bus_wb_clk.common.hw, 120763c5bd0SIcenowy Zheng 121553c7d5bSMaxime Ripard [CLK_MIXER0_DIV] = &mixer0_div_a83_clk.common.hw, 122553c7d5bSMaxime Ripard [CLK_MIXER1_DIV] = &mixer1_div_a83_clk.common.hw, 123553c7d5bSMaxime Ripard [CLK_WB_DIV] = &wb_div_a83_clk.common.hw, 124763c5bd0SIcenowy Zheng }, 12556808da9SJernej Skrabec .num = CLK_NUMBER_WITHOUT_ROT, 126763c5bd0SIcenowy Zheng }; 127763c5bd0SIcenowy Zheng 12819368d99SIcenowy Zheng static struct clk_hw_onecell_data sun8i_h3_de2_hw_clks = { 12919368d99SIcenowy Zheng .hws = { 13019368d99SIcenowy Zheng [CLK_MIXER0] = &mixer0_clk.common.hw, 13119368d99SIcenowy Zheng [CLK_MIXER1] = &mixer1_clk.common.hw, 13219368d99SIcenowy Zheng [CLK_WB] = &wb_clk.common.hw, 13319368d99SIcenowy Zheng 13419368d99SIcenowy Zheng [CLK_BUS_MIXER0] = &bus_mixer0_clk.common.hw, 13519368d99SIcenowy Zheng [CLK_BUS_MIXER1] = &bus_mixer1_clk.common.hw, 13619368d99SIcenowy Zheng [CLK_BUS_WB] = &bus_wb_clk.common.hw, 13719368d99SIcenowy Zheng 13819368d99SIcenowy Zheng [CLK_MIXER0_DIV] = &mixer0_div_clk.common.hw, 13919368d99SIcenowy Zheng [CLK_MIXER1_DIV] = &mixer1_div_clk.common.hw, 14019368d99SIcenowy Zheng [CLK_WB_DIV] = &wb_div_clk.common.hw, 14119368d99SIcenowy Zheng }, 14256808da9SJernej Skrabec .num = CLK_NUMBER_WITHOUT_ROT, 14319368d99SIcenowy Zheng }; 14419368d99SIcenowy Zheng 145763c5bd0SIcenowy Zheng static struct clk_hw_onecell_data sun8i_v3s_de2_hw_clks = { 146763c5bd0SIcenowy Zheng .hws = { 147763c5bd0SIcenowy Zheng [CLK_MIXER0] = &mixer0_clk.common.hw, 148763c5bd0SIcenowy Zheng [CLK_WB] = &wb_clk.common.hw, 149763c5bd0SIcenowy Zheng 150763c5bd0SIcenowy Zheng [CLK_BUS_MIXER0] = &bus_mixer0_clk.common.hw, 151763c5bd0SIcenowy Zheng [CLK_BUS_WB] = &bus_wb_clk.common.hw, 152763c5bd0SIcenowy Zheng 153763c5bd0SIcenowy Zheng [CLK_MIXER0_DIV] = &mixer0_div_clk.common.hw, 154763c5bd0SIcenowy Zheng [CLK_WB_DIV] = &wb_div_clk.common.hw, 155763c5bd0SIcenowy Zheng }, 15656808da9SJernej Skrabec .num = CLK_NUMBER_WITHOUT_ROT, 15756808da9SJernej Skrabec }; 15856808da9SJernej Skrabec 159b4bbce66SJernej Skrabec static struct clk_hw_onecell_data sun50i_a64_de2_hw_clks = { 160b4bbce66SJernej Skrabec .hws = { 161b4bbce66SJernej Skrabec [CLK_MIXER0] = &mixer0_clk.common.hw, 162b4bbce66SJernej Skrabec [CLK_MIXER1] = &mixer1_clk.common.hw, 163b4bbce66SJernej Skrabec [CLK_WB] = &wb_clk.common.hw, 164b4bbce66SJernej Skrabec [CLK_ROT] = &rot_clk.common.hw, 165b4bbce66SJernej Skrabec 166b4bbce66SJernej Skrabec [CLK_BUS_MIXER0] = &bus_mixer0_clk.common.hw, 167b4bbce66SJernej Skrabec [CLK_BUS_MIXER1] = &bus_mixer1_clk.common.hw, 168b4bbce66SJernej Skrabec [CLK_BUS_WB] = &bus_wb_clk.common.hw, 169b4bbce66SJernej Skrabec [CLK_BUS_ROT] = &bus_rot_clk.common.hw, 170b4bbce66SJernej Skrabec 171b4bbce66SJernej Skrabec [CLK_MIXER0_DIV] = &mixer0_div_clk.common.hw, 172b4bbce66SJernej Skrabec [CLK_MIXER1_DIV] = &mixer1_div_clk.common.hw, 173b4bbce66SJernej Skrabec [CLK_WB_DIV] = &wb_div_clk.common.hw, 174b4bbce66SJernej Skrabec [CLK_ROT_DIV] = &rot_div_clk.common.hw, 175b4bbce66SJernej Skrabec }, 176b4bbce66SJernej Skrabec .num = CLK_NUMBER_WITH_ROT, 177b4bbce66SJernej Skrabec }; 178b4bbce66SJernej Skrabec 179763c5bd0SIcenowy Zheng static struct ccu_reset_map sun8i_a83t_de2_resets[] = { 180763c5bd0SIcenowy Zheng [RST_MIXER0] = { 0x08, BIT(0) }, 181763c5bd0SIcenowy Zheng /* 182763c5bd0SIcenowy Zheng * For A83T, H3 and R40, mixer1 reset line is shared with wb, so 183763c5bd0SIcenowy Zheng * only RST_WB is exported here. 184763c5bd0SIcenowy Zheng * For V3s there's just no mixer1, so it also shares this struct. 185763c5bd0SIcenowy Zheng */ 186763c5bd0SIcenowy Zheng [RST_WB] = { 0x08, BIT(2) }, 187763c5bd0SIcenowy Zheng }; 188763c5bd0SIcenowy Zheng 189763c5bd0SIcenowy Zheng static struct ccu_reset_map sun50i_a64_de2_resets[] = { 190763c5bd0SIcenowy Zheng [RST_MIXER0] = { 0x08, BIT(0) }, 191763c5bd0SIcenowy Zheng [RST_MIXER1] = { 0x08, BIT(1) }, 192763c5bd0SIcenowy Zheng [RST_WB] = { 0x08, BIT(2) }, 193b4bbce66SJernej Skrabec [RST_ROT] = { 0x08, BIT(3) }, 194763c5bd0SIcenowy Zheng }; 195763c5bd0SIcenowy Zheng 1962b48dcb7SJernej Skrabec static struct ccu_reset_map sun50i_h5_de2_resets[] = { 1972b48dcb7SJernej Skrabec [RST_MIXER0] = { 0x08, BIT(0) }, 1982b48dcb7SJernej Skrabec [RST_MIXER1] = { 0x08, BIT(1) }, 1992b48dcb7SJernej Skrabec [RST_WB] = { 0x08, BIT(2) }, 2002b48dcb7SJernej Skrabec }; 2012b48dcb7SJernej Skrabec 202763c5bd0SIcenowy Zheng static const struct sunxi_ccu_desc sun8i_a83t_de2_clk_desc = { 203763c5bd0SIcenowy Zheng .ccu_clks = sun8i_a83t_de2_clks, 204763c5bd0SIcenowy Zheng .num_ccu_clks = ARRAY_SIZE(sun8i_a83t_de2_clks), 205763c5bd0SIcenowy Zheng 206763c5bd0SIcenowy Zheng .hw_clks = &sun8i_a83t_de2_hw_clks, 207763c5bd0SIcenowy Zheng 208763c5bd0SIcenowy Zheng .resets = sun8i_a83t_de2_resets, 209763c5bd0SIcenowy Zheng .num_resets = ARRAY_SIZE(sun8i_a83t_de2_resets), 210763c5bd0SIcenowy Zheng }; 211763c5bd0SIcenowy Zheng 21219368d99SIcenowy Zheng static const struct sunxi_ccu_desc sun8i_h3_de2_clk_desc = { 21319368d99SIcenowy Zheng .ccu_clks = sun8i_h3_de2_clks, 21419368d99SIcenowy Zheng .num_ccu_clks = ARRAY_SIZE(sun8i_h3_de2_clks), 21519368d99SIcenowy Zheng 21619368d99SIcenowy Zheng .hw_clks = &sun8i_h3_de2_hw_clks, 21719368d99SIcenowy Zheng 21819368d99SIcenowy Zheng .resets = sun8i_a83t_de2_resets, 21919368d99SIcenowy Zheng .num_resets = ARRAY_SIZE(sun8i_a83t_de2_resets), 22019368d99SIcenowy Zheng }; 22119368d99SIcenowy Zheng 222763c5bd0SIcenowy Zheng static const struct sunxi_ccu_desc sun50i_a64_de2_clk_desc = { 223b4bbce66SJernej Skrabec .ccu_clks = sun50i_a64_de2_clks, 224b4bbce66SJernej Skrabec .num_ccu_clks = ARRAY_SIZE(sun50i_a64_de2_clks), 225763c5bd0SIcenowy Zheng 226b4bbce66SJernej Skrabec .hw_clks = &sun50i_a64_de2_hw_clks, 227763c5bd0SIcenowy Zheng 228763c5bd0SIcenowy Zheng .resets = sun50i_a64_de2_resets, 229763c5bd0SIcenowy Zheng .num_resets = ARRAY_SIZE(sun50i_a64_de2_resets), 230763c5bd0SIcenowy Zheng }; 231763c5bd0SIcenowy Zheng 2322b48dcb7SJernej Skrabec static const struct sunxi_ccu_desc sun50i_h5_de2_clk_desc = { 2332b48dcb7SJernej Skrabec .ccu_clks = sun8i_h3_de2_clks, 2342b48dcb7SJernej Skrabec .num_ccu_clks = ARRAY_SIZE(sun8i_h3_de2_clks), 2352b48dcb7SJernej Skrabec 2362b48dcb7SJernej Skrabec .hw_clks = &sun8i_h3_de2_hw_clks, 2372b48dcb7SJernej Skrabec 2382b48dcb7SJernej Skrabec .resets = sun50i_h5_de2_resets, 2392b48dcb7SJernej Skrabec .num_resets = ARRAY_SIZE(sun50i_h5_de2_resets), 2402b48dcb7SJernej Skrabec }; 2412b48dcb7SJernej Skrabec 242763c5bd0SIcenowy Zheng static const struct sunxi_ccu_desc sun8i_v3s_de2_clk_desc = { 243763c5bd0SIcenowy Zheng .ccu_clks = sun8i_v3s_de2_clks, 244763c5bd0SIcenowy Zheng .num_ccu_clks = ARRAY_SIZE(sun8i_v3s_de2_clks), 245763c5bd0SIcenowy Zheng 246763c5bd0SIcenowy Zheng .hw_clks = &sun8i_v3s_de2_hw_clks, 247763c5bd0SIcenowy Zheng 248763c5bd0SIcenowy Zheng .resets = sun8i_a83t_de2_resets, 249763c5bd0SIcenowy Zheng .num_resets = ARRAY_SIZE(sun8i_a83t_de2_resets), 250763c5bd0SIcenowy Zheng }; 251763c5bd0SIcenowy Zheng 252763c5bd0SIcenowy Zheng static int sunxi_de2_clk_probe(struct platform_device *pdev) 253763c5bd0SIcenowy Zheng { 254763c5bd0SIcenowy Zheng struct resource *res; 255763c5bd0SIcenowy Zheng struct clk *bus_clk, *mod_clk; 256763c5bd0SIcenowy Zheng struct reset_control *rstc; 257763c5bd0SIcenowy Zheng void __iomem *reg; 258763c5bd0SIcenowy Zheng const struct sunxi_ccu_desc *ccu_desc; 259763c5bd0SIcenowy Zheng int ret; 260763c5bd0SIcenowy Zheng 261763c5bd0SIcenowy Zheng ccu_desc = of_device_get_match_data(&pdev->dev); 262763c5bd0SIcenowy Zheng if (!ccu_desc) 263763c5bd0SIcenowy Zheng return -EINVAL; 264763c5bd0SIcenowy Zheng 265763c5bd0SIcenowy Zheng res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 266763c5bd0SIcenowy Zheng reg = devm_ioremap_resource(&pdev->dev, res); 267763c5bd0SIcenowy Zheng if (IS_ERR(reg)) 268763c5bd0SIcenowy Zheng return PTR_ERR(reg); 269763c5bd0SIcenowy Zheng 270763c5bd0SIcenowy Zheng bus_clk = devm_clk_get(&pdev->dev, "bus"); 271763c5bd0SIcenowy Zheng if (IS_ERR(bus_clk)) { 272763c5bd0SIcenowy Zheng ret = PTR_ERR(bus_clk); 273763c5bd0SIcenowy Zheng if (ret != -EPROBE_DEFER) 274763c5bd0SIcenowy Zheng dev_err(&pdev->dev, "Couldn't get bus clk: %d\n", ret); 275763c5bd0SIcenowy Zheng return ret; 276763c5bd0SIcenowy Zheng } 277763c5bd0SIcenowy Zheng 278763c5bd0SIcenowy Zheng mod_clk = devm_clk_get(&pdev->dev, "mod"); 279763c5bd0SIcenowy Zheng if (IS_ERR(mod_clk)) { 280763c5bd0SIcenowy Zheng ret = PTR_ERR(mod_clk); 281763c5bd0SIcenowy Zheng if (ret != -EPROBE_DEFER) 282763c5bd0SIcenowy Zheng dev_err(&pdev->dev, "Couldn't get mod clk: %d\n", ret); 283763c5bd0SIcenowy Zheng return ret; 284763c5bd0SIcenowy Zheng } 285763c5bd0SIcenowy Zheng 286763c5bd0SIcenowy Zheng rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL); 287763c5bd0SIcenowy Zheng if (IS_ERR(rstc)) { 2881f6d640cSWei Yongjun ret = PTR_ERR(rstc); 289763c5bd0SIcenowy Zheng if (ret != -EPROBE_DEFER) 290763c5bd0SIcenowy Zheng dev_err(&pdev->dev, 291763c5bd0SIcenowy Zheng "Couldn't get reset control: %d\n", ret); 292763c5bd0SIcenowy Zheng return ret; 293763c5bd0SIcenowy Zheng } 294763c5bd0SIcenowy Zheng 295763c5bd0SIcenowy Zheng /* The clocks need to be enabled for us to access the registers */ 296763c5bd0SIcenowy Zheng ret = clk_prepare_enable(bus_clk); 297763c5bd0SIcenowy Zheng if (ret) { 298763c5bd0SIcenowy Zheng dev_err(&pdev->dev, "Couldn't enable bus clk: %d\n", ret); 299763c5bd0SIcenowy Zheng return ret; 300763c5bd0SIcenowy Zheng } 301763c5bd0SIcenowy Zheng 302763c5bd0SIcenowy Zheng ret = clk_prepare_enable(mod_clk); 303763c5bd0SIcenowy Zheng if (ret) { 304763c5bd0SIcenowy Zheng dev_err(&pdev->dev, "Couldn't enable mod clk: %d\n", ret); 305763c5bd0SIcenowy Zheng goto err_disable_bus_clk; 306763c5bd0SIcenowy Zheng } 307763c5bd0SIcenowy Zheng 308763c5bd0SIcenowy Zheng /* The reset control needs to be asserted for the controls to work */ 309763c5bd0SIcenowy Zheng ret = reset_control_deassert(rstc); 310763c5bd0SIcenowy Zheng if (ret) { 311763c5bd0SIcenowy Zheng dev_err(&pdev->dev, 312763c5bd0SIcenowy Zheng "Couldn't deassert reset control: %d\n", ret); 313763c5bd0SIcenowy Zheng goto err_disable_mod_clk; 314763c5bd0SIcenowy Zheng } 315763c5bd0SIcenowy Zheng 316763c5bd0SIcenowy Zheng ret = sunxi_ccu_probe(pdev->dev.of_node, reg, ccu_desc); 317763c5bd0SIcenowy Zheng if (ret) 318763c5bd0SIcenowy Zheng goto err_assert_reset; 319763c5bd0SIcenowy Zheng 320763c5bd0SIcenowy Zheng return 0; 321763c5bd0SIcenowy Zheng 322763c5bd0SIcenowy Zheng err_assert_reset: 323763c5bd0SIcenowy Zheng reset_control_assert(rstc); 324763c5bd0SIcenowy Zheng err_disable_mod_clk: 325763c5bd0SIcenowy Zheng clk_disable_unprepare(mod_clk); 326763c5bd0SIcenowy Zheng err_disable_bus_clk: 327763c5bd0SIcenowy Zheng clk_disable_unprepare(bus_clk); 328763c5bd0SIcenowy Zheng return ret; 329763c5bd0SIcenowy Zheng } 330763c5bd0SIcenowy Zheng 331763c5bd0SIcenowy Zheng static const struct of_device_id sunxi_de2_clk_ids[] = { 332763c5bd0SIcenowy Zheng { 333763c5bd0SIcenowy Zheng .compatible = "allwinner,sun8i-a83t-de2-clk", 334763c5bd0SIcenowy Zheng .data = &sun8i_a83t_de2_clk_desc, 335763c5bd0SIcenowy Zheng }, 336763c5bd0SIcenowy Zheng { 33719368d99SIcenowy Zheng .compatible = "allwinner,sun8i-h3-de2-clk", 33819368d99SIcenowy Zheng .data = &sun8i_h3_de2_clk_desc, 33919368d99SIcenowy Zheng }, 34019368d99SIcenowy Zheng { 341763c5bd0SIcenowy Zheng .compatible = "allwinner,sun8i-v3s-de2-clk", 342763c5bd0SIcenowy Zheng .data = &sun8i_v3s_de2_clk_desc, 343763c5bd0SIcenowy Zheng }, 344763c5bd0SIcenowy Zheng { 34501951563SIcenowy Zheng .compatible = "allwinner,sun50i-a64-de2-clk", 34601951563SIcenowy Zheng .data = &sun50i_a64_de2_clk_desc, 34701951563SIcenowy Zheng }, 34801951563SIcenowy Zheng { 349763c5bd0SIcenowy Zheng .compatible = "allwinner,sun50i-h5-de2-clk", 3502b48dcb7SJernej Skrabec .data = &sun50i_h5_de2_clk_desc, 351763c5bd0SIcenowy Zheng }, 35256808da9SJernej Skrabec { 35356808da9SJernej Skrabec .compatible = "allwinner,sun50i-h6-de3-clk", 354*75250eb7SJernej Skrabec .data = &sun50i_h5_de2_clk_desc, 35556808da9SJernej Skrabec }, 356763c5bd0SIcenowy Zheng { } 357763c5bd0SIcenowy Zheng }; 358763c5bd0SIcenowy Zheng 359763c5bd0SIcenowy Zheng static struct platform_driver sunxi_de2_clk_driver = { 360763c5bd0SIcenowy Zheng .probe = sunxi_de2_clk_probe, 361763c5bd0SIcenowy Zheng .driver = { 362763c5bd0SIcenowy Zheng .name = "sunxi-de2-clks", 363763c5bd0SIcenowy Zheng .of_match_table = sunxi_de2_clk_ids, 364763c5bd0SIcenowy Zheng }, 365763c5bd0SIcenowy Zheng }; 366763c5bd0SIcenowy Zheng builtin_platform_driver(sunxi_de2_clk_driver); 367