1*c942fddfSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */ 2c6a06374SMaxime Ripard /* 3c6a06374SMaxime Ripard * Copyright 2016 Maxime Ripard 4c6a06374SMaxime Ripard * 5c6a06374SMaxime Ripard * Maxime Ripard <maxime.ripard@free-electrons.com> 6c6a06374SMaxime Ripard */ 7c6a06374SMaxime Ripard 8c6a06374SMaxime Ripard #ifndef _CCU_SUN50I_A64_H_ 9c6a06374SMaxime Ripard #define _CCU_SUN50I_A64_H_ 10c6a06374SMaxime Ripard 11c6a06374SMaxime Ripard #include <dt-bindings/clock/sun50i-a64-ccu.h> 12c6a06374SMaxime Ripard #include <dt-bindings/reset/sun50i-a64-ccu.h> 13c6a06374SMaxime Ripard 14c6a06374SMaxime Ripard #define CLK_OSC_12M 0 15c6a06374SMaxime Ripard #define CLK_PLL_CPUX 1 16c6a06374SMaxime Ripard #define CLK_PLL_AUDIO_BASE 2 17c6a06374SMaxime Ripard #define CLK_PLL_AUDIO 3 18c6a06374SMaxime Ripard #define CLK_PLL_AUDIO_2X 4 19c6a06374SMaxime Ripard #define CLK_PLL_AUDIO_4X 5 20c6a06374SMaxime Ripard #define CLK_PLL_AUDIO_8X 6 218b2a3787SJagan Teki 228b2a3787SJagan Teki /* PLL_VIDEO0 exported for HDMI PHY */ 238b2a3787SJagan Teki 24c6a06374SMaxime Ripard #define CLK_PLL_VIDEO0_2X 8 25c6a06374SMaxime Ripard #define CLK_PLL_VE 9 26c6a06374SMaxime Ripard #define CLK_PLL_DDR0 10 27d85da227SChen-Yu Tsai 28d85da227SChen-Yu Tsai /* PLL_PERIPH0 exported for PRCM */ 29d85da227SChen-Yu Tsai 30c6a06374SMaxime Ripard #define CLK_PLL_PERIPH0_2X 12 31c6a06374SMaxime Ripard #define CLK_PLL_PERIPH1 13 32c6a06374SMaxime Ripard #define CLK_PLL_PERIPH1_2X 14 33c6a06374SMaxime Ripard #define CLK_PLL_VIDEO1 15 34c6a06374SMaxime Ripard #define CLK_PLL_GPU 16 35c6a06374SMaxime Ripard #define CLK_PLL_MIPI 17 36c6a06374SMaxime Ripard #define CLK_PLL_HSIC 18 37c6a06374SMaxime Ripard #define CLK_PLL_DE 19 38c6a06374SMaxime Ripard #define CLK_PLL_DDR1 20 39c6a06374SMaxime Ripard #define CLK_AXI 22 40c6a06374SMaxime Ripard #define CLK_APB 23 41c6a06374SMaxime Ripard #define CLK_AHB1 24 42c6a06374SMaxime Ripard #define CLK_APB1 25 43c6a06374SMaxime Ripard #define CLK_APB2 26 44c6a06374SMaxime Ripard #define CLK_AHB2 27 45c6a06374SMaxime Ripard 46c6a06374SMaxime Ripard /* All the bus gates are exported */ 47c6a06374SMaxime Ripard 48c6a06374SMaxime Ripard /* The first bunch of module clocks are exported */ 49c6a06374SMaxime Ripard 50c6a06374SMaxime Ripard #define CLK_USB_OHCI0_12M 90 51c6a06374SMaxime Ripard 52c6a06374SMaxime Ripard #define CLK_USB_OHCI1_12M 92 53c6a06374SMaxime Ripard 54c6a06374SMaxime Ripard /* All the DRAM gates are exported */ 55c6a06374SMaxime Ripard 56c6a06374SMaxime Ripard /* And the DSI and GPU module clock is exported */ 57c6a06374SMaxime Ripard 58c6a06374SMaxime Ripard #define CLK_NUMBER (CLK_GPU + 1) 59c6a06374SMaxime Ripard 60c6a06374SMaxime Ripard #endif /* _CCU_SUN50I_A64_H_ */ 61