xref: /openbmc/linux/drivers/clk/sprd/gate.h (revision 4b4193256c8d3bc3a5397b5cd9494c2ad386317d)
17a12f838SNishad Kamdar /* SPDX-License-Identifier: GPL-2.0 */
2cdb09f67SChunyan Zhang //
3cdb09f67SChunyan Zhang // Spreadtrum gate clock driver
4cdb09f67SChunyan Zhang //
5cdb09f67SChunyan Zhang // Copyright (C) 2017 Spreadtrum, Inc.
6cdb09f67SChunyan Zhang // Author: Chunyan Zhang <chunyan.zhang@spreadtrum.com>
7cdb09f67SChunyan Zhang 
8cdb09f67SChunyan Zhang #ifndef _SPRD_GATE_H_
9cdb09f67SChunyan Zhang #define _SPRD_GATE_H_
10cdb09f67SChunyan Zhang 
11cdb09f67SChunyan Zhang #include "common.h"
12cdb09f67SChunyan Zhang 
13cdb09f67SChunyan Zhang struct sprd_gate {
14cdb09f67SChunyan Zhang 	u32			enable_mask;
15cdb09f67SChunyan Zhang 	u16			flags;
16cdb09f67SChunyan Zhang 	u16			sc_offset;
17187e5cd2SXiaolong Zhang 	u16			udelay;
18cdb09f67SChunyan Zhang 
19cdb09f67SChunyan Zhang 	struct sprd_clk_common	common;
20cdb09f67SChunyan Zhang };
21cdb09f67SChunyan Zhang 
22*8b4f6b8dSChunyan Zhang /*
23*8b4f6b8dSChunyan Zhang  * sprd_gate->flags is used for:
24*8b4f6b8dSChunyan Zhang  * CLK_GATE_SET_TO_DISABLE	BIT(0)
25*8b4f6b8dSChunyan Zhang  * CLK_GATE_HIWORD_MASK		BIT(1)
26*8b4f6b8dSChunyan Zhang  * CLK_GATE_BIG_ENDIAN		BIT(2)
27*8b4f6b8dSChunyan Zhang  * so we define new flags from	BIT(3)
28*8b4f6b8dSChunyan Zhang  */
29*8b4f6b8dSChunyan Zhang #define SPRD_GATE_NON_AON BIT(3) /* not alway powered on, check before read */
30*8b4f6b8dSChunyan Zhang 
31ea8ca310SChunyan Zhang #define SPRD_SC_GATE_CLK_HW_INIT_FN(_struct, _name, _parent, _reg,	\
32187e5cd2SXiaolong Zhang 				    _sc_offset, _enable_mask, _flags,	\
33ea8ca310SChunyan Zhang 				    _gate_flags, _udelay, _ops, _fn)	\
34cdb09f67SChunyan Zhang 	struct sprd_gate _struct = {					\
35cdb09f67SChunyan Zhang 		.enable_mask	= _enable_mask,				\
36cdb09f67SChunyan Zhang 		.sc_offset	= _sc_offset,				\
37cdb09f67SChunyan Zhang 		.flags		= _gate_flags,				\
38187e5cd2SXiaolong Zhang 		.udelay		= _udelay,				\
39cdb09f67SChunyan Zhang 		.common	= {						\
40cdb09f67SChunyan Zhang 			.regmap		= NULL,				\
41cdb09f67SChunyan Zhang 			.reg		= _reg,				\
42ea8ca310SChunyan Zhang 			.hw.init	= _fn(_name, _parent,		\
43ea8ca310SChunyan Zhang 					      _ops, _flags),		\
44cdb09f67SChunyan Zhang 		}							\
45cdb09f67SChunyan Zhang 	}
46cdb09f67SChunyan Zhang 
47ea8ca310SChunyan Zhang #define SPRD_SC_GATE_CLK_OPS_UDELAY(_struct, _name, _parent, _reg,	\
48ea8ca310SChunyan Zhang 				    _sc_offset, _enable_mask, _flags,	\
49ea8ca310SChunyan Zhang 				    _gate_flags, _udelay, _ops)		\
50ea8ca310SChunyan Zhang 	SPRD_SC_GATE_CLK_HW_INIT_FN(_struct, _name, _parent, _reg,	\
51ea8ca310SChunyan Zhang 				    _sc_offset, _enable_mask, _flags,	\
52ea8ca310SChunyan Zhang 				    _gate_flags, _udelay, _ops, CLK_HW_INIT)
53ea8ca310SChunyan Zhang 
54187e5cd2SXiaolong Zhang #define SPRD_SC_GATE_CLK_OPS(_struct, _name, _parent, _reg, _sc_offset,	\
55187e5cd2SXiaolong Zhang 			     _enable_mask, _flags, _gate_flags, _ops)	\
56187e5cd2SXiaolong Zhang 	SPRD_SC_GATE_CLK_OPS_UDELAY(_struct, _name, _parent, _reg,	\
57187e5cd2SXiaolong Zhang 				    _sc_offset, _enable_mask, _flags,	\
58187e5cd2SXiaolong Zhang 				    _gate_flags, 0, _ops)
59187e5cd2SXiaolong Zhang 
60cdb09f67SChunyan Zhang #define SPRD_SC_GATE_CLK(_struct, _name, _parent, _reg, _sc_offset,	\
61cdb09f67SChunyan Zhang 			 _enable_mask, _flags, _gate_flags)		\
62cdb09f67SChunyan Zhang 	SPRD_SC_GATE_CLK_OPS(_struct, _name, _parent, _reg, _sc_offset,	\
63cdb09f67SChunyan Zhang 			     _enable_mask, _flags, _gate_flags,		\
64cdb09f67SChunyan Zhang 			     &sprd_sc_gate_ops)
65cdb09f67SChunyan Zhang 
66ea8ca310SChunyan Zhang #define SPRD_GATE_CLK(_struct, _name, _parent, _reg,			\
67ea8ca310SChunyan Zhang 		      _enable_mask, _flags, _gate_flags)		\
68ea8ca310SChunyan Zhang 	SPRD_SC_GATE_CLK_OPS(_struct, _name, _parent, _reg, 0,		\
69ea8ca310SChunyan Zhang 			     _enable_mask, _flags, _gate_flags,		\
70ea8ca310SChunyan Zhang 			     &sprd_gate_ops)
71ea8ca310SChunyan Zhang 
72187e5cd2SXiaolong Zhang #define SPRD_PLL_SC_GATE_CLK(_struct, _name, _parent, _reg, _sc_offset,	\
73ea8ca310SChunyan Zhang 			     _enable_mask, _flags, _gate_flags,		\
74ea8ca310SChunyan Zhang 			     _udelay)					\
75187e5cd2SXiaolong Zhang 	SPRD_SC_GATE_CLK_OPS_UDELAY(_struct, _name, _parent, _reg,	\
76187e5cd2SXiaolong Zhang 				    _sc_offset,	_enable_mask, _flags,	\
77187e5cd2SXiaolong Zhang 				    _gate_flags, _udelay,		\
78187e5cd2SXiaolong Zhang 				    &sprd_pll_sc_gate_ops)
79187e5cd2SXiaolong Zhang 
80ea8ca310SChunyan Zhang 
81ea8ca310SChunyan Zhang #define SPRD_SC_GATE_CLK_HW_OPS_UDELAY(_struct, _name, _parent, _reg,	\
82ea8ca310SChunyan Zhang 				       _sc_offset, _enable_mask,	\
83ea8ca310SChunyan Zhang 				       _flags, _gate_flags,		\
84ea8ca310SChunyan Zhang 				       _udelay, _ops)			\
85ea8ca310SChunyan Zhang 	SPRD_SC_GATE_CLK_HW_INIT_FN(_struct, _name, _parent, _reg,	\
86ea8ca310SChunyan Zhang 				    _sc_offset, _enable_mask, _flags,	\
87ea8ca310SChunyan Zhang 				    _gate_flags, _udelay, _ops,		\
88ea8ca310SChunyan Zhang 				    CLK_HW_INIT_HW)
89ea8ca310SChunyan Zhang 
90ea8ca310SChunyan Zhang #define SPRD_SC_GATE_CLK_HW_OPS(_struct, _name, _parent, _reg,		\
91ea8ca310SChunyan Zhang 				_sc_offset, _enable_mask, _flags,	\
92ea8ca310SChunyan Zhang 				_gate_flags, _ops)			\
93ea8ca310SChunyan Zhang 	SPRD_SC_GATE_CLK_HW_OPS_UDELAY(_struct, _name, _parent, _reg,	\
94ea8ca310SChunyan Zhang 				       _sc_offset, _enable_mask,	\
95ea8ca310SChunyan Zhang 				       _flags, _gate_flags, 0, _ops)
96ea8ca310SChunyan Zhang 
97ea8ca310SChunyan Zhang #define SPRD_SC_GATE_CLK_HW(_struct, _name, _parent, _reg,		\
98ea8ca310SChunyan Zhang 			    _sc_offset, _enable_mask, _flags,		\
99ea8ca310SChunyan Zhang 			    _gate_flags)				\
100ea8ca310SChunyan Zhang 	SPRD_SC_GATE_CLK_HW_OPS(_struct, _name, _parent, _reg,		\
101ea8ca310SChunyan Zhang 				_sc_offset, _enable_mask, _flags,	\
102ea8ca310SChunyan Zhang 				_gate_flags, &sprd_sc_gate_ops)
103ea8ca310SChunyan Zhang 
104ea8ca310SChunyan Zhang #define SPRD_GATE_CLK_HW(_struct, _name, _parent, _reg,			\
105ea8ca310SChunyan Zhang 			 _enable_mask, _flags, _gate_flags)		\
106ea8ca310SChunyan Zhang 	SPRD_SC_GATE_CLK_HW_OPS(_struct, _name, _parent, _reg, 0,	\
107ea8ca310SChunyan Zhang 				_enable_mask, _flags, _gate_flags,	\
108ea8ca310SChunyan Zhang 				&sprd_gate_ops)
109ea8ca310SChunyan Zhang 
110ea8ca310SChunyan Zhang #define SPRD_PLL_SC_GATE_CLK_HW(_struct, _name, _parent, _reg,		\
111ea8ca310SChunyan Zhang 				_sc_offset, _enable_mask, _flags,	\
112ea8ca310SChunyan Zhang 				_gate_flags, _udelay)			\
113ea8ca310SChunyan Zhang 	SPRD_SC_GATE_CLK_HW_OPS_UDELAY(_struct, _name, _parent, _reg,	\
114ea8ca310SChunyan Zhang 				       _sc_offset, _enable_mask,	\
115ea8ca310SChunyan Zhang 				       _flags, _gate_flags, _udelay,	\
116ea8ca310SChunyan Zhang 				       &sprd_pll_sc_gate_ops)
117ea8ca310SChunyan Zhang 
118ea8ca310SChunyan Zhang #define SPRD_SC_GATE_CLK_FW_NAME_OPS_UDELAY(_struct, _name, _parent,	\
119ea8ca310SChunyan Zhang 					    _reg, _sc_offset,		\
120ea8ca310SChunyan Zhang 					    _enable_mask, _flags,	\
121ea8ca310SChunyan Zhang 					    _gate_flags, _udelay, _ops)	\
122ea8ca310SChunyan Zhang 	SPRD_SC_GATE_CLK_HW_INIT_FN(_struct, _name, _parent, _reg,	\
123ea8ca310SChunyan Zhang 				    _sc_offset, _enable_mask, _flags,	\
124ea8ca310SChunyan Zhang 				    _gate_flags, _udelay, _ops,		\
125ea8ca310SChunyan Zhang 				    CLK_HW_INIT_FW_NAME)
126ea8ca310SChunyan Zhang 
127ea8ca310SChunyan Zhang #define SPRD_SC_GATE_CLK_FW_NAME_OPS(_struct, _name, _parent, _reg,	\
128ea8ca310SChunyan Zhang 				     _sc_offset, _enable_mask, _flags,	\
129ea8ca310SChunyan Zhang 				     _gate_flags, _ops)			\
130ea8ca310SChunyan Zhang 	SPRD_SC_GATE_CLK_FW_NAME_OPS_UDELAY(_struct, _name, _parent,	\
131ea8ca310SChunyan Zhang 					    _reg, _sc_offset,		\
132ea8ca310SChunyan Zhang 					    _enable_mask, _flags,	\
133ea8ca310SChunyan Zhang 					    _gate_flags, 0, _ops)
134ea8ca310SChunyan Zhang 
135ea8ca310SChunyan Zhang #define SPRD_SC_GATE_CLK_FW_NAME(_struct, _name, _parent, _reg,		\
136ea8ca310SChunyan Zhang 				 _sc_offset, _enable_mask, _flags,	\
137ea8ca310SChunyan Zhang 				 _gate_flags)				\
138ea8ca310SChunyan Zhang 	SPRD_SC_GATE_CLK_FW_NAME_OPS(_struct, _name, _parent, _reg,	\
139ea8ca310SChunyan Zhang 				     _sc_offset, _enable_mask, _flags,	\
140ea8ca310SChunyan Zhang 				     _gate_flags, &sprd_sc_gate_ops)
141ea8ca310SChunyan Zhang 
142ea8ca310SChunyan Zhang #define SPRD_GATE_CLK_FW_NAME(_struct, _name, _parent, _reg,		\
143ea8ca310SChunyan Zhang 			      _enable_mask, _flags, _gate_flags)	\
144ea8ca310SChunyan Zhang 	SPRD_SC_GATE_CLK_FW_NAME_OPS(_struct, _name, _parent, _reg, 0,	\
145ea8ca310SChunyan Zhang 				     _enable_mask, _flags, _gate_flags,	\
146ea8ca310SChunyan Zhang 				     &sprd_gate_ops)
147ea8ca310SChunyan Zhang 
148ea8ca310SChunyan Zhang #define SPRD_PLL_SC_GATE_CLK_FW_NAME(_struct, _name, _parent, _reg,	\
149ea8ca310SChunyan Zhang 				     _sc_offset, _enable_mask, _flags,	\
150ea8ca310SChunyan Zhang 				     _gate_flags, _udelay)		\
151ea8ca310SChunyan Zhang 	SPRD_SC_GATE_CLK_FW_NAME_OPS_UDELAY(_struct, _name, _parent,	\
152ea8ca310SChunyan Zhang 					    _reg, _sc_offset,		\
153ea8ca310SChunyan Zhang 					    _enable_mask, _flags,	\
154ea8ca310SChunyan Zhang 					    _gate_flags, _udelay,	\
155ea8ca310SChunyan Zhang 					    &sprd_pll_sc_gate_ops)
156ea8ca310SChunyan Zhang 
hw_to_sprd_gate(const struct clk_hw * hw)157cdb09f67SChunyan Zhang static inline struct sprd_gate *hw_to_sprd_gate(const struct clk_hw *hw)
158cdb09f67SChunyan Zhang {
159cdb09f67SChunyan Zhang 	struct sprd_clk_common *common = hw_to_sprd_clk_common(hw);
160cdb09f67SChunyan Zhang 
161cdb09f67SChunyan Zhang 	return container_of(common, struct sprd_gate, common);
162cdb09f67SChunyan Zhang }
163cdb09f67SChunyan Zhang 
164cdb09f67SChunyan Zhang extern const struct clk_ops sprd_gate_ops;
165cdb09f67SChunyan Zhang extern const struct clk_ops sprd_sc_gate_ops;
166187e5cd2SXiaolong Zhang extern const struct clk_ops sprd_pll_sc_gate_ops;
167cdb09f67SChunyan Zhang 
168cdb09f67SChunyan Zhang #endif /* _SPRD_GATE_H_ */
169