197fb5e8dSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only
2aec89f78SBastian Köcher /* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
3aec89f78SBastian Köcher */
4aec89f78SBastian Köcher
5d7a49c8dSVinod Koul #include <linux/clk-provider.h>
6aec89f78SBastian Köcher #include <linux/kernel.h>
7aec89f78SBastian Köcher #include <linux/init.h>
8aec89f78SBastian Köcher #include <linux/err.h>
9aec89f78SBastian Köcher #include <linux/ctype.h>
10aec89f78SBastian Köcher #include <linux/io.h>
11aec89f78SBastian Köcher #include <linux/of.h>
12aec89f78SBastian Köcher #include <linux/platform_device.h>
13aec89f78SBastian Köcher #include <linux/module.h>
14aec89f78SBastian Köcher #include <linux/regmap.h>
15aec89f78SBastian Köcher
16aec89f78SBastian Köcher #include <dt-bindings/clock/qcom,gcc-msm8994.h>
17aec89f78SBastian Köcher
18aec89f78SBastian Köcher #include "common.h"
19aec89f78SBastian Köcher #include "clk-regmap.h"
20aec89f78SBastian Köcher #include "clk-alpha-pll.h"
21aec89f78SBastian Köcher #include "clk-rcg.h"
22aec89f78SBastian Köcher #include "clk-branch.h"
23aec89f78SBastian Köcher #include "reset.h"
248c18b41bSKonrad Dybcio #include "gdsc.h"
25aec89f78SBastian Köcher
26aec89f78SBastian Köcher enum {
27aec89f78SBastian Köcher P_XO,
28aec89f78SBastian Köcher P_GPLL0,
29aec89f78SBastian Köcher P_GPLL4,
30aec89f78SBastian Köcher };
31aec89f78SBastian Köcher
32aec89f78SBastian Köcher static struct clk_alpha_pll gpll0_early = {
330519d1d0SKonrad Dybcio .offset = 0,
3428d3f06eSAbhishek Sahu .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
35aec89f78SBastian Köcher .clkr = {
36aec89f78SBastian Köcher .enable_reg = 0x1480,
37aec89f78SBastian Köcher .enable_mask = BIT(0),
380519d1d0SKonrad Dybcio .hw.init = &(struct clk_init_data){
39aec89f78SBastian Köcher .name = "gpll0_early",
400519d1d0SKonrad Dybcio .parent_data = &(const struct clk_parent_data){
410519d1d0SKonrad Dybcio .fw_name = "xo",
420519d1d0SKonrad Dybcio },
43aec89f78SBastian Köcher .num_parents = 1,
44aec89f78SBastian Köcher .ops = &clk_alpha_pll_ops,
45aec89f78SBastian Köcher },
46aec89f78SBastian Köcher },
47aec89f78SBastian Köcher };
48aec89f78SBastian Köcher
49aec89f78SBastian Köcher static struct clk_alpha_pll_postdiv gpll0 = {
500519d1d0SKonrad Dybcio .offset = 0,
5128d3f06eSAbhishek Sahu .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
520519d1d0SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){
53aec89f78SBastian Köcher .name = "gpll0",
54*5e1e12d2SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){
55*5e1e12d2SDmitry Baryshkov &gpll0_early.clkr.hw
56*5e1e12d2SDmitry Baryshkov },
57aec89f78SBastian Köcher .num_parents = 1,
58aec89f78SBastian Köcher .ops = &clk_alpha_pll_postdiv_ops,
59aec89f78SBastian Köcher },
60aec89f78SBastian Köcher };
61aec89f78SBastian Köcher
62aec89f78SBastian Köcher static struct clk_alpha_pll gpll4_early = {
63aec89f78SBastian Köcher .offset = 0x1dc0,
6428d3f06eSAbhishek Sahu .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
65aec89f78SBastian Köcher .clkr = {
66aec89f78SBastian Köcher .enable_reg = 0x1480,
67aec89f78SBastian Köcher .enable_mask = BIT(4),
680519d1d0SKonrad Dybcio .hw.init = &(struct clk_init_data){
69aec89f78SBastian Köcher .name = "gpll4_early",
700519d1d0SKonrad Dybcio .parent_data = &(const struct clk_parent_data){
710519d1d0SKonrad Dybcio .fw_name = "xo",
720519d1d0SKonrad Dybcio },
73aec89f78SBastian Köcher .num_parents = 1,
74aec89f78SBastian Köcher .ops = &clk_alpha_pll_ops,
75aec89f78SBastian Köcher },
76aec89f78SBastian Köcher },
77aec89f78SBastian Köcher };
78aec89f78SBastian Köcher
79aec89f78SBastian Köcher static struct clk_alpha_pll_postdiv gpll4 = {
80aec89f78SBastian Köcher .offset = 0x1dc0,
8171021db1SKonrad Dybcio .width = 4,
8228d3f06eSAbhishek Sahu .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
830519d1d0SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){
84aec89f78SBastian Köcher .name = "gpll4",
85*5e1e12d2SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){
86*5e1e12d2SDmitry Baryshkov &gpll4_early.clkr.hw
87*5e1e12d2SDmitry Baryshkov },
88aec89f78SBastian Köcher .num_parents = 1,
89aec89f78SBastian Köcher .ops = &clk_alpha_pll_postdiv_ops,
90aec89f78SBastian Köcher },
91aec89f78SBastian Köcher };
92aec89f78SBastian Köcher
930519d1d0SKonrad Dybcio static const struct parent_map gcc_xo_gpll0_map[] = {
940519d1d0SKonrad Dybcio { P_XO, 0 },
950519d1d0SKonrad Dybcio { P_GPLL0, 1 },
960519d1d0SKonrad Dybcio };
970519d1d0SKonrad Dybcio
980519d1d0SKonrad Dybcio static const struct clk_parent_data gcc_xo_gpll0[] = {
990519d1d0SKonrad Dybcio { .fw_name = "xo" },
1000519d1d0SKonrad Dybcio { .hw = &gpll0.clkr.hw },
1010519d1d0SKonrad Dybcio };
1020519d1d0SKonrad Dybcio
1030519d1d0SKonrad Dybcio static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
1040519d1d0SKonrad Dybcio { P_XO, 0 },
1050519d1d0SKonrad Dybcio { P_GPLL0, 1 },
1060519d1d0SKonrad Dybcio { P_GPLL4, 5 },
1070519d1d0SKonrad Dybcio };
1080519d1d0SKonrad Dybcio
1090519d1d0SKonrad Dybcio static const struct clk_parent_data gcc_xo_gpll0_gpll4[] = {
1100519d1d0SKonrad Dybcio { .fw_name = "xo" },
1110519d1d0SKonrad Dybcio { .hw = &gpll0.clkr.hw },
1120519d1d0SKonrad Dybcio { .hw = &gpll4.clkr.hw },
1130519d1d0SKonrad Dybcio };
1140519d1d0SKonrad Dybcio
115aec89f78SBastian Köcher static struct freq_tbl ftbl_ufs_axi_clk_src[] = {
116aec89f78SBastian Köcher F(50000000, P_GPLL0, 12, 0, 0),
117aec89f78SBastian Köcher F(100000000, P_GPLL0, 6, 0, 0),
118aec89f78SBastian Köcher F(150000000, P_GPLL0, 4, 0, 0),
119aec89f78SBastian Köcher F(171430000, P_GPLL0, 3.5, 0, 0),
120aec89f78SBastian Köcher F(200000000, P_GPLL0, 3, 0, 0),
121aec89f78SBastian Köcher F(240000000, P_GPLL0, 2.5, 0, 0),
122aec89f78SBastian Köcher { }
123aec89f78SBastian Köcher };
124aec89f78SBastian Köcher
125aec89f78SBastian Köcher static struct clk_rcg2 ufs_axi_clk_src = {
126aec89f78SBastian Köcher .cmd_rcgr = 0x1d68,
127aec89f78SBastian Köcher .mnd_width = 8,
128aec89f78SBastian Köcher .hid_width = 5,
129aec89f78SBastian Köcher .parent_map = gcc_xo_gpll0_map,
130aec89f78SBastian Köcher .freq_tbl = ftbl_ufs_axi_clk_src,
1310519d1d0SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){
132aec89f78SBastian Köcher .name = "ufs_axi_clk_src",
1330519d1d0SKonrad Dybcio .parent_data = gcc_xo_gpll0,
134eb2d5058SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
135aec89f78SBastian Köcher .ops = &clk_rcg2_ops,
136aec89f78SBastian Köcher },
137aec89f78SBastian Köcher };
138aec89f78SBastian Köcher
139aec89f78SBastian Köcher static struct freq_tbl ftbl_usb30_master_clk_src[] = {
140aec89f78SBastian Köcher F(19200000, P_XO, 1, 0, 0),
141aec89f78SBastian Köcher F(125000000, P_GPLL0, 1, 5, 24),
142aec89f78SBastian Köcher { }
143aec89f78SBastian Köcher };
144aec89f78SBastian Köcher
145aec89f78SBastian Köcher static struct clk_rcg2 usb30_master_clk_src = {
146aec89f78SBastian Köcher .cmd_rcgr = 0x03d4,
147aec89f78SBastian Köcher .mnd_width = 8,
148aec89f78SBastian Köcher .hid_width = 5,
149aec89f78SBastian Köcher .parent_map = gcc_xo_gpll0_map,
150aec89f78SBastian Köcher .freq_tbl = ftbl_usb30_master_clk_src,
1510519d1d0SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){
152aec89f78SBastian Köcher .name = "usb30_master_clk_src",
1530519d1d0SKonrad Dybcio .parent_data = gcc_xo_gpll0,
154eb2d5058SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
155aec89f78SBastian Köcher .ops = &clk_rcg2_ops,
156aec89f78SBastian Köcher },
157aec89f78SBastian Köcher };
158aec89f78SBastian Köcher
159aec89f78SBastian Köcher static struct freq_tbl ftbl_blsp_i2c_apps_clk_src[] = {
160aec89f78SBastian Köcher F(19200000, P_XO, 1, 0, 0),
161aec89f78SBastian Köcher F(50000000, P_GPLL0, 12, 0, 0),
162aec89f78SBastian Köcher { }
163aec89f78SBastian Köcher };
164aec89f78SBastian Köcher
165aec89f78SBastian Köcher static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
166aec89f78SBastian Köcher .cmd_rcgr = 0x0660,
167aec89f78SBastian Köcher .hid_width = 5,
168aec89f78SBastian Köcher .parent_map = gcc_xo_gpll0_map,
169aec89f78SBastian Köcher .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
1700519d1d0SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){
171aec89f78SBastian Köcher .name = "blsp1_qup1_i2c_apps_clk_src",
1720519d1d0SKonrad Dybcio .parent_data = gcc_xo_gpll0,
173eb2d5058SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
174aec89f78SBastian Köcher .ops = &clk_rcg2_ops,
175aec89f78SBastian Köcher },
176aec89f78SBastian Köcher };
177aec89f78SBastian Köcher
17880863521SKonrad Dybcio static struct freq_tbl ftbl_blsp1_qup1_spi_apps_clk_src[] = {
179aec89f78SBastian Köcher F(960000, P_XO, 10, 1, 2),
180aec89f78SBastian Köcher F(4800000, P_XO, 4, 0, 0),
181aec89f78SBastian Köcher F(9600000, P_XO, 2, 0, 0),
182aec89f78SBastian Köcher F(15000000, P_GPLL0, 10, 1, 4),
183aec89f78SBastian Köcher F(19200000, P_XO, 1, 0, 0),
184aec89f78SBastian Köcher F(24000000, P_GPLL0, 12.5, 1, 2),
185aec89f78SBastian Köcher F(25000000, P_GPLL0, 12, 1, 2),
186aec89f78SBastian Köcher F(48000000, P_GPLL0, 12.5, 0, 0),
187aec89f78SBastian Köcher F(50000000, P_GPLL0, 12, 0, 0),
188aec89f78SBastian Köcher { }
189aec89f78SBastian Köcher };
190aec89f78SBastian Köcher
191c09b8023SKonrad Dybcio static struct freq_tbl ftbl_blsp1_qup_spi_apps_clk_src_8992[] = {
192c09b8023SKonrad Dybcio F(960000, P_XO, 10, 1, 2),
193c09b8023SKonrad Dybcio F(4800000, P_XO, 4, 0, 0),
194c09b8023SKonrad Dybcio F(9600000, P_XO, 2, 0, 0),
195c09b8023SKonrad Dybcio F(15000000, P_GPLL0, 10, 1, 4),
196c09b8023SKonrad Dybcio F(19200000, P_XO, 1, 0, 0),
197c09b8023SKonrad Dybcio F(25000000, P_GPLL0, 12, 1, 2),
198c09b8023SKonrad Dybcio F(50000000, P_GPLL0, 12, 0, 0),
199c09b8023SKonrad Dybcio { }
200c09b8023SKonrad Dybcio };
201c09b8023SKonrad Dybcio
202aec89f78SBastian Köcher static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
203aec89f78SBastian Köcher .cmd_rcgr = 0x064c,
204aec89f78SBastian Köcher .mnd_width = 8,
205aec89f78SBastian Köcher .hid_width = 5,
206aec89f78SBastian Köcher .parent_map = gcc_xo_gpll0_map,
20780863521SKonrad Dybcio .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
2080519d1d0SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){
209aec89f78SBastian Köcher .name = "blsp1_qup1_spi_apps_clk_src",
2100519d1d0SKonrad Dybcio .parent_data = gcc_xo_gpll0,
211eb2d5058SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
212aec89f78SBastian Köcher .ops = &clk_rcg2_ops,
213aec89f78SBastian Köcher },
214aec89f78SBastian Köcher };
215aec89f78SBastian Köcher
216aec89f78SBastian Köcher static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
217aec89f78SBastian Köcher .cmd_rcgr = 0x06e0,
218aec89f78SBastian Köcher .hid_width = 5,
219aec89f78SBastian Köcher .parent_map = gcc_xo_gpll0_map,
220aec89f78SBastian Köcher .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
2210519d1d0SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){
222aec89f78SBastian Köcher .name = "blsp1_qup2_i2c_apps_clk_src",
2230519d1d0SKonrad Dybcio .parent_data = gcc_xo_gpll0,
224eb2d5058SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
225aec89f78SBastian Köcher .ops = &clk_rcg2_ops,
226aec89f78SBastian Köcher },
227aec89f78SBastian Köcher };
228aec89f78SBastian Köcher
22980863521SKonrad Dybcio static struct freq_tbl ftbl_blsp1_qup2_spi_apps_clk_src[] = {
23080863521SKonrad Dybcio F(960000, P_XO, 10, 1, 2),
23180863521SKonrad Dybcio F(4800000, P_XO, 4, 0, 0),
23280863521SKonrad Dybcio F(9600000, P_XO, 2, 0, 0),
23380863521SKonrad Dybcio F(15000000, P_GPLL0, 10, 1, 4),
23480863521SKonrad Dybcio F(19200000, P_XO, 1, 0, 0),
23580863521SKonrad Dybcio F(24000000, P_GPLL0, 12.5, 1, 2),
23680863521SKonrad Dybcio F(25000000, P_GPLL0, 12, 1, 2),
23780863521SKonrad Dybcio F(42860000, P_GPLL0, 14, 0, 0),
23880863521SKonrad Dybcio F(46150000, P_GPLL0, 13, 0, 0),
23980863521SKonrad Dybcio { }
24080863521SKonrad Dybcio };
24180863521SKonrad Dybcio
242aec89f78SBastian Köcher static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
243aec89f78SBastian Köcher .cmd_rcgr = 0x06cc,
244aec89f78SBastian Köcher .mnd_width = 8,
245aec89f78SBastian Köcher .hid_width = 5,
246aec89f78SBastian Köcher .parent_map = gcc_xo_gpll0_map,
24780863521SKonrad Dybcio .freq_tbl = ftbl_blsp1_qup2_spi_apps_clk_src,
2480519d1d0SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){
249aec89f78SBastian Köcher .name = "blsp1_qup2_spi_apps_clk_src",
2500519d1d0SKonrad Dybcio .parent_data = gcc_xo_gpll0,
251eb2d5058SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
252aec89f78SBastian Köcher .ops = &clk_rcg2_ops,
253aec89f78SBastian Köcher },
254aec89f78SBastian Köcher };
255aec89f78SBastian Köcher
256aec89f78SBastian Köcher static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
257aec89f78SBastian Köcher .cmd_rcgr = 0x0760,
258aec89f78SBastian Köcher .hid_width = 5,
259aec89f78SBastian Köcher .parent_map = gcc_xo_gpll0_map,
260aec89f78SBastian Köcher .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
2610519d1d0SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){
262aec89f78SBastian Köcher .name = "blsp1_qup3_i2c_apps_clk_src",
2630519d1d0SKonrad Dybcio .parent_data = gcc_xo_gpll0,
264eb2d5058SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
265aec89f78SBastian Köcher .ops = &clk_rcg2_ops,
266aec89f78SBastian Köcher },
267aec89f78SBastian Köcher };
268aec89f78SBastian Köcher
26980863521SKonrad Dybcio static struct freq_tbl ftbl_blsp1_qup3_4_spi_apps_clk_src[] = {
27080863521SKonrad Dybcio F(960000, P_XO, 10, 1, 2),
27180863521SKonrad Dybcio F(4800000, P_XO, 4, 0, 0),
27280863521SKonrad Dybcio F(9600000, P_XO, 2, 0, 0),
27380863521SKonrad Dybcio F(15000000, P_GPLL0, 10, 1, 4),
27480863521SKonrad Dybcio F(19200000, P_XO, 1, 0, 0),
27580863521SKonrad Dybcio F(24000000, P_GPLL0, 12.5, 1, 2),
27680863521SKonrad Dybcio F(25000000, P_GPLL0, 12, 1, 2),
27780863521SKonrad Dybcio F(42860000, P_GPLL0, 14, 0, 0),
27880863521SKonrad Dybcio F(44440000, P_GPLL0, 13.5, 0, 0),
27980863521SKonrad Dybcio { }
28080863521SKonrad Dybcio };
28180863521SKonrad Dybcio
282aec89f78SBastian Köcher static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
283aec89f78SBastian Köcher .cmd_rcgr = 0x074c,
284aec89f78SBastian Köcher .mnd_width = 8,
285aec89f78SBastian Köcher .hid_width = 5,
286aec89f78SBastian Köcher .parent_map = gcc_xo_gpll0_map,
28780863521SKonrad Dybcio .freq_tbl = ftbl_blsp1_qup3_4_spi_apps_clk_src,
2880519d1d0SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){
289aec89f78SBastian Köcher .name = "blsp1_qup3_spi_apps_clk_src",
2900519d1d0SKonrad Dybcio .parent_data = gcc_xo_gpll0,
291eb2d5058SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
292aec89f78SBastian Köcher .ops = &clk_rcg2_ops,
293aec89f78SBastian Köcher },
294aec89f78SBastian Köcher };
295aec89f78SBastian Köcher
296aec89f78SBastian Köcher static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
297aec89f78SBastian Köcher .cmd_rcgr = 0x07e0,
298aec89f78SBastian Köcher .hid_width = 5,
299aec89f78SBastian Köcher .parent_map = gcc_xo_gpll0_map,
300aec89f78SBastian Köcher .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
3010519d1d0SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){
302aec89f78SBastian Köcher .name = "blsp1_qup4_i2c_apps_clk_src",
3030519d1d0SKonrad Dybcio .parent_data = gcc_xo_gpll0,
304eb2d5058SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
305aec89f78SBastian Köcher .ops = &clk_rcg2_ops,
306aec89f78SBastian Köcher },
307aec89f78SBastian Köcher };
308aec89f78SBastian Köcher
309aec89f78SBastian Köcher static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
310aec89f78SBastian Köcher .cmd_rcgr = 0x07cc,
311aec89f78SBastian Köcher .mnd_width = 8,
312aec89f78SBastian Köcher .hid_width = 5,
313aec89f78SBastian Köcher .parent_map = gcc_xo_gpll0_map,
31480863521SKonrad Dybcio .freq_tbl = ftbl_blsp1_qup3_4_spi_apps_clk_src,
3150519d1d0SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){
316aec89f78SBastian Köcher .name = "blsp1_qup4_spi_apps_clk_src",
3170519d1d0SKonrad Dybcio .parent_data = gcc_xo_gpll0,
318eb2d5058SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
319aec89f78SBastian Köcher .ops = &clk_rcg2_ops,
320aec89f78SBastian Köcher },
321aec89f78SBastian Köcher };
322aec89f78SBastian Köcher
323aec89f78SBastian Köcher static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
324aec89f78SBastian Köcher .cmd_rcgr = 0x0860,
325aec89f78SBastian Köcher .hid_width = 5,
326aec89f78SBastian Köcher .parent_map = gcc_xo_gpll0_map,
327aec89f78SBastian Köcher .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
3280519d1d0SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){
329aec89f78SBastian Köcher .name = "blsp1_qup5_i2c_apps_clk_src",
3300519d1d0SKonrad Dybcio .parent_data = gcc_xo_gpll0,
331eb2d5058SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
332aec89f78SBastian Köcher .ops = &clk_rcg2_ops,
333aec89f78SBastian Köcher },
334aec89f78SBastian Köcher };
335aec89f78SBastian Köcher
33680863521SKonrad Dybcio static struct freq_tbl ftbl_blsp1_qup5_spi_apps_clk_src[] = {
33780863521SKonrad Dybcio F(960000, P_XO, 10, 1, 2),
33880863521SKonrad Dybcio F(4800000, P_XO, 4, 0, 0),
33980863521SKonrad Dybcio F(9600000, P_XO, 2, 0, 0),
34080863521SKonrad Dybcio F(15000000, P_GPLL0, 10, 1, 4),
34180863521SKonrad Dybcio F(19200000, P_XO, 1, 0, 0),
34280863521SKonrad Dybcio F(24000000, P_GPLL0, 12.5, 1, 2),
34380863521SKonrad Dybcio F(25000000, P_GPLL0, 12, 1, 2),
34480863521SKonrad Dybcio F(40000000, P_GPLL0, 15, 0, 0),
34580863521SKonrad Dybcio F(42860000, P_GPLL0, 14, 0, 0),
34680863521SKonrad Dybcio { }
34780863521SKonrad Dybcio };
34880863521SKonrad Dybcio
349aec89f78SBastian Köcher static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
350aec89f78SBastian Köcher .cmd_rcgr = 0x084c,
351aec89f78SBastian Köcher .mnd_width = 8,
352aec89f78SBastian Köcher .hid_width = 5,
353aec89f78SBastian Köcher .parent_map = gcc_xo_gpll0_map,
35480863521SKonrad Dybcio .freq_tbl = ftbl_blsp1_qup5_spi_apps_clk_src,
3550519d1d0SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){
356aec89f78SBastian Köcher .name = "blsp1_qup5_spi_apps_clk_src",
3570519d1d0SKonrad Dybcio .parent_data = gcc_xo_gpll0,
358eb2d5058SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
359aec89f78SBastian Köcher .ops = &clk_rcg2_ops,
360aec89f78SBastian Köcher },
361aec89f78SBastian Köcher };
362aec89f78SBastian Köcher
363aec89f78SBastian Köcher static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
364aec89f78SBastian Köcher .cmd_rcgr = 0x08e0,
365aec89f78SBastian Köcher .hid_width = 5,
366aec89f78SBastian Köcher .parent_map = gcc_xo_gpll0_map,
367aec89f78SBastian Köcher .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
3680519d1d0SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){
369aec89f78SBastian Köcher .name = "blsp1_qup6_i2c_apps_clk_src",
3700519d1d0SKonrad Dybcio .parent_data = gcc_xo_gpll0,
371eb2d5058SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
372aec89f78SBastian Köcher .ops = &clk_rcg2_ops,
373aec89f78SBastian Köcher },
374aec89f78SBastian Köcher };
375aec89f78SBastian Köcher
37680863521SKonrad Dybcio static struct freq_tbl ftbl_blsp1_qup6_spi_apps_clk_src[] = {
37780863521SKonrad Dybcio F(960000, P_XO, 10, 1, 2),
37880863521SKonrad Dybcio F(4800000, P_XO, 4, 0, 0),
37980863521SKonrad Dybcio F(9600000, P_XO, 2, 0, 0),
38080863521SKonrad Dybcio F(15000000, P_GPLL0, 10, 1, 4),
38180863521SKonrad Dybcio F(19200000, P_XO, 1, 0, 0),
38280863521SKonrad Dybcio F(24000000, P_GPLL0, 12.5, 1, 2),
38380863521SKonrad Dybcio F(27906976, P_GPLL0, 1, 2, 43),
38480863521SKonrad Dybcio F(41380000, P_GPLL0, 15, 0, 0),
38580863521SKonrad Dybcio F(42860000, P_GPLL0, 14, 0, 0),
38680863521SKonrad Dybcio { }
38780863521SKonrad Dybcio };
38880863521SKonrad Dybcio
389aec89f78SBastian Köcher static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
390aec89f78SBastian Köcher .cmd_rcgr = 0x08cc,
391aec89f78SBastian Köcher .mnd_width = 8,
392aec89f78SBastian Köcher .hid_width = 5,
393aec89f78SBastian Köcher .parent_map = gcc_xo_gpll0_map,
39480863521SKonrad Dybcio .freq_tbl = ftbl_blsp1_qup6_spi_apps_clk_src,
3950519d1d0SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){
396aec89f78SBastian Köcher .name = "blsp1_qup6_spi_apps_clk_src",
3970519d1d0SKonrad Dybcio .parent_data = gcc_xo_gpll0,
398eb2d5058SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
399aec89f78SBastian Köcher .ops = &clk_rcg2_ops,
400aec89f78SBastian Köcher },
401aec89f78SBastian Köcher };
402aec89f78SBastian Köcher
403aec89f78SBastian Köcher static struct freq_tbl ftbl_blsp_uart_apps_clk_src[] = {
404aec89f78SBastian Köcher F(3686400, P_GPLL0, 1, 96, 15625),
405aec89f78SBastian Köcher F(7372800, P_GPLL0, 1, 192, 15625),
406aec89f78SBastian Köcher F(14745600, P_GPLL0, 1, 384, 15625),
407aec89f78SBastian Köcher F(16000000, P_GPLL0, 5, 2, 15),
408aec89f78SBastian Köcher F(19200000, P_XO, 1, 0, 0),
409aec89f78SBastian Köcher F(24000000, P_GPLL0, 5, 1, 5),
410aec89f78SBastian Köcher F(32000000, P_GPLL0, 1, 4, 75),
411aec89f78SBastian Köcher F(40000000, P_GPLL0, 15, 0, 0),
412aec89f78SBastian Köcher F(46400000, P_GPLL0, 1, 29, 375),
413aec89f78SBastian Köcher F(48000000, P_GPLL0, 12.5, 0, 0),
414aec89f78SBastian Köcher F(51200000, P_GPLL0, 1, 32, 375),
415aec89f78SBastian Köcher F(56000000, P_GPLL0, 1, 7, 75),
416aec89f78SBastian Köcher F(58982400, P_GPLL0, 1, 1536, 15625),
417aec89f78SBastian Köcher F(60000000, P_GPLL0, 10, 0, 0),
418aec89f78SBastian Köcher F(63160000, P_GPLL0, 9.5, 0, 0),
419aec89f78SBastian Köcher { }
420aec89f78SBastian Köcher };
421aec89f78SBastian Köcher
422aec89f78SBastian Köcher static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
423aec89f78SBastian Köcher .cmd_rcgr = 0x068c,
424aec89f78SBastian Köcher .mnd_width = 16,
425aec89f78SBastian Köcher .hid_width = 5,
426aec89f78SBastian Köcher .parent_map = gcc_xo_gpll0_map,
427aec89f78SBastian Köcher .freq_tbl = ftbl_blsp_uart_apps_clk_src,
4280519d1d0SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){
429aec89f78SBastian Köcher .name = "blsp1_uart1_apps_clk_src",
4300519d1d0SKonrad Dybcio .parent_data = gcc_xo_gpll0,
431eb2d5058SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
432aec89f78SBastian Köcher .ops = &clk_rcg2_ops,
433aec89f78SBastian Köcher },
434aec89f78SBastian Köcher };
435aec89f78SBastian Köcher
436aec89f78SBastian Köcher static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
437aec89f78SBastian Köcher .cmd_rcgr = 0x070c,
438aec89f78SBastian Köcher .mnd_width = 16,
439aec89f78SBastian Köcher .hid_width = 5,
440aec89f78SBastian Köcher .parent_map = gcc_xo_gpll0_map,
441aec89f78SBastian Köcher .freq_tbl = ftbl_blsp_uart_apps_clk_src,
4420519d1d0SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){
443aec89f78SBastian Köcher .name = "blsp1_uart2_apps_clk_src",
4440519d1d0SKonrad Dybcio .parent_data = gcc_xo_gpll0,
445eb2d5058SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
446aec89f78SBastian Köcher .ops = &clk_rcg2_ops,
447aec89f78SBastian Köcher },
448aec89f78SBastian Köcher };
449aec89f78SBastian Köcher
450aec89f78SBastian Köcher static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
451aec89f78SBastian Köcher .cmd_rcgr = 0x078c,
452aec89f78SBastian Köcher .mnd_width = 16,
453aec89f78SBastian Köcher .hid_width = 5,
454aec89f78SBastian Köcher .parent_map = gcc_xo_gpll0_map,
455aec89f78SBastian Köcher .freq_tbl = ftbl_blsp_uart_apps_clk_src,
4560519d1d0SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){
457aec89f78SBastian Köcher .name = "blsp1_uart3_apps_clk_src",
4580519d1d0SKonrad Dybcio .parent_data = gcc_xo_gpll0,
459eb2d5058SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
460aec89f78SBastian Köcher .ops = &clk_rcg2_ops,
461aec89f78SBastian Köcher },
462aec89f78SBastian Köcher };
463aec89f78SBastian Köcher
464aec89f78SBastian Köcher static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
465aec89f78SBastian Köcher .cmd_rcgr = 0x080c,
466aec89f78SBastian Köcher .mnd_width = 16,
467aec89f78SBastian Köcher .hid_width = 5,
468aec89f78SBastian Köcher .parent_map = gcc_xo_gpll0_map,
469aec89f78SBastian Köcher .freq_tbl = ftbl_blsp_uart_apps_clk_src,
4700519d1d0SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){
471aec89f78SBastian Köcher .name = "blsp1_uart4_apps_clk_src",
4720519d1d0SKonrad Dybcio .parent_data = gcc_xo_gpll0,
473eb2d5058SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
474aec89f78SBastian Köcher .ops = &clk_rcg2_ops,
475aec89f78SBastian Köcher },
476aec89f78SBastian Köcher };
477aec89f78SBastian Köcher
478aec89f78SBastian Köcher static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
479aec89f78SBastian Köcher .cmd_rcgr = 0x088c,
480aec89f78SBastian Köcher .mnd_width = 16,
481aec89f78SBastian Köcher .hid_width = 5,
482aec89f78SBastian Köcher .parent_map = gcc_xo_gpll0_map,
483aec89f78SBastian Köcher .freq_tbl = ftbl_blsp_uart_apps_clk_src,
4840519d1d0SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){
485aec89f78SBastian Köcher .name = "blsp1_uart5_apps_clk_src",
4860519d1d0SKonrad Dybcio .parent_data = gcc_xo_gpll0,
487eb2d5058SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
488aec89f78SBastian Köcher .ops = &clk_rcg2_ops,
489aec89f78SBastian Köcher },
490aec89f78SBastian Köcher };
491aec89f78SBastian Köcher
492aec89f78SBastian Köcher static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
493aec89f78SBastian Köcher .cmd_rcgr = 0x090c,
494aec89f78SBastian Köcher .mnd_width = 16,
495aec89f78SBastian Köcher .hid_width = 5,
496aec89f78SBastian Köcher .parent_map = gcc_xo_gpll0_map,
497aec89f78SBastian Köcher .freq_tbl = ftbl_blsp_uart_apps_clk_src,
4980519d1d0SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){
499aec89f78SBastian Köcher .name = "blsp1_uart6_apps_clk_src",
5000519d1d0SKonrad Dybcio .parent_data = gcc_xo_gpll0,
501eb2d5058SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
502aec89f78SBastian Köcher .ops = &clk_rcg2_ops,
503aec89f78SBastian Köcher },
504aec89f78SBastian Köcher };
505aec89f78SBastian Köcher
506aec89f78SBastian Köcher static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
507aec89f78SBastian Köcher .cmd_rcgr = 0x09a0,
508aec89f78SBastian Köcher .hid_width = 5,
509aec89f78SBastian Köcher .parent_map = gcc_xo_gpll0_map,
510aec89f78SBastian Köcher .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
5110519d1d0SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){
512aec89f78SBastian Köcher .name = "blsp2_qup1_i2c_apps_clk_src",
5130519d1d0SKonrad Dybcio .parent_data = gcc_xo_gpll0,
514eb2d5058SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
515aec89f78SBastian Köcher .ops = &clk_rcg2_ops,
516aec89f78SBastian Köcher },
517aec89f78SBastian Köcher };
518aec89f78SBastian Köcher
51980863521SKonrad Dybcio static struct freq_tbl ftbl_blsp2_qup1_2_spi_apps_clk_src[] = {
52080863521SKonrad Dybcio F(960000, P_XO, 10, 1, 2),
52180863521SKonrad Dybcio F(4800000, P_XO, 4, 0, 0),
52280863521SKonrad Dybcio F(9600000, P_XO, 2, 0, 0),
52380863521SKonrad Dybcio F(15000000, P_GPLL0, 10, 1, 4),
52480863521SKonrad Dybcio F(19200000, P_XO, 1, 0, 0),
52580863521SKonrad Dybcio F(24000000, P_GPLL0, 12.5, 1, 2),
52680863521SKonrad Dybcio F(25000000, P_GPLL0, 12, 1, 2),
52780863521SKonrad Dybcio F(42860000, P_GPLL0, 14, 0, 0),
52880863521SKonrad Dybcio F(44440000, P_GPLL0, 13.5, 0, 0),
52980863521SKonrad Dybcio { }
53080863521SKonrad Dybcio };
53180863521SKonrad Dybcio
532aec89f78SBastian Köcher static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
533aec89f78SBastian Köcher .cmd_rcgr = 0x098c,
534aec89f78SBastian Köcher .mnd_width = 8,
535aec89f78SBastian Köcher .hid_width = 5,
536aec89f78SBastian Köcher .parent_map = gcc_xo_gpll0_map,
53780863521SKonrad Dybcio .freq_tbl = ftbl_blsp2_qup1_2_spi_apps_clk_src,
5380519d1d0SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){
539aec89f78SBastian Köcher .name = "blsp2_qup1_spi_apps_clk_src",
5400519d1d0SKonrad Dybcio .parent_data = gcc_xo_gpll0,
541eb2d5058SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
542aec89f78SBastian Köcher .ops = &clk_rcg2_ops,
543aec89f78SBastian Köcher },
544aec89f78SBastian Köcher };
545aec89f78SBastian Köcher
546aec89f78SBastian Köcher static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
547aec89f78SBastian Köcher .cmd_rcgr = 0x0a20,
548aec89f78SBastian Köcher .hid_width = 5,
549aec89f78SBastian Köcher .parent_map = gcc_xo_gpll0_map,
550aec89f78SBastian Köcher .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
5510519d1d0SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){
552aec89f78SBastian Köcher .name = "blsp2_qup2_i2c_apps_clk_src",
5530519d1d0SKonrad Dybcio .parent_data = gcc_xo_gpll0,
554eb2d5058SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
555aec89f78SBastian Köcher .ops = &clk_rcg2_ops,
556aec89f78SBastian Köcher },
557aec89f78SBastian Köcher };
558aec89f78SBastian Köcher
559aec89f78SBastian Köcher static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
560aec89f78SBastian Köcher .cmd_rcgr = 0x0a0c,
561aec89f78SBastian Köcher .mnd_width = 8,
562aec89f78SBastian Köcher .hid_width = 5,
563aec89f78SBastian Köcher .parent_map = gcc_xo_gpll0_map,
56480863521SKonrad Dybcio .freq_tbl = ftbl_blsp2_qup1_2_spi_apps_clk_src,
5650519d1d0SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){
566aec89f78SBastian Köcher .name = "blsp2_qup2_spi_apps_clk_src",
5670519d1d0SKonrad Dybcio .parent_data = gcc_xo_gpll0,
568eb2d5058SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
569aec89f78SBastian Köcher .ops = &clk_rcg2_ops,
570aec89f78SBastian Köcher },
571aec89f78SBastian Köcher };
572aec89f78SBastian Köcher
57380863521SKonrad Dybcio static struct freq_tbl ftbl_blsp2_qup3_4_spi_apps_clk_src[] = {
57480863521SKonrad Dybcio F(960000, P_XO, 10, 1, 2),
57580863521SKonrad Dybcio F(4800000, P_XO, 4, 0, 0),
57680863521SKonrad Dybcio F(9600000, P_XO, 2, 0, 0),
57780863521SKonrad Dybcio F(15000000, P_GPLL0, 10, 1, 4),
57880863521SKonrad Dybcio F(19200000, P_XO, 1, 0, 0),
57980863521SKonrad Dybcio F(24000000, P_GPLL0, 12.5, 1, 2),
58080863521SKonrad Dybcio F(25000000, P_GPLL0, 12, 1, 2),
58180863521SKonrad Dybcio F(42860000, P_GPLL0, 14, 0, 0),
58280863521SKonrad Dybcio F(48000000, P_GPLL0, 12.5, 0, 0),
58380863521SKonrad Dybcio { }
58480863521SKonrad Dybcio };
58580863521SKonrad Dybcio
586aec89f78SBastian Köcher static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
587aec89f78SBastian Köcher .cmd_rcgr = 0x0aa0,
588aec89f78SBastian Köcher .hid_width = 5,
589aec89f78SBastian Köcher .parent_map = gcc_xo_gpll0_map,
590aec89f78SBastian Köcher .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
5910519d1d0SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){
592aec89f78SBastian Köcher .name = "blsp2_qup3_i2c_apps_clk_src",
5930519d1d0SKonrad Dybcio .parent_data = gcc_xo_gpll0,
594eb2d5058SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
595aec89f78SBastian Köcher .ops = &clk_rcg2_ops,
596aec89f78SBastian Köcher },
597aec89f78SBastian Köcher };
598aec89f78SBastian Köcher
599aec89f78SBastian Köcher static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
600aec89f78SBastian Köcher .cmd_rcgr = 0x0a8c,
601aec89f78SBastian Köcher .mnd_width = 8,
602aec89f78SBastian Köcher .hid_width = 5,
603aec89f78SBastian Köcher .parent_map = gcc_xo_gpll0_map,
60480863521SKonrad Dybcio .freq_tbl = ftbl_blsp2_qup3_4_spi_apps_clk_src,
6050519d1d0SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){
606aec89f78SBastian Köcher .name = "blsp2_qup3_spi_apps_clk_src",
6070519d1d0SKonrad Dybcio .parent_data = gcc_xo_gpll0,
608eb2d5058SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
609aec89f78SBastian Köcher .ops = &clk_rcg2_ops,
610aec89f78SBastian Köcher },
611aec89f78SBastian Köcher };
612aec89f78SBastian Köcher
613aec89f78SBastian Köcher static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
614aec89f78SBastian Köcher .cmd_rcgr = 0x0b20,
615aec89f78SBastian Köcher .hid_width = 5,
616aec89f78SBastian Köcher .parent_map = gcc_xo_gpll0_map,
617aec89f78SBastian Köcher .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
6180519d1d0SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){
619aec89f78SBastian Köcher .name = "blsp2_qup4_i2c_apps_clk_src",
6200519d1d0SKonrad Dybcio .parent_data = gcc_xo_gpll0,
621eb2d5058SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
622aec89f78SBastian Köcher .ops = &clk_rcg2_ops,
623aec89f78SBastian Köcher },
624aec89f78SBastian Köcher };
625aec89f78SBastian Köcher
626aec89f78SBastian Köcher static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
627aec89f78SBastian Köcher .cmd_rcgr = 0x0b0c,
628aec89f78SBastian Köcher .mnd_width = 8,
629aec89f78SBastian Köcher .hid_width = 5,
630aec89f78SBastian Köcher .parent_map = gcc_xo_gpll0_map,
63180863521SKonrad Dybcio .freq_tbl = ftbl_blsp2_qup3_4_spi_apps_clk_src,
6320519d1d0SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){
633aec89f78SBastian Köcher .name = "blsp2_qup4_spi_apps_clk_src",
6340519d1d0SKonrad Dybcio .parent_data = gcc_xo_gpll0,
635eb2d5058SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
636aec89f78SBastian Köcher .ops = &clk_rcg2_ops,
637aec89f78SBastian Köcher },
638aec89f78SBastian Köcher };
639aec89f78SBastian Köcher
640aec89f78SBastian Köcher static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = {
641aec89f78SBastian Köcher .cmd_rcgr = 0x0ba0,
642aec89f78SBastian Köcher .hid_width = 5,
643aec89f78SBastian Köcher .parent_map = gcc_xo_gpll0_map,
644aec89f78SBastian Köcher .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
6450519d1d0SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){
646aec89f78SBastian Köcher .name = "blsp2_qup5_i2c_apps_clk_src",
6470519d1d0SKonrad Dybcio .parent_data = gcc_xo_gpll0,
648eb2d5058SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
649aec89f78SBastian Köcher .ops = &clk_rcg2_ops,
650aec89f78SBastian Köcher },
651aec89f78SBastian Köcher };
652aec89f78SBastian Köcher
653aec89f78SBastian Köcher static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = {
654aec89f78SBastian Köcher .cmd_rcgr = 0x0b8c,
655aec89f78SBastian Köcher .mnd_width = 8,
656aec89f78SBastian Köcher .hid_width = 5,
657aec89f78SBastian Köcher .parent_map = gcc_xo_gpll0_map,
65880863521SKonrad Dybcio /* BLSP1 QUP1 and BLSP2 QUP5 use the same freqs */
65980863521SKonrad Dybcio .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
6600519d1d0SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){
661aec89f78SBastian Köcher .name = "blsp2_qup5_spi_apps_clk_src",
6620519d1d0SKonrad Dybcio .parent_data = gcc_xo_gpll0,
663eb2d5058SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
664aec89f78SBastian Köcher .ops = &clk_rcg2_ops,
665aec89f78SBastian Köcher },
666aec89f78SBastian Köcher };
667aec89f78SBastian Köcher
668aec89f78SBastian Köcher static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = {
669aec89f78SBastian Köcher .cmd_rcgr = 0x0c20,
670aec89f78SBastian Köcher .hid_width = 5,
671aec89f78SBastian Köcher .parent_map = gcc_xo_gpll0_map,
672aec89f78SBastian Köcher .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
6730519d1d0SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){
674aec89f78SBastian Köcher .name = "blsp2_qup6_i2c_apps_clk_src",
6750519d1d0SKonrad Dybcio .parent_data = gcc_xo_gpll0,
676eb2d5058SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
677aec89f78SBastian Köcher .ops = &clk_rcg2_ops,
678aec89f78SBastian Köcher },
679aec89f78SBastian Köcher };
680aec89f78SBastian Köcher
68180863521SKonrad Dybcio static struct freq_tbl ftbl_blsp2_qup6_spi_apps_clk_src[] = {
68280863521SKonrad Dybcio F(960000, P_XO, 10, 1, 2),
68380863521SKonrad Dybcio F(4800000, P_XO, 4, 0, 0),
68480863521SKonrad Dybcio F(9600000, P_XO, 2, 0, 0),
68580863521SKonrad Dybcio F(15000000, P_GPLL0, 10, 1, 4),
68680863521SKonrad Dybcio F(19200000, P_XO, 1, 0, 0),
68780863521SKonrad Dybcio F(24000000, P_GPLL0, 12.5, 1, 2),
68880863521SKonrad Dybcio F(25000000, P_GPLL0, 12, 1, 2),
68980863521SKonrad Dybcio F(44440000, P_GPLL0, 13.5, 0, 0),
69080863521SKonrad Dybcio F(48000000, P_GPLL0, 12.5, 0, 0),
69180863521SKonrad Dybcio { }
69280863521SKonrad Dybcio };
69380863521SKonrad Dybcio
694aec89f78SBastian Köcher static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = {
695aec89f78SBastian Köcher .cmd_rcgr = 0x0c0c,
696aec89f78SBastian Köcher .mnd_width = 8,
697aec89f78SBastian Köcher .hid_width = 5,
698aec89f78SBastian Köcher .parent_map = gcc_xo_gpll0_map,
69980863521SKonrad Dybcio .freq_tbl = ftbl_blsp2_qup6_spi_apps_clk_src,
7000519d1d0SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){
701aec89f78SBastian Köcher .name = "blsp2_qup6_spi_apps_clk_src",
7020519d1d0SKonrad Dybcio .parent_data = gcc_xo_gpll0,
703eb2d5058SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
704aec89f78SBastian Köcher .ops = &clk_rcg2_ops,
705aec89f78SBastian Köcher },
706aec89f78SBastian Köcher };
707aec89f78SBastian Köcher
708aec89f78SBastian Köcher static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
709aec89f78SBastian Köcher .cmd_rcgr = 0x09cc,
710aec89f78SBastian Köcher .mnd_width = 16,
711aec89f78SBastian Köcher .hid_width = 5,
712aec89f78SBastian Köcher .parent_map = gcc_xo_gpll0_map,
713aec89f78SBastian Köcher .freq_tbl = ftbl_blsp_uart_apps_clk_src,
7140519d1d0SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){
715aec89f78SBastian Köcher .name = "blsp2_uart1_apps_clk_src",
7160519d1d0SKonrad Dybcio .parent_data = gcc_xo_gpll0,
717eb2d5058SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
718aec89f78SBastian Köcher .ops = &clk_rcg2_ops,
719aec89f78SBastian Köcher },
720aec89f78SBastian Köcher };
721aec89f78SBastian Köcher
722aec89f78SBastian Köcher static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
723aec89f78SBastian Köcher .cmd_rcgr = 0x0a4c,
724aec89f78SBastian Köcher .mnd_width = 16,
725aec89f78SBastian Köcher .hid_width = 5,
726aec89f78SBastian Köcher .parent_map = gcc_xo_gpll0_map,
727aec89f78SBastian Köcher .freq_tbl = ftbl_blsp_uart_apps_clk_src,
7280519d1d0SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){
729aec89f78SBastian Köcher .name = "blsp2_uart2_apps_clk_src",
7300519d1d0SKonrad Dybcio .parent_data = gcc_xo_gpll0,
731eb2d5058SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
732aec89f78SBastian Köcher .ops = &clk_rcg2_ops,
733aec89f78SBastian Köcher },
734aec89f78SBastian Köcher };
735aec89f78SBastian Köcher
736aec89f78SBastian Köcher static struct clk_rcg2 blsp2_uart3_apps_clk_src = {
737aec89f78SBastian Köcher .cmd_rcgr = 0x0acc,
738aec89f78SBastian Köcher .mnd_width = 16,
739aec89f78SBastian Köcher .hid_width = 5,
740aec89f78SBastian Köcher .parent_map = gcc_xo_gpll0_map,
741aec89f78SBastian Köcher .freq_tbl = ftbl_blsp_uart_apps_clk_src,
7420519d1d0SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){
743aec89f78SBastian Köcher .name = "blsp2_uart3_apps_clk_src",
7440519d1d0SKonrad Dybcio .parent_data = gcc_xo_gpll0,
745eb2d5058SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
746aec89f78SBastian Köcher .ops = &clk_rcg2_ops,
747aec89f78SBastian Köcher },
748aec89f78SBastian Köcher };
749aec89f78SBastian Köcher
750aec89f78SBastian Köcher static struct clk_rcg2 blsp2_uart4_apps_clk_src = {
751aec89f78SBastian Köcher .cmd_rcgr = 0x0b4c,
752aec89f78SBastian Köcher .mnd_width = 16,
753aec89f78SBastian Köcher .hid_width = 5,
754aec89f78SBastian Köcher .parent_map = gcc_xo_gpll0_map,
755aec89f78SBastian Köcher .freq_tbl = ftbl_blsp_uart_apps_clk_src,
7560519d1d0SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){
757aec89f78SBastian Köcher .name = "blsp2_uart4_apps_clk_src",
7580519d1d0SKonrad Dybcio .parent_data = gcc_xo_gpll0,
759eb2d5058SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
760aec89f78SBastian Köcher .ops = &clk_rcg2_ops,
761aec89f78SBastian Köcher },
762aec89f78SBastian Köcher };
763aec89f78SBastian Köcher
764aec89f78SBastian Köcher static struct clk_rcg2 blsp2_uart5_apps_clk_src = {
765aec89f78SBastian Köcher .cmd_rcgr = 0x0bcc,
766aec89f78SBastian Köcher .mnd_width = 16,
767aec89f78SBastian Köcher .hid_width = 5,
768aec89f78SBastian Köcher .parent_map = gcc_xo_gpll0_map,
769aec89f78SBastian Köcher .freq_tbl = ftbl_blsp_uart_apps_clk_src,
7700519d1d0SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){
771aec89f78SBastian Köcher .name = "blsp2_uart5_apps_clk_src",
7720519d1d0SKonrad Dybcio .parent_data = gcc_xo_gpll0,
773eb2d5058SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
774aec89f78SBastian Köcher .ops = &clk_rcg2_ops,
775aec89f78SBastian Köcher },
776aec89f78SBastian Köcher };
777aec89f78SBastian Köcher
778aec89f78SBastian Köcher static struct clk_rcg2 blsp2_uart6_apps_clk_src = {
779aec89f78SBastian Köcher .cmd_rcgr = 0x0c4c,
780aec89f78SBastian Köcher .mnd_width = 16,
781aec89f78SBastian Köcher .hid_width = 5,
782aec89f78SBastian Köcher .parent_map = gcc_xo_gpll0_map,
783aec89f78SBastian Köcher .freq_tbl = ftbl_blsp_uart_apps_clk_src,
7840519d1d0SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){
785aec89f78SBastian Köcher .name = "blsp2_uart6_apps_clk_src",
7860519d1d0SKonrad Dybcio .parent_data = gcc_xo_gpll0,
787eb2d5058SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
788aec89f78SBastian Köcher .ops = &clk_rcg2_ops,
789aec89f78SBastian Köcher },
790aec89f78SBastian Köcher };
791aec89f78SBastian Köcher
792aec89f78SBastian Köcher static struct freq_tbl ftbl_gp1_clk_src[] = {
793aec89f78SBastian Köcher F(19200000, P_XO, 1, 0, 0),
794aec89f78SBastian Köcher F(100000000, P_GPLL0, 6, 0, 0),
795aec89f78SBastian Köcher F(200000000, P_GPLL0, 3, 0, 0),
796aec89f78SBastian Köcher { }
797aec89f78SBastian Köcher };
798aec89f78SBastian Köcher
799aec89f78SBastian Köcher static struct clk_rcg2 gp1_clk_src = {
800aec89f78SBastian Köcher .cmd_rcgr = 0x1904,
801aec89f78SBastian Köcher .mnd_width = 8,
802aec89f78SBastian Köcher .hid_width = 5,
803aec89f78SBastian Köcher .parent_map = gcc_xo_gpll0_map,
804aec89f78SBastian Köcher .freq_tbl = ftbl_gp1_clk_src,
8050519d1d0SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){
806aec89f78SBastian Köcher .name = "gp1_clk_src",
8070519d1d0SKonrad Dybcio .parent_data = gcc_xo_gpll0,
808eb2d5058SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
809aec89f78SBastian Köcher .ops = &clk_rcg2_ops,
810aec89f78SBastian Köcher },
811aec89f78SBastian Köcher };
812aec89f78SBastian Köcher
813aec89f78SBastian Köcher static struct freq_tbl ftbl_gp2_clk_src[] = {
814aec89f78SBastian Köcher F(19200000, P_XO, 1, 0, 0),
815aec89f78SBastian Köcher F(100000000, P_GPLL0, 6, 0, 0),
816aec89f78SBastian Köcher F(200000000, P_GPLL0, 3, 0, 0),
817aec89f78SBastian Köcher { }
818aec89f78SBastian Köcher };
819aec89f78SBastian Köcher
820aec89f78SBastian Köcher static struct clk_rcg2 gp2_clk_src = {
821aec89f78SBastian Köcher .cmd_rcgr = 0x1944,
822aec89f78SBastian Köcher .mnd_width = 8,
823aec89f78SBastian Köcher .hid_width = 5,
824aec89f78SBastian Köcher .parent_map = gcc_xo_gpll0_map,
825aec89f78SBastian Köcher .freq_tbl = ftbl_gp2_clk_src,
8260519d1d0SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){
827aec89f78SBastian Köcher .name = "gp2_clk_src",
8280519d1d0SKonrad Dybcio .parent_data = gcc_xo_gpll0,
829eb2d5058SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
830aec89f78SBastian Köcher .ops = &clk_rcg2_ops,
831aec89f78SBastian Köcher },
832aec89f78SBastian Köcher };
833aec89f78SBastian Köcher
834aec89f78SBastian Köcher static struct freq_tbl ftbl_gp3_clk_src[] = {
835aec89f78SBastian Köcher F(19200000, P_XO, 1, 0, 0),
836aec89f78SBastian Köcher F(100000000, P_GPLL0, 6, 0, 0),
837aec89f78SBastian Köcher F(200000000, P_GPLL0, 3, 0, 0),
838aec89f78SBastian Köcher { }
839aec89f78SBastian Köcher };
840aec89f78SBastian Köcher
841aec89f78SBastian Köcher static struct clk_rcg2 gp3_clk_src = {
842aec89f78SBastian Köcher .cmd_rcgr = 0x1984,
843aec89f78SBastian Köcher .mnd_width = 8,
844aec89f78SBastian Köcher .hid_width = 5,
845aec89f78SBastian Köcher .parent_map = gcc_xo_gpll0_map,
846aec89f78SBastian Köcher .freq_tbl = ftbl_gp3_clk_src,
8470519d1d0SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){
848aec89f78SBastian Köcher .name = "gp3_clk_src",
8490519d1d0SKonrad Dybcio .parent_data = gcc_xo_gpll0,
850eb2d5058SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
851aec89f78SBastian Köcher .ops = &clk_rcg2_ops,
852aec89f78SBastian Köcher },
853aec89f78SBastian Köcher };
854aec89f78SBastian Köcher
855aec89f78SBastian Köcher static struct freq_tbl ftbl_pcie_0_aux_clk_src[] = {
856aec89f78SBastian Köcher F(1011000, P_XO, 1, 1, 19),
857aec89f78SBastian Köcher { }
858aec89f78SBastian Köcher };
859aec89f78SBastian Köcher
860aec89f78SBastian Köcher static struct clk_rcg2 pcie_0_aux_clk_src = {
861aec89f78SBastian Köcher .cmd_rcgr = 0x1b00,
862aec89f78SBastian Köcher .mnd_width = 8,
863aec89f78SBastian Köcher .hid_width = 5,
864aec89f78SBastian Köcher .freq_tbl = ftbl_pcie_0_aux_clk_src,
8650519d1d0SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){
866aec89f78SBastian Köcher .name = "pcie_0_aux_clk_src",
8670519d1d0SKonrad Dybcio .parent_data = &(const struct clk_parent_data){
8680519d1d0SKonrad Dybcio .fw_name = "xo",
8690519d1d0SKonrad Dybcio },
870aec89f78SBastian Köcher .num_parents = 1,
871aec89f78SBastian Köcher .ops = &clk_rcg2_ops,
872aec89f78SBastian Köcher },
873aec89f78SBastian Köcher };
874aec89f78SBastian Köcher
875aec89f78SBastian Köcher static struct freq_tbl ftbl_pcie_pipe_clk_src[] = {
876aec89f78SBastian Köcher F(125000000, P_XO, 1, 0, 0),
877aec89f78SBastian Köcher { }
878aec89f78SBastian Köcher };
879aec89f78SBastian Köcher
880aec89f78SBastian Köcher static struct clk_rcg2 pcie_0_pipe_clk_src = {
881aec89f78SBastian Köcher .cmd_rcgr = 0x1adc,
882aec89f78SBastian Köcher .hid_width = 5,
883aec89f78SBastian Köcher .freq_tbl = ftbl_pcie_pipe_clk_src,
8840519d1d0SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){
885aec89f78SBastian Köcher .name = "pcie_0_pipe_clk_src",
8860519d1d0SKonrad Dybcio .parent_data = &(const struct clk_parent_data){
8870519d1d0SKonrad Dybcio .fw_name = "xo",
8880519d1d0SKonrad Dybcio },
889aec89f78SBastian Köcher .num_parents = 1,
890aec89f78SBastian Köcher .ops = &clk_rcg2_ops,
891aec89f78SBastian Köcher },
892aec89f78SBastian Köcher };
893aec89f78SBastian Köcher
894aec89f78SBastian Köcher static struct freq_tbl ftbl_pcie_1_aux_clk_src[] = {
895aec89f78SBastian Köcher F(1011000, P_XO, 1, 1, 19),
896aec89f78SBastian Köcher { }
897aec89f78SBastian Köcher };
898aec89f78SBastian Köcher
899aec89f78SBastian Köcher static struct clk_rcg2 pcie_1_aux_clk_src = {
900aec89f78SBastian Köcher .cmd_rcgr = 0x1b80,
901aec89f78SBastian Köcher .mnd_width = 8,
902aec89f78SBastian Köcher .hid_width = 5,
903aec89f78SBastian Köcher .freq_tbl = ftbl_pcie_1_aux_clk_src,
9040519d1d0SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){
905aec89f78SBastian Köcher .name = "pcie_1_aux_clk_src",
9060519d1d0SKonrad Dybcio .parent_data = &(const struct clk_parent_data){
9070519d1d0SKonrad Dybcio .fw_name = "xo",
9080519d1d0SKonrad Dybcio },
909aec89f78SBastian Köcher .num_parents = 1,
910aec89f78SBastian Köcher .ops = &clk_rcg2_ops,
911aec89f78SBastian Köcher },
912aec89f78SBastian Köcher };
913aec89f78SBastian Köcher
914aec89f78SBastian Köcher static struct clk_rcg2 pcie_1_pipe_clk_src = {
915aec89f78SBastian Köcher .cmd_rcgr = 0x1b5c,
916aec89f78SBastian Köcher .hid_width = 5,
917aec89f78SBastian Köcher .freq_tbl = ftbl_pcie_pipe_clk_src,
9180519d1d0SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){
919aec89f78SBastian Köcher .name = "pcie_1_pipe_clk_src",
9200519d1d0SKonrad Dybcio .parent_data = &(const struct clk_parent_data){
9210519d1d0SKonrad Dybcio .fw_name = "xo",
9220519d1d0SKonrad Dybcio },
923aec89f78SBastian Köcher .num_parents = 1,
924aec89f78SBastian Köcher .ops = &clk_rcg2_ops,
925aec89f78SBastian Köcher },
926aec89f78SBastian Köcher };
927aec89f78SBastian Köcher
928aec89f78SBastian Köcher static struct freq_tbl ftbl_pdm2_clk_src[] = {
929aec89f78SBastian Köcher F(60000000, P_GPLL0, 10, 0, 0),
930aec89f78SBastian Köcher { }
931aec89f78SBastian Köcher };
932aec89f78SBastian Köcher
933aec89f78SBastian Köcher static struct clk_rcg2 pdm2_clk_src = {
934aec89f78SBastian Köcher .cmd_rcgr = 0x0cd0,
935aec89f78SBastian Köcher .hid_width = 5,
936aec89f78SBastian Köcher .parent_map = gcc_xo_gpll0_map,
937aec89f78SBastian Köcher .freq_tbl = ftbl_pdm2_clk_src,
9380519d1d0SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){
939aec89f78SBastian Köcher .name = "pdm2_clk_src",
9400519d1d0SKonrad Dybcio .parent_data = gcc_xo_gpll0,
941eb2d5058SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
942aec89f78SBastian Köcher .ops = &clk_rcg2_ops,
943aec89f78SBastian Köcher },
944aec89f78SBastian Köcher };
945aec89f78SBastian Köcher
946aec89f78SBastian Köcher static struct freq_tbl ftbl_sdcc1_apps_clk_src[] = {
947aec89f78SBastian Köcher F(144000, P_XO, 16, 3, 25),
948aec89f78SBastian Köcher F(400000, P_XO, 12, 1, 4),
949aec89f78SBastian Köcher F(20000000, P_GPLL0, 15, 1, 2),
950aec89f78SBastian Köcher F(25000000, P_GPLL0, 12, 1, 2),
951aec89f78SBastian Köcher F(50000000, P_GPLL0, 12, 0, 0),
952aec89f78SBastian Köcher F(100000000, P_GPLL0, 6, 0, 0),
953aec89f78SBastian Köcher F(192000000, P_GPLL4, 2, 0, 0),
954aec89f78SBastian Köcher F(384000000, P_GPLL4, 1, 0, 0),
955aec89f78SBastian Köcher { }
956aec89f78SBastian Köcher };
957aec89f78SBastian Köcher
958c09b8023SKonrad Dybcio static struct freq_tbl ftbl_sdcc1_apps_clk_src_8992[] = {
959c09b8023SKonrad Dybcio F(144000, P_XO, 16, 3, 25),
960c09b8023SKonrad Dybcio F(400000, P_XO, 12, 1, 4),
961c09b8023SKonrad Dybcio F(20000000, P_GPLL0, 15, 1, 2),
962c09b8023SKonrad Dybcio F(25000000, P_GPLL0, 12, 1, 2),
963c09b8023SKonrad Dybcio F(50000000, P_GPLL0, 12, 0, 0),
964c09b8023SKonrad Dybcio F(100000000, P_GPLL0, 6, 0, 0),
965c09b8023SKonrad Dybcio F(172000000, P_GPLL4, 2, 0, 0),
966c09b8023SKonrad Dybcio F(344000000, P_GPLL4, 1, 0, 0),
967c09b8023SKonrad Dybcio { }
968c09b8023SKonrad Dybcio };
969c09b8023SKonrad Dybcio
970aec89f78SBastian Köcher static struct clk_rcg2 sdcc1_apps_clk_src = {
971aec89f78SBastian Köcher .cmd_rcgr = 0x04d0,
972aec89f78SBastian Köcher .mnd_width = 8,
973aec89f78SBastian Köcher .hid_width = 5,
974aec89f78SBastian Köcher .parent_map = gcc_xo_gpll0_gpll4_map,
975aec89f78SBastian Köcher .freq_tbl = ftbl_sdcc1_apps_clk_src,
9760519d1d0SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){
977aec89f78SBastian Köcher .name = "sdcc1_apps_clk_src",
9780519d1d0SKonrad Dybcio .parent_data = gcc_xo_gpll0_gpll4,
979eb2d5058SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
9805f5001a9SRajendra Nayak .ops = &clk_rcg2_floor_ops,
981aec89f78SBastian Köcher },
982aec89f78SBastian Köcher };
983aec89f78SBastian Köcher
984aec89f78SBastian Köcher static struct freq_tbl ftbl_sdcc2_4_apps_clk_src[] = {
985aec89f78SBastian Köcher F(144000, P_XO, 16, 3, 25),
986aec89f78SBastian Köcher F(400000, P_XO, 12, 1, 4),
987aec89f78SBastian Köcher F(20000000, P_GPLL0, 15, 1, 2),
988aec89f78SBastian Köcher F(25000000, P_GPLL0, 12, 1, 2),
989aec89f78SBastian Köcher F(50000000, P_GPLL0, 12, 0, 0),
990aec89f78SBastian Köcher F(100000000, P_GPLL0, 6, 0, 0),
991aec89f78SBastian Köcher F(200000000, P_GPLL0, 3, 0, 0),
992aec89f78SBastian Köcher { }
993aec89f78SBastian Köcher };
994aec89f78SBastian Köcher
995aec89f78SBastian Köcher static struct clk_rcg2 sdcc2_apps_clk_src = {
996aec89f78SBastian Köcher .cmd_rcgr = 0x0510,
997aec89f78SBastian Köcher .mnd_width = 8,
998aec89f78SBastian Köcher .hid_width = 5,
999aec89f78SBastian Köcher .parent_map = gcc_xo_gpll0_map,
1000aec89f78SBastian Köcher .freq_tbl = ftbl_sdcc2_4_apps_clk_src,
10010519d1d0SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){
1002aec89f78SBastian Köcher .name = "sdcc2_apps_clk_src",
10030519d1d0SKonrad Dybcio .parent_data = gcc_xo_gpll0,
1004eb2d5058SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
10055f5001a9SRajendra Nayak .ops = &clk_rcg2_floor_ops,
1006aec89f78SBastian Köcher },
1007aec89f78SBastian Köcher };
1008aec89f78SBastian Köcher
1009aec89f78SBastian Köcher static struct clk_rcg2 sdcc3_apps_clk_src = {
1010aec89f78SBastian Köcher .cmd_rcgr = 0x0550,
1011aec89f78SBastian Köcher .mnd_width = 8,
1012aec89f78SBastian Köcher .hid_width = 5,
1013aec89f78SBastian Köcher .parent_map = gcc_xo_gpll0_map,
1014aec89f78SBastian Köcher .freq_tbl = ftbl_sdcc2_4_apps_clk_src,
10150519d1d0SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){
1016aec89f78SBastian Köcher .name = "sdcc3_apps_clk_src",
10170519d1d0SKonrad Dybcio .parent_data = gcc_xo_gpll0,
1018eb2d5058SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
10195f5001a9SRajendra Nayak .ops = &clk_rcg2_floor_ops,
1020aec89f78SBastian Köcher },
1021aec89f78SBastian Köcher };
1022aec89f78SBastian Köcher
1023aec89f78SBastian Köcher static struct clk_rcg2 sdcc4_apps_clk_src = {
1024aec89f78SBastian Köcher .cmd_rcgr = 0x0590,
1025aec89f78SBastian Köcher .mnd_width = 8,
1026aec89f78SBastian Köcher .hid_width = 5,
1027aec89f78SBastian Köcher .parent_map = gcc_xo_gpll0_map,
1028aec89f78SBastian Köcher .freq_tbl = ftbl_sdcc2_4_apps_clk_src,
10290519d1d0SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){
1030aec89f78SBastian Köcher .name = "sdcc4_apps_clk_src",
10310519d1d0SKonrad Dybcio .parent_data = gcc_xo_gpll0,
1032eb2d5058SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
10335f5001a9SRajendra Nayak .ops = &clk_rcg2_floor_ops,
1034aec89f78SBastian Köcher },
1035aec89f78SBastian Köcher };
1036aec89f78SBastian Köcher
1037aec89f78SBastian Köcher static struct freq_tbl ftbl_tsif_ref_clk_src[] = {
1038aec89f78SBastian Köcher F(105500, P_XO, 1, 1, 182),
1039aec89f78SBastian Köcher { }
1040aec89f78SBastian Köcher };
1041aec89f78SBastian Köcher
1042aec89f78SBastian Köcher static struct clk_rcg2 tsif_ref_clk_src = {
1043aec89f78SBastian Köcher .cmd_rcgr = 0x0d90,
1044aec89f78SBastian Köcher .mnd_width = 8,
1045aec89f78SBastian Köcher .hid_width = 5,
1046aec89f78SBastian Köcher .freq_tbl = ftbl_tsif_ref_clk_src,
10470519d1d0SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){
1048aec89f78SBastian Köcher .name = "tsif_ref_clk_src",
10490519d1d0SKonrad Dybcio .parent_data = &(const struct clk_parent_data){
10500519d1d0SKonrad Dybcio .fw_name = "xo",
10510519d1d0SKonrad Dybcio },
1052aec89f78SBastian Köcher .num_parents = 1,
1053aec89f78SBastian Köcher .ops = &clk_rcg2_ops,
1054aec89f78SBastian Köcher },
1055aec89f78SBastian Köcher };
1056aec89f78SBastian Köcher
1057aec89f78SBastian Köcher static struct freq_tbl ftbl_usb30_mock_utmi_clk_src[] = {
1058aec89f78SBastian Köcher F(19200000, P_XO, 1, 0, 0),
1059aec89f78SBastian Köcher F(60000000, P_GPLL0, 10, 0, 0),
1060aec89f78SBastian Köcher { }
1061aec89f78SBastian Köcher };
1062aec89f78SBastian Köcher
1063aec89f78SBastian Köcher static struct clk_rcg2 usb30_mock_utmi_clk_src = {
1064aec89f78SBastian Köcher .cmd_rcgr = 0x03e8,
1065aec89f78SBastian Köcher .hid_width = 5,
1066aec89f78SBastian Köcher .parent_map = gcc_xo_gpll0_map,
1067aec89f78SBastian Köcher .freq_tbl = ftbl_usb30_mock_utmi_clk_src,
10680519d1d0SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){
1069aec89f78SBastian Köcher .name = "usb30_mock_utmi_clk_src",
10700519d1d0SKonrad Dybcio .parent_data = gcc_xo_gpll0,
1071eb2d5058SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
1072aec89f78SBastian Köcher .ops = &clk_rcg2_ops,
1073aec89f78SBastian Köcher },
1074aec89f78SBastian Köcher };
1075aec89f78SBastian Köcher
1076aec89f78SBastian Köcher static struct freq_tbl ftbl_usb3_phy_aux_clk_src[] = {
1077aec89f78SBastian Köcher F(1200000, P_XO, 16, 0, 0),
1078aec89f78SBastian Köcher { }
1079aec89f78SBastian Köcher };
1080aec89f78SBastian Köcher
1081aec89f78SBastian Köcher static struct clk_rcg2 usb3_phy_aux_clk_src = {
1082aec89f78SBastian Köcher .cmd_rcgr = 0x1414,
1083aec89f78SBastian Köcher .hid_width = 5,
1084aec89f78SBastian Köcher .freq_tbl = ftbl_usb3_phy_aux_clk_src,
10850519d1d0SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){
1086aec89f78SBastian Köcher .name = "usb3_phy_aux_clk_src",
10870519d1d0SKonrad Dybcio .parent_data = &(const struct clk_parent_data){
10880519d1d0SKonrad Dybcio .fw_name = "xo",
10890519d1d0SKonrad Dybcio },
1090aec89f78SBastian Köcher .num_parents = 1,
1091aec89f78SBastian Köcher .ops = &clk_rcg2_ops,
1092aec89f78SBastian Köcher },
1093aec89f78SBastian Köcher };
1094aec89f78SBastian Köcher
1095aec89f78SBastian Köcher static struct freq_tbl ftbl_usb_hs_system_clk_src[] = {
1096aec89f78SBastian Köcher F(75000000, P_GPLL0, 8, 0, 0),
1097aec89f78SBastian Köcher { }
1098aec89f78SBastian Köcher };
1099aec89f78SBastian Köcher
1100aec89f78SBastian Köcher static struct clk_rcg2 usb_hs_system_clk_src = {
1101aec89f78SBastian Köcher .cmd_rcgr = 0x0490,
1102aec89f78SBastian Köcher .hid_width = 5,
1103aec89f78SBastian Köcher .parent_map = gcc_xo_gpll0_map,
1104aec89f78SBastian Köcher .freq_tbl = ftbl_usb_hs_system_clk_src,
11050519d1d0SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){
1106aec89f78SBastian Köcher .name = "usb_hs_system_clk_src",
11070519d1d0SKonrad Dybcio .parent_data = gcc_xo_gpll0,
1108eb2d5058SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
1109aec89f78SBastian Köcher .ops = &clk_rcg2_ops,
1110aec89f78SBastian Köcher },
1111aec89f78SBastian Köcher };
1112aec89f78SBastian Köcher
1113aec89f78SBastian Köcher static struct clk_branch gcc_blsp1_ahb_clk = {
1114aec89f78SBastian Köcher .halt_reg = 0x05c4,
1115aec89f78SBastian Köcher .halt_check = BRANCH_HALT_VOTED,
1116aec89f78SBastian Köcher .clkr = {
1117aec89f78SBastian Köcher .enable_reg = 0x1484,
1118aec89f78SBastian Köcher .enable_mask = BIT(17),
11190519d1d0SKonrad Dybcio .hw.init = &(struct clk_init_data){
1120aec89f78SBastian Köcher .name = "gcc_blsp1_ahb_clk",
1121aec89f78SBastian Köcher .ops = &clk_branch2_ops,
1122aec89f78SBastian Köcher },
1123aec89f78SBastian Köcher },
1124aec89f78SBastian Köcher };
1125aec89f78SBastian Köcher
1126aec89f78SBastian Köcher static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
1127aec89f78SBastian Köcher .halt_reg = 0x0648,
1128aec89f78SBastian Köcher .clkr = {
1129aec89f78SBastian Köcher .enable_reg = 0x0648,
1130aec89f78SBastian Köcher .enable_mask = BIT(0),
11310519d1d0SKonrad Dybcio .hw.init = &(struct clk_init_data){
1132aec89f78SBastian Köcher .name = "gcc_blsp1_qup1_i2c_apps_clk",
11330519d1d0SKonrad Dybcio .parent_hws = (const struct clk_hw *[]){ &blsp1_qup1_i2c_apps_clk_src.clkr.hw },
1134aec89f78SBastian Köcher .num_parents = 1,
1135aec89f78SBastian Köcher .flags = CLK_SET_RATE_PARENT,
1136aec89f78SBastian Köcher .ops = &clk_branch2_ops,
1137aec89f78SBastian Köcher },
1138aec89f78SBastian Köcher },
1139aec89f78SBastian Köcher };
1140aec89f78SBastian Köcher
1141aec89f78SBastian Köcher static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
1142aec89f78SBastian Köcher .halt_reg = 0x0644,
1143aec89f78SBastian Köcher .clkr = {
1144aec89f78SBastian Köcher .enable_reg = 0x0644,
1145aec89f78SBastian Köcher .enable_mask = BIT(0),
11460519d1d0SKonrad Dybcio .hw.init = &(struct clk_init_data){
1147aec89f78SBastian Köcher .name = "gcc_blsp1_qup1_spi_apps_clk",
11480519d1d0SKonrad Dybcio .parent_hws = (const struct clk_hw *[]){ &blsp1_qup1_spi_apps_clk_src.clkr.hw },
1149aec89f78SBastian Köcher .num_parents = 1,
1150aec89f78SBastian Köcher .flags = CLK_SET_RATE_PARENT,
1151aec89f78SBastian Köcher .ops = &clk_branch2_ops,
1152aec89f78SBastian Köcher },
1153aec89f78SBastian Köcher },
1154aec89f78SBastian Köcher };
1155aec89f78SBastian Köcher
1156aec89f78SBastian Köcher static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
1157aec89f78SBastian Köcher .halt_reg = 0x06c8,
1158aec89f78SBastian Köcher .clkr = {
1159aec89f78SBastian Köcher .enable_reg = 0x06c8,
1160aec89f78SBastian Köcher .enable_mask = BIT(0),
11610519d1d0SKonrad Dybcio .hw.init = &(struct clk_init_data){
1162aec89f78SBastian Köcher .name = "gcc_blsp1_qup2_i2c_apps_clk",
11630519d1d0SKonrad Dybcio .parent_hws = (const struct clk_hw *[]){ &blsp1_qup2_i2c_apps_clk_src.clkr.hw },
1164aec89f78SBastian Köcher .num_parents = 1,
1165aec89f78SBastian Köcher .flags = CLK_SET_RATE_PARENT,
1166aec89f78SBastian Köcher .ops = &clk_branch2_ops,
1167aec89f78SBastian Köcher },
1168aec89f78SBastian Köcher },
1169aec89f78SBastian Köcher };
1170aec89f78SBastian Köcher
1171aec89f78SBastian Köcher static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
1172aec89f78SBastian Köcher .halt_reg = 0x06c4,
1173aec89f78SBastian Köcher .clkr = {
1174aec89f78SBastian Köcher .enable_reg = 0x06c4,
1175aec89f78SBastian Köcher .enable_mask = BIT(0),
11760519d1d0SKonrad Dybcio .hw.init = &(struct clk_init_data){
1177aec89f78SBastian Köcher .name = "gcc_blsp1_qup2_spi_apps_clk",
11780519d1d0SKonrad Dybcio .parent_hws = (const struct clk_hw *[]){ &blsp1_qup2_spi_apps_clk_src.clkr.hw },
1179aec89f78SBastian Köcher .num_parents = 1,
1180aec89f78SBastian Köcher .flags = CLK_SET_RATE_PARENT,
1181aec89f78SBastian Köcher .ops = &clk_branch2_ops,
1182aec89f78SBastian Köcher },
1183aec89f78SBastian Köcher },
1184aec89f78SBastian Köcher };
1185aec89f78SBastian Köcher
1186aec89f78SBastian Köcher static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
1187aec89f78SBastian Köcher .halt_reg = 0x0748,
1188aec89f78SBastian Köcher .clkr = {
1189aec89f78SBastian Köcher .enable_reg = 0x0748,
1190aec89f78SBastian Köcher .enable_mask = BIT(0),
11910519d1d0SKonrad Dybcio .hw.init = &(struct clk_init_data){
1192aec89f78SBastian Köcher .name = "gcc_blsp1_qup3_i2c_apps_clk",
11930519d1d0SKonrad Dybcio .parent_hws = (const struct clk_hw *[]){ &blsp1_qup3_i2c_apps_clk_src.clkr.hw },
1194aec89f78SBastian Köcher .num_parents = 1,
1195aec89f78SBastian Köcher .flags = CLK_SET_RATE_PARENT,
1196aec89f78SBastian Köcher .ops = &clk_branch2_ops,
1197aec89f78SBastian Köcher },
1198aec89f78SBastian Köcher },
1199aec89f78SBastian Köcher };
1200aec89f78SBastian Köcher
1201aec89f78SBastian Köcher static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
1202aec89f78SBastian Köcher .halt_reg = 0x0744,
1203aec89f78SBastian Köcher .clkr = {
1204aec89f78SBastian Köcher .enable_reg = 0x0744,
1205aec89f78SBastian Köcher .enable_mask = BIT(0),
12060519d1d0SKonrad Dybcio .hw.init = &(struct clk_init_data){
1207aec89f78SBastian Köcher .name = "gcc_blsp1_qup3_spi_apps_clk",
12080519d1d0SKonrad Dybcio .parent_hws = (const struct clk_hw *[]){ &blsp1_qup3_spi_apps_clk_src.clkr.hw },
1209aec89f78SBastian Köcher .num_parents = 1,
1210aec89f78SBastian Köcher .flags = CLK_SET_RATE_PARENT,
1211aec89f78SBastian Köcher .ops = &clk_branch2_ops,
1212aec89f78SBastian Köcher },
1213aec89f78SBastian Köcher },
1214aec89f78SBastian Köcher };
1215aec89f78SBastian Köcher
1216aec89f78SBastian Köcher static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
1217aec89f78SBastian Köcher .halt_reg = 0x07c8,
1218aec89f78SBastian Köcher .clkr = {
1219aec89f78SBastian Köcher .enable_reg = 0x07c8,
1220aec89f78SBastian Köcher .enable_mask = BIT(0),
12210519d1d0SKonrad Dybcio .hw.init = &(struct clk_init_data){
1222aec89f78SBastian Köcher .name = "gcc_blsp1_qup4_i2c_apps_clk",
12230519d1d0SKonrad Dybcio .parent_hws = (const struct clk_hw *[]){ &blsp1_qup4_i2c_apps_clk_src.clkr.hw },
1224aec89f78SBastian Köcher .num_parents = 1,
1225aec89f78SBastian Köcher .flags = CLK_SET_RATE_PARENT,
1226aec89f78SBastian Köcher .ops = &clk_branch2_ops,
1227aec89f78SBastian Köcher },
1228aec89f78SBastian Köcher },
1229aec89f78SBastian Köcher };
1230aec89f78SBastian Köcher
1231aec89f78SBastian Köcher static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
1232aec89f78SBastian Köcher .halt_reg = 0x07c4,
1233aec89f78SBastian Köcher .clkr = {
1234aec89f78SBastian Köcher .enable_reg = 0x07c4,
1235aec89f78SBastian Köcher .enable_mask = BIT(0),
12360519d1d0SKonrad Dybcio .hw.init = &(struct clk_init_data){
1237aec89f78SBastian Köcher .name = "gcc_blsp1_qup4_spi_apps_clk",
12380519d1d0SKonrad Dybcio .parent_hws = (const struct clk_hw *[]){ &blsp1_qup4_spi_apps_clk_src.clkr.hw },
1239aec89f78SBastian Köcher .num_parents = 1,
1240aec89f78SBastian Köcher .flags = CLK_SET_RATE_PARENT,
1241aec89f78SBastian Köcher .ops = &clk_branch2_ops,
1242aec89f78SBastian Köcher },
1243aec89f78SBastian Köcher },
1244aec89f78SBastian Köcher };
1245aec89f78SBastian Köcher
1246aec89f78SBastian Köcher static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
1247aec89f78SBastian Köcher .halt_reg = 0x0848,
1248aec89f78SBastian Köcher .clkr = {
1249aec89f78SBastian Köcher .enable_reg = 0x0848,
1250aec89f78SBastian Köcher .enable_mask = BIT(0),
12510519d1d0SKonrad Dybcio .hw.init = &(struct clk_init_data){
1252aec89f78SBastian Köcher .name = "gcc_blsp1_qup5_i2c_apps_clk",
12530519d1d0SKonrad Dybcio .parent_hws = (const struct clk_hw *[]){ &blsp1_qup5_i2c_apps_clk_src.clkr.hw },
1254aec89f78SBastian Köcher .num_parents = 1,
1255aec89f78SBastian Köcher .flags = CLK_SET_RATE_PARENT,
1256aec89f78SBastian Köcher .ops = &clk_branch2_ops,
1257aec89f78SBastian Köcher },
1258aec89f78SBastian Köcher },
1259aec89f78SBastian Köcher };
1260aec89f78SBastian Köcher
1261aec89f78SBastian Köcher static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
1262aec89f78SBastian Köcher .halt_reg = 0x0844,
1263aec89f78SBastian Köcher .clkr = {
1264aec89f78SBastian Köcher .enable_reg = 0x0844,
1265aec89f78SBastian Köcher .enable_mask = BIT(0),
12660519d1d0SKonrad Dybcio .hw.init = &(struct clk_init_data){
1267aec89f78SBastian Köcher .name = "gcc_blsp1_qup5_spi_apps_clk",
12680519d1d0SKonrad Dybcio .parent_hws = (const struct clk_hw *[]){ &blsp1_qup5_spi_apps_clk_src.clkr.hw },
1269aec89f78SBastian Köcher .num_parents = 1,
1270aec89f78SBastian Köcher .flags = CLK_SET_RATE_PARENT,
1271aec89f78SBastian Köcher .ops = &clk_branch2_ops,
1272aec89f78SBastian Köcher },
1273aec89f78SBastian Köcher },
1274aec89f78SBastian Köcher };
1275aec89f78SBastian Köcher
1276aec89f78SBastian Köcher static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
1277aec89f78SBastian Köcher .halt_reg = 0x08c8,
1278aec89f78SBastian Köcher .clkr = {
1279aec89f78SBastian Köcher .enable_reg = 0x08c8,
1280aec89f78SBastian Köcher .enable_mask = BIT(0),
12810519d1d0SKonrad Dybcio .hw.init = &(struct clk_init_data){
1282aec89f78SBastian Köcher .name = "gcc_blsp1_qup6_i2c_apps_clk",
12830519d1d0SKonrad Dybcio .parent_hws = (const struct clk_hw *[]){ &blsp1_qup6_i2c_apps_clk_src.clkr.hw },
1284aec89f78SBastian Köcher .num_parents = 1,
1285aec89f78SBastian Köcher .flags = CLK_SET_RATE_PARENT,
1286aec89f78SBastian Köcher .ops = &clk_branch2_ops,
1287aec89f78SBastian Köcher },
1288aec89f78SBastian Köcher },
1289aec89f78SBastian Köcher };
1290aec89f78SBastian Köcher
1291aec89f78SBastian Köcher static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
1292aec89f78SBastian Köcher .halt_reg = 0x08c4,
1293aec89f78SBastian Köcher .clkr = {
1294aec89f78SBastian Köcher .enable_reg = 0x08c4,
1295aec89f78SBastian Köcher .enable_mask = BIT(0),
12960519d1d0SKonrad Dybcio .hw.init = &(struct clk_init_data){
1297aec89f78SBastian Köcher .name = "gcc_blsp1_qup6_spi_apps_clk",
12980519d1d0SKonrad Dybcio .parent_hws = (const struct clk_hw *[]){ &blsp1_qup6_spi_apps_clk_src.clkr.hw },
1299aec89f78SBastian Köcher .num_parents = 1,
1300aec89f78SBastian Köcher .flags = CLK_SET_RATE_PARENT,
1301aec89f78SBastian Köcher .ops = &clk_branch2_ops,
1302aec89f78SBastian Köcher },
1303aec89f78SBastian Köcher },
1304aec89f78SBastian Köcher };
1305aec89f78SBastian Köcher
1306aec89f78SBastian Köcher static struct clk_branch gcc_blsp1_uart1_apps_clk = {
1307aec89f78SBastian Köcher .halt_reg = 0x0684,
1308aec89f78SBastian Köcher .clkr = {
1309aec89f78SBastian Köcher .enable_reg = 0x0684,
1310aec89f78SBastian Köcher .enable_mask = BIT(0),
13110519d1d0SKonrad Dybcio .hw.init = &(struct clk_init_data){
1312aec89f78SBastian Köcher .name = "gcc_blsp1_uart1_apps_clk",
13130519d1d0SKonrad Dybcio .parent_hws = (const struct clk_hw *[]){ &blsp1_uart1_apps_clk_src.clkr.hw },
1314aec89f78SBastian Köcher .num_parents = 1,
1315aec89f78SBastian Köcher .flags = CLK_SET_RATE_PARENT,
1316aec89f78SBastian Köcher .ops = &clk_branch2_ops,
1317aec89f78SBastian Köcher },
1318aec89f78SBastian Köcher },
1319aec89f78SBastian Köcher };
1320aec89f78SBastian Köcher
1321aec89f78SBastian Köcher static struct clk_branch gcc_blsp1_uart2_apps_clk = {
1322aec89f78SBastian Köcher .halt_reg = 0x0704,
1323aec89f78SBastian Köcher .clkr = {
1324aec89f78SBastian Köcher .enable_reg = 0x0704,
1325aec89f78SBastian Köcher .enable_mask = BIT(0),
13260519d1d0SKonrad Dybcio .hw.init = &(struct clk_init_data){
1327aec89f78SBastian Köcher .name = "gcc_blsp1_uart2_apps_clk",
13280519d1d0SKonrad Dybcio .parent_hws = (const struct clk_hw *[]){ &blsp1_uart2_apps_clk_src.clkr.hw },
1329aec89f78SBastian Köcher .num_parents = 1,
1330aec89f78SBastian Köcher .flags = CLK_SET_RATE_PARENT,
1331aec89f78SBastian Köcher .ops = &clk_branch2_ops,
1332aec89f78SBastian Köcher },
1333aec89f78SBastian Köcher },
1334aec89f78SBastian Köcher };
1335aec89f78SBastian Köcher
1336aec89f78SBastian Köcher static struct clk_branch gcc_blsp1_uart3_apps_clk = {
1337aec89f78SBastian Köcher .halt_reg = 0x0784,
1338aec89f78SBastian Köcher .clkr = {
1339aec89f78SBastian Köcher .enable_reg = 0x0784,
1340aec89f78SBastian Köcher .enable_mask = BIT(0),
13410519d1d0SKonrad Dybcio .hw.init = &(struct clk_init_data){
1342aec89f78SBastian Köcher .name = "gcc_blsp1_uart3_apps_clk",
13430519d1d0SKonrad Dybcio .parent_hws = (const struct clk_hw *[]){ &blsp1_uart3_apps_clk_src.clkr.hw },
1344aec89f78SBastian Köcher .num_parents = 1,
1345aec89f78SBastian Köcher .flags = CLK_SET_RATE_PARENT,
1346aec89f78SBastian Köcher .ops = &clk_branch2_ops,
1347aec89f78SBastian Köcher },
1348aec89f78SBastian Köcher },
1349aec89f78SBastian Köcher };
1350aec89f78SBastian Köcher
1351aec89f78SBastian Köcher static struct clk_branch gcc_blsp1_uart4_apps_clk = {
1352aec89f78SBastian Köcher .halt_reg = 0x0804,
1353aec89f78SBastian Köcher .clkr = {
1354aec89f78SBastian Köcher .enable_reg = 0x0804,
1355aec89f78SBastian Köcher .enable_mask = BIT(0),
13560519d1d0SKonrad Dybcio .hw.init = &(struct clk_init_data){
1357aec89f78SBastian Köcher .name = "gcc_blsp1_uart4_apps_clk",
13580519d1d0SKonrad Dybcio .parent_hws = (const struct clk_hw *[]){ &blsp1_uart4_apps_clk_src.clkr.hw },
1359aec89f78SBastian Köcher .num_parents = 1,
1360aec89f78SBastian Köcher .flags = CLK_SET_RATE_PARENT,
1361aec89f78SBastian Köcher .ops = &clk_branch2_ops,
1362aec89f78SBastian Köcher },
1363aec89f78SBastian Köcher },
1364aec89f78SBastian Köcher };
1365aec89f78SBastian Köcher
1366aec89f78SBastian Köcher static struct clk_branch gcc_blsp1_uart5_apps_clk = {
1367aec89f78SBastian Köcher .halt_reg = 0x0884,
1368aec89f78SBastian Köcher .clkr = {
1369aec89f78SBastian Köcher .enable_reg = 0x0884,
1370aec89f78SBastian Köcher .enable_mask = BIT(0),
13710519d1d0SKonrad Dybcio .hw.init = &(struct clk_init_data){
1372aec89f78SBastian Köcher .name = "gcc_blsp1_uart5_apps_clk",
13730519d1d0SKonrad Dybcio .parent_hws = (const struct clk_hw *[]){ &blsp1_uart5_apps_clk_src.clkr.hw },
1374aec89f78SBastian Köcher .num_parents = 1,
1375aec89f78SBastian Köcher .flags = CLK_SET_RATE_PARENT,
1376aec89f78SBastian Köcher .ops = &clk_branch2_ops,
1377aec89f78SBastian Köcher },
1378aec89f78SBastian Köcher },
1379aec89f78SBastian Köcher };
1380aec89f78SBastian Köcher
1381aec89f78SBastian Köcher static struct clk_branch gcc_blsp1_uart6_apps_clk = {
1382aec89f78SBastian Köcher .halt_reg = 0x0904,
1383aec89f78SBastian Köcher .clkr = {
1384aec89f78SBastian Köcher .enable_reg = 0x0904,
1385aec89f78SBastian Köcher .enable_mask = BIT(0),
13860519d1d0SKonrad Dybcio .hw.init = &(struct clk_init_data){
1387aec89f78SBastian Köcher .name = "gcc_blsp1_uart6_apps_clk",
13880519d1d0SKonrad Dybcio .parent_hws = (const struct clk_hw *[]){ &blsp1_uart6_apps_clk_src.clkr.hw },
1389aec89f78SBastian Köcher .num_parents = 1,
1390aec89f78SBastian Köcher .flags = CLK_SET_RATE_PARENT,
1391aec89f78SBastian Köcher .ops = &clk_branch2_ops,
1392aec89f78SBastian Köcher },
1393aec89f78SBastian Köcher },
1394aec89f78SBastian Köcher };
1395aec89f78SBastian Köcher
1396aec89f78SBastian Köcher static struct clk_branch gcc_blsp2_ahb_clk = {
1397aec89f78SBastian Köcher .halt_reg = 0x0944,
1398aec89f78SBastian Köcher .halt_check = BRANCH_HALT_VOTED,
1399aec89f78SBastian Köcher .clkr = {
1400aec89f78SBastian Köcher .enable_reg = 0x1484,
1401aec89f78SBastian Köcher .enable_mask = BIT(15),
14020519d1d0SKonrad Dybcio .hw.init = &(struct clk_init_data){
1403aec89f78SBastian Köcher .name = "gcc_blsp2_ahb_clk",
1404aec89f78SBastian Köcher .ops = &clk_branch2_ops,
1405aec89f78SBastian Köcher },
1406aec89f78SBastian Köcher },
1407aec89f78SBastian Köcher };
1408aec89f78SBastian Köcher
1409aec89f78SBastian Köcher static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
1410aec89f78SBastian Köcher .halt_reg = 0x0988,
1411aec89f78SBastian Köcher .clkr = {
1412aec89f78SBastian Köcher .enable_reg = 0x0988,
1413aec89f78SBastian Köcher .enable_mask = BIT(0),
14140519d1d0SKonrad Dybcio .hw.init = &(struct clk_init_data){
1415aec89f78SBastian Köcher .name = "gcc_blsp2_qup1_i2c_apps_clk",
14160519d1d0SKonrad Dybcio .parent_hws = (const struct clk_hw *[]){ &blsp2_qup1_i2c_apps_clk_src.clkr.hw },
1417aec89f78SBastian Köcher .num_parents = 1,
1418aec89f78SBastian Köcher .flags = CLK_SET_RATE_PARENT,
1419aec89f78SBastian Köcher .ops = &clk_branch2_ops,
1420aec89f78SBastian Köcher },
1421aec89f78SBastian Köcher },
1422aec89f78SBastian Köcher };
1423aec89f78SBastian Köcher
1424aec89f78SBastian Köcher static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
1425aec89f78SBastian Köcher .halt_reg = 0x0984,
1426aec89f78SBastian Köcher .clkr = {
1427aec89f78SBastian Köcher .enable_reg = 0x0984,
1428aec89f78SBastian Köcher .enable_mask = BIT(0),
14290519d1d0SKonrad Dybcio .hw.init = &(struct clk_init_data){
1430aec89f78SBastian Köcher .name = "gcc_blsp2_qup1_spi_apps_clk",
14310519d1d0SKonrad Dybcio .parent_hws = (const struct clk_hw *[]){ &blsp2_qup1_spi_apps_clk_src.clkr.hw },
1432aec89f78SBastian Köcher .num_parents = 1,
1433aec89f78SBastian Köcher .flags = CLK_SET_RATE_PARENT,
1434aec89f78SBastian Köcher .ops = &clk_branch2_ops,
1435aec89f78SBastian Köcher },
1436aec89f78SBastian Köcher },
1437aec89f78SBastian Köcher };
1438aec89f78SBastian Köcher
1439aec89f78SBastian Köcher static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
1440aec89f78SBastian Köcher .halt_reg = 0x0a08,
1441aec89f78SBastian Köcher .clkr = {
1442aec89f78SBastian Köcher .enable_reg = 0x0a08,
1443aec89f78SBastian Köcher .enable_mask = BIT(0),
14440519d1d0SKonrad Dybcio .hw.init = &(struct clk_init_data){
1445aec89f78SBastian Köcher .name = "gcc_blsp2_qup2_i2c_apps_clk",
14460519d1d0SKonrad Dybcio .parent_hws = (const struct clk_hw *[]){ &blsp2_qup2_i2c_apps_clk_src.clkr.hw },
1447aec89f78SBastian Köcher .num_parents = 1,
1448aec89f78SBastian Köcher .flags = CLK_SET_RATE_PARENT,
1449aec89f78SBastian Köcher .ops = &clk_branch2_ops,
1450aec89f78SBastian Köcher },
1451aec89f78SBastian Köcher },
1452aec89f78SBastian Köcher };
1453aec89f78SBastian Köcher
1454aec89f78SBastian Köcher static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
1455aec89f78SBastian Köcher .halt_reg = 0x0a04,
1456aec89f78SBastian Köcher .clkr = {
1457aec89f78SBastian Köcher .enable_reg = 0x0a04,
1458aec89f78SBastian Köcher .enable_mask = BIT(0),
14590519d1d0SKonrad Dybcio .hw.init = &(struct clk_init_data){
1460aec89f78SBastian Köcher .name = "gcc_blsp2_qup2_spi_apps_clk",
14610519d1d0SKonrad Dybcio .parent_hws = (const struct clk_hw *[]){ &blsp2_qup2_spi_apps_clk_src.clkr.hw },
1462aec89f78SBastian Köcher .num_parents = 1,
1463aec89f78SBastian Köcher .flags = CLK_SET_RATE_PARENT,
1464aec89f78SBastian Köcher .ops = &clk_branch2_ops,
1465aec89f78SBastian Köcher },
1466aec89f78SBastian Köcher },
1467aec89f78SBastian Köcher };
1468aec89f78SBastian Köcher
1469aec89f78SBastian Köcher static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
1470aec89f78SBastian Köcher .halt_reg = 0x0a88,
1471aec89f78SBastian Köcher .clkr = {
1472aec89f78SBastian Köcher .enable_reg = 0x0a88,
1473aec89f78SBastian Köcher .enable_mask = BIT(0),
14740519d1d0SKonrad Dybcio .hw.init = &(struct clk_init_data){
1475aec89f78SBastian Köcher .name = "gcc_blsp2_qup3_i2c_apps_clk",
14760519d1d0SKonrad Dybcio .parent_hws = (const struct clk_hw *[]){ &blsp2_qup3_i2c_apps_clk_src.clkr.hw },
1477aec89f78SBastian Köcher .num_parents = 1,
1478aec89f78SBastian Köcher .flags = CLK_SET_RATE_PARENT,
1479aec89f78SBastian Köcher .ops = &clk_branch2_ops,
1480aec89f78SBastian Köcher },
1481aec89f78SBastian Köcher },
1482aec89f78SBastian Köcher };
1483aec89f78SBastian Köcher
1484aec89f78SBastian Köcher static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
1485aec89f78SBastian Köcher .halt_reg = 0x0a84,
1486aec89f78SBastian Köcher .clkr = {
1487aec89f78SBastian Köcher .enable_reg = 0x0a84,
1488aec89f78SBastian Köcher .enable_mask = BIT(0),
14890519d1d0SKonrad Dybcio .hw.init = &(struct clk_init_data){
1490aec89f78SBastian Köcher .name = "gcc_blsp2_qup3_spi_apps_clk",
14910519d1d0SKonrad Dybcio .parent_hws = (const struct clk_hw *[]){ &blsp2_qup3_spi_apps_clk_src.clkr.hw },
1492aec89f78SBastian Köcher .num_parents = 1,
1493aec89f78SBastian Köcher .flags = CLK_SET_RATE_PARENT,
1494aec89f78SBastian Köcher .ops = &clk_branch2_ops,
1495aec89f78SBastian Köcher },
1496aec89f78SBastian Köcher },
1497aec89f78SBastian Köcher };
1498aec89f78SBastian Köcher
1499aec89f78SBastian Köcher static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {
1500aec89f78SBastian Köcher .halt_reg = 0x0b08,
1501aec89f78SBastian Köcher .clkr = {
1502aec89f78SBastian Köcher .enable_reg = 0x0b08,
1503aec89f78SBastian Köcher .enable_mask = BIT(0),
15040519d1d0SKonrad Dybcio .hw.init = &(struct clk_init_data){
1505aec89f78SBastian Köcher .name = "gcc_blsp2_qup4_i2c_apps_clk",
15060519d1d0SKonrad Dybcio .parent_hws = (const struct clk_hw *[]){ &blsp2_qup4_i2c_apps_clk_src.clkr.hw },
1507aec89f78SBastian Köcher .num_parents = 1,
1508aec89f78SBastian Köcher .flags = CLK_SET_RATE_PARENT,
1509aec89f78SBastian Köcher .ops = &clk_branch2_ops,
1510aec89f78SBastian Köcher },
1511aec89f78SBastian Köcher },
1512aec89f78SBastian Köcher };
1513aec89f78SBastian Köcher
1514aec89f78SBastian Köcher static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {
1515aec89f78SBastian Köcher .halt_reg = 0x0b04,
1516aec89f78SBastian Köcher .clkr = {
1517aec89f78SBastian Köcher .enable_reg = 0x0b04,
1518aec89f78SBastian Köcher .enable_mask = BIT(0),
15190519d1d0SKonrad Dybcio .hw.init = &(struct clk_init_data){
1520aec89f78SBastian Köcher .name = "gcc_blsp2_qup4_spi_apps_clk",
15210519d1d0SKonrad Dybcio .parent_hws = (const struct clk_hw *[]){ &blsp2_qup4_spi_apps_clk_src.clkr.hw },
1522aec89f78SBastian Köcher .num_parents = 1,
1523aec89f78SBastian Köcher .flags = CLK_SET_RATE_PARENT,
1524aec89f78SBastian Köcher .ops = &clk_branch2_ops,
1525aec89f78SBastian Köcher },
1526aec89f78SBastian Köcher },
1527aec89f78SBastian Köcher };
1528aec89f78SBastian Köcher
1529aec89f78SBastian Köcher static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = {
1530aec89f78SBastian Köcher .halt_reg = 0x0b88,
1531aec89f78SBastian Köcher .clkr = {
1532aec89f78SBastian Köcher .enable_reg = 0x0b88,
1533aec89f78SBastian Köcher .enable_mask = BIT(0),
15340519d1d0SKonrad Dybcio .hw.init = &(struct clk_init_data){
1535aec89f78SBastian Köcher .name = "gcc_blsp2_qup5_i2c_apps_clk",
15360519d1d0SKonrad Dybcio .parent_hws = (const struct clk_hw *[]){ &blsp2_qup5_i2c_apps_clk_src.clkr.hw },
1537aec89f78SBastian Köcher .num_parents = 1,
1538aec89f78SBastian Köcher .flags = CLK_SET_RATE_PARENT,
1539aec89f78SBastian Köcher .ops = &clk_branch2_ops,
1540aec89f78SBastian Köcher },
1541aec89f78SBastian Köcher },
1542aec89f78SBastian Köcher };
1543aec89f78SBastian Köcher
1544aec89f78SBastian Köcher static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = {
1545aec89f78SBastian Köcher .halt_reg = 0x0b84,
1546aec89f78SBastian Köcher .clkr = {
1547aec89f78SBastian Köcher .enable_reg = 0x0b84,
1548aec89f78SBastian Köcher .enable_mask = BIT(0),
15490519d1d0SKonrad Dybcio .hw.init = &(struct clk_init_data){
1550aec89f78SBastian Köcher .name = "gcc_blsp2_qup5_spi_apps_clk",
15510519d1d0SKonrad Dybcio .parent_hws = (const struct clk_hw *[]){ &blsp2_qup5_spi_apps_clk_src.clkr.hw },
1552aec89f78SBastian Köcher .num_parents = 1,
1553aec89f78SBastian Köcher .flags = CLK_SET_RATE_PARENT,
1554aec89f78SBastian Köcher .ops = &clk_branch2_ops,
1555aec89f78SBastian Köcher },
1556aec89f78SBastian Köcher },
1557aec89f78SBastian Köcher };
1558aec89f78SBastian Köcher
1559aec89f78SBastian Köcher static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = {
1560aec89f78SBastian Köcher .halt_reg = 0x0c08,
1561aec89f78SBastian Köcher .clkr = {
1562aec89f78SBastian Köcher .enable_reg = 0x0c08,
1563aec89f78SBastian Köcher .enable_mask = BIT(0),
15640519d1d0SKonrad Dybcio .hw.init = &(struct clk_init_data){
1565aec89f78SBastian Köcher .name = "gcc_blsp2_qup6_i2c_apps_clk",
15660519d1d0SKonrad Dybcio .parent_hws = (const struct clk_hw *[]){ &blsp2_qup6_i2c_apps_clk_src.clkr.hw },
1567aec89f78SBastian Köcher .num_parents = 1,
1568aec89f78SBastian Köcher .flags = CLK_SET_RATE_PARENT,
1569aec89f78SBastian Köcher .ops = &clk_branch2_ops,
1570aec89f78SBastian Köcher },
1571aec89f78SBastian Köcher },
1572aec89f78SBastian Köcher };
1573aec89f78SBastian Köcher
1574aec89f78SBastian Köcher static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = {
1575aec89f78SBastian Köcher .halt_reg = 0x0c04,
1576aec89f78SBastian Köcher .clkr = {
1577aec89f78SBastian Köcher .enable_reg = 0x0c04,
1578aec89f78SBastian Köcher .enable_mask = BIT(0),
15790519d1d0SKonrad Dybcio .hw.init = &(struct clk_init_data){
1580aec89f78SBastian Köcher .name = "gcc_blsp2_qup6_spi_apps_clk",
15810519d1d0SKonrad Dybcio .parent_hws = (const struct clk_hw *[]){ &blsp2_qup6_spi_apps_clk_src.clkr.hw },
1582aec89f78SBastian Köcher .num_parents = 1,
1583aec89f78SBastian Köcher .flags = CLK_SET_RATE_PARENT,
1584aec89f78SBastian Köcher .ops = &clk_branch2_ops,
1585aec89f78SBastian Köcher },
1586aec89f78SBastian Köcher },
1587aec89f78SBastian Köcher };
1588aec89f78SBastian Köcher
1589aec89f78SBastian Köcher static struct clk_branch gcc_blsp2_uart1_apps_clk = {
1590aec89f78SBastian Köcher .halt_reg = 0x09c4,
1591aec89f78SBastian Köcher .clkr = {
1592aec89f78SBastian Köcher .enable_reg = 0x09c4,
1593aec89f78SBastian Köcher .enable_mask = BIT(0),
15940519d1d0SKonrad Dybcio .hw.init = &(struct clk_init_data){
1595aec89f78SBastian Köcher .name = "gcc_blsp2_uart1_apps_clk",
15960519d1d0SKonrad Dybcio .parent_hws = (const struct clk_hw *[]){ &blsp2_uart1_apps_clk_src.clkr.hw },
1597aec89f78SBastian Köcher .num_parents = 1,
1598aec89f78SBastian Köcher .flags = CLK_SET_RATE_PARENT,
1599aec89f78SBastian Köcher .ops = &clk_branch2_ops,
1600aec89f78SBastian Köcher },
1601aec89f78SBastian Köcher },
1602aec89f78SBastian Köcher };
1603aec89f78SBastian Köcher
1604aec89f78SBastian Köcher static struct clk_branch gcc_blsp2_uart2_apps_clk = {
1605aec89f78SBastian Köcher .halt_reg = 0x0a44,
1606aec89f78SBastian Köcher .clkr = {
1607aec89f78SBastian Köcher .enable_reg = 0x0a44,
1608aec89f78SBastian Köcher .enable_mask = BIT(0),
16090519d1d0SKonrad Dybcio .hw.init = &(struct clk_init_data){
1610aec89f78SBastian Köcher .name = "gcc_blsp2_uart2_apps_clk",
16110519d1d0SKonrad Dybcio .parent_hws = (const struct clk_hw *[]){ &blsp2_uart2_apps_clk_src.clkr.hw },
1612aec89f78SBastian Köcher .num_parents = 1,
1613aec89f78SBastian Köcher .flags = CLK_SET_RATE_PARENT,
1614aec89f78SBastian Köcher .ops = &clk_branch2_ops,
1615aec89f78SBastian Köcher },
1616aec89f78SBastian Köcher },
1617aec89f78SBastian Köcher };
1618aec89f78SBastian Köcher
1619aec89f78SBastian Köcher static struct clk_branch gcc_blsp2_uart3_apps_clk = {
1620aec89f78SBastian Köcher .halt_reg = 0x0ac4,
1621aec89f78SBastian Köcher .clkr = {
1622aec89f78SBastian Köcher .enable_reg = 0x0ac4,
1623aec89f78SBastian Köcher .enable_mask = BIT(0),
16240519d1d0SKonrad Dybcio .hw.init = &(struct clk_init_data){
1625aec89f78SBastian Köcher .name = "gcc_blsp2_uart3_apps_clk",
16260519d1d0SKonrad Dybcio .parent_hws = (const struct clk_hw *[]){ &blsp2_uart3_apps_clk_src.clkr.hw },
1627aec89f78SBastian Köcher .num_parents = 1,
1628aec89f78SBastian Köcher .flags = CLK_SET_RATE_PARENT,
1629aec89f78SBastian Köcher .ops = &clk_branch2_ops,
1630aec89f78SBastian Köcher },
1631aec89f78SBastian Köcher },
1632aec89f78SBastian Köcher };
1633aec89f78SBastian Köcher
1634aec89f78SBastian Köcher static struct clk_branch gcc_blsp2_uart4_apps_clk = {
1635aec89f78SBastian Köcher .halt_reg = 0x0b44,
1636aec89f78SBastian Köcher .clkr = {
1637aec89f78SBastian Köcher .enable_reg = 0x0b44,
1638aec89f78SBastian Köcher .enable_mask = BIT(0),
16390519d1d0SKonrad Dybcio .hw.init = &(struct clk_init_data){
1640aec89f78SBastian Köcher .name = "gcc_blsp2_uart4_apps_clk",
16410519d1d0SKonrad Dybcio .parent_hws = (const struct clk_hw *[]){ &blsp2_uart4_apps_clk_src.clkr.hw },
1642aec89f78SBastian Köcher .num_parents = 1,
1643aec89f78SBastian Köcher .flags = CLK_SET_RATE_PARENT,
1644aec89f78SBastian Köcher .ops = &clk_branch2_ops,
1645aec89f78SBastian Köcher },
1646aec89f78SBastian Köcher },
1647aec89f78SBastian Köcher };
1648aec89f78SBastian Köcher
1649aec89f78SBastian Köcher static struct clk_branch gcc_blsp2_uart5_apps_clk = {
1650aec89f78SBastian Köcher .halt_reg = 0x0bc4,
1651aec89f78SBastian Köcher .clkr = {
1652aec89f78SBastian Köcher .enable_reg = 0x0bc4,
1653aec89f78SBastian Köcher .enable_mask = BIT(0),
16540519d1d0SKonrad Dybcio .hw.init = &(struct clk_init_data){
1655aec89f78SBastian Köcher .name = "gcc_blsp2_uart5_apps_clk",
16560519d1d0SKonrad Dybcio .parent_hws = (const struct clk_hw *[]){ &blsp2_uart5_apps_clk_src.clkr.hw },
1657aec89f78SBastian Köcher .num_parents = 1,
1658aec89f78SBastian Köcher .flags = CLK_SET_RATE_PARENT,
1659aec89f78SBastian Köcher .ops = &clk_branch2_ops,
1660aec89f78SBastian Köcher },
1661aec89f78SBastian Köcher },
1662aec89f78SBastian Köcher };
1663aec89f78SBastian Köcher
1664aec89f78SBastian Köcher static struct clk_branch gcc_blsp2_uart6_apps_clk = {
1665aec89f78SBastian Köcher .halt_reg = 0x0c44,
1666aec89f78SBastian Köcher .clkr = {
1667aec89f78SBastian Köcher .enable_reg = 0x0c44,
1668aec89f78SBastian Köcher .enable_mask = BIT(0),
16690519d1d0SKonrad Dybcio .hw.init = &(struct clk_init_data){
1670aec89f78SBastian Köcher .name = "gcc_blsp2_uart6_apps_clk",
16710519d1d0SKonrad Dybcio .parent_hws = (const struct clk_hw *[]){ &blsp2_uart6_apps_clk_src.clkr.hw },
1672aec89f78SBastian Köcher .num_parents = 1,
1673aec89f78SBastian Köcher .flags = CLK_SET_RATE_PARENT,
1674aec89f78SBastian Köcher .ops = &clk_branch2_ops,
1675aec89f78SBastian Köcher },
1676aec89f78SBastian Köcher },
1677aec89f78SBastian Köcher };
1678aec89f78SBastian Köcher
1679aec89f78SBastian Köcher static struct clk_branch gcc_gp1_clk = {
1680aec89f78SBastian Köcher .halt_reg = 0x1900,
1681aec89f78SBastian Köcher .clkr = {
1682aec89f78SBastian Köcher .enable_reg = 0x1900,
1683aec89f78SBastian Köcher .enable_mask = BIT(0),
16840519d1d0SKonrad Dybcio .hw.init = &(struct clk_init_data){
1685aec89f78SBastian Köcher .name = "gcc_gp1_clk",
16860519d1d0SKonrad Dybcio .parent_hws = (const struct clk_hw *[]){ &gp1_clk_src.clkr.hw },
1687aec89f78SBastian Köcher .num_parents = 1,
1688aec89f78SBastian Köcher .flags = CLK_SET_RATE_PARENT,
1689aec89f78SBastian Köcher .ops = &clk_branch2_ops,
1690aec89f78SBastian Köcher },
1691aec89f78SBastian Köcher },
1692aec89f78SBastian Köcher };
1693aec89f78SBastian Köcher
1694aec89f78SBastian Köcher static struct clk_branch gcc_gp2_clk = {
1695aec89f78SBastian Köcher .halt_reg = 0x1940,
1696aec89f78SBastian Köcher .clkr = {
1697aec89f78SBastian Köcher .enable_reg = 0x1940,
1698aec89f78SBastian Köcher .enable_mask = BIT(0),
16990519d1d0SKonrad Dybcio .hw.init = &(struct clk_init_data){
1700aec89f78SBastian Köcher .name = "gcc_gp2_clk",
17010519d1d0SKonrad Dybcio .parent_hws = (const struct clk_hw *[]){ &gp2_clk_src.clkr.hw },
1702aec89f78SBastian Köcher .num_parents = 1,
1703aec89f78SBastian Köcher .flags = CLK_SET_RATE_PARENT,
1704aec89f78SBastian Köcher .ops = &clk_branch2_ops,
1705aec89f78SBastian Köcher },
1706aec89f78SBastian Köcher },
1707aec89f78SBastian Köcher };
1708aec89f78SBastian Köcher
1709aec89f78SBastian Köcher static struct clk_branch gcc_gp3_clk = {
1710aec89f78SBastian Köcher .halt_reg = 0x1980,
1711aec89f78SBastian Köcher .clkr = {
1712aec89f78SBastian Köcher .enable_reg = 0x1980,
1713aec89f78SBastian Köcher .enable_mask = BIT(0),
17140519d1d0SKonrad Dybcio .hw.init = &(struct clk_init_data){
1715aec89f78SBastian Köcher .name = "gcc_gp3_clk",
17160519d1d0SKonrad Dybcio .parent_hws = (const struct clk_hw *[]){ &gp3_clk_src.clkr.hw },
1717aec89f78SBastian Köcher .num_parents = 1,
1718aec89f78SBastian Köcher .flags = CLK_SET_RATE_PARENT,
1719aec89f78SBastian Köcher .ops = &clk_branch2_ops,
1720aec89f78SBastian Köcher },
1721aec89f78SBastian Köcher },
1722aec89f78SBastian Köcher };
1723aec89f78SBastian Köcher
17248c18b41bSKonrad Dybcio static struct clk_branch gcc_lpass_q6_axi_clk = {
17258c18b41bSKonrad Dybcio .halt_reg = 0x0280,
17268c18b41bSKonrad Dybcio .clkr = {
17278c18b41bSKonrad Dybcio .enable_reg = 0x0280,
17288c18b41bSKonrad Dybcio .enable_mask = BIT(0),
17290519d1d0SKonrad Dybcio .hw.init = &(struct clk_init_data){
17308c18b41bSKonrad Dybcio .name = "gcc_lpass_q6_axi_clk",
17318c18b41bSKonrad Dybcio .ops = &clk_branch2_ops,
17328c18b41bSKonrad Dybcio },
17338c18b41bSKonrad Dybcio },
17348c18b41bSKonrad Dybcio };
17358c18b41bSKonrad Dybcio
17368c18b41bSKonrad Dybcio static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
17378c18b41bSKonrad Dybcio .halt_reg = 0x0284,
17388c18b41bSKonrad Dybcio .clkr = {
17398c18b41bSKonrad Dybcio .enable_reg = 0x0284,
17408c18b41bSKonrad Dybcio .enable_mask = BIT(0),
17410519d1d0SKonrad Dybcio .hw.init = &(struct clk_init_data){
17428c18b41bSKonrad Dybcio .name = "gcc_mss_q6_bimc_axi_clk",
17438c18b41bSKonrad Dybcio .ops = &clk_branch2_ops,
17448c18b41bSKonrad Dybcio },
17458c18b41bSKonrad Dybcio },
17468c18b41bSKonrad Dybcio };
17478c18b41bSKonrad Dybcio
1748aec89f78SBastian Köcher static struct clk_branch gcc_pcie_0_aux_clk = {
1749aec89f78SBastian Köcher .halt_reg = 0x1ad4,
1750aec89f78SBastian Köcher .clkr = {
1751aec89f78SBastian Köcher .enable_reg = 0x1ad4,
1752aec89f78SBastian Köcher .enable_mask = BIT(0),
17530519d1d0SKonrad Dybcio .hw.init = &(struct clk_init_data){
1754aec89f78SBastian Köcher .name = "gcc_pcie_0_aux_clk",
17550519d1d0SKonrad Dybcio .parent_hws = (const struct clk_hw *[]){ &pcie_0_aux_clk_src.clkr.hw },
1756aec89f78SBastian Köcher .num_parents = 1,
1757aec89f78SBastian Köcher .flags = CLK_SET_RATE_PARENT,
1758aec89f78SBastian Köcher .ops = &clk_branch2_ops,
1759aec89f78SBastian Köcher },
1760aec89f78SBastian Köcher },
1761aec89f78SBastian Köcher };
1762aec89f78SBastian Köcher
17638c18b41bSKonrad Dybcio static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
17648c18b41bSKonrad Dybcio .halt_reg = 0x1ad0,
17658c18b41bSKonrad Dybcio .clkr = {
17668c18b41bSKonrad Dybcio .enable_reg = 0x1ad0,
17678c18b41bSKonrad Dybcio .enable_mask = BIT(0),
17680519d1d0SKonrad Dybcio .hw.init = &(struct clk_init_data){
17698c18b41bSKonrad Dybcio .name = "gcc_pcie_0_cfg_ahb_clk",
17708c18b41bSKonrad Dybcio .ops = &clk_branch2_ops,
17718c18b41bSKonrad Dybcio },
17728c18b41bSKonrad Dybcio },
17738c18b41bSKonrad Dybcio };
17748c18b41bSKonrad Dybcio
17758c18b41bSKonrad Dybcio static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
17768c18b41bSKonrad Dybcio .halt_reg = 0x1acc,
17778c18b41bSKonrad Dybcio .clkr = {
17788c18b41bSKonrad Dybcio .enable_reg = 0x1acc,
17798c18b41bSKonrad Dybcio .enable_mask = BIT(0),
17800519d1d0SKonrad Dybcio .hw.init = &(struct clk_init_data){
17818c18b41bSKonrad Dybcio .name = "gcc_pcie_0_mstr_axi_clk",
17828c18b41bSKonrad Dybcio .ops = &clk_branch2_ops,
17838c18b41bSKonrad Dybcio },
17848c18b41bSKonrad Dybcio },
17858c18b41bSKonrad Dybcio };
17868c18b41bSKonrad Dybcio
1787aec89f78SBastian Köcher static struct clk_branch gcc_pcie_0_pipe_clk = {
1788aec89f78SBastian Köcher .halt_reg = 0x1ad8,
1789aec89f78SBastian Köcher .halt_check = BRANCH_HALT_DELAY,
1790aec89f78SBastian Köcher .clkr = {
1791aec89f78SBastian Köcher .enable_reg = 0x1ad8,
1792aec89f78SBastian Köcher .enable_mask = BIT(0),
17930519d1d0SKonrad Dybcio .hw.init = &(struct clk_init_data){
1794aec89f78SBastian Köcher .name = "gcc_pcie_0_pipe_clk",
17950519d1d0SKonrad Dybcio .parent_hws = (const struct clk_hw *[]){ &pcie_0_pipe_clk_src.clkr.hw },
1796aec89f78SBastian Köcher .num_parents = 1,
1797aec89f78SBastian Köcher .flags = CLK_SET_RATE_PARENT,
1798aec89f78SBastian Köcher .ops = &clk_branch2_ops,
1799aec89f78SBastian Köcher },
1800aec89f78SBastian Köcher },
1801aec89f78SBastian Köcher };
1802aec89f78SBastian Köcher
18038c18b41bSKonrad Dybcio static struct clk_branch gcc_pcie_0_slv_axi_clk = {
18048c18b41bSKonrad Dybcio .halt_reg = 0x1ac8,
18058c18b41bSKonrad Dybcio .halt_check = BRANCH_HALT_DELAY,
18068c18b41bSKonrad Dybcio .clkr = {
18078c18b41bSKonrad Dybcio .enable_reg = 0x1ac8,
18088c18b41bSKonrad Dybcio .enable_mask = BIT(0),
18090519d1d0SKonrad Dybcio .hw.init = &(struct clk_init_data){
18108c18b41bSKonrad Dybcio .name = "gcc_pcie_0_slv_axi_clk",
18118c18b41bSKonrad Dybcio .ops = &clk_branch2_ops,
18128c18b41bSKonrad Dybcio },
18138c18b41bSKonrad Dybcio },
18148c18b41bSKonrad Dybcio };
18158c18b41bSKonrad Dybcio
1816aec89f78SBastian Köcher static struct clk_branch gcc_pcie_1_aux_clk = {
1817aec89f78SBastian Köcher .halt_reg = 0x1b54,
1818aec89f78SBastian Köcher .clkr = {
1819aec89f78SBastian Köcher .enable_reg = 0x1b54,
1820aec89f78SBastian Köcher .enable_mask = BIT(0),
18210519d1d0SKonrad Dybcio .hw.init = &(struct clk_init_data){
1822aec89f78SBastian Köcher .name = "gcc_pcie_1_aux_clk",
18230519d1d0SKonrad Dybcio .parent_hws = (const struct clk_hw *[]){ &pcie_1_aux_clk_src.clkr.hw },
1824aec89f78SBastian Köcher .num_parents = 1,
1825aec89f78SBastian Köcher .flags = CLK_SET_RATE_PARENT,
1826aec89f78SBastian Köcher .ops = &clk_branch2_ops,
1827aec89f78SBastian Köcher },
1828aec89f78SBastian Köcher },
1829aec89f78SBastian Köcher };
1830aec89f78SBastian Köcher
18318c18b41bSKonrad Dybcio static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
18328c18b41bSKonrad Dybcio .halt_reg = 0x1b54,
18338c18b41bSKonrad Dybcio .clkr = {
18348c18b41bSKonrad Dybcio .enable_reg = 0x1b54,
18358c18b41bSKonrad Dybcio .enable_mask = BIT(0),
18360519d1d0SKonrad Dybcio .hw.init = &(struct clk_init_data){
18378c18b41bSKonrad Dybcio .name = "gcc_pcie_1_cfg_ahb_clk",
18388c18b41bSKonrad Dybcio .ops = &clk_branch2_ops,
18398c18b41bSKonrad Dybcio },
18408c18b41bSKonrad Dybcio },
18418c18b41bSKonrad Dybcio };
18428c18b41bSKonrad Dybcio
18438c18b41bSKonrad Dybcio static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
18448c18b41bSKonrad Dybcio .halt_reg = 0x1b50,
18458c18b41bSKonrad Dybcio .clkr = {
18468c18b41bSKonrad Dybcio .enable_reg = 0x1b50,
18478c18b41bSKonrad Dybcio .enable_mask = BIT(0),
18480519d1d0SKonrad Dybcio .hw.init = &(struct clk_init_data){
18498c18b41bSKonrad Dybcio .name = "gcc_pcie_1_mstr_axi_clk",
18508c18b41bSKonrad Dybcio .ops = &clk_branch2_ops,
18518c18b41bSKonrad Dybcio },
18528c18b41bSKonrad Dybcio },
18538c18b41bSKonrad Dybcio };
18548c18b41bSKonrad Dybcio
1855aec89f78SBastian Köcher static struct clk_branch gcc_pcie_1_pipe_clk = {
1856aec89f78SBastian Köcher .halt_reg = 0x1b58,
1857aec89f78SBastian Köcher .halt_check = BRANCH_HALT_DELAY,
1858aec89f78SBastian Köcher .clkr = {
1859aec89f78SBastian Köcher .enable_reg = 0x1b58,
1860aec89f78SBastian Köcher .enable_mask = BIT(0),
18610519d1d0SKonrad Dybcio .hw.init = &(struct clk_init_data){
1862aec89f78SBastian Köcher .name = "gcc_pcie_1_pipe_clk",
18630519d1d0SKonrad Dybcio .parent_hws = (const struct clk_hw *[]){ &pcie_1_pipe_clk_src.clkr.hw },
1864aec89f78SBastian Köcher .num_parents = 1,
1865aec89f78SBastian Köcher .flags = CLK_SET_RATE_PARENT,
1866aec89f78SBastian Köcher .ops = &clk_branch2_ops,
1867aec89f78SBastian Köcher },
1868aec89f78SBastian Köcher },
1869aec89f78SBastian Köcher };
1870aec89f78SBastian Köcher
18718c18b41bSKonrad Dybcio static struct clk_branch gcc_pcie_1_slv_axi_clk = {
18728c18b41bSKonrad Dybcio .halt_reg = 0x1b48,
18738c18b41bSKonrad Dybcio .clkr = {
18748c18b41bSKonrad Dybcio .enable_reg = 0x1b48,
18758c18b41bSKonrad Dybcio .enable_mask = BIT(0),
18760519d1d0SKonrad Dybcio .hw.init = &(struct clk_init_data){
18778c18b41bSKonrad Dybcio .name = "gcc_pcie_1_slv_axi_clk",
18788c18b41bSKonrad Dybcio .ops = &clk_branch2_ops,
18798c18b41bSKonrad Dybcio },
18808c18b41bSKonrad Dybcio },
18818c18b41bSKonrad Dybcio };
18828c18b41bSKonrad Dybcio
1883aec89f78SBastian Köcher static struct clk_branch gcc_pdm2_clk = {
1884aec89f78SBastian Köcher .halt_reg = 0x0ccc,
1885aec89f78SBastian Köcher .clkr = {
1886aec89f78SBastian Köcher .enable_reg = 0x0ccc,
1887aec89f78SBastian Köcher .enable_mask = BIT(0),
18880519d1d0SKonrad Dybcio .hw.init = &(struct clk_init_data){
1889aec89f78SBastian Köcher .name = "gcc_pdm2_clk",
18900519d1d0SKonrad Dybcio .parent_hws = (const struct clk_hw *[]){ &pdm2_clk_src.clkr.hw },
1891aec89f78SBastian Köcher .num_parents = 1,
1892aec89f78SBastian Köcher .flags = CLK_SET_RATE_PARENT,
1893aec89f78SBastian Köcher .ops = &clk_branch2_ops,
1894aec89f78SBastian Köcher },
1895aec89f78SBastian Köcher },
1896aec89f78SBastian Köcher };
1897aec89f78SBastian Köcher
18988c18b41bSKonrad Dybcio static struct clk_branch gcc_pdm_ahb_clk = {
18998c18b41bSKonrad Dybcio .halt_reg = 0x0cc4,
19008c18b41bSKonrad Dybcio .clkr = {
19018c18b41bSKonrad Dybcio .enable_reg = 0x0cc4,
19028c18b41bSKonrad Dybcio .enable_mask = BIT(0),
19030519d1d0SKonrad Dybcio .hw.init = &(struct clk_init_data){
19048c18b41bSKonrad Dybcio .name = "gcc_pdm_ahb_clk",
19058c18b41bSKonrad Dybcio .ops = &clk_branch2_ops,
19068c18b41bSKonrad Dybcio },
19078c18b41bSKonrad Dybcio },
19088c18b41bSKonrad Dybcio };
19098c18b41bSKonrad Dybcio
1910aec89f78SBastian Köcher static struct clk_branch gcc_sdcc1_apps_clk = {
1911aec89f78SBastian Köcher .halt_reg = 0x04c4,
1912aec89f78SBastian Köcher .clkr = {
1913aec89f78SBastian Köcher .enable_reg = 0x04c4,
1914aec89f78SBastian Köcher .enable_mask = BIT(0),
19150519d1d0SKonrad Dybcio .hw.init = &(struct clk_init_data){
1916aec89f78SBastian Köcher .name = "gcc_sdcc1_apps_clk",
19170519d1d0SKonrad Dybcio .parent_hws = (const struct clk_hw *[]){ &sdcc1_apps_clk_src.clkr.hw },
1918aec89f78SBastian Köcher .num_parents = 1,
1919aec89f78SBastian Köcher .flags = CLK_SET_RATE_PARENT,
1920aec89f78SBastian Köcher .ops = &clk_branch2_ops,
1921aec89f78SBastian Köcher },
1922aec89f78SBastian Köcher },
1923aec89f78SBastian Köcher };
1924aec89f78SBastian Köcher
1925eaff16bcSJeremy McNicoll static struct clk_branch gcc_sdcc1_ahb_clk = {
1926eaff16bcSJeremy McNicoll .halt_reg = 0x04c8,
1927eaff16bcSJeremy McNicoll .clkr = {
1928eaff16bcSJeremy McNicoll .enable_reg = 0x04c8,
1929eaff16bcSJeremy McNicoll .enable_mask = BIT(0),
19300519d1d0SKonrad Dybcio .hw.init = &(struct clk_init_data){
1931eaff16bcSJeremy McNicoll .name = "gcc_sdcc1_ahb_clk",
1932eaff16bcSJeremy McNicoll .ops = &clk_branch2_ops,
1933eaff16bcSJeremy McNicoll },
1934eaff16bcSJeremy McNicoll },
1935eaff16bcSJeremy McNicoll };
1936eaff16bcSJeremy McNicoll
19378c18b41bSKonrad Dybcio static struct clk_branch gcc_sdcc2_ahb_clk = {
19388c18b41bSKonrad Dybcio .halt_reg = 0x0508,
19398c18b41bSKonrad Dybcio .clkr = {
19408c18b41bSKonrad Dybcio .enable_reg = 0x0508,
19418c18b41bSKonrad Dybcio .enable_mask = BIT(0),
19420519d1d0SKonrad Dybcio .hw.init = &(struct clk_init_data){
19438c18b41bSKonrad Dybcio .name = "gcc_sdcc2_ahb_clk",
19448c18b41bSKonrad Dybcio .ops = &clk_branch2_ops,
19458c18b41bSKonrad Dybcio },
19468c18b41bSKonrad Dybcio },
19478c18b41bSKonrad Dybcio };
19488c18b41bSKonrad Dybcio
1949aec89f78SBastian Köcher static struct clk_branch gcc_sdcc2_apps_clk = {
1950aec89f78SBastian Köcher .halt_reg = 0x0504,
1951aec89f78SBastian Köcher .clkr = {
1952aec89f78SBastian Köcher .enable_reg = 0x0504,
1953aec89f78SBastian Köcher .enable_mask = BIT(0),
19540519d1d0SKonrad Dybcio .hw.init = &(struct clk_init_data){
1955aec89f78SBastian Köcher .name = "gcc_sdcc2_apps_clk",
19560519d1d0SKonrad Dybcio .parent_hws = (const struct clk_hw *[]){ &sdcc2_apps_clk_src.clkr.hw },
1957aec89f78SBastian Köcher .num_parents = 1,
1958aec89f78SBastian Köcher .flags = CLK_SET_RATE_PARENT,
1959aec89f78SBastian Köcher .ops = &clk_branch2_ops,
1960aec89f78SBastian Köcher },
1961aec89f78SBastian Köcher },
1962aec89f78SBastian Köcher };
1963aec89f78SBastian Köcher
19648c18b41bSKonrad Dybcio static struct clk_branch gcc_sdcc3_ahb_clk = {
19658c18b41bSKonrad Dybcio .halt_reg = 0x0548,
19668c18b41bSKonrad Dybcio .clkr = {
19678c18b41bSKonrad Dybcio .enable_reg = 0x0548,
19688c18b41bSKonrad Dybcio .enable_mask = BIT(0),
19690519d1d0SKonrad Dybcio .hw.init = &(struct clk_init_data){
19708c18b41bSKonrad Dybcio .name = "gcc_sdcc3_ahb_clk",
19718c18b41bSKonrad Dybcio .ops = &clk_branch2_ops,
19728c18b41bSKonrad Dybcio },
19738c18b41bSKonrad Dybcio },
19748c18b41bSKonrad Dybcio };
19758c18b41bSKonrad Dybcio
1976aec89f78SBastian Köcher static struct clk_branch gcc_sdcc3_apps_clk = {
1977aec89f78SBastian Köcher .halt_reg = 0x0544,
1978aec89f78SBastian Köcher .clkr = {
1979aec89f78SBastian Köcher .enable_reg = 0x0544,
1980aec89f78SBastian Köcher .enable_mask = BIT(0),
19810519d1d0SKonrad Dybcio .hw.init = &(struct clk_init_data){
1982aec89f78SBastian Köcher .name = "gcc_sdcc3_apps_clk",
19830519d1d0SKonrad Dybcio .parent_hws = (const struct clk_hw *[]){ &sdcc3_apps_clk_src.clkr.hw },
1984aec89f78SBastian Köcher .num_parents = 1,
1985aec89f78SBastian Köcher .flags = CLK_SET_RATE_PARENT,
1986aec89f78SBastian Köcher .ops = &clk_branch2_ops,
1987aec89f78SBastian Köcher },
1988aec89f78SBastian Köcher },
1989aec89f78SBastian Köcher };
1990aec89f78SBastian Köcher
19918c18b41bSKonrad Dybcio static struct clk_branch gcc_sdcc4_ahb_clk = {
19928c18b41bSKonrad Dybcio .halt_reg = 0x0588,
19938c18b41bSKonrad Dybcio .clkr = {
19948c18b41bSKonrad Dybcio .enable_reg = 0x0588,
19958c18b41bSKonrad Dybcio .enable_mask = BIT(0),
19960519d1d0SKonrad Dybcio .hw.init = &(struct clk_init_data){
19978c18b41bSKonrad Dybcio .name = "gcc_sdcc4_ahb_clk",
19988c18b41bSKonrad Dybcio .ops = &clk_branch2_ops,
19998c18b41bSKonrad Dybcio },
20008c18b41bSKonrad Dybcio },
20018c18b41bSKonrad Dybcio };
20028c18b41bSKonrad Dybcio
2003aec89f78SBastian Köcher static struct clk_branch gcc_sdcc4_apps_clk = {
2004aec89f78SBastian Köcher .halt_reg = 0x0584,
2005aec89f78SBastian Köcher .clkr = {
2006aec89f78SBastian Köcher .enable_reg = 0x0584,
2007aec89f78SBastian Köcher .enable_mask = BIT(0),
20080519d1d0SKonrad Dybcio .hw.init = &(struct clk_init_data){
2009aec89f78SBastian Köcher .name = "gcc_sdcc4_apps_clk",
20100519d1d0SKonrad Dybcio .parent_hws = (const struct clk_hw *[]){ &sdcc4_apps_clk_src.clkr.hw },
2011aec89f78SBastian Köcher .num_parents = 1,
2012aec89f78SBastian Köcher .flags = CLK_SET_RATE_PARENT,
2013aec89f78SBastian Köcher .ops = &clk_branch2_ops,
2014aec89f78SBastian Köcher },
2015aec89f78SBastian Köcher },
2016aec89f78SBastian Köcher };
2017aec89f78SBastian Köcher
2018aec89f78SBastian Köcher static struct clk_branch gcc_sys_noc_ufs_axi_clk = {
2019aec89f78SBastian Köcher .halt_reg = 0x1d7c,
2020aec89f78SBastian Köcher .clkr = {
2021aec89f78SBastian Köcher .enable_reg = 0x1d7c,
2022aec89f78SBastian Köcher .enable_mask = BIT(0),
20230519d1d0SKonrad Dybcio .hw.init = &(struct clk_init_data){
2024aec89f78SBastian Köcher .name = "gcc_sys_noc_ufs_axi_clk",
20250519d1d0SKonrad Dybcio .parent_hws = (const struct clk_hw *[]){ &ufs_axi_clk_src.clkr.hw },
2026aec89f78SBastian Köcher .num_parents = 1,
2027aec89f78SBastian Köcher .flags = CLK_SET_RATE_PARENT,
2028aec89f78SBastian Köcher .ops = &clk_branch2_ops,
2029aec89f78SBastian Köcher },
2030aec89f78SBastian Köcher },
2031aec89f78SBastian Köcher };
2032aec89f78SBastian Köcher
2033aec89f78SBastian Köcher static struct clk_branch gcc_sys_noc_usb3_axi_clk = {
2034aec89f78SBastian Köcher .halt_reg = 0x03fc,
2035aec89f78SBastian Köcher .clkr = {
2036aec89f78SBastian Köcher .enable_reg = 0x03fc,
2037aec89f78SBastian Köcher .enable_mask = BIT(0),
20380519d1d0SKonrad Dybcio .hw.init = &(struct clk_init_data){
2039aec89f78SBastian Köcher .name = "gcc_sys_noc_usb3_axi_clk",
20400519d1d0SKonrad Dybcio .parent_hws = (const struct clk_hw *[]){ &usb30_master_clk_src.clkr.hw },
2041aec89f78SBastian Köcher .num_parents = 1,
2042aec89f78SBastian Köcher .flags = CLK_SET_RATE_PARENT,
2043aec89f78SBastian Köcher .ops = &clk_branch2_ops,
2044aec89f78SBastian Köcher },
2045aec89f78SBastian Köcher },
2046aec89f78SBastian Köcher };
2047aec89f78SBastian Köcher
20488c18b41bSKonrad Dybcio static struct clk_branch gcc_tsif_ahb_clk = {
20498c18b41bSKonrad Dybcio .halt_reg = 0x0d84,
20508c18b41bSKonrad Dybcio .clkr = {
20518c18b41bSKonrad Dybcio .enable_reg = 0x0d84,
20528c18b41bSKonrad Dybcio .enable_mask = BIT(0),
20530519d1d0SKonrad Dybcio .hw.init = &(struct clk_init_data){
20548c18b41bSKonrad Dybcio .name = "gcc_tsif_ahb_clk",
20558c18b41bSKonrad Dybcio .ops = &clk_branch2_ops,
20568c18b41bSKonrad Dybcio },
20578c18b41bSKonrad Dybcio },
20588c18b41bSKonrad Dybcio };
20598c18b41bSKonrad Dybcio
2060aec89f78SBastian Köcher static struct clk_branch gcc_tsif_ref_clk = {
2061aec89f78SBastian Köcher .halt_reg = 0x0d88,
2062aec89f78SBastian Köcher .clkr = {
2063aec89f78SBastian Köcher .enable_reg = 0x0d88,
2064aec89f78SBastian Köcher .enable_mask = BIT(0),
20650519d1d0SKonrad Dybcio .hw.init = &(struct clk_init_data){
2066aec89f78SBastian Köcher .name = "gcc_tsif_ref_clk",
20670519d1d0SKonrad Dybcio .parent_hws = (const struct clk_hw *[]){ &tsif_ref_clk_src.clkr.hw },
2068aec89f78SBastian Köcher .num_parents = 1,
2069aec89f78SBastian Köcher .flags = CLK_SET_RATE_PARENT,
2070aec89f78SBastian Köcher .ops = &clk_branch2_ops,
2071aec89f78SBastian Köcher },
2072aec89f78SBastian Köcher },
2073aec89f78SBastian Köcher };
2074aec89f78SBastian Köcher
20758c18b41bSKonrad Dybcio static struct clk_branch gcc_ufs_ahb_clk = {
20768c18b41bSKonrad Dybcio .halt_reg = 0x1d4c,
20778c18b41bSKonrad Dybcio .clkr = {
20788c18b41bSKonrad Dybcio .enable_reg = 0x1d4c,
20798c18b41bSKonrad Dybcio .enable_mask = BIT(0),
20800519d1d0SKonrad Dybcio .hw.init = &(struct clk_init_data){
20818c18b41bSKonrad Dybcio .name = "gcc_ufs_ahb_clk",
20828c18b41bSKonrad Dybcio .ops = &clk_branch2_ops,
20838c18b41bSKonrad Dybcio },
20848c18b41bSKonrad Dybcio },
20858c18b41bSKonrad Dybcio };
20868c18b41bSKonrad Dybcio
2087aec89f78SBastian Köcher static struct clk_branch gcc_ufs_axi_clk = {
2088aec89f78SBastian Köcher .halt_reg = 0x1d48,
2089aec89f78SBastian Köcher .clkr = {
2090aec89f78SBastian Köcher .enable_reg = 0x1d48,
2091aec89f78SBastian Köcher .enable_mask = BIT(0),
20920519d1d0SKonrad Dybcio .hw.init = &(struct clk_init_data){
2093aec89f78SBastian Köcher .name = "gcc_ufs_axi_clk",
20940519d1d0SKonrad Dybcio .parent_hws = (const struct clk_hw *[]){ &ufs_axi_clk_src.clkr.hw },
2095aec89f78SBastian Köcher .num_parents = 1,
2096aec89f78SBastian Köcher .flags = CLK_SET_RATE_PARENT,
2097aec89f78SBastian Köcher .ops = &clk_branch2_ops,
2098aec89f78SBastian Köcher },
2099aec89f78SBastian Köcher },
2100aec89f78SBastian Köcher };
2101aec89f78SBastian Köcher
2102aec89f78SBastian Köcher static struct clk_branch gcc_ufs_rx_cfg_clk = {
2103aec89f78SBastian Köcher .halt_reg = 0x1d54,
2104aec89f78SBastian Köcher .clkr = {
2105aec89f78SBastian Köcher .enable_reg = 0x1d54,
2106aec89f78SBastian Köcher .enable_mask = BIT(0),
21070519d1d0SKonrad Dybcio .hw.init = &(struct clk_init_data){
2108aec89f78SBastian Köcher .name = "gcc_ufs_rx_cfg_clk",
21090519d1d0SKonrad Dybcio .parent_hws = (const struct clk_hw *[]){ &ufs_axi_clk_src.clkr.hw },
2110aec89f78SBastian Köcher .num_parents = 1,
2111aec89f78SBastian Köcher .flags = CLK_SET_RATE_PARENT,
2112aec89f78SBastian Köcher .ops = &clk_branch2_ops,
2113aec89f78SBastian Köcher },
2114aec89f78SBastian Köcher },
2115aec89f78SBastian Köcher };
2116aec89f78SBastian Köcher
21178c18b41bSKonrad Dybcio static struct clk_branch gcc_ufs_rx_symbol_0_clk = {
21188c18b41bSKonrad Dybcio .halt_reg = 0x1d60,
21198c18b41bSKonrad Dybcio .halt_check = BRANCH_HALT_DELAY,
21208c18b41bSKonrad Dybcio .clkr = {
21218c18b41bSKonrad Dybcio .enable_reg = 0x1d60,
21228c18b41bSKonrad Dybcio .enable_mask = BIT(0),
21230519d1d0SKonrad Dybcio .hw.init = &(struct clk_init_data){
21248c18b41bSKonrad Dybcio .name = "gcc_ufs_rx_symbol_0_clk",
21258c18b41bSKonrad Dybcio .ops = &clk_branch2_ops,
21268c18b41bSKonrad Dybcio },
21278c18b41bSKonrad Dybcio },
21288c18b41bSKonrad Dybcio };
21298c18b41bSKonrad Dybcio
21308c18b41bSKonrad Dybcio static struct clk_branch gcc_ufs_rx_symbol_1_clk = {
21318c18b41bSKonrad Dybcio .halt_reg = 0x1d64,
21328c18b41bSKonrad Dybcio .halt_check = BRANCH_HALT_DELAY,
21338c18b41bSKonrad Dybcio .clkr = {
21348c18b41bSKonrad Dybcio .enable_reg = 0x1d64,
21358c18b41bSKonrad Dybcio .enable_mask = BIT(0),
21360519d1d0SKonrad Dybcio .hw.init = &(struct clk_init_data){
21378c18b41bSKonrad Dybcio .name = "gcc_ufs_rx_symbol_1_clk",
21388c18b41bSKonrad Dybcio .ops = &clk_branch2_ops,
21398c18b41bSKonrad Dybcio },
21408c18b41bSKonrad Dybcio },
21418c18b41bSKonrad Dybcio };
21428c18b41bSKonrad Dybcio
2143aec89f78SBastian Köcher static struct clk_branch gcc_ufs_tx_cfg_clk = {
2144aec89f78SBastian Köcher .halt_reg = 0x1d50,
2145aec89f78SBastian Köcher .clkr = {
2146aec89f78SBastian Köcher .enable_reg = 0x1d50,
2147aec89f78SBastian Köcher .enable_mask = BIT(0),
21480519d1d0SKonrad Dybcio .hw.init = &(struct clk_init_data){
2149aec89f78SBastian Köcher .name = "gcc_ufs_tx_cfg_clk",
21500519d1d0SKonrad Dybcio .parent_hws = (const struct clk_hw *[]){ &ufs_axi_clk_src.clkr.hw },
2151aec89f78SBastian Köcher .num_parents = 1,
2152aec89f78SBastian Köcher .flags = CLK_SET_RATE_PARENT,
2153aec89f78SBastian Köcher .ops = &clk_branch2_ops,
2154aec89f78SBastian Köcher },
2155aec89f78SBastian Köcher },
2156aec89f78SBastian Köcher };
2157aec89f78SBastian Köcher
21588c18b41bSKonrad Dybcio static struct clk_branch gcc_ufs_tx_symbol_0_clk = {
21598c18b41bSKonrad Dybcio .halt_reg = 0x1d58,
21608c18b41bSKonrad Dybcio .halt_check = BRANCH_HALT_DELAY,
21618c18b41bSKonrad Dybcio .clkr = {
21628c18b41bSKonrad Dybcio .enable_reg = 0x1d58,
21638c18b41bSKonrad Dybcio .enable_mask = BIT(0),
21640519d1d0SKonrad Dybcio .hw.init = &(struct clk_init_data){
21658c18b41bSKonrad Dybcio .name = "gcc_ufs_tx_symbol_0_clk",
21668c18b41bSKonrad Dybcio .ops = &clk_branch2_ops,
21678c18b41bSKonrad Dybcio },
21688c18b41bSKonrad Dybcio },
21698c18b41bSKonrad Dybcio };
21708c18b41bSKonrad Dybcio
21718c18b41bSKonrad Dybcio static struct clk_branch gcc_ufs_tx_symbol_1_clk = {
21728c18b41bSKonrad Dybcio .halt_reg = 0x1d5c,
21738c18b41bSKonrad Dybcio .halt_check = BRANCH_HALT_DELAY,
21748c18b41bSKonrad Dybcio .clkr = {
21758c18b41bSKonrad Dybcio .enable_reg = 0x1d5c,
21768c18b41bSKonrad Dybcio .enable_mask = BIT(0),
21770519d1d0SKonrad Dybcio .hw.init = &(struct clk_init_data){
21788c18b41bSKonrad Dybcio .name = "gcc_ufs_tx_symbol_1_clk",
21798c18b41bSKonrad Dybcio .ops = &clk_branch2_ops,
21808c18b41bSKonrad Dybcio },
21818c18b41bSKonrad Dybcio },
21828c18b41bSKonrad Dybcio };
21838c18b41bSKonrad Dybcio
21848c18b41bSKonrad Dybcio static struct clk_branch gcc_usb2_hs_phy_sleep_clk = {
21858c18b41bSKonrad Dybcio .halt_reg = 0x04ac,
21868c18b41bSKonrad Dybcio .clkr = {
21878c18b41bSKonrad Dybcio .enable_reg = 0x04ac,
21888c18b41bSKonrad Dybcio .enable_mask = BIT(0),
21890519d1d0SKonrad Dybcio .hw.init = &(struct clk_init_data){
21908c18b41bSKonrad Dybcio .name = "gcc_usb2_hs_phy_sleep_clk",
21910519d1d0SKonrad Dybcio .parent_data = &(const struct clk_parent_data){
21920519d1d0SKonrad Dybcio .fw_name = "sleep",
21930519d1d0SKonrad Dybcio .name = "sleep"
21940519d1d0SKonrad Dybcio },
21950519d1d0SKonrad Dybcio .num_parents = 1,
21968c18b41bSKonrad Dybcio .ops = &clk_branch2_ops,
21978c18b41bSKonrad Dybcio },
21988c18b41bSKonrad Dybcio },
21998c18b41bSKonrad Dybcio };
22008c18b41bSKonrad Dybcio
2201aec89f78SBastian Köcher static struct clk_branch gcc_usb30_master_clk = {
2202aec89f78SBastian Köcher .halt_reg = 0x03c8,
2203aec89f78SBastian Köcher .clkr = {
2204aec89f78SBastian Köcher .enable_reg = 0x03c8,
2205aec89f78SBastian Köcher .enable_mask = BIT(0),
22060519d1d0SKonrad Dybcio .hw.init = &(struct clk_init_data){
2207aec89f78SBastian Köcher .name = "gcc_usb30_master_clk",
22080519d1d0SKonrad Dybcio .parent_hws = (const struct clk_hw *[]){ &usb30_master_clk_src.clkr.hw },
2209aec89f78SBastian Köcher .num_parents = 1,
2210aec89f78SBastian Köcher .flags = CLK_SET_RATE_PARENT,
2211aec89f78SBastian Köcher .ops = &clk_branch2_ops,
2212aec89f78SBastian Köcher },
2213aec89f78SBastian Köcher },
2214aec89f78SBastian Köcher };
2215aec89f78SBastian Köcher
2216aec89f78SBastian Köcher static struct clk_branch gcc_usb30_mock_utmi_clk = {
2217aec89f78SBastian Köcher .halt_reg = 0x03d0,
2218aec89f78SBastian Köcher .clkr = {
2219aec89f78SBastian Köcher .enable_reg = 0x03d0,
2220aec89f78SBastian Köcher .enable_mask = BIT(0),
22210519d1d0SKonrad Dybcio .hw.init = &(struct clk_init_data){
2222aec89f78SBastian Köcher .name = "gcc_usb30_mock_utmi_clk",
22230519d1d0SKonrad Dybcio .parent_hws = (const struct clk_hw *[]){ &usb30_mock_utmi_clk_src.clkr.hw },
2224aec89f78SBastian Köcher .num_parents = 1,
2225aec89f78SBastian Köcher .flags = CLK_SET_RATE_PARENT,
2226aec89f78SBastian Köcher .ops = &clk_branch2_ops,
2227aec89f78SBastian Köcher },
2228aec89f78SBastian Köcher },
2229aec89f78SBastian Köcher };
2230aec89f78SBastian Köcher
22318c18b41bSKonrad Dybcio static struct clk_branch gcc_usb30_sleep_clk = {
22328c18b41bSKonrad Dybcio .halt_reg = 0x03cc,
22338c18b41bSKonrad Dybcio .clkr = {
22348c18b41bSKonrad Dybcio .enable_reg = 0x03cc,
22358c18b41bSKonrad Dybcio .enable_mask = BIT(0),
22360519d1d0SKonrad Dybcio .hw.init = &(struct clk_init_data){
22378c18b41bSKonrad Dybcio .name = "gcc_usb30_sleep_clk",
22380519d1d0SKonrad Dybcio .parent_data = &(const struct clk_parent_data){
22390519d1d0SKonrad Dybcio .fw_name = "sleep",
22400519d1d0SKonrad Dybcio .name = "sleep"
22410519d1d0SKonrad Dybcio },
22420519d1d0SKonrad Dybcio .num_parents = 1,
22438c18b41bSKonrad Dybcio .ops = &clk_branch2_ops,
22448c18b41bSKonrad Dybcio },
22458c18b41bSKonrad Dybcio },
22468c18b41bSKonrad Dybcio };
22478c18b41bSKonrad Dybcio
2248aec89f78SBastian Köcher static struct clk_branch gcc_usb3_phy_aux_clk = {
2249aec89f78SBastian Köcher .halt_reg = 0x1408,
2250aec89f78SBastian Köcher .clkr = {
2251aec89f78SBastian Köcher .enable_reg = 0x1408,
2252aec89f78SBastian Köcher .enable_mask = BIT(0),
22530519d1d0SKonrad Dybcio .hw.init = &(struct clk_init_data){
2254aec89f78SBastian Köcher .name = "gcc_usb3_phy_aux_clk",
22550519d1d0SKonrad Dybcio .parent_hws = (const struct clk_hw *[]){ &usb3_phy_aux_clk_src.clkr.hw },
2256aec89f78SBastian Köcher .num_parents = 1,
2257aec89f78SBastian Köcher .flags = CLK_SET_RATE_PARENT,
2258aec89f78SBastian Köcher .ops = &clk_branch2_ops,
2259aec89f78SBastian Köcher },
2260aec89f78SBastian Köcher },
2261aec89f78SBastian Köcher };
2262aec89f78SBastian Köcher
2263b8f415c6SKonrad Dybcio static struct clk_branch gcc_usb3_phy_pipe_clk = {
2264b8f415c6SKonrad Dybcio .halt_reg = 0x140c,
2265b8f415c6SKonrad Dybcio .halt_check = BRANCH_HALT_SKIP,
2266b8f415c6SKonrad Dybcio .clkr = {
2267b8f415c6SKonrad Dybcio .enable_reg = 0x140c,
2268b8f415c6SKonrad Dybcio .enable_mask = BIT(0),
2269b8f415c6SKonrad Dybcio .hw.init = &(struct clk_init_data){
2270b8f415c6SKonrad Dybcio .name = "gcc_usb3_phy_pipe_clk",
2271b8f415c6SKonrad Dybcio .ops = &clk_branch2_ops,
2272b8f415c6SKonrad Dybcio },
2273b8f415c6SKonrad Dybcio },
2274b8f415c6SKonrad Dybcio };
2275b8f415c6SKonrad Dybcio
22768c18b41bSKonrad Dybcio static struct clk_branch gcc_usb_hs_ahb_clk = {
22778c18b41bSKonrad Dybcio .halt_reg = 0x0488,
22788c18b41bSKonrad Dybcio .clkr = {
22798c18b41bSKonrad Dybcio .enable_reg = 0x0488,
22808c18b41bSKonrad Dybcio .enable_mask = BIT(0),
22810519d1d0SKonrad Dybcio .hw.init = &(struct clk_init_data){
22828c18b41bSKonrad Dybcio .name = "gcc_usb_hs_ahb_clk",
22838c18b41bSKonrad Dybcio .ops = &clk_branch2_ops,
22848c18b41bSKonrad Dybcio },
22858c18b41bSKonrad Dybcio },
22868c18b41bSKonrad Dybcio };
22878c18b41bSKonrad Dybcio
2288aec89f78SBastian Köcher static struct clk_branch gcc_usb_hs_system_clk = {
2289aec89f78SBastian Köcher .halt_reg = 0x0484,
2290aec89f78SBastian Köcher .clkr = {
2291aec89f78SBastian Köcher .enable_reg = 0x0484,
2292aec89f78SBastian Köcher .enable_mask = BIT(0),
22930519d1d0SKonrad Dybcio .hw.init = &(struct clk_init_data){
2294aec89f78SBastian Köcher .name = "gcc_usb_hs_system_clk",
22950519d1d0SKonrad Dybcio .parent_hws = (const struct clk_hw *[]){ &usb_hs_system_clk_src.clkr.hw },
2296aec89f78SBastian Köcher .num_parents = 1,
2297aec89f78SBastian Köcher .flags = CLK_SET_RATE_PARENT,
2298aec89f78SBastian Köcher .ops = &clk_branch2_ops,
2299aec89f78SBastian Köcher },
2300aec89f78SBastian Köcher },
2301aec89f78SBastian Köcher };
2302aec89f78SBastian Köcher
23038c18b41bSKonrad Dybcio static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
23048c18b41bSKonrad Dybcio .halt_reg = 0x1a84,
23058c18b41bSKonrad Dybcio .clkr = {
23068c18b41bSKonrad Dybcio .enable_reg = 0x1a84,
23078c18b41bSKonrad Dybcio .enable_mask = BIT(0),
23080519d1d0SKonrad Dybcio .hw.init = &(struct clk_init_data){
23098c18b41bSKonrad Dybcio .name = "gcc_usb_phy_cfg_ahb2phy_clk",
23108c18b41bSKonrad Dybcio .ops = &clk_branch2_ops,
23118c18b41bSKonrad Dybcio },
23128c18b41bSKonrad Dybcio },
23138c18b41bSKonrad Dybcio };
23148c18b41bSKonrad Dybcio
2315b8f415c6SKonrad Dybcio static struct clk_branch gpll0_out_mmsscc = {
2316b8f415c6SKonrad Dybcio .halt_check = BRANCH_HALT_DELAY,
2317b8f415c6SKonrad Dybcio .clkr = {
2318b8f415c6SKonrad Dybcio .enable_reg = 0x1484,
2319b8f415c6SKonrad Dybcio .enable_mask = BIT(26),
2320b8f415c6SKonrad Dybcio .hw.init = &(struct clk_init_data){
2321b8f415c6SKonrad Dybcio .name = "gpll0_out_mmsscc",
2322b8f415c6SKonrad Dybcio .parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw },
2323b8f415c6SKonrad Dybcio .num_parents = 1,
2324b8f415c6SKonrad Dybcio .ops = &clk_branch2_ops,
2325b8f415c6SKonrad Dybcio },
2326b8f415c6SKonrad Dybcio },
2327b8f415c6SKonrad Dybcio };
2328b8f415c6SKonrad Dybcio
2329b8f415c6SKonrad Dybcio static struct clk_branch gpll0_out_msscc = {
2330b8f415c6SKonrad Dybcio .halt_check = BRANCH_HALT_DELAY,
2331b8f415c6SKonrad Dybcio .clkr = {
2332b8f415c6SKonrad Dybcio .enable_reg = 0x1484,
2333b8f415c6SKonrad Dybcio .enable_mask = BIT(27),
2334b8f415c6SKonrad Dybcio .hw.init = &(struct clk_init_data){
2335b8f415c6SKonrad Dybcio .name = "gpll0_out_msscc",
2336b8f415c6SKonrad Dybcio .parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw },
2337b8f415c6SKonrad Dybcio .num_parents = 1,
2338b8f415c6SKonrad Dybcio .ops = &clk_branch2_ops,
2339b8f415c6SKonrad Dybcio },
2340b8f415c6SKonrad Dybcio },
2341b8f415c6SKonrad Dybcio };
2342b8f415c6SKonrad Dybcio
2343b8f415c6SKonrad Dybcio static struct clk_branch pcie_0_phy_ldo = {
2344b8f415c6SKonrad Dybcio .halt_reg = 0x1e00,
2345b8f415c6SKonrad Dybcio .halt_check = BRANCH_HALT_SKIP,
2346b8f415c6SKonrad Dybcio .clkr = {
2347b8f415c6SKonrad Dybcio .enable_reg = 0x1E00,
2348b8f415c6SKonrad Dybcio .enable_mask = BIT(0),
2349b8f415c6SKonrad Dybcio .hw.init = &(struct clk_init_data){
2350b8f415c6SKonrad Dybcio .name = "pcie_0_phy_ldo",
2351b8f415c6SKonrad Dybcio .ops = &clk_branch2_ops,
2352b8f415c6SKonrad Dybcio },
2353b8f415c6SKonrad Dybcio },
2354b8f415c6SKonrad Dybcio };
2355b8f415c6SKonrad Dybcio
2356b8f415c6SKonrad Dybcio static struct clk_branch pcie_1_phy_ldo = {
2357b8f415c6SKonrad Dybcio .halt_reg = 0x1e04,
2358b8f415c6SKonrad Dybcio .halt_check = BRANCH_HALT_SKIP,
2359b8f415c6SKonrad Dybcio .clkr = {
2360b8f415c6SKonrad Dybcio .enable_reg = 0x1E04,
2361b8f415c6SKonrad Dybcio .enable_mask = BIT(0),
2362b8f415c6SKonrad Dybcio .hw.init = &(struct clk_init_data){
2363b8f415c6SKonrad Dybcio .name = "pcie_1_phy_ldo",
2364b8f415c6SKonrad Dybcio .ops = &clk_branch2_ops,
2365b8f415c6SKonrad Dybcio },
2366b8f415c6SKonrad Dybcio },
2367b8f415c6SKonrad Dybcio };
2368b8f415c6SKonrad Dybcio
2369b8f415c6SKonrad Dybcio static struct clk_branch ufs_phy_ldo = {
2370b8f415c6SKonrad Dybcio .halt_reg = 0x1e0c,
2371b8f415c6SKonrad Dybcio .halt_check = BRANCH_HALT_SKIP,
2372b8f415c6SKonrad Dybcio .clkr = {
2373b8f415c6SKonrad Dybcio .enable_reg = 0x1E0C,
2374b8f415c6SKonrad Dybcio .enable_mask = BIT(0),
2375b8f415c6SKonrad Dybcio .hw.init = &(struct clk_init_data){
2376b8f415c6SKonrad Dybcio .name = "ufs_phy_ldo",
2377b8f415c6SKonrad Dybcio .ops = &clk_branch2_ops,
2378b8f415c6SKonrad Dybcio },
2379b8f415c6SKonrad Dybcio },
2380b8f415c6SKonrad Dybcio };
2381b8f415c6SKonrad Dybcio
2382b8f415c6SKonrad Dybcio static struct clk_branch usb_ss_phy_ldo = {
2383b8f415c6SKonrad Dybcio .halt_reg = 0x1e08,
2384b8f415c6SKonrad Dybcio .halt_check = BRANCH_HALT_SKIP,
2385b8f415c6SKonrad Dybcio .clkr = {
2386b8f415c6SKonrad Dybcio .enable_reg = 0x1E08,
2387b8f415c6SKonrad Dybcio .enable_mask = BIT(0),
2388b8f415c6SKonrad Dybcio .hw.init = &(struct clk_init_data){
2389b8f415c6SKonrad Dybcio .name = "usb_ss_phy_ldo",
2390b8f415c6SKonrad Dybcio .ops = &clk_branch2_ops,
2391b8f415c6SKonrad Dybcio },
2392b8f415c6SKonrad Dybcio },
2393b8f415c6SKonrad Dybcio };
2394b8f415c6SKonrad Dybcio
2395b8f415c6SKonrad Dybcio static struct clk_branch gcc_boot_rom_ahb_clk = {
2396b8f415c6SKonrad Dybcio .halt_reg = 0x0e04,
2397b8f415c6SKonrad Dybcio .halt_check = BRANCH_HALT_VOTED,
2398b8f415c6SKonrad Dybcio .hwcg_reg = 0x0e04,
2399b8f415c6SKonrad Dybcio .hwcg_bit = 1,
2400b8f415c6SKonrad Dybcio .clkr = {
2401b8f415c6SKonrad Dybcio .enable_reg = 0x1484,
2402b8f415c6SKonrad Dybcio .enable_mask = BIT(10),
2403b8f415c6SKonrad Dybcio .hw.init = &(struct clk_init_data){
2404b8f415c6SKonrad Dybcio .name = "gcc_boot_rom_ahb_clk",
2405b8f415c6SKonrad Dybcio .ops = &clk_branch2_ops,
2406b8f415c6SKonrad Dybcio },
2407b8f415c6SKonrad Dybcio },
2408b8f415c6SKonrad Dybcio };
2409b8f415c6SKonrad Dybcio
2410b8f415c6SKonrad Dybcio static struct clk_branch gcc_prng_ahb_clk = {
2411b8f415c6SKonrad Dybcio .halt_reg = 0x0d04,
2412b8f415c6SKonrad Dybcio .halt_check = BRANCH_HALT_VOTED,
2413b8f415c6SKonrad Dybcio .clkr = {
2414b8f415c6SKonrad Dybcio .enable_reg = 0x1484,
2415b8f415c6SKonrad Dybcio .enable_mask = BIT(13),
2416b8f415c6SKonrad Dybcio .hw.init = &(struct clk_init_data){
2417b8f415c6SKonrad Dybcio .name = "gcc_prng_ahb_clk",
2418b8f415c6SKonrad Dybcio .ops = &clk_branch2_ops,
2419b8f415c6SKonrad Dybcio },
2420b8f415c6SKonrad Dybcio },
2421b8f415c6SKonrad Dybcio };
2422b8f415c6SKonrad Dybcio
24238c18b41bSKonrad Dybcio static struct gdsc pcie_0_gdsc = {
24248c18b41bSKonrad Dybcio .gdscr = 0x1ac4,
24258c18b41bSKonrad Dybcio .pd = {
24268c18b41bSKonrad Dybcio .name = "pcie_0",
24278c18b41bSKonrad Dybcio },
24288c18b41bSKonrad Dybcio .pwrsts = PWRSTS_OFF_ON,
24298c18b41bSKonrad Dybcio };
24308c18b41bSKonrad Dybcio
24318c18b41bSKonrad Dybcio static struct gdsc pcie_1_gdsc = {
24328c18b41bSKonrad Dybcio .gdscr = 0x1b44,
24338c18b41bSKonrad Dybcio .pd = {
24348c18b41bSKonrad Dybcio .name = "pcie_1",
24358c18b41bSKonrad Dybcio },
24368c18b41bSKonrad Dybcio .pwrsts = PWRSTS_OFF_ON,
24378c18b41bSKonrad Dybcio };
24388c18b41bSKonrad Dybcio
24398c18b41bSKonrad Dybcio static struct gdsc usb30_gdsc = {
24408c18b41bSKonrad Dybcio .gdscr = 0x3c4,
24418c18b41bSKonrad Dybcio .pd = {
24428c18b41bSKonrad Dybcio .name = "usb30",
24438c18b41bSKonrad Dybcio },
24448c18b41bSKonrad Dybcio .pwrsts = PWRSTS_OFF_ON,
24458c18b41bSKonrad Dybcio };
24468c18b41bSKonrad Dybcio
24478c18b41bSKonrad Dybcio static struct gdsc ufs_gdsc = {
24488c18b41bSKonrad Dybcio .gdscr = 0x1d44,
24498c18b41bSKonrad Dybcio .pd = {
24508c18b41bSKonrad Dybcio .name = "ufs",
24518c18b41bSKonrad Dybcio },
24528c18b41bSKonrad Dybcio .pwrsts = PWRSTS_OFF_ON,
24538c18b41bSKonrad Dybcio };
24548c18b41bSKonrad Dybcio
2455aec89f78SBastian Köcher static struct clk_regmap *gcc_msm8994_clocks[] = {
2456aec89f78SBastian Köcher [GPLL0_EARLY] = &gpll0_early.clkr,
2457aec89f78SBastian Köcher [GPLL0] = &gpll0.clkr,
2458aec89f78SBastian Köcher [GPLL4_EARLY] = &gpll4_early.clkr,
2459aec89f78SBastian Köcher [GPLL4] = &gpll4.clkr,
2460aec89f78SBastian Köcher [UFS_AXI_CLK_SRC] = &ufs_axi_clk_src.clkr,
2461aec89f78SBastian Köcher [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,
2462aec89f78SBastian Köcher [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
2463aec89f78SBastian Köcher [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
2464aec89f78SBastian Köcher [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
2465aec89f78SBastian Köcher [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
2466aec89f78SBastian Köcher [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
2467aec89f78SBastian Köcher [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
2468aec89f78SBastian Köcher [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
2469aec89f78SBastian Köcher [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
2470aec89f78SBastian Köcher [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
2471aec89f78SBastian Köcher [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
2472aec89f78SBastian Köcher [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
2473aec89f78SBastian Köcher [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
2474aec89f78SBastian Köcher [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
2475aec89f78SBastian Köcher [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
2476aec89f78SBastian Köcher [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
2477aec89f78SBastian Köcher [BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr,
2478aec89f78SBastian Köcher [BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr,
2479aec89f78SBastian Köcher [BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr,
2480aec89f78SBastian Köcher [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr,
2481aec89f78SBastian Köcher [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr,
2482aec89f78SBastian Köcher [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr,
2483aec89f78SBastian Köcher [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr,
2484aec89f78SBastian Köcher [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr,
2485aec89f78SBastian Köcher [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr,
2486aec89f78SBastian Köcher [BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr,
2487aec89f78SBastian Köcher [BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr,
2488aec89f78SBastian Köcher [BLSP2_QUP5_I2C_APPS_CLK_SRC] = &blsp2_qup5_i2c_apps_clk_src.clkr,
2489aec89f78SBastian Köcher [BLSP2_QUP5_SPI_APPS_CLK_SRC] = &blsp2_qup5_spi_apps_clk_src.clkr,
2490aec89f78SBastian Köcher [BLSP2_QUP6_I2C_APPS_CLK_SRC] = &blsp2_qup6_i2c_apps_clk_src.clkr,
2491aec89f78SBastian Köcher [BLSP2_QUP6_SPI_APPS_CLK_SRC] = &blsp2_qup6_spi_apps_clk_src.clkr,
2492aec89f78SBastian Köcher [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr,
2493aec89f78SBastian Köcher [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr,
2494aec89f78SBastian Köcher [BLSP2_UART3_APPS_CLK_SRC] = &blsp2_uart3_apps_clk_src.clkr,
2495aec89f78SBastian Köcher [BLSP2_UART4_APPS_CLK_SRC] = &blsp2_uart4_apps_clk_src.clkr,
2496aec89f78SBastian Köcher [BLSP2_UART5_APPS_CLK_SRC] = &blsp2_uart5_apps_clk_src.clkr,
2497aec89f78SBastian Köcher [BLSP2_UART6_APPS_CLK_SRC] = &blsp2_uart6_apps_clk_src.clkr,
2498aec89f78SBastian Köcher [GP1_CLK_SRC] = &gp1_clk_src.clkr,
2499aec89f78SBastian Köcher [GP2_CLK_SRC] = &gp2_clk_src.clkr,
2500aec89f78SBastian Köcher [GP3_CLK_SRC] = &gp3_clk_src.clkr,
2501aec89f78SBastian Köcher [PCIE_0_AUX_CLK_SRC] = &pcie_0_aux_clk_src.clkr,
2502aec89f78SBastian Köcher [PCIE_0_PIPE_CLK_SRC] = &pcie_0_pipe_clk_src.clkr,
2503aec89f78SBastian Köcher [PCIE_1_AUX_CLK_SRC] = &pcie_1_aux_clk_src.clkr,
2504aec89f78SBastian Köcher [PCIE_1_PIPE_CLK_SRC] = &pcie_1_pipe_clk_src.clkr,
2505aec89f78SBastian Köcher [PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
2506aec89f78SBastian Köcher [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
2507aec89f78SBastian Köcher [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
2508aec89f78SBastian Köcher [SDCC3_APPS_CLK_SRC] = &sdcc3_apps_clk_src.clkr,
2509aec89f78SBastian Köcher [SDCC4_APPS_CLK_SRC] = &sdcc4_apps_clk_src.clkr,
2510aec89f78SBastian Köcher [TSIF_REF_CLK_SRC] = &tsif_ref_clk_src.clkr,
2511aec89f78SBastian Köcher [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
2512aec89f78SBastian Köcher [USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr,
2513aec89f78SBastian Köcher [USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr,
2514aec89f78SBastian Köcher [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
2515aec89f78SBastian Köcher [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
2516aec89f78SBastian Köcher [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
2517aec89f78SBastian Köcher [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
2518aec89f78SBastian Köcher [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
2519aec89f78SBastian Köcher [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
2520aec89f78SBastian Köcher [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
2521aec89f78SBastian Köcher [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
2522aec89f78SBastian Köcher [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
2523aec89f78SBastian Köcher [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
2524aec89f78SBastian Köcher [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
2525aec89f78SBastian Köcher [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
2526aec89f78SBastian Köcher [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
2527aec89f78SBastian Köcher [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
2528aec89f78SBastian Köcher [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
2529aec89f78SBastian Köcher [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
2530aec89f78SBastian Köcher [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
2531aec89f78SBastian Köcher [GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr,
2532aec89f78SBastian Köcher [GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr,
2533aec89f78SBastian Köcher [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,
2534aec89f78SBastian Köcher [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr,
2535aec89f78SBastian Köcher [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr,
2536aec89f78SBastian Köcher [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr,
2537aec89f78SBastian Köcher [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr,
2538aec89f78SBastian Köcher [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr,
2539aec89f78SBastian Köcher [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr,
2540aec89f78SBastian Köcher [GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr,
2541aec89f78SBastian Köcher [GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr,
2542aec89f78SBastian Köcher [GCC_BLSP2_QUP5_I2C_APPS_CLK] = &gcc_blsp2_qup5_i2c_apps_clk.clkr,
2543aec89f78SBastian Köcher [GCC_BLSP2_QUP5_SPI_APPS_CLK] = &gcc_blsp2_qup5_spi_apps_clk.clkr,
2544aec89f78SBastian Köcher [GCC_BLSP2_QUP6_I2C_APPS_CLK] = &gcc_blsp2_qup6_i2c_apps_clk.clkr,
2545aec89f78SBastian Köcher [GCC_BLSP2_QUP6_SPI_APPS_CLK] = &gcc_blsp2_qup6_spi_apps_clk.clkr,
2546aec89f78SBastian Köcher [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr,
2547aec89f78SBastian Köcher [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr,
2548aec89f78SBastian Köcher [GCC_BLSP2_UART3_APPS_CLK] = &gcc_blsp2_uart3_apps_clk.clkr,
2549aec89f78SBastian Köcher [GCC_BLSP2_UART4_APPS_CLK] = &gcc_blsp2_uart4_apps_clk.clkr,
2550aec89f78SBastian Köcher [GCC_BLSP2_UART5_APPS_CLK] = &gcc_blsp2_uart5_apps_clk.clkr,
2551aec89f78SBastian Köcher [GCC_BLSP2_UART6_APPS_CLK] = &gcc_blsp2_uart6_apps_clk.clkr,
2552aec89f78SBastian Köcher [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
2553aec89f78SBastian Köcher [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
2554aec89f78SBastian Köcher [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
25558c18b41bSKonrad Dybcio [GCC_LPASS_Q6_AXI_CLK] = &gcc_lpass_q6_axi_clk.clkr,
25568c18b41bSKonrad Dybcio [GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr,
2557aec89f78SBastian Köcher [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
25588c18b41bSKonrad Dybcio [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
25598c18b41bSKonrad Dybcio [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
2560aec89f78SBastian Köcher [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
25618c18b41bSKonrad Dybcio [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
2562aec89f78SBastian Köcher [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
25638c18b41bSKonrad Dybcio [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
25648c18b41bSKonrad Dybcio [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
2565aec89f78SBastian Köcher [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
25668c18b41bSKonrad Dybcio [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
2567aec89f78SBastian Köcher [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
25688c18b41bSKonrad Dybcio [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
2569eaff16bcSJeremy McNicoll [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
25708c18b41bSKonrad Dybcio [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
25718c18b41bSKonrad Dybcio [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
25728c18b41bSKonrad Dybcio [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
25738c18b41bSKonrad Dybcio [GCC_SDCC3_AHB_CLK] = &gcc_sdcc3_ahb_clk.clkr,
25748c18b41bSKonrad Dybcio [GCC_SDCC3_APPS_CLK] = &gcc_sdcc3_apps_clk.clkr,
25758c18b41bSKonrad Dybcio [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
25768c18b41bSKonrad Dybcio [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
2577aec89f78SBastian Köcher [GCC_SYS_NOC_UFS_AXI_CLK] = &gcc_sys_noc_ufs_axi_clk.clkr,
2578aec89f78SBastian Köcher [GCC_SYS_NOC_USB3_AXI_CLK] = &gcc_sys_noc_usb3_axi_clk.clkr,
25798c18b41bSKonrad Dybcio [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr,
2580aec89f78SBastian Köcher [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
25818c18b41bSKonrad Dybcio [GCC_UFS_AHB_CLK] = &gcc_ufs_ahb_clk.clkr,
2582aec89f78SBastian Köcher [GCC_UFS_AXI_CLK] = &gcc_ufs_axi_clk.clkr,
2583aec89f78SBastian Köcher [GCC_UFS_RX_CFG_CLK] = &gcc_ufs_rx_cfg_clk.clkr,
25848c18b41bSKonrad Dybcio [GCC_UFS_RX_SYMBOL_0_CLK] = &gcc_ufs_rx_symbol_0_clk.clkr,
25858c18b41bSKonrad Dybcio [GCC_UFS_RX_SYMBOL_1_CLK] = &gcc_ufs_rx_symbol_1_clk.clkr,
2586aec89f78SBastian Köcher [GCC_UFS_TX_CFG_CLK] = &gcc_ufs_tx_cfg_clk.clkr,
25878c18b41bSKonrad Dybcio [GCC_UFS_TX_SYMBOL_0_CLK] = &gcc_ufs_tx_symbol_0_clk.clkr,
25888c18b41bSKonrad Dybcio [GCC_UFS_TX_SYMBOL_1_CLK] = &gcc_ufs_tx_symbol_1_clk.clkr,
25898c18b41bSKonrad Dybcio [GCC_USB2_HS_PHY_SLEEP_CLK] = &gcc_usb2_hs_phy_sleep_clk.clkr,
2590aec89f78SBastian Köcher [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,
2591aec89f78SBastian Köcher [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,
25928c18b41bSKonrad Dybcio [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr,
2593aec89f78SBastian Köcher [GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr,
2594b8f415c6SKonrad Dybcio [GCC_USB3_PHY_PIPE_CLK] = &gcc_usb3_phy_pipe_clk.clkr,
25958c18b41bSKonrad Dybcio [GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr,
2596aec89f78SBastian Köcher [GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr,
25978c18b41bSKonrad Dybcio [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr,
2598b8f415c6SKonrad Dybcio [GPLL0_OUT_MMSSCC] = &gpll0_out_mmsscc.clkr,
2599b8f415c6SKonrad Dybcio [GPLL0_OUT_MSSCC] = &gpll0_out_msscc.clkr,
2600b8f415c6SKonrad Dybcio [PCIE_0_PHY_LDO] = &pcie_0_phy_ldo.clkr,
2601b8f415c6SKonrad Dybcio [PCIE_1_PHY_LDO] = &pcie_1_phy_ldo.clkr,
2602b8f415c6SKonrad Dybcio [UFS_PHY_LDO] = &ufs_phy_ldo.clkr,
2603b8f415c6SKonrad Dybcio [USB_SS_PHY_LDO] = &usb_ss_phy_ldo.clkr,
2604b8f415c6SKonrad Dybcio [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
2605b8f415c6SKonrad Dybcio [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
26063494894aSKonrad Dybcio
26073494894aSKonrad Dybcio /*
26083494894aSKonrad Dybcio * The following clocks should NOT be managed by this driver, but they once were
26093494894aSKonrad Dybcio * mistakengly added. Now they are only here to indicate that they are not defined
26103494894aSKonrad Dybcio * on purpose, even though the names will stay in the header file (for ABI sanity).
26113494894aSKonrad Dybcio */
26123494894aSKonrad Dybcio [CONFIG_NOC_CLK_SRC] = NULL,
26133494894aSKonrad Dybcio [PERIPH_NOC_CLK_SRC] = NULL,
26143494894aSKonrad Dybcio [SYSTEM_NOC_CLK_SRC] = NULL,
26158c18b41bSKonrad Dybcio };
26168c18b41bSKonrad Dybcio
26178c18b41bSKonrad Dybcio static struct gdsc *gcc_msm8994_gdscs[] = {
261835bb1e6eSKonrad Dybcio /* This GDSC does not exist, but ABI has to remain intact */
261935bb1e6eSKonrad Dybcio [PCIE_GDSC] = NULL,
26208c18b41bSKonrad Dybcio [PCIE_0_GDSC] = &pcie_0_gdsc,
26218c18b41bSKonrad Dybcio [PCIE_1_GDSC] = &pcie_1_gdsc,
26228c18b41bSKonrad Dybcio [USB30_GDSC] = &usb30_gdsc,
26238c18b41bSKonrad Dybcio [UFS_GDSC] = &ufs_gdsc,
26248c18b41bSKonrad Dybcio };
26258c18b41bSKonrad Dybcio
26268c18b41bSKonrad Dybcio static const struct qcom_reset_map gcc_msm8994_resets[] = {
26278c18b41bSKonrad Dybcio [USB3_PHY_RESET] = { 0x1400 },
26288c18b41bSKonrad Dybcio [USB3PHY_PHY_RESET] = { 0x1404 },
2629a888dc4cSKonrad Dybcio [MSS_RESET] = { 0x1680 },
26308c18b41bSKonrad Dybcio [PCIE_PHY_0_RESET] = { 0x1b18 },
26318c18b41bSKonrad Dybcio [PCIE_PHY_1_RESET] = { 0x1b98 },
26328c18b41bSKonrad Dybcio [QUSB2_PHY_RESET] = { 0x04b8 },
2633aec89f78SBastian Köcher };
2634aec89f78SBastian Köcher
2635aec89f78SBastian Köcher static const struct regmap_config gcc_msm8994_regmap_config = {
2636aec89f78SBastian Köcher .reg_bits = 32,
2637aec89f78SBastian Köcher .reg_stride = 4,
2638aec89f78SBastian Köcher .val_bits = 32,
2639aec89f78SBastian Köcher .max_register = 0x2000,
2640aec89f78SBastian Köcher .fast_io = true,
2641aec89f78SBastian Köcher };
2642aec89f78SBastian Köcher
2643aec89f78SBastian Köcher static const struct qcom_cc_desc gcc_msm8994_desc = {
2644aec89f78SBastian Köcher .config = &gcc_msm8994_regmap_config,
2645aec89f78SBastian Köcher .clks = gcc_msm8994_clocks,
2646aec89f78SBastian Köcher .num_clks = ARRAY_SIZE(gcc_msm8994_clocks),
26478c18b41bSKonrad Dybcio .resets = gcc_msm8994_resets,
26488c18b41bSKonrad Dybcio .num_resets = ARRAY_SIZE(gcc_msm8994_resets),
26498c18b41bSKonrad Dybcio .gdscs = gcc_msm8994_gdscs,
26508c18b41bSKonrad Dybcio .num_gdscs = ARRAY_SIZE(gcc_msm8994_gdscs),
2651aec89f78SBastian Köcher };
2652aec89f78SBastian Köcher
2653aec89f78SBastian Köcher static const struct of_device_id gcc_msm8994_match_table[] = {
2654c09b8023SKonrad Dybcio { .compatible = "qcom,gcc-msm8992" },
2655c09b8023SKonrad Dybcio { .compatible = "qcom,gcc-msm8994" }, /* V2 and V2.1 */
2656aec89f78SBastian Köcher {}
2657aec89f78SBastian Köcher };
2658aec89f78SBastian Köcher MODULE_DEVICE_TABLE(of, gcc_msm8994_match_table);
2659aec89f78SBastian Köcher
gcc_msm8994_probe(struct platform_device * pdev)2660aec89f78SBastian Köcher static int gcc_msm8994_probe(struct platform_device *pdev)
2661aec89f78SBastian Köcher {
2662c09b8023SKonrad Dybcio if (of_device_is_compatible(pdev->dev.of_node, "qcom,gcc-msm8992")) {
2663c09b8023SKonrad Dybcio /* MSM8992 features less clocks and some have different freq tables */
2664c09b8023SKonrad Dybcio gcc_msm8994_desc.clks[UFS_AXI_CLK_SRC] = NULL;
2665c09b8023SKonrad Dybcio gcc_msm8994_desc.clks[GCC_LPASS_Q6_AXI_CLK] = NULL;
2666c09b8023SKonrad Dybcio gcc_msm8994_desc.clks[UFS_PHY_LDO] = NULL;
2667c09b8023SKonrad Dybcio gcc_msm8994_desc.clks[GCC_UFS_AHB_CLK] = NULL;
2668c09b8023SKonrad Dybcio gcc_msm8994_desc.clks[GCC_UFS_AXI_CLK] = NULL;
2669c09b8023SKonrad Dybcio gcc_msm8994_desc.clks[GCC_UFS_RX_CFG_CLK] = NULL;
2670c09b8023SKonrad Dybcio gcc_msm8994_desc.clks[GCC_UFS_RX_SYMBOL_0_CLK] = NULL;
2671c09b8023SKonrad Dybcio gcc_msm8994_desc.clks[GCC_UFS_RX_SYMBOL_1_CLK] = NULL;
2672c09b8023SKonrad Dybcio gcc_msm8994_desc.clks[GCC_UFS_TX_CFG_CLK] = NULL;
2673c09b8023SKonrad Dybcio gcc_msm8994_desc.clks[GCC_UFS_TX_SYMBOL_0_CLK] = NULL;
2674c09b8023SKonrad Dybcio gcc_msm8994_desc.clks[GCC_UFS_TX_SYMBOL_1_CLK] = NULL;
2675c09b8023SKonrad Dybcio
2676c09b8023SKonrad Dybcio sdcc1_apps_clk_src.freq_tbl = ftbl_sdcc1_apps_clk_src_8992;
2677c09b8023SKonrad Dybcio blsp1_qup1_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
2678c09b8023SKonrad Dybcio blsp1_qup2_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
2679c09b8023SKonrad Dybcio blsp1_qup3_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
2680c09b8023SKonrad Dybcio blsp1_qup4_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
2681c09b8023SKonrad Dybcio blsp1_qup5_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
2682c09b8023SKonrad Dybcio blsp1_qup6_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
2683c09b8023SKonrad Dybcio blsp2_qup1_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
2684c09b8023SKonrad Dybcio blsp2_qup2_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
2685c09b8023SKonrad Dybcio blsp2_qup3_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
2686c09b8023SKonrad Dybcio blsp2_qup4_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
2687c09b8023SKonrad Dybcio blsp2_qup5_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
2688c09b8023SKonrad Dybcio blsp2_qup6_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
2689c09b8023SKonrad Dybcio
2690c09b8023SKonrad Dybcio /*
2691c09b8023SKonrad Dybcio * Some 8992 boards might *possibly* use
2692c09b8023SKonrad Dybcio * PCIe1 clocks and controller, but it's not
2693c09b8023SKonrad Dybcio * standard and they should be disabled otherwise.
2694c09b8023SKonrad Dybcio */
2695c09b8023SKonrad Dybcio gcc_msm8994_desc.clks[PCIE_1_AUX_CLK_SRC] = NULL;
2696c09b8023SKonrad Dybcio gcc_msm8994_desc.clks[PCIE_1_PIPE_CLK_SRC] = NULL;
2697c09b8023SKonrad Dybcio gcc_msm8994_desc.clks[PCIE_1_PHY_LDO] = NULL;
2698c09b8023SKonrad Dybcio gcc_msm8994_desc.clks[GCC_PCIE_1_AUX_CLK] = NULL;
2699c09b8023SKonrad Dybcio gcc_msm8994_desc.clks[GCC_PCIE_1_CFG_AHB_CLK] = NULL;
2700c09b8023SKonrad Dybcio gcc_msm8994_desc.clks[GCC_PCIE_1_MSTR_AXI_CLK] = NULL;
2701c09b8023SKonrad Dybcio gcc_msm8994_desc.clks[GCC_PCIE_1_PIPE_CLK] = NULL;
2702c09b8023SKonrad Dybcio gcc_msm8994_desc.clks[GCC_PCIE_1_SLV_AXI_CLK] = NULL;
2703c09b8023SKonrad Dybcio gcc_msm8994_desc.clks[GCC_SYS_NOC_UFS_AXI_CLK] = NULL;
2704c09b8023SKonrad Dybcio }
2705c09b8023SKonrad Dybcio
2706aec89f78SBastian Köcher return qcom_cc_probe(pdev, &gcc_msm8994_desc);
2707aec89f78SBastian Köcher }
2708aec89f78SBastian Köcher
2709aec89f78SBastian Köcher static struct platform_driver gcc_msm8994_driver = {
2710aec89f78SBastian Köcher .probe = gcc_msm8994_probe,
2711aec89f78SBastian Köcher .driver = {
2712aec89f78SBastian Köcher .name = "gcc-msm8994",
2713aec89f78SBastian Köcher .of_match_table = gcc_msm8994_match_table,
2714aec89f78SBastian Köcher },
2715aec89f78SBastian Köcher };
2716aec89f78SBastian Köcher
gcc_msm8994_init(void)2717aec89f78SBastian Köcher static int __init gcc_msm8994_init(void)
2718aec89f78SBastian Köcher {
2719aec89f78SBastian Köcher return platform_driver_register(&gcc_msm8994_driver);
2720aec89f78SBastian Köcher }
2721aec89f78SBastian Köcher core_initcall(gcc_msm8994_init);
2722aec89f78SBastian Köcher
gcc_msm8994_exit(void)2723aec89f78SBastian Köcher static void __exit gcc_msm8994_exit(void)
2724aec89f78SBastian Köcher {
2725aec89f78SBastian Köcher platform_driver_unregister(&gcc_msm8994_driver);
2726aec89f78SBastian Köcher }
2727aec89f78SBastian Köcher module_exit(gcc_msm8994_exit);
2728aec89f78SBastian Köcher
2729aec89f78SBastian Köcher MODULE_DESCRIPTION("Qualcomm GCC MSM8994 Driver");
2730aec89f78SBastian Köcher MODULE_LICENSE("GPL v2");
2731aec89f78SBastian Köcher MODULE_ALIAS("platform:gcc-msm8994");
2732