1 /* 2 * Copyright (c) 2014, The Linux Foundation. All rights reserved. 3 * 4 * This software is licensed under the terms of the GNU General Public 5 * License version 2, as published by the Free Software Foundation, and 6 * may be copied, distributed, and modified under those terms. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14 #include <linux/kernel.h> 15 #include <linux/bitops.h> 16 #include <linux/err.h> 17 #include <linux/platform_device.h> 18 #include <linux/module.h> 19 #include <linux/of.h> 20 #include <linux/of_device.h> 21 #include <linux/clk-provider.h> 22 #include <linux/regmap.h> 23 #include <linux/reset-controller.h> 24 25 #include <dt-bindings/clock/qcom,gcc-ipq806x.h> 26 #include <dt-bindings/reset/qcom,gcc-ipq806x.h> 27 28 #include "common.h" 29 #include "clk-regmap.h" 30 #include "clk-pll.h" 31 #include "clk-rcg.h" 32 #include "clk-branch.h" 33 #include "reset.h" 34 35 static struct clk_pll pll3 = { 36 .l_reg = 0x3164, 37 .m_reg = 0x3168, 38 .n_reg = 0x316c, 39 .config_reg = 0x3174, 40 .mode_reg = 0x3160, 41 .status_reg = 0x3178, 42 .status_bit = 16, 43 .clkr.hw.init = &(struct clk_init_data){ 44 .name = "pll3", 45 .parent_names = (const char *[]){ "pxo" }, 46 .num_parents = 1, 47 .ops = &clk_pll_ops, 48 }, 49 }; 50 51 static struct clk_pll pll8 = { 52 .l_reg = 0x3144, 53 .m_reg = 0x3148, 54 .n_reg = 0x314c, 55 .config_reg = 0x3154, 56 .mode_reg = 0x3140, 57 .status_reg = 0x3158, 58 .status_bit = 16, 59 .clkr.hw.init = &(struct clk_init_data){ 60 .name = "pll8", 61 .parent_names = (const char *[]){ "pxo" }, 62 .num_parents = 1, 63 .ops = &clk_pll_ops, 64 }, 65 }; 66 67 static struct clk_regmap pll8_vote = { 68 .enable_reg = 0x34c0, 69 .enable_mask = BIT(8), 70 .hw.init = &(struct clk_init_data){ 71 .name = "pll8_vote", 72 .parent_names = (const char *[]){ "pll8" }, 73 .num_parents = 1, 74 .ops = &clk_pll_vote_ops, 75 }, 76 }; 77 78 static struct clk_pll pll14 = { 79 .l_reg = 0x31c4, 80 .m_reg = 0x31c8, 81 .n_reg = 0x31cc, 82 .config_reg = 0x31d4, 83 .mode_reg = 0x31c0, 84 .status_reg = 0x31d8, 85 .status_bit = 16, 86 .clkr.hw.init = &(struct clk_init_data){ 87 .name = "pll14", 88 .parent_names = (const char *[]){ "pxo" }, 89 .num_parents = 1, 90 .ops = &clk_pll_ops, 91 }, 92 }; 93 94 static struct clk_regmap pll14_vote = { 95 .enable_reg = 0x34c0, 96 .enable_mask = BIT(14), 97 .hw.init = &(struct clk_init_data){ 98 .name = "pll14_vote", 99 .parent_names = (const char *[]){ "pll14" }, 100 .num_parents = 1, 101 .ops = &clk_pll_vote_ops, 102 }, 103 }; 104 105 #define P_PXO 0 106 #define P_PLL8 1 107 #define P_PLL3 1 108 #define P_PLL0 2 109 #define P_CXO 2 110 111 static const u8 gcc_pxo_pll8_map[] = { 112 [P_PXO] = 0, 113 [P_PLL8] = 3, 114 }; 115 116 static const char *gcc_pxo_pll8[] = { 117 "pxo", 118 "pll8_vote", 119 }; 120 121 static const u8 gcc_pxo_pll8_cxo_map[] = { 122 [P_PXO] = 0, 123 [P_PLL8] = 3, 124 [P_CXO] = 5, 125 }; 126 127 static const char *gcc_pxo_pll8_cxo[] = { 128 "pxo", 129 "pll8_vote", 130 "cxo", 131 }; 132 133 static const u8 gcc_pxo_pll3_map[] = { 134 [P_PXO] = 0, 135 [P_PLL3] = 1, 136 }; 137 138 static const u8 gcc_pxo_pll3_sata_map[] = { 139 [P_PXO] = 0, 140 [P_PLL3] = 6, 141 }; 142 143 static const char *gcc_pxo_pll3[] = { 144 "pxo", 145 "pll3", 146 }; 147 148 static const u8 gcc_pxo_pll8_pll0[] = { 149 [P_PXO] = 0, 150 [P_PLL8] = 3, 151 [P_PLL0] = 2, 152 }; 153 154 static const char *gcc_pxo_pll8_pll0_map[] = { 155 "pxo", 156 "pll8_vote", 157 "pll0", 158 }; 159 160 static struct freq_tbl clk_tbl_gsbi_uart[] = { 161 { 1843200, P_PLL8, 2, 6, 625 }, 162 { 3686400, P_PLL8, 2, 12, 625 }, 163 { 7372800, P_PLL8, 2, 24, 625 }, 164 { 14745600, P_PLL8, 2, 48, 625 }, 165 { 16000000, P_PLL8, 4, 1, 6 }, 166 { 24000000, P_PLL8, 4, 1, 4 }, 167 { 32000000, P_PLL8, 4, 1, 3 }, 168 { 40000000, P_PLL8, 1, 5, 48 }, 169 { 46400000, P_PLL8, 1, 29, 240 }, 170 { 48000000, P_PLL8, 4, 1, 2 }, 171 { 51200000, P_PLL8, 1, 2, 15 }, 172 { 56000000, P_PLL8, 1, 7, 48 }, 173 { 58982400, P_PLL8, 1, 96, 625 }, 174 { 64000000, P_PLL8, 2, 1, 3 }, 175 { } 176 }; 177 178 static struct clk_rcg gsbi1_uart_src = { 179 .ns_reg = 0x29d4, 180 .md_reg = 0x29d0, 181 .mn = { 182 .mnctr_en_bit = 8, 183 .mnctr_reset_bit = 7, 184 .mnctr_mode_shift = 5, 185 .n_val_shift = 16, 186 .m_val_shift = 16, 187 .width = 16, 188 }, 189 .p = { 190 .pre_div_shift = 3, 191 .pre_div_width = 2, 192 }, 193 .s = { 194 .src_sel_shift = 0, 195 .parent_map = gcc_pxo_pll8_map, 196 }, 197 .freq_tbl = clk_tbl_gsbi_uart, 198 .clkr = { 199 .enable_reg = 0x29d4, 200 .enable_mask = BIT(11), 201 .hw.init = &(struct clk_init_data){ 202 .name = "gsbi1_uart_src", 203 .parent_names = gcc_pxo_pll8, 204 .num_parents = 2, 205 .ops = &clk_rcg_ops, 206 .flags = CLK_SET_PARENT_GATE, 207 }, 208 }, 209 }; 210 211 static struct clk_branch gsbi1_uart_clk = { 212 .halt_reg = 0x2fcc, 213 .halt_bit = 12, 214 .clkr = { 215 .enable_reg = 0x29d4, 216 .enable_mask = BIT(9), 217 .hw.init = &(struct clk_init_data){ 218 .name = "gsbi1_uart_clk", 219 .parent_names = (const char *[]){ 220 "gsbi1_uart_src", 221 }, 222 .num_parents = 1, 223 .ops = &clk_branch_ops, 224 .flags = CLK_SET_RATE_PARENT, 225 }, 226 }, 227 }; 228 229 static struct clk_rcg gsbi2_uart_src = { 230 .ns_reg = 0x29f4, 231 .md_reg = 0x29f0, 232 .mn = { 233 .mnctr_en_bit = 8, 234 .mnctr_reset_bit = 7, 235 .mnctr_mode_shift = 5, 236 .n_val_shift = 16, 237 .m_val_shift = 16, 238 .width = 16, 239 }, 240 .p = { 241 .pre_div_shift = 3, 242 .pre_div_width = 2, 243 }, 244 .s = { 245 .src_sel_shift = 0, 246 .parent_map = gcc_pxo_pll8_map, 247 }, 248 .freq_tbl = clk_tbl_gsbi_uart, 249 .clkr = { 250 .enable_reg = 0x29f4, 251 .enable_mask = BIT(11), 252 .hw.init = &(struct clk_init_data){ 253 .name = "gsbi2_uart_src", 254 .parent_names = gcc_pxo_pll8, 255 .num_parents = 2, 256 .ops = &clk_rcg_ops, 257 .flags = CLK_SET_PARENT_GATE, 258 }, 259 }, 260 }; 261 262 static struct clk_branch gsbi2_uart_clk = { 263 .halt_reg = 0x2fcc, 264 .halt_bit = 8, 265 .clkr = { 266 .enable_reg = 0x29f4, 267 .enable_mask = BIT(9), 268 .hw.init = &(struct clk_init_data){ 269 .name = "gsbi2_uart_clk", 270 .parent_names = (const char *[]){ 271 "gsbi2_uart_src", 272 }, 273 .num_parents = 1, 274 .ops = &clk_branch_ops, 275 .flags = CLK_SET_RATE_PARENT, 276 }, 277 }, 278 }; 279 280 static struct clk_rcg gsbi4_uart_src = { 281 .ns_reg = 0x2a34, 282 .md_reg = 0x2a30, 283 .mn = { 284 .mnctr_en_bit = 8, 285 .mnctr_reset_bit = 7, 286 .mnctr_mode_shift = 5, 287 .n_val_shift = 16, 288 .m_val_shift = 16, 289 .width = 16, 290 }, 291 .p = { 292 .pre_div_shift = 3, 293 .pre_div_width = 2, 294 }, 295 .s = { 296 .src_sel_shift = 0, 297 .parent_map = gcc_pxo_pll8_map, 298 }, 299 .freq_tbl = clk_tbl_gsbi_uart, 300 .clkr = { 301 .enable_reg = 0x2a34, 302 .enable_mask = BIT(11), 303 .hw.init = &(struct clk_init_data){ 304 .name = "gsbi4_uart_src", 305 .parent_names = gcc_pxo_pll8, 306 .num_parents = 2, 307 .ops = &clk_rcg_ops, 308 .flags = CLK_SET_PARENT_GATE, 309 }, 310 }, 311 }; 312 313 static struct clk_branch gsbi4_uart_clk = { 314 .halt_reg = 0x2fd0, 315 .halt_bit = 26, 316 .clkr = { 317 .enable_reg = 0x2a34, 318 .enable_mask = BIT(9), 319 .hw.init = &(struct clk_init_data){ 320 .name = "gsbi4_uart_clk", 321 .parent_names = (const char *[]){ 322 "gsbi4_uart_src", 323 }, 324 .num_parents = 1, 325 .ops = &clk_branch_ops, 326 .flags = CLK_SET_RATE_PARENT, 327 }, 328 }, 329 }; 330 331 static struct clk_rcg gsbi5_uart_src = { 332 .ns_reg = 0x2a54, 333 .md_reg = 0x2a50, 334 .mn = { 335 .mnctr_en_bit = 8, 336 .mnctr_reset_bit = 7, 337 .mnctr_mode_shift = 5, 338 .n_val_shift = 16, 339 .m_val_shift = 16, 340 .width = 16, 341 }, 342 .p = { 343 .pre_div_shift = 3, 344 .pre_div_width = 2, 345 }, 346 .s = { 347 .src_sel_shift = 0, 348 .parent_map = gcc_pxo_pll8_map, 349 }, 350 .freq_tbl = clk_tbl_gsbi_uart, 351 .clkr = { 352 .enable_reg = 0x2a54, 353 .enable_mask = BIT(11), 354 .hw.init = &(struct clk_init_data){ 355 .name = "gsbi5_uart_src", 356 .parent_names = gcc_pxo_pll8, 357 .num_parents = 2, 358 .ops = &clk_rcg_ops, 359 .flags = CLK_SET_PARENT_GATE, 360 }, 361 }, 362 }; 363 364 static struct clk_branch gsbi5_uart_clk = { 365 .halt_reg = 0x2fd0, 366 .halt_bit = 22, 367 .clkr = { 368 .enable_reg = 0x2a54, 369 .enable_mask = BIT(9), 370 .hw.init = &(struct clk_init_data){ 371 .name = "gsbi5_uart_clk", 372 .parent_names = (const char *[]){ 373 "gsbi5_uart_src", 374 }, 375 .num_parents = 1, 376 .ops = &clk_branch_ops, 377 .flags = CLK_SET_RATE_PARENT, 378 }, 379 }, 380 }; 381 382 static struct clk_rcg gsbi6_uart_src = { 383 .ns_reg = 0x2a74, 384 .md_reg = 0x2a70, 385 .mn = { 386 .mnctr_en_bit = 8, 387 .mnctr_reset_bit = 7, 388 .mnctr_mode_shift = 5, 389 .n_val_shift = 16, 390 .m_val_shift = 16, 391 .width = 16, 392 }, 393 .p = { 394 .pre_div_shift = 3, 395 .pre_div_width = 2, 396 }, 397 .s = { 398 .src_sel_shift = 0, 399 .parent_map = gcc_pxo_pll8_map, 400 }, 401 .freq_tbl = clk_tbl_gsbi_uart, 402 .clkr = { 403 .enable_reg = 0x2a74, 404 .enable_mask = BIT(11), 405 .hw.init = &(struct clk_init_data){ 406 .name = "gsbi6_uart_src", 407 .parent_names = gcc_pxo_pll8, 408 .num_parents = 2, 409 .ops = &clk_rcg_ops, 410 .flags = CLK_SET_PARENT_GATE, 411 }, 412 }, 413 }; 414 415 static struct clk_branch gsbi6_uart_clk = { 416 .halt_reg = 0x2fd0, 417 .halt_bit = 18, 418 .clkr = { 419 .enable_reg = 0x2a74, 420 .enable_mask = BIT(9), 421 .hw.init = &(struct clk_init_data){ 422 .name = "gsbi6_uart_clk", 423 .parent_names = (const char *[]){ 424 "gsbi6_uart_src", 425 }, 426 .num_parents = 1, 427 .ops = &clk_branch_ops, 428 .flags = CLK_SET_RATE_PARENT, 429 }, 430 }, 431 }; 432 433 static struct clk_rcg gsbi7_uart_src = { 434 .ns_reg = 0x2a94, 435 .md_reg = 0x2a90, 436 .mn = { 437 .mnctr_en_bit = 8, 438 .mnctr_reset_bit = 7, 439 .mnctr_mode_shift = 5, 440 .n_val_shift = 16, 441 .m_val_shift = 16, 442 .width = 16, 443 }, 444 .p = { 445 .pre_div_shift = 3, 446 .pre_div_width = 2, 447 }, 448 .s = { 449 .src_sel_shift = 0, 450 .parent_map = gcc_pxo_pll8_map, 451 }, 452 .freq_tbl = clk_tbl_gsbi_uart, 453 .clkr = { 454 .enable_reg = 0x2a94, 455 .enable_mask = BIT(11), 456 .hw.init = &(struct clk_init_data){ 457 .name = "gsbi7_uart_src", 458 .parent_names = gcc_pxo_pll8, 459 .num_parents = 2, 460 .ops = &clk_rcg_ops, 461 .flags = CLK_SET_PARENT_GATE, 462 }, 463 }, 464 }; 465 466 static struct clk_branch gsbi7_uart_clk = { 467 .halt_reg = 0x2fd0, 468 .halt_bit = 14, 469 .clkr = { 470 .enable_reg = 0x2a94, 471 .enable_mask = BIT(9), 472 .hw.init = &(struct clk_init_data){ 473 .name = "gsbi7_uart_clk", 474 .parent_names = (const char *[]){ 475 "gsbi7_uart_src", 476 }, 477 .num_parents = 1, 478 .ops = &clk_branch_ops, 479 .flags = CLK_SET_RATE_PARENT, 480 }, 481 }, 482 }; 483 484 static struct freq_tbl clk_tbl_gsbi_qup[] = { 485 { 1100000, P_PXO, 1, 2, 49 }, 486 { 5400000, P_PXO, 1, 1, 5 }, 487 { 10800000, P_PXO, 1, 2, 5 }, 488 { 15060000, P_PLL8, 1, 2, 51 }, 489 { 24000000, P_PLL8, 4, 1, 4 }, 490 { 25600000, P_PLL8, 1, 1, 15 }, 491 { 27000000, P_PXO, 1, 0, 0 }, 492 { 48000000, P_PLL8, 4, 1, 2 }, 493 { 51200000, P_PLL8, 1, 2, 15 }, 494 { } 495 }; 496 497 static struct clk_rcg gsbi1_qup_src = { 498 .ns_reg = 0x29cc, 499 .md_reg = 0x29c8, 500 .mn = { 501 .mnctr_en_bit = 8, 502 .mnctr_reset_bit = 7, 503 .mnctr_mode_shift = 5, 504 .n_val_shift = 16, 505 .m_val_shift = 16, 506 .width = 8, 507 }, 508 .p = { 509 .pre_div_shift = 3, 510 .pre_div_width = 2, 511 }, 512 .s = { 513 .src_sel_shift = 0, 514 .parent_map = gcc_pxo_pll8_map, 515 }, 516 .freq_tbl = clk_tbl_gsbi_qup, 517 .clkr = { 518 .enable_reg = 0x29cc, 519 .enable_mask = BIT(11), 520 .hw.init = &(struct clk_init_data){ 521 .name = "gsbi1_qup_src", 522 .parent_names = gcc_pxo_pll8, 523 .num_parents = 2, 524 .ops = &clk_rcg_ops, 525 .flags = CLK_SET_PARENT_GATE, 526 }, 527 }, 528 }; 529 530 static struct clk_branch gsbi1_qup_clk = { 531 .halt_reg = 0x2fcc, 532 .halt_bit = 11, 533 .clkr = { 534 .enable_reg = 0x29cc, 535 .enable_mask = BIT(9), 536 .hw.init = &(struct clk_init_data){ 537 .name = "gsbi1_qup_clk", 538 .parent_names = (const char *[]){ "gsbi1_qup_src" }, 539 .num_parents = 1, 540 .ops = &clk_branch_ops, 541 .flags = CLK_SET_RATE_PARENT, 542 }, 543 }, 544 }; 545 546 static struct clk_rcg gsbi2_qup_src = { 547 .ns_reg = 0x29ec, 548 .md_reg = 0x29e8, 549 .mn = { 550 .mnctr_en_bit = 8, 551 .mnctr_reset_bit = 7, 552 .mnctr_mode_shift = 5, 553 .n_val_shift = 16, 554 .m_val_shift = 16, 555 .width = 8, 556 }, 557 .p = { 558 .pre_div_shift = 3, 559 .pre_div_width = 2, 560 }, 561 .s = { 562 .src_sel_shift = 0, 563 .parent_map = gcc_pxo_pll8_map, 564 }, 565 .freq_tbl = clk_tbl_gsbi_qup, 566 .clkr = { 567 .enable_reg = 0x29ec, 568 .enable_mask = BIT(11), 569 .hw.init = &(struct clk_init_data){ 570 .name = "gsbi2_qup_src", 571 .parent_names = gcc_pxo_pll8, 572 .num_parents = 2, 573 .ops = &clk_rcg_ops, 574 .flags = CLK_SET_PARENT_GATE, 575 }, 576 }, 577 }; 578 579 static struct clk_branch gsbi2_qup_clk = { 580 .halt_reg = 0x2fcc, 581 .halt_bit = 6, 582 .clkr = { 583 .enable_reg = 0x29ec, 584 .enable_mask = BIT(9), 585 .hw.init = &(struct clk_init_data){ 586 .name = "gsbi2_qup_clk", 587 .parent_names = (const char *[]){ "gsbi2_qup_src" }, 588 .num_parents = 1, 589 .ops = &clk_branch_ops, 590 .flags = CLK_SET_RATE_PARENT, 591 }, 592 }, 593 }; 594 595 static struct clk_rcg gsbi4_qup_src = { 596 .ns_reg = 0x2a2c, 597 .md_reg = 0x2a28, 598 .mn = { 599 .mnctr_en_bit = 8, 600 .mnctr_reset_bit = 7, 601 .mnctr_mode_shift = 5, 602 .n_val_shift = 16, 603 .m_val_shift = 16, 604 .width = 8, 605 }, 606 .p = { 607 .pre_div_shift = 3, 608 .pre_div_width = 2, 609 }, 610 .s = { 611 .src_sel_shift = 0, 612 .parent_map = gcc_pxo_pll8_map, 613 }, 614 .freq_tbl = clk_tbl_gsbi_qup, 615 .clkr = { 616 .enable_reg = 0x2a2c, 617 .enable_mask = BIT(11), 618 .hw.init = &(struct clk_init_data){ 619 .name = "gsbi4_qup_src", 620 .parent_names = gcc_pxo_pll8, 621 .num_parents = 2, 622 .ops = &clk_rcg_ops, 623 .flags = CLK_SET_PARENT_GATE, 624 }, 625 }, 626 }; 627 628 static struct clk_branch gsbi4_qup_clk = { 629 .halt_reg = 0x2fd0, 630 .halt_bit = 24, 631 .clkr = { 632 .enable_reg = 0x2a2c, 633 .enable_mask = BIT(9), 634 .hw.init = &(struct clk_init_data){ 635 .name = "gsbi4_qup_clk", 636 .parent_names = (const char *[]){ "gsbi4_qup_src" }, 637 .num_parents = 1, 638 .ops = &clk_branch_ops, 639 .flags = CLK_SET_RATE_PARENT, 640 }, 641 }, 642 }; 643 644 static struct clk_rcg gsbi5_qup_src = { 645 .ns_reg = 0x2a4c, 646 .md_reg = 0x2a48, 647 .mn = { 648 .mnctr_en_bit = 8, 649 .mnctr_reset_bit = 7, 650 .mnctr_mode_shift = 5, 651 .n_val_shift = 16, 652 .m_val_shift = 16, 653 .width = 8, 654 }, 655 .p = { 656 .pre_div_shift = 3, 657 .pre_div_width = 2, 658 }, 659 .s = { 660 .src_sel_shift = 0, 661 .parent_map = gcc_pxo_pll8_map, 662 }, 663 .freq_tbl = clk_tbl_gsbi_qup, 664 .clkr = { 665 .enable_reg = 0x2a4c, 666 .enable_mask = BIT(11), 667 .hw.init = &(struct clk_init_data){ 668 .name = "gsbi5_qup_src", 669 .parent_names = gcc_pxo_pll8, 670 .num_parents = 2, 671 .ops = &clk_rcg_ops, 672 .flags = CLK_SET_PARENT_GATE, 673 }, 674 }, 675 }; 676 677 static struct clk_branch gsbi5_qup_clk = { 678 .halt_reg = 0x2fd0, 679 .halt_bit = 20, 680 .clkr = { 681 .enable_reg = 0x2a4c, 682 .enable_mask = BIT(9), 683 .hw.init = &(struct clk_init_data){ 684 .name = "gsbi5_qup_clk", 685 .parent_names = (const char *[]){ "gsbi5_qup_src" }, 686 .num_parents = 1, 687 .ops = &clk_branch_ops, 688 .flags = CLK_SET_RATE_PARENT, 689 }, 690 }, 691 }; 692 693 static struct clk_rcg gsbi6_qup_src = { 694 .ns_reg = 0x2a6c, 695 .md_reg = 0x2a68, 696 .mn = { 697 .mnctr_en_bit = 8, 698 .mnctr_reset_bit = 7, 699 .mnctr_mode_shift = 5, 700 .n_val_shift = 16, 701 .m_val_shift = 16, 702 .width = 8, 703 }, 704 .p = { 705 .pre_div_shift = 3, 706 .pre_div_width = 2, 707 }, 708 .s = { 709 .src_sel_shift = 0, 710 .parent_map = gcc_pxo_pll8_map, 711 }, 712 .freq_tbl = clk_tbl_gsbi_qup, 713 .clkr = { 714 .enable_reg = 0x2a6c, 715 .enable_mask = BIT(11), 716 .hw.init = &(struct clk_init_data){ 717 .name = "gsbi6_qup_src", 718 .parent_names = gcc_pxo_pll8, 719 .num_parents = 2, 720 .ops = &clk_rcg_ops, 721 .flags = CLK_SET_PARENT_GATE, 722 }, 723 }, 724 }; 725 726 static struct clk_branch gsbi6_qup_clk = { 727 .halt_reg = 0x2fd0, 728 .halt_bit = 16, 729 .clkr = { 730 .enable_reg = 0x2a6c, 731 .enable_mask = BIT(9), 732 .hw.init = &(struct clk_init_data){ 733 .name = "gsbi6_qup_clk", 734 .parent_names = (const char *[]){ "gsbi6_qup_src" }, 735 .num_parents = 1, 736 .ops = &clk_branch_ops, 737 .flags = CLK_SET_RATE_PARENT, 738 }, 739 }, 740 }; 741 742 static struct clk_rcg gsbi7_qup_src = { 743 .ns_reg = 0x2a8c, 744 .md_reg = 0x2a88, 745 .mn = { 746 .mnctr_en_bit = 8, 747 .mnctr_reset_bit = 7, 748 .mnctr_mode_shift = 5, 749 .n_val_shift = 16, 750 .m_val_shift = 16, 751 .width = 8, 752 }, 753 .p = { 754 .pre_div_shift = 3, 755 .pre_div_width = 2, 756 }, 757 .s = { 758 .src_sel_shift = 0, 759 .parent_map = gcc_pxo_pll8_map, 760 }, 761 .freq_tbl = clk_tbl_gsbi_qup, 762 .clkr = { 763 .enable_reg = 0x2a8c, 764 .enable_mask = BIT(11), 765 .hw.init = &(struct clk_init_data){ 766 .name = "gsbi7_qup_src", 767 .parent_names = gcc_pxo_pll8, 768 .num_parents = 2, 769 .ops = &clk_rcg_ops, 770 .flags = CLK_SET_PARENT_GATE, 771 }, 772 }, 773 }; 774 775 static struct clk_branch gsbi7_qup_clk = { 776 .halt_reg = 0x2fd0, 777 .halt_bit = 12, 778 .clkr = { 779 .enable_reg = 0x2a8c, 780 .enable_mask = BIT(9), 781 .hw.init = &(struct clk_init_data){ 782 .name = "gsbi7_qup_clk", 783 .parent_names = (const char *[]){ "gsbi7_qup_src" }, 784 .num_parents = 1, 785 .ops = &clk_branch_ops, 786 .flags = CLK_SET_RATE_PARENT, 787 }, 788 }, 789 }; 790 791 static struct clk_branch gsbi1_h_clk = { 792 .hwcg_reg = 0x29c0, 793 .hwcg_bit = 6, 794 .halt_reg = 0x2fcc, 795 .halt_bit = 13, 796 .clkr = { 797 .enable_reg = 0x29c0, 798 .enable_mask = BIT(4), 799 .hw.init = &(struct clk_init_data){ 800 .name = "gsbi1_h_clk", 801 .ops = &clk_branch_ops, 802 .flags = CLK_IS_ROOT, 803 }, 804 }, 805 }; 806 807 static struct clk_branch gsbi2_h_clk = { 808 .hwcg_reg = 0x29e0, 809 .hwcg_bit = 6, 810 .halt_reg = 0x2fcc, 811 .halt_bit = 9, 812 .clkr = { 813 .enable_reg = 0x29e0, 814 .enable_mask = BIT(4), 815 .hw.init = &(struct clk_init_data){ 816 .name = "gsbi2_h_clk", 817 .ops = &clk_branch_ops, 818 .flags = CLK_IS_ROOT, 819 }, 820 }, 821 }; 822 823 static struct clk_branch gsbi4_h_clk = { 824 .hwcg_reg = 0x2a20, 825 .hwcg_bit = 6, 826 .halt_reg = 0x2fd0, 827 .halt_bit = 27, 828 .clkr = { 829 .enable_reg = 0x2a20, 830 .enable_mask = BIT(4), 831 .hw.init = &(struct clk_init_data){ 832 .name = "gsbi4_h_clk", 833 .ops = &clk_branch_ops, 834 .flags = CLK_IS_ROOT, 835 }, 836 }, 837 }; 838 839 static struct clk_branch gsbi5_h_clk = { 840 .hwcg_reg = 0x2a40, 841 .hwcg_bit = 6, 842 .halt_reg = 0x2fd0, 843 .halt_bit = 23, 844 .clkr = { 845 .enable_reg = 0x2a40, 846 .enable_mask = BIT(4), 847 .hw.init = &(struct clk_init_data){ 848 .name = "gsbi5_h_clk", 849 .ops = &clk_branch_ops, 850 .flags = CLK_IS_ROOT, 851 }, 852 }, 853 }; 854 855 static struct clk_branch gsbi6_h_clk = { 856 .hwcg_reg = 0x2a60, 857 .hwcg_bit = 6, 858 .halt_reg = 0x2fd0, 859 .halt_bit = 19, 860 .clkr = { 861 .enable_reg = 0x2a60, 862 .enable_mask = BIT(4), 863 .hw.init = &(struct clk_init_data){ 864 .name = "gsbi6_h_clk", 865 .ops = &clk_branch_ops, 866 .flags = CLK_IS_ROOT, 867 }, 868 }, 869 }; 870 871 static struct clk_branch gsbi7_h_clk = { 872 .hwcg_reg = 0x2a80, 873 .hwcg_bit = 6, 874 .halt_reg = 0x2fd0, 875 .halt_bit = 15, 876 .clkr = { 877 .enable_reg = 0x2a80, 878 .enable_mask = BIT(4), 879 .hw.init = &(struct clk_init_data){ 880 .name = "gsbi7_h_clk", 881 .ops = &clk_branch_ops, 882 .flags = CLK_IS_ROOT, 883 }, 884 }, 885 }; 886 887 static const struct freq_tbl clk_tbl_gp[] = { 888 { 12500000, P_PXO, 2, 0, 0 }, 889 { 25000000, P_PXO, 1, 0, 0 }, 890 { 64000000, P_PLL8, 2, 1, 3 }, 891 { 76800000, P_PLL8, 1, 1, 5 }, 892 { 96000000, P_PLL8, 4, 0, 0 }, 893 { 128000000, P_PLL8, 3, 0, 0 }, 894 { 192000000, P_PLL8, 2, 0, 0 }, 895 { } 896 }; 897 898 static struct clk_rcg gp0_src = { 899 .ns_reg = 0x2d24, 900 .md_reg = 0x2d00, 901 .mn = { 902 .mnctr_en_bit = 8, 903 .mnctr_reset_bit = 7, 904 .mnctr_mode_shift = 5, 905 .n_val_shift = 16, 906 .m_val_shift = 16, 907 .width = 8, 908 }, 909 .p = { 910 .pre_div_shift = 3, 911 .pre_div_width = 2, 912 }, 913 .s = { 914 .src_sel_shift = 0, 915 .parent_map = gcc_pxo_pll8_cxo_map, 916 }, 917 .freq_tbl = clk_tbl_gp, 918 .clkr = { 919 .enable_reg = 0x2d24, 920 .enable_mask = BIT(11), 921 .hw.init = &(struct clk_init_data){ 922 .name = "gp0_src", 923 .parent_names = gcc_pxo_pll8_cxo, 924 .num_parents = 3, 925 .ops = &clk_rcg_ops, 926 .flags = CLK_SET_PARENT_GATE, 927 }, 928 } 929 }; 930 931 static struct clk_branch gp0_clk = { 932 .halt_reg = 0x2fd8, 933 .halt_bit = 7, 934 .clkr = { 935 .enable_reg = 0x2d24, 936 .enable_mask = BIT(9), 937 .hw.init = &(struct clk_init_data){ 938 .name = "gp0_clk", 939 .parent_names = (const char *[]){ "gp0_src" }, 940 .num_parents = 1, 941 .ops = &clk_branch_ops, 942 .flags = CLK_SET_RATE_PARENT, 943 }, 944 }, 945 }; 946 947 static struct clk_rcg gp1_src = { 948 .ns_reg = 0x2d44, 949 .md_reg = 0x2d40, 950 .mn = { 951 .mnctr_en_bit = 8, 952 .mnctr_reset_bit = 7, 953 .mnctr_mode_shift = 5, 954 .n_val_shift = 16, 955 .m_val_shift = 16, 956 .width = 8, 957 }, 958 .p = { 959 .pre_div_shift = 3, 960 .pre_div_width = 2, 961 }, 962 .s = { 963 .src_sel_shift = 0, 964 .parent_map = gcc_pxo_pll8_cxo_map, 965 }, 966 .freq_tbl = clk_tbl_gp, 967 .clkr = { 968 .enable_reg = 0x2d44, 969 .enable_mask = BIT(11), 970 .hw.init = &(struct clk_init_data){ 971 .name = "gp1_src", 972 .parent_names = gcc_pxo_pll8_cxo, 973 .num_parents = 3, 974 .ops = &clk_rcg_ops, 975 .flags = CLK_SET_RATE_GATE, 976 }, 977 } 978 }; 979 980 static struct clk_branch gp1_clk = { 981 .halt_reg = 0x2fd8, 982 .halt_bit = 6, 983 .clkr = { 984 .enable_reg = 0x2d44, 985 .enable_mask = BIT(9), 986 .hw.init = &(struct clk_init_data){ 987 .name = "gp1_clk", 988 .parent_names = (const char *[]){ "gp1_src" }, 989 .num_parents = 1, 990 .ops = &clk_branch_ops, 991 .flags = CLK_SET_RATE_PARENT, 992 }, 993 }, 994 }; 995 996 static struct clk_rcg gp2_src = { 997 .ns_reg = 0x2d64, 998 .md_reg = 0x2d60, 999 .mn = { 1000 .mnctr_en_bit = 8, 1001 .mnctr_reset_bit = 7, 1002 .mnctr_mode_shift = 5, 1003 .n_val_shift = 16, 1004 .m_val_shift = 16, 1005 .width = 8, 1006 }, 1007 .p = { 1008 .pre_div_shift = 3, 1009 .pre_div_width = 2, 1010 }, 1011 .s = { 1012 .src_sel_shift = 0, 1013 .parent_map = gcc_pxo_pll8_cxo_map, 1014 }, 1015 .freq_tbl = clk_tbl_gp, 1016 .clkr = { 1017 .enable_reg = 0x2d64, 1018 .enable_mask = BIT(11), 1019 .hw.init = &(struct clk_init_data){ 1020 .name = "gp2_src", 1021 .parent_names = gcc_pxo_pll8_cxo, 1022 .num_parents = 3, 1023 .ops = &clk_rcg_ops, 1024 .flags = CLK_SET_RATE_GATE, 1025 }, 1026 } 1027 }; 1028 1029 static struct clk_branch gp2_clk = { 1030 .halt_reg = 0x2fd8, 1031 .halt_bit = 5, 1032 .clkr = { 1033 .enable_reg = 0x2d64, 1034 .enable_mask = BIT(9), 1035 .hw.init = &(struct clk_init_data){ 1036 .name = "gp2_clk", 1037 .parent_names = (const char *[]){ "gp2_src" }, 1038 .num_parents = 1, 1039 .ops = &clk_branch_ops, 1040 .flags = CLK_SET_RATE_PARENT, 1041 }, 1042 }, 1043 }; 1044 1045 static struct clk_branch pmem_clk = { 1046 .hwcg_reg = 0x25a0, 1047 .hwcg_bit = 6, 1048 .halt_reg = 0x2fc8, 1049 .halt_bit = 20, 1050 .clkr = { 1051 .enable_reg = 0x25a0, 1052 .enable_mask = BIT(4), 1053 .hw.init = &(struct clk_init_data){ 1054 .name = "pmem_clk", 1055 .ops = &clk_branch_ops, 1056 .flags = CLK_IS_ROOT, 1057 }, 1058 }, 1059 }; 1060 1061 static struct clk_rcg prng_src = { 1062 .ns_reg = 0x2e80, 1063 .p = { 1064 .pre_div_shift = 3, 1065 .pre_div_width = 4, 1066 }, 1067 .s = { 1068 .src_sel_shift = 0, 1069 .parent_map = gcc_pxo_pll8_map, 1070 }, 1071 .clkr = { 1072 .hw.init = &(struct clk_init_data){ 1073 .name = "prng_src", 1074 .parent_names = gcc_pxo_pll8, 1075 .num_parents = 2, 1076 .ops = &clk_rcg_ops, 1077 }, 1078 }, 1079 }; 1080 1081 static struct clk_branch prng_clk = { 1082 .halt_reg = 0x2fd8, 1083 .halt_check = BRANCH_HALT_VOTED, 1084 .halt_bit = 10, 1085 .clkr = { 1086 .enable_reg = 0x3080, 1087 .enable_mask = BIT(10), 1088 .hw.init = &(struct clk_init_data){ 1089 .name = "prng_clk", 1090 .parent_names = (const char *[]){ "prng_src" }, 1091 .num_parents = 1, 1092 .ops = &clk_branch_ops, 1093 }, 1094 }, 1095 }; 1096 1097 static const struct freq_tbl clk_tbl_sdc[] = { 1098 { 144000, P_PXO, 5, 18,625 }, 1099 { 400000, P_PLL8, 4, 1, 240 }, 1100 { 16000000, P_PLL8, 4, 1, 6 }, 1101 { 17070000, P_PLL8, 1, 2, 45 }, 1102 { 20210000, P_PLL8, 1, 1, 19 }, 1103 { 24000000, P_PLL8, 4, 1, 4 }, 1104 { 48000000, P_PLL8, 4, 1, 2 }, 1105 { 64000000, P_PLL8, 3, 1, 2 }, 1106 { 96000000, P_PLL8, 4, 0, 0 }, 1107 { 192000000, P_PLL8, 2, 0, 0 }, 1108 { } 1109 }; 1110 1111 static struct clk_rcg sdc1_src = { 1112 .ns_reg = 0x282c, 1113 .md_reg = 0x2828, 1114 .mn = { 1115 .mnctr_en_bit = 8, 1116 .mnctr_reset_bit = 7, 1117 .mnctr_mode_shift = 5, 1118 .n_val_shift = 16, 1119 .m_val_shift = 16, 1120 .width = 8, 1121 }, 1122 .p = { 1123 .pre_div_shift = 3, 1124 .pre_div_width = 2, 1125 }, 1126 .s = { 1127 .src_sel_shift = 0, 1128 .parent_map = gcc_pxo_pll8_map, 1129 }, 1130 .freq_tbl = clk_tbl_sdc, 1131 .clkr = { 1132 .enable_reg = 0x282c, 1133 .enable_mask = BIT(11), 1134 .hw.init = &(struct clk_init_data){ 1135 .name = "sdc1_src", 1136 .parent_names = gcc_pxo_pll8, 1137 .num_parents = 2, 1138 .ops = &clk_rcg_ops, 1139 .flags = CLK_SET_RATE_GATE, 1140 }, 1141 } 1142 }; 1143 1144 static struct clk_branch sdc1_clk = { 1145 .halt_reg = 0x2fc8, 1146 .halt_bit = 6, 1147 .clkr = { 1148 .enable_reg = 0x282c, 1149 .enable_mask = BIT(9), 1150 .hw.init = &(struct clk_init_data){ 1151 .name = "sdc1_clk", 1152 .parent_names = (const char *[]){ "sdc1_src" }, 1153 .num_parents = 1, 1154 .ops = &clk_branch_ops, 1155 .flags = CLK_SET_RATE_PARENT, 1156 }, 1157 }, 1158 }; 1159 1160 static struct clk_rcg sdc3_src = { 1161 .ns_reg = 0x286c, 1162 .md_reg = 0x2868, 1163 .mn = { 1164 .mnctr_en_bit = 8, 1165 .mnctr_reset_bit = 7, 1166 .mnctr_mode_shift = 5, 1167 .n_val_shift = 16, 1168 .m_val_shift = 16, 1169 .width = 8, 1170 }, 1171 .p = { 1172 .pre_div_shift = 3, 1173 .pre_div_width = 2, 1174 }, 1175 .s = { 1176 .src_sel_shift = 0, 1177 .parent_map = gcc_pxo_pll8_map, 1178 }, 1179 .freq_tbl = clk_tbl_sdc, 1180 .clkr = { 1181 .enable_reg = 0x286c, 1182 .enable_mask = BIT(11), 1183 .hw.init = &(struct clk_init_data){ 1184 .name = "sdc3_src", 1185 .parent_names = gcc_pxo_pll8, 1186 .num_parents = 2, 1187 .ops = &clk_rcg_ops, 1188 .flags = CLK_SET_RATE_GATE, 1189 }, 1190 } 1191 }; 1192 1193 static struct clk_branch sdc3_clk = { 1194 .halt_reg = 0x2fc8, 1195 .halt_bit = 4, 1196 .clkr = { 1197 .enable_reg = 0x286c, 1198 .enable_mask = BIT(9), 1199 .hw.init = &(struct clk_init_data){ 1200 .name = "sdc3_clk", 1201 .parent_names = (const char *[]){ "sdc3_src" }, 1202 .num_parents = 1, 1203 .ops = &clk_branch_ops, 1204 .flags = CLK_SET_RATE_PARENT, 1205 }, 1206 }, 1207 }; 1208 1209 static struct clk_branch sdc1_h_clk = { 1210 .hwcg_reg = 0x2820, 1211 .hwcg_bit = 6, 1212 .halt_reg = 0x2fc8, 1213 .halt_bit = 11, 1214 .clkr = { 1215 .enable_reg = 0x2820, 1216 .enable_mask = BIT(4), 1217 .hw.init = &(struct clk_init_data){ 1218 .name = "sdc1_h_clk", 1219 .ops = &clk_branch_ops, 1220 .flags = CLK_IS_ROOT, 1221 }, 1222 }, 1223 }; 1224 1225 static struct clk_branch sdc3_h_clk = { 1226 .hwcg_reg = 0x2860, 1227 .hwcg_bit = 6, 1228 .halt_reg = 0x2fc8, 1229 .halt_bit = 9, 1230 .clkr = { 1231 .enable_reg = 0x2860, 1232 .enable_mask = BIT(4), 1233 .hw.init = &(struct clk_init_data){ 1234 .name = "sdc3_h_clk", 1235 .ops = &clk_branch_ops, 1236 .flags = CLK_IS_ROOT, 1237 }, 1238 }, 1239 }; 1240 1241 static const struct freq_tbl clk_tbl_tsif_ref[] = { 1242 { 105000, P_PXO, 1, 1, 256 }, 1243 { } 1244 }; 1245 1246 static struct clk_rcg tsif_ref_src = { 1247 .ns_reg = 0x2710, 1248 .md_reg = 0x270c, 1249 .mn = { 1250 .mnctr_en_bit = 8, 1251 .mnctr_reset_bit = 7, 1252 .mnctr_mode_shift = 5, 1253 .n_val_shift = 16, 1254 .m_val_shift = 16, 1255 .width = 16, 1256 }, 1257 .p = { 1258 .pre_div_shift = 3, 1259 .pre_div_width = 2, 1260 }, 1261 .s = { 1262 .src_sel_shift = 0, 1263 .parent_map = gcc_pxo_pll8_map, 1264 }, 1265 .freq_tbl = clk_tbl_tsif_ref, 1266 .clkr = { 1267 .enable_reg = 0x2710, 1268 .enable_mask = BIT(11), 1269 .hw.init = &(struct clk_init_data){ 1270 .name = "tsif_ref_src", 1271 .parent_names = gcc_pxo_pll8, 1272 .num_parents = 2, 1273 .ops = &clk_rcg_ops, 1274 .flags = CLK_SET_RATE_GATE, 1275 }, 1276 } 1277 }; 1278 1279 static struct clk_branch tsif_ref_clk = { 1280 .halt_reg = 0x2fd4, 1281 .halt_bit = 5, 1282 .clkr = { 1283 .enable_reg = 0x2710, 1284 .enable_mask = BIT(9), 1285 .hw.init = &(struct clk_init_data){ 1286 .name = "tsif_ref_clk", 1287 .parent_names = (const char *[]){ "tsif_ref_src" }, 1288 .num_parents = 1, 1289 .ops = &clk_branch_ops, 1290 .flags = CLK_SET_RATE_PARENT, 1291 }, 1292 }, 1293 }; 1294 1295 static struct clk_branch tsif_h_clk = { 1296 .hwcg_reg = 0x2700, 1297 .hwcg_bit = 6, 1298 .halt_reg = 0x2fd4, 1299 .halt_bit = 7, 1300 .clkr = { 1301 .enable_reg = 0x2700, 1302 .enable_mask = BIT(4), 1303 .hw.init = &(struct clk_init_data){ 1304 .name = "tsif_h_clk", 1305 .ops = &clk_branch_ops, 1306 .flags = CLK_IS_ROOT, 1307 }, 1308 }, 1309 }; 1310 1311 static struct clk_branch dma_bam_h_clk = { 1312 .hwcg_reg = 0x25c0, 1313 .hwcg_bit = 6, 1314 .halt_reg = 0x2fc8, 1315 .halt_bit = 12, 1316 .clkr = { 1317 .enable_reg = 0x25c0, 1318 .enable_mask = BIT(4), 1319 .hw.init = &(struct clk_init_data){ 1320 .name = "dma_bam_h_clk", 1321 .ops = &clk_branch_ops, 1322 .flags = CLK_IS_ROOT, 1323 }, 1324 }, 1325 }; 1326 1327 static struct clk_branch adm0_clk = { 1328 .halt_reg = 0x2fdc, 1329 .halt_check = BRANCH_HALT_VOTED, 1330 .halt_bit = 12, 1331 .clkr = { 1332 .enable_reg = 0x3080, 1333 .enable_mask = BIT(2), 1334 .hw.init = &(struct clk_init_data){ 1335 .name = "adm0_clk", 1336 .ops = &clk_branch_ops, 1337 .flags = CLK_IS_ROOT, 1338 }, 1339 }, 1340 }; 1341 1342 static struct clk_branch adm0_pbus_clk = { 1343 .hwcg_reg = 0x2208, 1344 .hwcg_bit = 6, 1345 .halt_reg = 0x2fdc, 1346 .halt_check = BRANCH_HALT_VOTED, 1347 .halt_bit = 11, 1348 .clkr = { 1349 .enable_reg = 0x3080, 1350 .enable_mask = BIT(3), 1351 .hw.init = &(struct clk_init_data){ 1352 .name = "adm0_pbus_clk", 1353 .ops = &clk_branch_ops, 1354 .flags = CLK_IS_ROOT, 1355 }, 1356 }, 1357 }; 1358 1359 static struct clk_branch pmic_arb0_h_clk = { 1360 .halt_reg = 0x2fd8, 1361 .halt_check = BRANCH_HALT_VOTED, 1362 .halt_bit = 22, 1363 .clkr = { 1364 .enable_reg = 0x3080, 1365 .enable_mask = BIT(8), 1366 .hw.init = &(struct clk_init_data){ 1367 .name = "pmic_arb0_h_clk", 1368 .ops = &clk_branch_ops, 1369 .flags = CLK_IS_ROOT, 1370 }, 1371 }, 1372 }; 1373 1374 static struct clk_branch pmic_arb1_h_clk = { 1375 .halt_reg = 0x2fd8, 1376 .halt_check = BRANCH_HALT_VOTED, 1377 .halt_bit = 21, 1378 .clkr = { 1379 .enable_reg = 0x3080, 1380 .enable_mask = BIT(9), 1381 .hw.init = &(struct clk_init_data){ 1382 .name = "pmic_arb1_h_clk", 1383 .ops = &clk_branch_ops, 1384 .flags = CLK_IS_ROOT, 1385 }, 1386 }, 1387 }; 1388 1389 static struct clk_branch pmic_ssbi2_clk = { 1390 .halt_reg = 0x2fd8, 1391 .halt_check = BRANCH_HALT_VOTED, 1392 .halt_bit = 23, 1393 .clkr = { 1394 .enable_reg = 0x3080, 1395 .enable_mask = BIT(7), 1396 .hw.init = &(struct clk_init_data){ 1397 .name = "pmic_ssbi2_clk", 1398 .ops = &clk_branch_ops, 1399 .flags = CLK_IS_ROOT, 1400 }, 1401 }, 1402 }; 1403 1404 static struct clk_branch rpm_msg_ram_h_clk = { 1405 .hwcg_reg = 0x27e0, 1406 .hwcg_bit = 6, 1407 .halt_reg = 0x2fd8, 1408 .halt_check = BRANCH_HALT_VOTED, 1409 .halt_bit = 12, 1410 .clkr = { 1411 .enable_reg = 0x3080, 1412 .enable_mask = BIT(6), 1413 .hw.init = &(struct clk_init_data){ 1414 .name = "rpm_msg_ram_h_clk", 1415 .ops = &clk_branch_ops, 1416 .flags = CLK_IS_ROOT, 1417 }, 1418 }, 1419 }; 1420 1421 static const struct freq_tbl clk_tbl_pcie_ref[] = { 1422 { 100000000, P_PLL3, 12, 0, 0 }, 1423 { } 1424 }; 1425 1426 static struct clk_rcg pcie_ref_src = { 1427 .ns_reg = 0x3860, 1428 .p = { 1429 .pre_div_shift = 3, 1430 .pre_div_width = 4, 1431 }, 1432 .s = { 1433 .src_sel_shift = 0, 1434 .parent_map = gcc_pxo_pll3_map, 1435 }, 1436 .freq_tbl = clk_tbl_pcie_ref, 1437 .clkr = { 1438 .enable_reg = 0x3860, 1439 .enable_mask = BIT(11), 1440 .hw.init = &(struct clk_init_data){ 1441 .name = "pcie_ref_src", 1442 .parent_names = gcc_pxo_pll3, 1443 .num_parents = 2, 1444 .ops = &clk_rcg_ops, 1445 .flags = CLK_SET_RATE_GATE, 1446 }, 1447 }, 1448 }; 1449 1450 static struct clk_branch pcie_ref_src_clk = { 1451 .halt_reg = 0x2fdc, 1452 .halt_bit = 30, 1453 .clkr = { 1454 .enable_reg = 0x3860, 1455 .enable_mask = BIT(9), 1456 .hw.init = &(struct clk_init_data){ 1457 .name = "pcie_ref_src_clk", 1458 .parent_names = (const char *[]){ "pcie_ref_src" }, 1459 .num_parents = 1, 1460 .ops = &clk_branch_ops, 1461 .flags = CLK_SET_RATE_PARENT, 1462 }, 1463 }, 1464 }; 1465 1466 static struct clk_branch pcie_a_clk = { 1467 .halt_reg = 0x2fc0, 1468 .halt_bit = 13, 1469 .clkr = { 1470 .enable_reg = 0x22c0, 1471 .enable_mask = BIT(4), 1472 .hw.init = &(struct clk_init_data){ 1473 .name = "pcie_a_clk", 1474 .ops = &clk_branch_ops, 1475 .flags = CLK_IS_ROOT, 1476 }, 1477 }, 1478 }; 1479 1480 static struct clk_branch pcie_aux_clk = { 1481 .halt_reg = 0x2fdc, 1482 .halt_bit = 31, 1483 .clkr = { 1484 .enable_reg = 0x22c8, 1485 .enable_mask = BIT(4), 1486 .hw.init = &(struct clk_init_data){ 1487 .name = "pcie_aux_clk", 1488 .ops = &clk_branch_ops, 1489 .flags = CLK_IS_ROOT, 1490 }, 1491 }, 1492 }; 1493 1494 static struct clk_branch pcie_h_clk = { 1495 .halt_reg = 0x2fd4, 1496 .halt_bit = 8, 1497 .clkr = { 1498 .enable_reg = 0x22cc, 1499 .enable_mask = BIT(4), 1500 .hw.init = &(struct clk_init_data){ 1501 .name = "pcie_h_clk", 1502 .ops = &clk_branch_ops, 1503 .flags = CLK_IS_ROOT, 1504 }, 1505 }, 1506 }; 1507 1508 static struct clk_branch pcie_phy_clk = { 1509 .halt_reg = 0x2fdc, 1510 .halt_bit = 29, 1511 .clkr = { 1512 .enable_reg = 0x22d0, 1513 .enable_mask = BIT(4), 1514 .hw.init = &(struct clk_init_data){ 1515 .name = "pcie_phy_clk", 1516 .ops = &clk_branch_ops, 1517 .flags = CLK_IS_ROOT, 1518 }, 1519 }, 1520 }; 1521 1522 static struct clk_rcg pcie1_ref_src = { 1523 .ns_reg = 0x3aa0, 1524 .p = { 1525 .pre_div_shift = 3, 1526 .pre_div_width = 4, 1527 }, 1528 .s = { 1529 .src_sel_shift = 0, 1530 .parent_map = gcc_pxo_pll3_map, 1531 }, 1532 .freq_tbl = clk_tbl_pcie_ref, 1533 .clkr = { 1534 .enable_reg = 0x3aa0, 1535 .enable_mask = BIT(11), 1536 .hw.init = &(struct clk_init_data){ 1537 .name = "pcie1_ref_src", 1538 .parent_names = gcc_pxo_pll3, 1539 .num_parents = 2, 1540 .ops = &clk_rcg_ops, 1541 .flags = CLK_SET_RATE_GATE, 1542 }, 1543 }, 1544 }; 1545 1546 static struct clk_branch pcie1_ref_src_clk = { 1547 .halt_reg = 0x2fdc, 1548 .halt_bit = 27, 1549 .clkr = { 1550 .enable_reg = 0x3aa0, 1551 .enable_mask = BIT(9), 1552 .hw.init = &(struct clk_init_data){ 1553 .name = "pcie1_ref_src_clk", 1554 .parent_names = (const char *[]){ "pcie1_ref_src" }, 1555 .num_parents = 1, 1556 .ops = &clk_branch_ops, 1557 .flags = CLK_SET_RATE_PARENT, 1558 }, 1559 }, 1560 }; 1561 1562 static struct clk_branch pcie1_a_clk = { 1563 .halt_reg = 0x2fc0, 1564 .halt_bit = 10, 1565 .clkr = { 1566 .enable_reg = 0x3a80, 1567 .enable_mask = BIT(4), 1568 .hw.init = &(struct clk_init_data){ 1569 .name = "pcie1_a_clk", 1570 .ops = &clk_branch_ops, 1571 .flags = CLK_IS_ROOT, 1572 }, 1573 }, 1574 }; 1575 1576 static struct clk_branch pcie1_aux_clk = { 1577 .halt_reg = 0x2fdc, 1578 .halt_bit = 28, 1579 .clkr = { 1580 .enable_reg = 0x3a88, 1581 .enable_mask = BIT(4), 1582 .hw.init = &(struct clk_init_data){ 1583 .name = "pcie1_aux_clk", 1584 .ops = &clk_branch_ops, 1585 .flags = CLK_IS_ROOT, 1586 }, 1587 }, 1588 }; 1589 1590 static struct clk_branch pcie1_h_clk = { 1591 .halt_reg = 0x2fd4, 1592 .halt_bit = 9, 1593 .clkr = { 1594 .enable_reg = 0x3a8c, 1595 .enable_mask = BIT(4), 1596 .hw.init = &(struct clk_init_data){ 1597 .name = "pcie1_h_clk", 1598 .ops = &clk_branch_ops, 1599 .flags = CLK_IS_ROOT, 1600 }, 1601 }, 1602 }; 1603 1604 static struct clk_branch pcie1_phy_clk = { 1605 .halt_reg = 0x2fdc, 1606 .halt_bit = 26, 1607 .clkr = { 1608 .enable_reg = 0x3a90, 1609 .enable_mask = BIT(4), 1610 .hw.init = &(struct clk_init_data){ 1611 .name = "pcie1_phy_clk", 1612 .ops = &clk_branch_ops, 1613 .flags = CLK_IS_ROOT, 1614 }, 1615 }, 1616 }; 1617 1618 static struct clk_rcg pcie2_ref_src = { 1619 .ns_reg = 0x3ae0, 1620 .p = { 1621 .pre_div_shift = 3, 1622 .pre_div_width = 4, 1623 }, 1624 .s = { 1625 .src_sel_shift = 0, 1626 .parent_map = gcc_pxo_pll3_map, 1627 }, 1628 .freq_tbl = clk_tbl_pcie_ref, 1629 .clkr = { 1630 .enable_reg = 0x3ae0, 1631 .enable_mask = BIT(11), 1632 .hw.init = &(struct clk_init_data){ 1633 .name = "pcie2_ref_src", 1634 .parent_names = gcc_pxo_pll3, 1635 .num_parents = 2, 1636 .ops = &clk_rcg_ops, 1637 .flags = CLK_SET_RATE_GATE, 1638 }, 1639 }, 1640 }; 1641 1642 static struct clk_branch pcie2_ref_src_clk = { 1643 .halt_reg = 0x2fdc, 1644 .halt_bit = 24, 1645 .clkr = { 1646 .enable_reg = 0x3ae0, 1647 .enable_mask = BIT(9), 1648 .hw.init = &(struct clk_init_data){ 1649 .name = "pcie2_ref_src_clk", 1650 .parent_names = (const char *[]){ "pcie2_ref_src" }, 1651 .num_parents = 1, 1652 .ops = &clk_branch_ops, 1653 .flags = CLK_SET_RATE_PARENT, 1654 }, 1655 }, 1656 }; 1657 1658 static struct clk_branch pcie2_a_clk = { 1659 .halt_reg = 0x2fc0, 1660 .halt_bit = 9, 1661 .clkr = { 1662 .enable_reg = 0x3ac0, 1663 .enable_mask = BIT(4), 1664 .hw.init = &(struct clk_init_data){ 1665 .name = "pcie2_a_clk", 1666 .ops = &clk_branch_ops, 1667 .flags = CLK_IS_ROOT, 1668 }, 1669 }, 1670 }; 1671 1672 static struct clk_branch pcie2_aux_clk = { 1673 .halt_reg = 0x2fdc, 1674 .halt_bit = 25, 1675 .clkr = { 1676 .enable_reg = 0x3ac8, 1677 .enable_mask = BIT(4), 1678 .hw.init = &(struct clk_init_data){ 1679 .name = "pcie2_aux_clk", 1680 .ops = &clk_branch_ops, 1681 .flags = CLK_IS_ROOT, 1682 }, 1683 }, 1684 }; 1685 1686 static struct clk_branch pcie2_h_clk = { 1687 .halt_reg = 0x2fd4, 1688 .halt_bit = 10, 1689 .clkr = { 1690 .enable_reg = 0x3acc, 1691 .enable_mask = BIT(4), 1692 .hw.init = &(struct clk_init_data){ 1693 .name = "pcie2_h_clk", 1694 .ops = &clk_branch_ops, 1695 .flags = CLK_IS_ROOT, 1696 }, 1697 }, 1698 }; 1699 1700 static struct clk_branch pcie2_phy_clk = { 1701 .halt_reg = 0x2fdc, 1702 .halt_bit = 23, 1703 .clkr = { 1704 .enable_reg = 0x3ad0, 1705 .enable_mask = BIT(4), 1706 .hw.init = &(struct clk_init_data){ 1707 .name = "pcie2_phy_clk", 1708 .ops = &clk_branch_ops, 1709 .flags = CLK_IS_ROOT, 1710 }, 1711 }, 1712 }; 1713 1714 static const struct freq_tbl clk_tbl_sata_ref[] = { 1715 { 100000000, P_PLL3, 12, 0, 0 }, 1716 { } 1717 }; 1718 1719 static struct clk_rcg sata_ref_src = { 1720 .ns_reg = 0x2c08, 1721 .p = { 1722 .pre_div_shift = 3, 1723 .pre_div_width = 4, 1724 }, 1725 .s = { 1726 .src_sel_shift = 0, 1727 .parent_map = gcc_pxo_pll3_sata_map, 1728 }, 1729 .freq_tbl = clk_tbl_sata_ref, 1730 .clkr = { 1731 .enable_reg = 0x2c08, 1732 .enable_mask = BIT(7), 1733 .hw.init = &(struct clk_init_data){ 1734 .name = "sata_ref_src", 1735 .parent_names = gcc_pxo_pll3, 1736 .num_parents = 2, 1737 .ops = &clk_rcg_ops, 1738 .flags = CLK_SET_RATE_GATE, 1739 }, 1740 }, 1741 }; 1742 1743 static struct clk_branch sata_rxoob_clk = { 1744 .halt_reg = 0x2fdc, 1745 .halt_bit = 20, 1746 .clkr = { 1747 .enable_reg = 0x2c0c, 1748 .enable_mask = BIT(4), 1749 .hw.init = &(struct clk_init_data){ 1750 .name = "sata_rxoob_clk", 1751 .parent_names = (const char *[]){ "sata_ref_src" }, 1752 .num_parents = 1, 1753 .ops = &clk_branch_ops, 1754 .flags = CLK_SET_RATE_PARENT, 1755 }, 1756 }, 1757 }; 1758 1759 static struct clk_branch sata_pmalive_clk = { 1760 .halt_reg = 0x2fdc, 1761 .halt_bit = 19, 1762 .clkr = { 1763 .enable_reg = 0x2c10, 1764 .enable_mask = BIT(4), 1765 .hw.init = &(struct clk_init_data){ 1766 .name = "sata_pmalive_clk", 1767 .parent_names = (const char *[]){ "sata_ref_src" }, 1768 .num_parents = 1, 1769 .ops = &clk_branch_ops, 1770 .flags = CLK_SET_RATE_PARENT, 1771 }, 1772 }, 1773 }; 1774 1775 static struct clk_branch sata_phy_ref_clk = { 1776 .halt_reg = 0x2fdc, 1777 .halt_bit = 18, 1778 .clkr = { 1779 .enable_reg = 0x2c14, 1780 .enable_mask = BIT(4), 1781 .hw.init = &(struct clk_init_data){ 1782 .name = "sata_phy_ref_clk", 1783 .parent_names = (const char *[]){ "pxo" }, 1784 .num_parents = 1, 1785 .ops = &clk_branch_ops, 1786 }, 1787 }, 1788 }; 1789 1790 static struct clk_branch sata_a_clk = { 1791 .halt_reg = 0x2fc0, 1792 .halt_bit = 12, 1793 .clkr = { 1794 .enable_reg = 0x2c20, 1795 .enable_mask = BIT(4), 1796 .hw.init = &(struct clk_init_data){ 1797 .name = "sata_a_clk", 1798 .ops = &clk_branch_ops, 1799 .flags = CLK_IS_ROOT, 1800 }, 1801 }, 1802 }; 1803 1804 static struct clk_branch sata_h_clk = { 1805 .halt_reg = 0x2fdc, 1806 .halt_bit = 21, 1807 .clkr = { 1808 .enable_reg = 0x2c00, 1809 .enable_mask = BIT(4), 1810 .hw.init = &(struct clk_init_data){ 1811 .name = "sata_h_clk", 1812 .ops = &clk_branch_ops, 1813 .flags = CLK_IS_ROOT, 1814 }, 1815 }, 1816 }; 1817 1818 static struct clk_branch sfab_sata_s_h_clk = { 1819 .halt_reg = 0x2fc4, 1820 .halt_bit = 14, 1821 .clkr = { 1822 .enable_reg = 0x2480, 1823 .enable_mask = BIT(4), 1824 .hw.init = &(struct clk_init_data){ 1825 .name = "sfab_sata_s_h_clk", 1826 .ops = &clk_branch_ops, 1827 .flags = CLK_IS_ROOT, 1828 }, 1829 }, 1830 }; 1831 1832 static struct clk_branch sata_phy_cfg_clk = { 1833 .halt_reg = 0x2fcc, 1834 .halt_bit = 14, 1835 .clkr = { 1836 .enable_reg = 0x2c40, 1837 .enable_mask = BIT(4), 1838 .hw.init = &(struct clk_init_data){ 1839 .name = "sata_phy_cfg_clk", 1840 .ops = &clk_branch_ops, 1841 .flags = CLK_IS_ROOT, 1842 }, 1843 }, 1844 }; 1845 1846 static const struct freq_tbl clk_tbl_usb30_master[] = { 1847 { 125000000, P_PLL0, 1, 5, 32 }, 1848 { } 1849 }; 1850 1851 static struct clk_rcg usb30_master_clk_src = { 1852 .ns_reg = 0x3b2c, 1853 .md_reg = 0x3b28, 1854 .mn = { 1855 .mnctr_en_bit = 8, 1856 .mnctr_reset_bit = 7, 1857 .mnctr_mode_shift = 5, 1858 .n_val_shift = 16, 1859 .m_val_shift = 16, 1860 .width = 8, 1861 }, 1862 .p = { 1863 .pre_div_shift = 3, 1864 .pre_div_width = 2, 1865 }, 1866 .s = { 1867 .src_sel_shift = 0, 1868 .parent_map = gcc_pxo_pll8_pll0, 1869 }, 1870 .freq_tbl = clk_tbl_usb30_master, 1871 .clkr = { 1872 .enable_reg = 0x3b2c, 1873 .enable_mask = BIT(11), 1874 .hw.init = &(struct clk_init_data){ 1875 .name = "usb30_master_ref_src", 1876 .parent_names = gcc_pxo_pll8_pll0_map, 1877 .num_parents = 3, 1878 .ops = &clk_rcg_ops, 1879 .flags = CLK_SET_RATE_GATE, 1880 }, 1881 }, 1882 }; 1883 1884 static struct clk_branch usb30_0_branch_clk = { 1885 .halt_reg = 0x2fc4, 1886 .halt_bit = 22, 1887 .clkr = { 1888 .enable_reg = 0x3b24, 1889 .enable_mask = BIT(4), 1890 .hw.init = &(struct clk_init_data){ 1891 .name = "usb30_0_branch_clk", 1892 .parent_names = (const char *[]){ "usb30_master_ref_src", }, 1893 .num_parents = 1, 1894 .ops = &clk_branch_ops, 1895 .flags = CLK_SET_RATE_PARENT, 1896 }, 1897 }, 1898 }; 1899 1900 static struct clk_branch usb30_1_branch_clk = { 1901 .halt_reg = 0x2fc4, 1902 .halt_bit = 17, 1903 .clkr = { 1904 .enable_reg = 0x3b34, 1905 .enable_mask = BIT(4), 1906 .hw.init = &(struct clk_init_data){ 1907 .name = "usb30_1_branch_clk", 1908 .parent_names = (const char *[]){ "usb30_master_ref_src", }, 1909 .num_parents = 1, 1910 .ops = &clk_branch_ops, 1911 .flags = CLK_SET_RATE_PARENT, 1912 }, 1913 }, 1914 }; 1915 1916 static const struct freq_tbl clk_tbl_usb30_utmi[] = { 1917 { 60000000, P_PLL8, 1, 5, 32 }, 1918 { } 1919 }; 1920 1921 static struct clk_rcg usb30_utmi_clk = { 1922 .ns_reg = 0x3b44, 1923 .md_reg = 0x3b40, 1924 .mn = { 1925 .mnctr_en_bit = 8, 1926 .mnctr_reset_bit = 7, 1927 .mnctr_mode_shift = 5, 1928 .n_val_shift = 16, 1929 .m_val_shift = 16, 1930 .width = 8, 1931 }, 1932 .p = { 1933 .pre_div_shift = 3, 1934 .pre_div_width = 2, 1935 }, 1936 .s = { 1937 .src_sel_shift = 0, 1938 .parent_map = gcc_pxo_pll8_pll0, 1939 }, 1940 .freq_tbl = clk_tbl_usb30_utmi, 1941 .clkr = { 1942 .enable_reg = 0x3b44, 1943 .enable_mask = BIT(11), 1944 .hw.init = &(struct clk_init_data){ 1945 .name = "usb30_utmi_clk", 1946 .parent_names = gcc_pxo_pll8_pll0_map, 1947 .num_parents = 3, 1948 .ops = &clk_rcg_ops, 1949 .flags = CLK_SET_RATE_GATE, 1950 }, 1951 }, 1952 }; 1953 1954 static struct clk_branch usb30_0_utmi_clk_ctl = { 1955 .halt_reg = 0x2fc4, 1956 .halt_bit = 21, 1957 .clkr = { 1958 .enable_reg = 0x3b48, 1959 .enable_mask = BIT(4), 1960 .hw.init = &(struct clk_init_data){ 1961 .name = "usb30_0_utmi_clk_ctl", 1962 .parent_names = (const char *[]){ "usb30_utmi_clk", }, 1963 .num_parents = 1, 1964 .ops = &clk_branch_ops, 1965 .flags = CLK_SET_RATE_PARENT, 1966 }, 1967 }, 1968 }; 1969 1970 static struct clk_branch usb30_1_utmi_clk_ctl = { 1971 .halt_reg = 0x2fc4, 1972 .halt_bit = 15, 1973 .clkr = { 1974 .enable_reg = 0x3b4c, 1975 .enable_mask = BIT(4), 1976 .hw.init = &(struct clk_init_data){ 1977 .name = "usb30_1_utmi_clk_ctl", 1978 .parent_names = (const char *[]){ "usb30_utmi_clk", }, 1979 .num_parents = 1, 1980 .ops = &clk_branch_ops, 1981 .flags = CLK_SET_RATE_PARENT, 1982 }, 1983 }, 1984 }; 1985 1986 static const struct freq_tbl clk_tbl_usb[] = { 1987 { 60000000, P_PLL8, 1, 5, 32 }, 1988 { } 1989 }; 1990 1991 static struct clk_rcg usb_hs1_xcvr_clk_src = { 1992 .ns_reg = 0x290C, 1993 .md_reg = 0x2908, 1994 .mn = { 1995 .mnctr_en_bit = 8, 1996 .mnctr_reset_bit = 7, 1997 .mnctr_mode_shift = 5, 1998 .n_val_shift = 16, 1999 .m_val_shift = 16, 2000 .width = 8, 2001 }, 2002 .p = { 2003 .pre_div_shift = 3, 2004 .pre_div_width = 2, 2005 }, 2006 .s = { 2007 .src_sel_shift = 0, 2008 .parent_map = gcc_pxo_pll8_pll0, 2009 }, 2010 .freq_tbl = clk_tbl_usb, 2011 .clkr = { 2012 .enable_reg = 0x2968, 2013 .enable_mask = BIT(11), 2014 .hw.init = &(struct clk_init_data){ 2015 .name = "usb_hs1_xcvr_src", 2016 .parent_names = gcc_pxo_pll8_pll0_map, 2017 .num_parents = 3, 2018 .ops = &clk_rcg_ops, 2019 .flags = CLK_SET_RATE_GATE, 2020 }, 2021 }, 2022 }; 2023 2024 static struct clk_branch usb_hs1_xcvr_clk = { 2025 .halt_reg = 0x2fcc, 2026 .halt_bit = 17, 2027 .clkr = { 2028 .enable_reg = 0x290c, 2029 .enable_mask = BIT(9), 2030 .hw.init = &(struct clk_init_data){ 2031 .name = "usb_hs1_xcvr_clk", 2032 .parent_names = (const char *[]){ "usb_hs1_xcvr_src" }, 2033 .num_parents = 1, 2034 .ops = &clk_branch_ops, 2035 .flags = CLK_SET_RATE_PARENT, 2036 }, 2037 }, 2038 }; 2039 2040 static struct clk_branch usb_hs1_h_clk = { 2041 .hwcg_reg = 0x2900, 2042 .hwcg_bit = 6, 2043 .halt_reg = 0x2fc8, 2044 .halt_bit = 1, 2045 .clkr = { 2046 .enable_reg = 0x2900, 2047 .enable_mask = BIT(4), 2048 .hw.init = &(struct clk_init_data){ 2049 .name = "usb_hs1_h_clk", 2050 .ops = &clk_branch_ops, 2051 .flags = CLK_IS_ROOT, 2052 }, 2053 }, 2054 }; 2055 2056 static struct clk_rcg usb_fs1_xcvr_clk_src = { 2057 .ns_reg = 0x2968, 2058 .md_reg = 0x2964, 2059 .mn = { 2060 .mnctr_en_bit = 8, 2061 .mnctr_reset_bit = 7, 2062 .mnctr_mode_shift = 5, 2063 .n_val_shift = 16, 2064 .m_val_shift = 16, 2065 .width = 8, 2066 }, 2067 .p = { 2068 .pre_div_shift = 3, 2069 .pre_div_width = 2, 2070 }, 2071 .s = { 2072 .src_sel_shift = 0, 2073 .parent_map = gcc_pxo_pll8_pll0, 2074 }, 2075 .freq_tbl = clk_tbl_usb, 2076 .clkr = { 2077 .enable_reg = 0x2968, 2078 .enable_mask = BIT(11), 2079 .hw.init = &(struct clk_init_data){ 2080 .name = "usb_fs1_xcvr_src", 2081 .parent_names = gcc_pxo_pll8_pll0_map, 2082 .num_parents = 3, 2083 .ops = &clk_rcg_ops, 2084 .flags = CLK_SET_RATE_GATE, 2085 }, 2086 }, 2087 }; 2088 2089 static struct clk_branch usb_fs1_xcvr_clk = { 2090 .halt_reg = 0x2fcc, 2091 .halt_bit = 17, 2092 .clkr = { 2093 .enable_reg = 0x2968, 2094 .enable_mask = BIT(9), 2095 .hw.init = &(struct clk_init_data){ 2096 .name = "usb_fs1_xcvr_clk", 2097 .parent_names = (const char *[]){ "usb_fs1_xcvr_src", }, 2098 .num_parents = 1, 2099 .ops = &clk_branch_ops, 2100 .flags = CLK_SET_RATE_PARENT, 2101 }, 2102 }, 2103 }; 2104 2105 static struct clk_branch usb_fs1_sys_clk = { 2106 .halt_reg = 0x2fcc, 2107 .halt_bit = 18, 2108 .clkr = { 2109 .enable_reg = 0x296c, 2110 .enable_mask = BIT(4), 2111 .hw.init = &(struct clk_init_data){ 2112 .name = "usb_fs1_sys_clk", 2113 .parent_names = (const char *[]){ "usb_fs1_xcvr_src", }, 2114 .num_parents = 1, 2115 .ops = &clk_branch_ops, 2116 .flags = CLK_SET_RATE_PARENT, 2117 }, 2118 }, 2119 }; 2120 2121 static struct clk_branch usb_fs1_h_clk = { 2122 .halt_reg = 0x2fcc, 2123 .halt_bit = 19, 2124 .clkr = { 2125 .enable_reg = 0x2960, 2126 .enable_mask = BIT(4), 2127 .hw.init = &(struct clk_init_data){ 2128 .name = "usb_fs1_h_clk", 2129 .ops = &clk_branch_ops, 2130 .flags = CLK_IS_ROOT, 2131 }, 2132 }, 2133 }; 2134 2135 static struct clk_regmap *gcc_ipq806x_clks[] = { 2136 [PLL3] = &pll3.clkr, 2137 [PLL8] = &pll8.clkr, 2138 [PLL8_VOTE] = &pll8_vote, 2139 [PLL14] = &pll14.clkr, 2140 [PLL14_VOTE] = &pll14_vote, 2141 [GSBI1_UART_SRC] = &gsbi1_uart_src.clkr, 2142 [GSBI1_UART_CLK] = &gsbi1_uart_clk.clkr, 2143 [GSBI2_UART_SRC] = &gsbi2_uart_src.clkr, 2144 [GSBI2_UART_CLK] = &gsbi2_uart_clk.clkr, 2145 [GSBI4_UART_SRC] = &gsbi4_uart_src.clkr, 2146 [GSBI4_UART_CLK] = &gsbi4_uart_clk.clkr, 2147 [GSBI5_UART_SRC] = &gsbi5_uart_src.clkr, 2148 [GSBI5_UART_CLK] = &gsbi5_uart_clk.clkr, 2149 [GSBI6_UART_SRC] = &gsbi6_uart_src.clkr, 2150 [GSBI6_UART_CLK] = &gsbi6_uart_clk.clkr, 2151 [GSBI7_UART_SRC] = &gsbi7_uart_src.clkr, 2152 [GSBI7_UART_CLK] = &gsbi7_uart_clk.clkr, 2153 [GSBI1_QUP_SRC] = &gsbi1_qup_src.clkr, 2154 [GSBI1_QUP_CLK] = &gsbi1_qup_clk.clkr, 2155 [GSBI2_QUP_SRC] = &gsbi2_qup_src.clkr, 2156 [GSBI2_QUP_CLK] = &gsbi2_qup_clk.clkr, 2157 [GSBI4_QUP_SRC] = &gsbi4_qup_src.clkr, 2158 [GSBI4_QUP_CLK] = &gsbi4_qup_clk.clkr, 2159 [GSBI5_QUP_SRC] = &gsbi5_qup_src.clkr, 2160 [GSBI5_QUP_CLK] = &gsbi5_qup_clk.clkr, 2161 [GSBI6_QUP_SRC] = &gsbi6_qup_src.clkr, 2162 [GSBI6_QUP_CLK] = &gsbi6_qup_clk.clkr, 2163 [GSBI7_QUP_SRC] = &gsbi7_qup_src.clkr, 2164 [GSBI7_QUP_CLK] = &gsbi7_qup_clk.clkr, 2165 [GP0_SRC] = &gp0_src.clkr, 2166 [GP0_CLK] = &gp0_clk.clkr, 2167 [GP1_SRC] = &gp1_src.clkr, 2168 [GP1_CLK] = &gp1_clk.clkr, 2169 [GP2_SRC] = &gp2_src.clkr, 2170 [GP2_CLK] = &gp2_clk.clkr, 2171 [PMEM_A_CLK] = &pmem_clk.clkr, 2172 [PRNG_SRC] = &prng_src.clkr, 2173 [PRNG_CLK] = &prng_clk.clkr, 2174 [SDC1_SRC] = &sdc1_src.clkr, 2175 [SDC1_CLK] = &sdc1_clk.clkr, 2176 [SDC3_SRC] = &sdc3_src.clkr, 2177 [SDC3_CLK] = &sdc3_clk.clkr, 2178 [TSIF_REF_SRC] = &tsif_ref_src.clkr, 2179 [TSIF_REF_CLK] = &tsif_ref_clk.clkr, 2180 [DMA_BAM_H_CLK] = &dma_bam_h_clk.clkr, 2181 [GSBI1_H_CLK] = &gsbi1_h_clk.clkr, 2182 [GSBI2_H_CLK] = &gsbi2_h_clk.clkr, 2183 [GSBI4_H_CLK] = &gsbi4_h_clk.clkr, 2184 [GSBI5_H_CLK] = &gsbi5_h_clk.clkr, 2185 [GSBI6_H_CLK] = &gsbi6_h_clk.clkr, 2186 [GSBI7_H_CLK] = &gsbi7_h_clk.clkr, 2187 [TSIF_H_CLK] = &tsif_h_clk.clkr, 2188 [SDC1_H_CLK] = &sdc1_h_clk.clkr, 2189 [SDC3_H_CLK] = &sdc3_h_clk.clkr, 2190 [ADM0_CLK] = &adm0_clk.clkr, 2191 [ADM0_PBUS_CLK] = &adm0_pbus_clk.clkr, 2192 [PCIE_A_CLK] = &pcie_a_clk.clkr, 2193 [PCIE_AUX_CLK] = &pcie_aux_clk.clkr, 2194 [PCIE_H_CLK] = &pcie_h_clk.clkr, 2195 [PCIE_PHY_CLK] = &pcie_phy_clk.clkr, 2196 [SFAB_SATA_S_H_CLK] = &sfab_sata_s_h_clk.clkr, 2197 [PMIC_ARB0_H_CLK] = &pmic_arb0_h_clk.clkr, 2198 [PMIC_ARB1_H_CLK] = &pmic_arb1_h_clk.clkr, 2199 [PMIC_SSBI2_CLK] = &pmic_ssbi2_clk.clkr, 2200 [RPM_MSG_RAM_H_CLK] = &rpm_msg_ram_h_clk.clkr, 2201 [SATA_H_CLK] = &sata_h_clk.clkr, 2202 [SATA_CLK_SRC] = &sata_ref_src.clkr, 2203 [SATA_RXOOB_CLK] = &sata_rxoob_clk.clkr, 2204 [SATA_PMALIVE_CLK] = &sata_pmalive_clk.clkr, 2205 [SATA_PHY_REF_CLK] = &sata_phy_ref_clk.clkr, 2206 [SATA_A_CLK] = &sata_a_clk.clkr, 2207 [SATA_PHY_CFG_CLK] = &sata_phy_cfg_clk.clkr, 2208 [PCIE_ALT_REF_SRC] = &pcie_ref_src.clkr, 2209 [PCIE_ALT_REF_CLK] = &pcie_ref_src_clk.clkr, 2210 [PCIE_1_A_CLK] = &pcie1_a_clk.clkr, 2211 [PCIE_1_AUX_CLK] = &pcie1_aux_clk.clkr, 2212 [PCIE_1_H_CLK] = &pcie1_h_clk.clkr, 2213 [PCIE_1_PHY_CLK] = &pcie1_phy_clk.clkr, 2214 [PCIE_1_ALT_REF_SRC] = &pcie1_ref_src.clkr, 2215 [PCIE_1_ALT_REF_CLK] = &pcie1_ref_src_clk.clkr, 2216 [PCIE_2_A_CLK] = &pcie2_a_clk.clkr, 2217 [PCIE_2_AUX_CLK] = &pcie2_aux_clk.clkr, 2218 [PCIE_2_H_CLK] = &pcie2_h_clk.clkr, 2219 [PCIE_2_PHY_CLK] = &pcie2_phy_clk.clkr, 2220 [PCIE_2_ALT_REF_SRC] = &pcie2_ref_src.clkr, 2221 [PCIE_2_ALT_REF_CLK] = &pcie2_ref_src_clk.clkr, 2222 [USB30_MASTER_SRC] = &usb30_master_clk_src.clkr, 2223 [USB30_0_MASTER_CLK] = &usb30_0_branch_clk.clkr, 2224 [USB30_1_MASTER_CLK] = &usb30_1_branch_clk.clkr, 2225 [USB30_UTMI_SRC] = &usb30_utmi_clk.clkr, 2226 [USB30_0_UTMI_CLK] = &usb30_0_utmi_clk_ctl.clkr, 2227 [USB30_1_UTMI_CLK] = &usb30_1_utmi_clk_ctl.clkr, 2228 [USB_HS1_H_CLK] = &usb_hs1_h_clk.clkr, 2229 [USB_HS1_XCVR_SRC] = &usb_hs1_xcvr_clk_src.clkr, 2230 [USB_HS1_XCVR_CLK] = &usb_hs1_xcvr_clk.clkr, 2231 [USB_FS1_H_CLK] = &usb_fs1_h_clk.clkr, 2232 [USB_FS1_XCVR_SRC] = &usb_fs1_xcvr_clk_src.clkr, 2233 [USB_FS1_XCVR_CLK] = &usb_fs1_xcvr_clk.clkr, 2234 [USB_FS1_SYSTEM_CLK] = &usb_fs1_sys_clk.clkr, 2235 }; 2236 2237 static const struct qcom_reset_map gcc_ipq806x_resets[] = { 2238 [QDSS_STM_RESET] = { 0x2060, 6 }, 2239 [AFAB_SMPSS_S_RESET] = { 0x20b8, 2 }, 2240 [AFAB_SMPSS_M1_RESET] = { 0x20b8, 1 }, 2241 [AFAB_SMPSS_M0_RESET] = { 0x20b8, 0 }, 2242 [AFAB_EBI1_CH0_RESET] = { 0x20c0, 7 }, 2243 [AFAB_EBI1_CH1_RESET] = { 0x20c4, 7 }, 2244 [SFAB_ADM0_M0_RESET] = { 0x21e0, 7 }, 2245 [SFAB_ADM0_M1_RESET] = { 0x21e4, 7 }, 2246 [SFAB_ADM0_M2_RESET] = { 0x21e8, 7 }, 2247 [ADM0_C2_RESET] = { 0x220c, 4 }, 2248 [ADM0_C1_RESET] = { 0x220c, 3 }, 2249 [ADM0_C0_RESET] = { 0x220c, 2 }, 2250 [ADM0_PBUS_RESET] = { 0x220c, 1 }, 2251 [ADM0_RESET] = { 0x220c, 0 }, 2252 [QDSS_CLKS_SW_RESET] = { 0x2260, 5 }, 2253 [QDSS_POR_RESET] = { 0x2260, 4 }, 2254 [QDSS_TSCTR_RESET] = { 0x2260, 3 }, 2255 [QDSS_HRESET_RESET] = { 0x2260, 2 }, 2256 [QDSS_AXI_RESET] = { 0x2260, 1 }, 2257 [QDSS_DBG_RESET] = { 0x2260, 0 }, 2258 [SFAB_PCIE_M_RESET] = { 0x22d8, 1 }, 2259 [SFAB_PCIE_S_RESET] = { 0x22d8, 0 }, 2260 [PCIE_EXT_RESET] = { 0x22dc, 6 }, 2261 [PCIE_PHY_RESET] = { 0x22dc, 5 }, 2262 [PCIE_PCI_RESET] = { 0x22dc, 4 }, 2263 [PCIE_POR_RESET] = { 0x22dc, 3 }, 2264 [PCIE_HCLK_RESET] = { 0x22dc, 2 }, 2265 [PCIE_ACLK_RESET] = { 0x22dc, 0 }, 2266 [SFAB_LPASS_RESET] = { 0x23a0, 7 }, 2267 [SFAB_AFAB_M_RESET] = { 0x23e0, 7 }, 2268 [AFAB_SFAB_M0_RESET] = { 0x2420, 7 }, 2269 [AFAB_SFAB_M1_RESET] = { 0x2424, 7 }, 2270 [SFAB_SATA_S_RESET] = { 0x2480, 7 }, 2271 [SFAB_DFAB_M_RESET] = { 0x2500, 7 }, 2272 [DFAB_SFAB_M_RESET] = { 0x2520, 7 }, 2273 [DFAB_SWAY0_RESET] = { 0x2540, 7 }, 2274 [DFAB_SWAY1_RESET] = { 0x2544, 7 }, 2275 [DFAB_ARB0_RESET] = { 0x2560, 7 }, 2276 [DFAB_ARB1_RESET] = { 0x2564, 7 }, 2277 [PPSS_PROC_RESET] = { 0x2594, 1 }, 2278 [PPSS_RESET] = { 0x2594, 0 }, 2279 [DMA_BAM_RESET] = { 0x25c0, 7 }, 2280 [SPS_TIC_H_RESET] = { 0x2600, 7 }, 2281 [SFAB_CFPB_M_RESET] = { 0x2680, 7 }, 2282 [SFAB_CFPB_S_RESET] = { 0x26c0, 7 }, 2283 [TSIF_H_RESET] = { 0x2700, 7 }, 2284 [CE1_H_RESET] = { 0x2720, 7 }, 2285 [CE1_CORE_RESET] = { 0x2724, 7 }, 2286 [CE1_SLEEP_RESET] = { 0x2728, 7 }, 2287 [CE2_H_RESET] = { 0x2740, 7 }, 2288 [CE2_CORE_RESET] = { 0x2744, 7 }, 2289 [SFAB_SFPB_M_RESET] = { 0x2780, 7 }, 2290 [SFAB_SFPB_S_RESET] = { 0x27a0, 7 }, 2291 [RPM_PROC_RESET] = { 0x27c0, 7 }, 2292 [PMIC_SSBI2_RESET] = { 0x280c, 12 }, 2293 [SDC1_RESET] = { 0x2830, 0 }, 2294 [SDC2_RESET] = { 0x2850, 0 }, 2295 [SDC3_RESET] = { 0x2870, 0 }, 2296 [SDC4_RESET] = { 0x2890, 0 }, 2297 [USB_HS1_RESET] = { 0x2910, 0 }, 2298 [USB_HSIC_RESET] = { 0x2934, 0 }, 2299 [USB_FS1_XCVR_RESET] = { 0x2974, 1 }, 2300 [USB_FS1_RESET] = { 0x2974, 0 }, 2301 [GSBI1_RESET] = { 0x29dc, 0 }, 2302 [GSBI2_RESET] = { 0x29fc, 0 }, 2303 [GSBI3_RESET] = { 0x2a1c, 0 }, 2304 [GSBI4_RESET] = { 0x2a3c, 0 }, 2305 [GSBI5_RESET] = { 0x2a5c, 0 }, 2306 [GSBI6_RESET] = { 0x2a7c, 0 }, 2307 [GSBI7_RESET] = { 0x2a9c, 0 }, 2308 [SPDM_RESET] = { 0x2b6c, 0 }, 2309 [SEC_CTRL_RESET] = { 0x2b80, 7 }, 2310 [TLMM_H_RESET] = { 0x2ba0, 7 }, 2311 [SFAB_SATA_M_RESET] = { 0x2c18, 0 }, 2312 [SATA_RESET] = { 0x2c1c, 0 }, 2313 [TSSC_RESET] = { 0x2ca0, 7 }, 2314 [PDM_RESET] = { 0x2cc0, 12 }, 2315 [MPM_H_RESET] = { 0x2da0, 7 }, 2316 [MPM_RESET] = { 0x2da4, 0 }, 2317 [SFAB_SMPSS_S_RESET] = { 0x2e00, 7 }, 2318 [PRNG_RESET] = { 0x2e80, 12 }, 2319 [SFAB_CE3_M_RESET] = { 0x36c8, 1 }, 2320 [SFAB_CE3_S_RESET] = { 0x36c8, 0 }, 2321 [CE3_SLEEP_RESET] = { 0x36d0, 7 }, 2322 [PCIE_1_M_RESET] = { 0x3a98, 1 }, 2323 [PCIE_1_S_RESET] = { 0x3a98, 0 }, 2324 [PCIE_1_EXT_RESET] = { 0x3a9c, 6 }, 2325 [PCIE_1_PHY_RESET] = { 0x3a9c, 5 }, 2326 [PCIE_1_PCI_RESET] = { 0x3a9c, 4 }, 2327 [PCIE_1_POR_RESET] = { 0x3a9c, 3 }, 2328 [PCIE_1_HCLK_RESET] = { 0x3a9c, 2 }, 2329 [PCIE_1_ACLK_RESET] = { 0x3a9c, 0 }, 2330 [PCIE_2_M_RESET] = { 0x3ad8, 1 }, 2331 [PCIE_2_S_RESET] = { 0x3ad8, 0 }, 2332 [PCIE_2_EXT_RESET] = { 0x3adc, 6 }, 2333 [PCIE_2_PHY_RESET] = { 0x3adc, 5 }, 2334 [PCIE_2_PCI_RESET] = { 0x3adc, 4 }, 2335 [PCIE_2_POR_RESET] = { 0x3adc, 3 }, 2336 [PCIE_2_HCLK_RESET] = { 0x3adc, 2 }, 2337 [PCIE_2_ACLK_RESET] = { 0x3adc, 0 }, 2338 [SFAB_USB30_S_RESET] = { 0x3b54, 1 }, 2339 [SFAB_USB30_M_RESET] = { 0x3b54, 0 }, 2340 [USB30_0_PORT2_HS_PHY_RESET] = { 0x3b50, 5 }, 2341 [USB30_0_MASTER_RESET] = { 0x3b50, 4 }, 2342 [USB30_0_SLEEP_RESET] = { 0x3b50, 3 }, 2343 [USB30_0_UTMI_PHY_RESET] = { 0x3b50, 2 }, 2344 [USB30_0_POWERON_RESET] = { 0x3b50, 1 }, 2345 [USB30_0_PHY_RESET] = { 0x3b50, 0 }, 2346 [USB30_1_MASTER_RESET] = { 0x3b58, 4 }, 2347 [USB30_1_SLEEP_RESET] = { 0x3b58, 3 }, 2348 [USB30_1_UTMI_PHY_RESET] = { 0x3b58, 2 }, 2349 [USB30_1_POWERON_RESET] = { 0x3b58, 1 }, 2350 [USB30_1_PHY_RESET] = { 0x3b58, 0 }, 2351 [NSSFB0_RESET] = { 0x3b60, 6 }, 2352 [NSSFB1_RESET] = { 0x3b60, 7 }, 2353 }; 2354 2355 static const struct regmap_config gcc_ipq806x_regmap_config = { 2356 .reg_bits = 32, 2357 .reg_stride = 4, 2358 .val_bits = 32, 2359 .max_register = 0x3e40, 2360 .fast_io = true, 2361 }; 2362 2363 static const struct qcom_cc_desc gcc_ipq806x_desc = { 2364 .config = &gcc_ipq806x_regmap_config, 2365 .clks = gcc_ipq806x_clks, 2366 .num_clks = ARRAY_SIZE(gcc_ipq806x_clks), 2367 .resets = gcc_ipq806x_resets, 2368 .num_resets = ARRAY_SIZE(gcc_ipq806x_resets), 2369 }; 2370 2371 static const struct of_device_id gcc_ipq806x_match_table[] = { 2372 { .compatible = "qcom,gcc-ipq8064" }, 2373 { } 2374 }; 2375 MODULE_DEVICE_TABLE(of, gcc_ipq806x_match_table); 2376 2377 static int gcc_ipq806x_probe(struct platform_device *pdev) 2378 { 2379 struct clk *clk; 2380 struct device *dev = &pdev->dev; 2381 2382 /* Temporary until RPM clocks supported */ 2383 clk = clk_register_fixed_rate(dev, "cxo", NULL, CLK_IS_ROOT, 25000000); 2384 if (IS_ERR(clk)) 2385 return PTR_ERR(clk); 2386 2387 clk = clk_register_fixed_rate(dev, "pxo", NULL, CLK_IS_ROOT, 25000000); 2388 if (IS_ERR(clk)) 2389 return PTR_ERR(clk); 2390 2391 return qcom_cc_probe(pdev, &gcc_ipq806x_desc); 2392 } 2393 2394 static int gcc_ipq806x_remove(struct platform_device *pdev) 2395 { 2396 qcom_cc_remove(pdev); 2397 return 0; 2398 } 2399 2400 static struct platform_driver gcc_ipq806x_driver = { 2401 .probe = gcc_ipq806x_probe, 2402 .remove = gcc_ipq806x_remove, 2403 .driver = { 2404 .name = "gcc-ipq806x", 2405 .owner = THIS_MODULE, 2406 .of_match_table = gcc_ipq806x_match_table, 2407 }, 2408 }; 2409 2410 static int __init gcc_ipq806x_init(void) 2411 { 2412 return platform_driver_register(&gcc_ipq806x_driver); 2413 } 2414 core_initcall(gcc_ipq806x_init); 2415 2416 static void __exit gcc_ipq806x_exit(void) 2417 { 2418 platform_driver_unregister(&gcc_ipq806x_driver); 2419 } 2420 module_exit(gcc_ipq806x_exit); 2421 2422 MODULE_DESCRIPTION("QCOM GCC IPQ806x Driver"); 2423 MODULE_LICENSE("GPL v2"); 2424 MODULE_ALIAS("platform:gcc-ipq806x"); 2425