1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2015, 2018, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021, 2023, Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #include <linux/kernel.h> 8 #include <linux/export.h> 9 #include <linux/clk-provider.h> 10 #include <linux/regmap.h> 11 #include <linux/delay.h> 12 13 #include "clk-alpha-pll.h" 14 #include "common.h" 15 16 #define PLL_MODE(p) ((p)->offset + 0x0) 17 # define PLL_OUTCTRL BIT(0) 18 # define PLL_BYPASSNL BIT(1) 19 # define PLL_RESET_N BIT(2) 20 # define PLL_OFFLINE_REQ BIT(7) 21 # define PLL_LOCK_COUNT_SHIFT 8 22 # define PLL_LOCK_COUNT_MASK 0x3f 23 # define PLL_BIAS_COUNT_SHIFT 14 24 # define PLL_BIAS_COUNT_MASK 0x3f 25 # define PLL_VOTE_FSM_ENA BIT(20) 26 # define PLL_FSM_ENA BIT(20) 27 # define PLL_VOTE_FSM_RESET BIT(21) 28 # define PLL_UPDATE BIT(22) 29 # define PLL_UPDATE_BYPASS BIT(23) 30 # define PLL_FSM_LEGACY_MODE BIT(24) 31 # define PLL_OFFLINE_ACK BIT(28) 32 # define ALPHA_PLL_ACK_LATCH BIT(29) 33 # define PLL_ACTIVE_FLAG BIT(30) 34 # define PLL_LOCK_DET BIT(31) 35 36 #define PLL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_L_VAL]) 37 #define PLL_CAL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_CAL_L_VAL]) 38 #define PLL_ALPHA_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL]) 39 #define PLL_ALPHA_VAL_U(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL_U]) 40 41 #define PLL_USER_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL]) 42 # define PLL_POST_DIV_SHIFT 8 43 # define PLL_POST_DIV_MASK(p) GENMASK((p)->width - 1, 0) 44 # define PLL_ALPHA_EN BIT(24) 45 # define PLL_ALPHA_MODE BIT(25) 46 # define PLL_VCO_SHIFT 20 47 # define PLL_VCO_MASK 0x3 48 49 #define PLL_USER_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL_U]) 50 #define PLL_USER_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL_U1]) 51 52 #define PLL_CONFIG_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL]) 53 #define PLL_CONFIG_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U]) 54 #define PLL_CONFIG_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U1]) 55 #define PLL_CONFIG_CTL_U2(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U2]) 56 #define PLL_TEST_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL]) 57 #define PLL_TEST_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U]) 58 #define PLL_TEST_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U1]) 59 #define PLL_TEST_CTL_U2(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U2]) 60 #define PLL_STATUS(p) ((p)->offset + (p)->regs[PLL_OFF_STATUS]) 61 #define PLL_OPMODE(p) ((p)->offset + (p)->regs[PLL_OFF_OPMODE]) 62 #define PLL_FRAC(p) ((p)->offset + (p)->regs[PLL_OFF_FRAC]) 63 64 const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = { 65 [CLK_ALPHA_PLL_TYPE_DEFAULT] = { 66 [PLL_OFF_L_VAL] = 0x04, 67 [PLL_OFF_ALPHA_VAL] = 0x08, 68 [PLL_OFF_ALPHA_VAL_U] = 0x0c, 69 [PLL_OFF_USER_CTL] = 0x10, 70 [PLL_OFF_USER_CTL_U] = 0x14, 71 [PLL_OFF_CONFIG_CTL] = 0x18, 72 [PLL_OFF_TEST_CTL] = 0x1c, 73 [PLL_OFF_TEST_CTL_U] = 0x20, 74 [PLL_OFF_STATUS] = 0x24, 75 }, 76 [CLK_ALPHA_PLL_TYPE_HUAYRA] = { 77 [PLL_OFF_L_VAL] = 0x04, 78 [PLL_OFF_ALPHA_VAL] = 0x08, 79 [PLL_OFF_USER_CTL] = 0x10, 80 [PLL_OFF_CONFIG_CTL] = 0x14, 81 [PLL_OFF_CONFIG_CTL_U] = 0x18, 82 [PLL_OFF_TEST_CTL] = 0x1c, 83 [PLL_OFF_TEST_CTL_U] = 0x20, 84 [PLL_OFF_STATUS] = 0x24, 85 }, 86 [CLK_ALPHA_PLL_TYPE_BRAMMO] = { 87 [PLL_OFF_L_VAL] = 0x04, 88 [PLL_OFF_ALPHA_VAL] = 0x08, 89 [PLL_OFF_ALPHA_VAL_U] = 0x0c, 90 [PLL_OFF_USER_CTL] = 0x10, 91 [PLL_OFF_CONFIG_CTL] = 0x18, 92 [PLL_OFF_TEST_CTL] = 0x1c, 93 [PLL_OFF_STATUS] = 0x24, 94 }, 95 [CLK_ALPHA_PLL_TYPE_FABIA] = { 96 [PLL_OFF_L_VAL] = 0x04, 97 [PLL_OFF_USER_CTL] = 0x0c, 98 [PLL_OFF_USER_CTL_U] = 0x10, 99 [PLL_OFF_CONFIG_CTL] = 0x14, 100 [PLL_OFF_CONFIG_CTL_U] = 0x18, 101 [PLL_OFF_TEST_CTL] = 0x1c, 102 [PLL_OFF_TEST_CTL_U] = 0x20, 103 [PLL_OFF_STATUS] = 0x24, 104 [PLL_OFF_OPMODE] = 0x2c, 105 [PLL_OFF_FRAC] = 0x38, 106 }, 107 [CLK_ALPHA_PLL_TYPE_TRION] = { 108 [PLL_OFF_L_VAL] = 0x04, 109 [PLL_OFF_CAL_L_VAL] = 0x08, 110 [PLL_OFF_USER_CTL] = 0x0c, 111 [PLL_OFF_USER_CTL_U] = 0x10, 112 [PLL_OFF_USER_CTL_U1] = 0x14, 113 [PLL_OFF_CONFIG_CTL] = 0x18, 114 [PLL_OFF_CONFIG_CTL_U] = 0x1c, 115 [PLL_OFF_CONFIG_CTL_U1] = 0x20, 116 [PLL_OFF_TEST_CTL] = 0x24, 117 [PLL_OFF_TEST_CTL_U] = 0x28, 118 [PLL_OFF_TEST_CTL_U1] = 0x2c, 119 [PLL_OFF_STATUS] = 0x30, 120 [PLL_OFF_OPMODE] = 0x38, 121 [PLL_OFF_ALPHA_VAL] = 0x40, 122 }, 123 [CLK_ALPHA_PLL_TYPE_AGERA] = { 124 [PLL_OFF_L_VAL] = 0x04, 125 [PLL_OFF_ALPHA_VAL] = 0x08, 126 [PLL_OFF_USER_CTL] = 0x0c, 127 [PLL_OFF_CONFIG_CTL] = 0x10, 128 [PLL_OFF_CONFIG_CTL_U] = 0x14, 129 [PLL_OFF_TEST_CTL] = 0x18, 130 [PLL_OFF_TEST_CTL_U] = 0x1c, 131 [PLL_OFF_STATUS] = 0x2c, 132 }, 133 [CLK_ALPHA_PLL_TYPE_ZONDA] = { 134 [PLL_OFF_L_VAL] = 0x04, 135 [PLL_OFF_ALPHA_VAL] = 0x08, 136 [PLL_OFF_USER_CTL] = 0x0c, 137 [PLL_OFF_CONFIG_CTL] = 0x10, 138 [PLL_OFF_CONFIG_CTL_U] = 0x14, 139 [PLL_OFF_CONFIG_CTL_U1] = 0x18, 140 [PLL_OFF_TEST_CTL] = 0x1c, 141 [PLL_OFF_TEST_CTL_U] = 0x20, 142 [PLL_OFF_TEST_CTL_U1] = 0x24, 143 [PLL_OFF_OPMODE] = 0x28, 144 [PLL_OFF_STATUS] = 0x38, 145 }, 146 [CLK_ALPHA_PLL_TYPE_LUCID_EVO] = { 147 [PLL_OFF_OPMODE] = 0x04, 148 [PLL_OFF_STATUS] = 0x0c, 149 [PLL_OFF_L_VAL] = 0x10, 150 [PLL_OFF_ALPHA_VAL] = 0x14, 151 [PLL_OFF_USER_CTL] = 0x18, 152 [PLL_OFF_USER_CTL_U] = 0x1c, 153 [PLL_OFF_CONFIG_CTL] = 0x20, 154 [PLL_OFF_CONFIG_CTL_U] = 0x24, 155 [PLL_OFF_CONFIG_CTL_U1] = 0x28, 156 [PLL_OFF_TEST_CTL] = 0x2c, 157 [PLL_OFF_TEST_CTL_U] = 0x30, 158 [PLL_OFF_TEST_CTL_U1] = 0x34, 159 }, 160 [CLK_ALPHA_PLL_TYPE_LUCID_OLE] = { 161 [PLL_OFF_OPMODE] = 0x04, 162 [PLL_OFF_STATE] = 0x08, 163 [PLL_OFF_STATUS] = 0x0c, 164 [PLL_OFF_L_VAL] = 0x10, 165 [PLL_OFF_ALPHA_VAL] = 0x14, 166 [PLL_OFF_USER_CTL] = 0x18, 167 [PLL_OFF_USER_CTL_U] = 0x1c, 168 [PLL_OFF_CONFIG_CTL] = 0x20, 169 [PLL_OFF_CONFIG_CTL_U] = 0x24, 170 [PLL_OFF_CONFIG_CTL_U1] = 0x28, 171 [PLL_OFF_TEST_CTL] = 0x2c, 172 [PLL_OFF_TEST_CTL_U] = 0x30, 173 [PLL_OFF_TEST_CTL_U1] = 0x34, 174 [PLL_OFF_TEST_CTL_U2] = 0x38, 175 }, 176 [CLK_ALPHA_PLL_TYPE_RIVIAN_EVO] = { 177 [PLL_OFF_OPMODE] = 0x04, 178 [PLL_OFF_STATUS] = 0x0c, 179 [PLL_OFF_L_VAL] = 0x10, 180 [PLL_OFF_USER_CTL] = 0x14, 181 [PLL_OFF_USER_CTL_U] = 0x18, 182 [PLL_OFF_CONFIG_CTL] = 0x1c, 183 [PLL_OFF_CONFIG_CTL_U] = 0x20, 184 [PLL_OFF_CONFIG_CTL_U1] = 0x24, 185 [PLL_OFF_TEST_CTL] = 0x28, 186 [PLL_OFF_TEST_CTL_U] = 0x2c, 187 }, 188 [CLK_ALPHA_PLL_TYPE_DEFAULT_EVO] = { 189 [PLL_OFF_L_VAL] = 0x04, 190 [PLL_OFF_ALPHA_VAL] = 0x08, 191 [PLL_OFF_ALPHA_VAL_U] = 0x0c, 192 [PLL_OFF_TEST_CTL] = 0x10, 193 [PLL_OFF_TEST_CTL_U] = 0x14, 194 [PLL_OFF_USER_CTL] = 0x18, 195 [PLL_OFF_USER_CTL_U] = 0x1c, 196 [PLL_OFF_CONFIG_CTL] = 0x20, 197 [PLL_OFF_STATUS] = 0x24, 198 }, 199 [CLK_ALPHA_PLL_TYPE_BRAMMO_EVO] = { 200 [PLL_OFF_L_VAL] = 0x04, 201 [PLL_OFF_ALPHA_VAL] = 0x08, 202 [PLL_OFF_ALPHA_VAL_U] = 0x0c, 203 [PLL_OFF_TEST_CTL] = 0x10, 204 [PLL_OFF_TEST_CTL_U] = 0x14, 205 [PLL_OFF_USER_CTL] = 0x18, 206 [PLL_OFF_CONFIG_CTL] = 0x1C, 207 [PLL_OFF_STATUS] = 0x20, 208 }, 209 [CLK_ALPHA_PLL_TYPE_STROMER] = { 210 [PLL_OFF_L_VAL] = 0x08, 211 [PLL_OFF_ALPHA_VAL] = 0x10, 212 [PLL_OFF_ALPHA_VAL_U] = 0x14, 213 [PLL_OFF_USER_CTL] = 0x18, 214 [PLL_OFF_USER_CTL_U] = 0x1c, 215 [PLL_OFF_CONFIG_CTL] = 0x20, 216 [PLL_OFF_TEST_CTL] = 0x30, 217 [PLL_OFF_TEST_CTL_U] = 0x34, 218 [PLL_OFF_STATUS] = 0x28, 219 }, 220 [CLK_ALPHA_PLL_TYPE_STROMER_PLUS] = { 221 [PLL_OFF_L_VAL] = 0x04, 222 [PLL_OFF_USER_CTL] = 0x08, 223 [PLL_OFF_USER_CTL_U] = 0x0c, 224 [PLL_OFF_CONFIG_CTL] = 0x10, 225 [PLL_OFF_TEST_CTL] = 0x14, 226 [PLL_OFF_TEST_CTL_U] = 0x18, 227 [PLL_OFF_STATUS] = 0x1c, 228 [PLL_OFF_ALPHA_VAL] = 0x24, 229 [PLL_OFF_ALPHA_VAL_U] = 0x28, 230 }, 231 [CLK_ALPHA_PLL_TYPE_ZONDA_OLE] = { 232 [PLL_OFF_L_VAL] = 0x04, 233 [PLL_OFF_ALPHA_VAL] = 0x08, 234 [PLL_OFF_USER_CTL] = 0x0c, 235 [PLL_OFF_USER_CTL_U] = 0x10, 236 [PLL_OFF_CONFIG_CTL] = 0x14, 237 [PLL_OFF_CONFIG_CTL_U] = 0x18, 238 [PLL_OFF_CONFIG_CTL_U1] = 0x1c, 239 [PLL_OFF_CONFIG_CTL_U2] = 0x20, 240 [PLL_OFF_TEST_CTL] = 0x24, 241 [PLL_OFF_TEST_CTL_U] = 0x28, 242 [PLL_OFF_TEST_CTL_U1] = 0x2c, 243 [PLL_OFF_OPMODE] = 0x30, 244 [PLL_OFF_STATUS] = 0x3c, 245 }, 246 [CLK_ALPHA_PLL_TYPE_NSS_HUAYRA] = { 247 [PLL_OFF_L_VAL] = 0x04, 248 [PLL_OFF_ALPHA_VAL] = 0x08, 249 [PLL_OFF_TEST_CTL] = 0x0c, 250 [PLL_OFF_TEST_CTL_U] = 0x10, 251 [PLL_OFF_USER_CTL] = 0x14, 252 [PLL_OFF_CONFIG_CTL] = 0x18, 253 [PLL_OFF_CONFIG_CTL_U] = 0x1c, 254 [PLL_OFF_STATUS] = 0x20, 255 }, 256 257 }; 258 EXPORT_SYMBOL_GPL(clk_alpha_pll_regs); 259 260 /* 261 * Even though 40 bits are present, use only 32 for ease of calculation. 262 */ 263 #define ALPHA_REG_BITWIDTH 40 264 #define ALPHA_REG_16BIT_WIDTH 16 265 #define ALPHA_BITWIDTH 32U 266 #define ALPHA_SHIFT(w) min(w, ALPHA_BITWIDTH) 267 268 #define ALPHA_PLL_STATUS_REG_SHIFT 8 269 270 #define PLL_HUAYRA_M_WIDTH 8 271 #define PLL_HUAYRA_M_SHIFT 8 272 #define PLL_HUAYRA_M_MASK 0xff 273 #define PLL_HUAYRA_N_SHIFT 0 274 #define PLL_HUAYRA_N_MASK 0xff 275 #define PLL_HUAYRA_ALPHA_WIDTH 16 276 277 #define PLL_STANDBY 0x0 278 #define PLL_RUN 0x1 279 #define PLL_OUT_MASK 0x7 280 #define PLL_RATE_MARGIN 500 281 282 /* TRION PLL specific settings and offsets */ 283 #define TRION_PLL_CAL_VAL 0x44 284 #define TRION_PCAL_DONE BIT(26) 285 286 /* LUCID PLL specific settings and offsets */ 287 #define LUCID_PCAL_DONE BIT(27) 288 289 /* LUCID 5LPE PLL specific settings and offsets */ 290 #define LUCID_5LPE_PCAL_DONE BIT(11) 291 #define LUCID_5LPE_ALPHA_PLL_ACK_LATCH BIT(13) 292 #define LUCID_5LPE_PLL_LATCH_INPUT BIT(14) 293 #define LUCID_5LPE_ENABLE_VOTE_RUN BIT(21) 294 295 /* LUCID EVO PLL specific settings and offsets */ 296 #define LUCID_EVO_PCAL_NOT_DONE BIT(8) 297 #define LUCID_EVO_ENABLE_VOTE_RUN BIT(25) 298 #define LUCID_EVO_PLL_L_VAL_MASK GENMASK(15, 0) 299 #define LUCID_EVO_PLL_CAL_L_VAL_SHIFT 16 300 301 /* ZONDA PLL specific */ 302 #define ZONDA_PLL_OUT_MASK 0xf 303 #define ZONDA_STAY_IN_CFA BIT(16) 304 #define ZONDA_PLL_FREQ_LOCK_DET BIT(29) 305 306 #define pll_alpha_width(p) \ 307 ((PLL_ALPHA_VAL_U(p) - PLL_ALPHA_VAL(p) == 4) ? \ 308 ALPHA_REG_BITWIDTH : ALPHA_REG_16BIT_WIDTH) 309 310 #define pll_has_64bit_config(p) ((PLL_CONFIG_CTL_U(p) - PLL_CONFIG_CTL(p)) == 4) 311 312 #define to_clk_alpha_pll(_hw) container_of(to_clk_regmap(_hw), \ 313 struct clk_alpha_pll, clkr) 314 315 #define to_clk_alpha_pll_postdiv(_hw) container_of(to_clk_regmap(_hw), \ 316 struct clk_alpha_pll_postdiv, clkr) 317 318 static int wait_for_pll(struct clk_alpha_pll *pll, u32 mask, bool inverse, 319 const char *action) 320 { 321 u32 val; 322 int count; 323 int ret; 324 const char *name = clk_hw_get_name(&pll->clkr.hw); 325 326 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 327 if (ret) 328 return ret; 329 330 for (count = 200; count > 0; count--) { 331 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 332 if (ret) 333 return ret; 334 if (inverse && !(val & mask)) 335 return 0; 336 else if ((val & mask) == mask) 337 return 0; 338 339 udelay(1); 340 } 341 342 WARN(1, "%s failed to %s!\n", name, action); 343 return -ETIMEDOUT; 344 } 345 346 #define wait_for_pll_enable_active(pll) \ 347 wait_for_pll(pll, PLL_ACTIVE_FLAG, 0, "enable") 348 349 #define wait_for_pll_enable_lock(pll) \ 350 wait_for_pll(pll, PLL_LOCK_DET, 0, "enable") 351 352 #define wait_for_zonda_pll_freq_lock(pll) \ 353 wait_for_pll(pll, ZONDA_PLL_FREQ_LOCK_DET, 0, "freq enable") 354 355 #define wait_for_pll_disable(pll) \ 356 wait_for_pll(pll, PLL_ACTIVE_FLAG, 1, "disable") 357 358 #define wait_for_pll_offline(pll) \ 359 wait_for_pll(pll, PLL_OFFLINE_ACK, 0, "offline") 360 361 #define wait_for_pll_update(pll) \ 362 wait_for_pll(pll, PLL_UPDATE, 1, "update") 363 364 #define wait_for_pll_update_ack_set(pll) \ 365 wait_for_pll(pll, ALPHA_PLL_ACK_LATCH, 0, "update_ack_set") 366 367 #define wait_for_pll_update_ack_clear(pll) \ 368 wait_for_pll(pll, ALPHA_PLL_ACK_LATCH, 1, "update_ack_clear") 369 370 static void clk_alpha_pll_write_config(struct regmap *regmap, unsigned int reg, 371 unsigned int val) 372 { 373 if (val) 374 regmap_write(regmap, reg, val); 375 } 376 377 void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 378 const struct alpha_pll_config *config) 379 { 380 u32 val, mask; 381 382 regmap_write(regmap, PLL_L_VAL(pll), config->l); 383 regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha); 384 regmap_write(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); 385 386 if (pll_has_64bit_config(pll)) 387 regmap_write(regmap, PLL_CONFIG_CTL_U(pll), 388 config->config_ctl_hi_val); 389 390 if (pll_alpha_width(pll) > 32) 391 regmap_write(regmap, PLL_ALPHA_VAL_U(pll), config->alpha_hi); 392 393 val = config->main_output_mask; 394 val |= config->aux_output_mask; 395 val |= config->aux2_output_mask; 396 val |= config->early_output_mask; 397 val |= config->pre_div_val; 398 val |= config->post_div_val; 399 val |= config->vco_val; 400 val |= config->alpha_en_mask; 401 val |= config->alpha_mode_mask; 402 403 mask = config->main_output_mask; 404 mask |= config->aux_output_mask; 405 mask |= config->aux2_output_mask; 406 mask |= config->early_output_mask; 407 mask |= config->pre_div_mask; 408 mask |= config->post_div_mask; 409 mask |= config->vco_mask; 410 411 regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val); 412 413 if (config->test_ctl_mask) 414 regmap_update_bits(regmap, PLL_TEST_CTL(pll), 415 config->test_ctl_mask, 416 config->test_ctl_val); 417 else 418 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), 419 config->test_ctl_val); 420 421 if (config->test_ctl_hi_mask) 422 regmap_update_bits(regmap, PLL_TEST_CTL_U(pll), 423 config->test_ctl_hi_mask, 424 config->test_ctl_hi_val); 425 else 426 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), 427 config->test_ctl_hi_val); 428 429 if (pll->flags & SUPPORTS_FSM_MODE) 430 qcom_pll_set_fsm_mode(regmap, PLL_MODE(pll), 6, 0); 431 } 432 EXPORT_SYMBOL_GPL(clk_alpha_pll_configure); 433 434 static int clk_alpha_pll_hwfsm_enable(struct clk_hw *hw) 435 { 436 int ret; 437 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 438 u32 val; 439 440 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 441 if (ret) 442 return ret; 443 444 val |= PLL_FSM_ENA; 445 446 if (pll->flags & SUPPORTS_OFFLINE_REQ) 447 val &= ~PLL_OFFLINE_REQ; 448 449 ret = regmap_write(pll->clkr.regmap, PLL_MODE(pll), val); 450 if (ret) 451 return ret; 452 453 /* Make sure enable request goes through before waiting for update */ 454 mb(); 455 456 return wait_for_pll_enable_active(pll); 457 } 458 459 static void clk_alpha_pll_hwfsm_disable(struct clk_hw *hw) 460 { 461 int ret; 462 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 463 u32 val; 464 465 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 466 if (ret) 467 return; 468 469 if (pll->flags & SUPPORTS_OFFLINE_REQ) { 470 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), 471 PLL_OFFLINE_REQ, PLL_OFFLINE_REQ); 472 if (ret) 473 return; 474 475 ret = wait_for_pll_offline(pll); 476 if (ret) 477 return; 478 } 479 480 /* Disable hwfsm */ 481 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), 482 PLL_FSM_ENA, 0); 483 if (ret) 484 return; 485 486 wait_for_pll_disable(pll); 487 } 488 489 static int pll_is_enabled(struct clk_hw *hw, u32 mask) 490 { 491 int ret; 492 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 493 u32 val; 494 495 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 496 if (ret) 497 return ret; 498 499 return !!(val & mask); 500 } 501 502 static int clk_alpha_pll_hwfsm_is_enabled(struct clk_hw *hw) 503 { 504 return pll_is_enabled(hw, PLL_ACTIVE_FLAG); 505 } 506 507 static int clk_alpha_pll_is_enabled(struct clk_hw *hw) 508 { 509 return pll_is_enabled(hw, PLL_LOCK_DET); 510 } 511 512 static int clk_alpha_pll_enable(struct clk_hw *hw) 513 { 514 int ret; 515 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 516 u32 val, mask; 517 518 mask = PLL_OUTCTRL | PLL_RESET_N | PLL_BYPASSNL; 519 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 520 if (ret) 521 return ret; 522 523 /* If in FSM mode, just vote for it */ 524 if (val & PLL_VOTE_FSM_ENA) { 525 ret = clk_enable_regmap(hw); 526 if (ret) 527 return ret; 528 return wait_for_pll_enable_active(pll); 529 } 530 531 /* Skip if already enabled */ 532 if ((val & mask) == mask) 533 return 0; 534 535 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), 536 PLL_BYPASSNL, PLL_BYPASSNL); 537 if (ret) 538 return ret; 539 540 /* 541 * H/W requires a 5us delay between disabling the bypass and 542 * de-asserting the reset. 543 */ 544 mb(); 545 udelay(5); 546 547 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), 548 PLL_RESET_N, PLL_RESET_N); 549 if (ret) 550 return ret; 551 552 ret = wait_for_pll_enable_lock(pll); 553 if (ret) 554 return ret; 555 556 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), 557 PLL_OUTCTRL, PLL_OUTCTRL); 558 559 /* Ensure that the write above goes through before returning. */ 560 mb(); 561 return ret; 562 } 563 564 static void clk_alpha_pll_disable(struct clk_hw *hw) 565 { 566 int ret; 567 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 568 u32 val, mask; 569 570 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 571 if (ret) 572 return; 573 574 /* If in FSM mode, just unvote it */ 575 if (val & PLL_VOTE_FSM_ENA) { 576 clk_disable_regmap(hw); 577 return; 578 } 579 580 mask = PLL_OUTCTRL; 581 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), mask, 0); 582 583 /* Delay of 2 output clock ticks required until output is disabled */ 584 mb(); 585 udelay(1); 586 587 mask = PLL_RESET_N | PLL_BYPASSNL; 588 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), mask, 0); 589 } 590 591 static unsigned long 592 alpha_pll_calc_rate(u64 prate, u32 l, u32 a, u32 alpha_width) 593 { 594 return (prate * l) + ((prate * a) >> ALPHA_SHIFT(alpha_width)); 595 } 596 597 static unsigned long 598 alpha_pll_round_rate(unsigned long rate, unsigned long prate, u32 *l, u64 *a, 599 u32 alpha_width) 600 { 601 u64 remainder; 602 u64 quotient; 603 604 quotient = rate; 605 remainder = do_div(quotient, prate); 606 *l = quotient; 607 608 if (!remainder) { 609 *a = 0; 610 return rate; 611 } 612 613 /* Upper ALPHA_BITWIDTH bits of Alpha */ 614 quotient = remainder << ALPHA_SHIFT(alpha_width); 615 616 remainder = do_div(quotient, prate); 617 618 if (remainder) 619 quotient++; 620 621 *a = quotient; 622 return alpha_pll_calc_rate(prate, *l, *a, alpha_width); 623 } 624 625 static const struct pll_vco * 626 alpha_pll_find_vco(const struct clk_alpha_pll *pll, unsigned long rate) 627 { 628 const struct pll_vco *v = pll->vco_table; 629 const struct pll_vco *end = v + pll->num_vco; 630 631 for (; v < end; v++) 632 if (rate >= v->min_freq && rate <= v->max_freq) 633 return v; 634 635 return NULL; 636 } 637 638 static unsigned long 639 clk_alpha_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 640 { 641 u32 l, low, high, ctl; 642 u64 a = 0, prate = parent_rate; 643 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 644 u32 alpha_width = pll_alpha_width(pll); 645 646 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); 647 648 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); 649 if (ctl & PLL_ALPHA_EN) { 650 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &low); 651 if (alpha_width > 32) { 652 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), 653 &high); 654 a = (u64)high << 32 | low; 655 } else { 656 a = low & GENMASK(alpha_width - 1, 0); 657 } 658 659 if (alpha_width > ALPHA_BITWIDTH) 660 a >>= alpha_width - ALPHA_BITWIDTH; 661 } 662 663 return alpha_pll_calc_rate(prate, l, a, alpha_width); 664 } 665 666 667 static int __clk_alpha_pll_update_latch(struct clk_alpha_pll *pll) 668 { 669 int ret; 670 u32 mode; 671 672 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &mode); 673 674 /* Latch the input to the PLL */ 675 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE, 676 PLL_UPDATE); 677 678 /* Wait for 2 reference cycle before checking ACK bit */ 679 udelay(1); 680 681 /* 682 * PLL will latch the new L, Alpha and freq control word. 683 * PLL will respond by raising PLL_ACK_LATCH output when new programming 684 * has been latched in and PLL is being updated. When 685 * UPDATE_LOGIC_BYPASS bit is not set, PLL_UPDATE will be cleared 686 * automatically by hardware when PLL_ACK_LATCH is asserted by PLL. 687 */ 688 if (mode & PLL_UPDATE_BYPASS) { 689 ret = wait_for_pll_update_ack_set(pll); 690 if (ret) 691 return ret; 692 693 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE, 0); 694 } else { 695 ret = wait_for_pll_update(pll); 696 if (ret) 697 return ret; 698 } 699 700 ret = wait_for_pll_update_ack_clear(pll); 701 if (ret) 702 return ret; 703 704 /* Wait for PLL output to stabilize */ 705 udelay(10); 706 707 return 0; 708 } 709 710 static int clk_alpha_pll_update_latch(struct clk_alpha_pll *pll, 711 int (*is_enabled)(struct clk_hw *)) 712 { 713 if (!is_enabled(&pll->clkr.hw) || 714 !(pll->flags & SUPPORTS_DYNAMIC_UPDATE)) 715 return 0; 716 717 return __clk_alpha_pll_update_latch(pll); 718 } 719 720 static int __clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate, 721 unsigned long prate, 722 int (*is_enabled)(struct clk_hw *)) 723 { 724 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 725 const struct pll_vco *vco; 726 u32 l, alpha_width = pll_alpha_width(pll); 727 u64 a; 728 729 rate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width); 730 vco = alpha_pll_find_vco(pll, rate); 731 if (pll->vco_table && !vco) { 732 pr_err("%s: alpha pll not in a valid vco range\n", 733 clk_hw_get_name(hw)); 734 return -EINVAL; 735 } 736 737 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 738 739 if (alpha_width > ALPHA_BITWIDTH) 740 a <<= alpha_width - ALPHA_BITWIDTH; 741 742 if (alpha_width > 32) 743 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), a >> 32); 744 745 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); 746 747 if (vco) { 748 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 749 PLL_VCO_MASK << PLL_VCO_SHIFT, 750 vco->val << PLL_VCO_SHIFT); 751 } 752 753 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 754 PLL_ALPHA_EN, PLL_ALPHA_EN); 755 756 return clk_alpha_pll_update_latch(pll, is_enabled); 757 } 758 759 static int clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate, 760 unsigned long prate) 761 { 762 return __clk_alpha_pll_set_rate(hw, rate, prate, 763 clk_alpha_pll_is_enabled); 764 } 765 766 static int clk_alpha_pll_hwfsm_set_rate(struct clk_hw *hw, unsigned long rate, 767 unsigned long prate) 768 { 769 return __clk_alpha_pll_set_rate(hw, rate, prate, 770 clk_alpha_pll_hwfsm_is_enabled); 771 } 772 773 static long clk_alpha_pll_round_rate(struct clk_hw *hw, unsigned long rate, 774 unsigned long *prate) 775 { 776 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 777 u32 l, alpha_width = pll_alpha_width(pll); 778 u64 a; 779 unsigned long min_freq, max_freq; 780 781 rate = alpha_pll_round_rate(rate, *prate, &l, &a, alpha_width); 782 if (!pll->vco_table || alpha_pll_find_vco(pll, rate)) 783 return rate; 784 785 min_freq = pll->vco_table[0].min_freq; 786 max_freq = pll->vco_table[pll->num_vco - 1].max_freq; 787 788 return clamp(rate, min_freq, max_freq); 789 } 790 791 static unsigned long 792 alpha_huayra_pll_calc_rate(u64 prate, u32 l, u32 a) 793 { 794 /* 795 * a contains 16 bit alpha_val in two’s complement number in the range 796 * of [-0.5, 0.5). 797 */ 798 if (a >= BIT(PLL_HUAYRA_ALPHA_WIDTH - 1)) 799 l -= 1; 800 801 return (prate * l) + (prate * a >> PLL_HUAYRA_ALPHA_WIDTH); 802 } 803 804 static unsigned long 805 alpha_huayra_pll_round_rate(unsigned long rate, unsigned long prate, 806 u32 *l, u32 *a) 807 { 808 u64 remainder; 809 u64 quotient; 810 811 quotient = rate; 812 remainder = do_div(quotient, prate); 813 *l = quotient; 814 815 if (!remainder) { 816 *a = 0; 817 return rate; 818 } 819 820 quotient = remainder << PLL_HUAYRA_ALPHA_WIDTH; 821 remainder = do_div(quotient, prate); 822 823 if (remainder) 824 quotient++; 825 826 /* 827 * alpha_val should be in two’s complement number in the range 828 * of [-0.5, 0.5) so if quotient >= 0.5 then increment the l value 829 * since alpha value will be subtracted in this case. 830 */ 831 if (quotient >= BIT(PLL_HUAYRA_ALPHA_WIDTH - 1)) 832 *l += 1; 833 834 *a = quotient; 835 return alpha_huayra_pll_calc_rate(prate, *l, *a); 836 } 837 838 static unsigned long 839 alpha_pll_huayra_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 840 { 841 u64 rate = parent_rate, tmp; 842 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 843 u32 l, alpha = 0, ctl, alpha_m, alpha_n; 844 845 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); 846 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); 847 848 if (ctl & PLL_ALPHA_EN) { 849 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &alpha); 850 /* 851 * Depending upon alpha_mode, it can be treated as M/N value or 852 * as a two’s complement number. When alpha_mode=1, 853 * pll_alpha_val<15:8>=M and pll_apla_val<7:0>=N 854 * 855 * Fout=FIN*(L+(M/N)) 856 * 857 * M is a signed number (-128 to 127) and N is unsigned 858 * (0 to 255). M/N has to be within +/-0.5. 859 * 860 * When alpha_mode=0, it is a two’s complement number in the 861 * range [-0.5, 0.5). 862 * 863 * Fout=FIN*(L+(alpha_val)/2^16) 864 * 865 * where alpha_val is two’s complement number. 866 */ 867 if (!(ctl & PLL_ALPHA_MODE)) 868 return alpha_huayra_pll_calc_rate(rate, l, alpha); 869 870 alpha_m = alpha >> PLL_HUAYRA_M_SHIFT & PLL_HUAYRA_M_MASK; 871 alpha_n = alpha >> PLL_HUAYRA_N_SHIFT & PLL_HUAYRA_N_MASK; 872 873 rate *= l; 874 tmp = parent_rate; 875 if (alpha_m >= BIT(PLL_HUAYRA_M_WIDTH - 1)) { 876 alpha_m = BIT(PLL_HUAYRA_M_WIDTH) - alpha_m; 877 tmp *= alpha_m; 878 do_div(tmp, alpha_n); 879 rate -= tmp; 880 } else { 881 tmp *= alpha_m; 882 do_div(tmp, alpha_n); 883 rate += tmp; 884 } 885 886 return rate; 887 } 888 889 return alpha_huayra_pll_calc_rate(rate, l, alpha); 890 } 891 892 static int alpha_pll_huayra_set_rate(struct clk_hw *hw, unsigned long rate, 893 unsigned long prate) 894 { 895 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 896 u32 l, a, ctl, cur_alpha = 0; 897 898 rate = alpha_huayra_pll_round_rate(rate, prate, &l, &a); 899 900 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); 901 902 if (ctl & PLL_ALPHA_EN) 903 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &cur_alpha); 904 905 /* 906 * Huayra PLL supports PLL dynamic programming. User can change L_VAL, 907 * without having to go through the power on sequence. 908 */ 909 if (clk_alpha_pll_is_enabled(hw)) { 910 if (cur_alpha != a) { 911 pr_err("%s: clock needs to be gated\n", 912 clk_hw_get_name(hw)); 913 return -EBUSY; 914 } 915 916 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 917 /* Ensure that the write above goes to detect L val change. */ 918 mb(); 919 return wait_for_pll_enable_lock(pll); 920 } 921 922 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 923 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); 924 925 if (a == 0) 926 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 927 PLL_ALPHA_EN, 0x0); 928 else 929 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 930 PLL_ALPHA_EN | PLL_ALPHA_MODE, PLL_ALPHA_EN); 931 932 return 0; 933 } 934 935 static long alpha_pll_huayra_round_rate(struct clk_hw *hw, unsigned long rate, 936 unsigned long *prate) 937 { 938 u32 l, a; 939 940 return alpha_huayra_pll_round_rate(rate, *prate, &l, &a); 941 } 942 943 static int trion_pll_is_enabled(struct clk_alpha_pll *pll, 944 struct regmap *regmap) 945 { 946 u32 mode_val, opmode_val; 947 int ret; 948 949 ret = regmap_read(regmap, PLL_MODE(pll), &mode_val); 950 ret |= regmap_read(regmap, PLL_OPMODE(pll), &opmode_val); 951 if (ret) 952 return 0; 953 954 return ((opmode_val & PLL_RUN) && (mode_val & PLL_OUTCTRL)); 955 } 956 957 static int clk_trion_pll_is_enabled(struct clk_hw *hw) 958 { 959 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 960 961 return trion_pll_is_enabled(pll, pll->clkr.regmap); 962 } 963 964 static int clk_trion_pll_enable(struct clk_hw *hw) 965 { 966 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 967 struct regmap *regmap = pll->clkr.regmap; 968 u32 val; 969 int ret; 970 971 ret = regmap_read(regmap, PLL_MODE(pll), &val); 972 if (ret) 973 return ret; 974 975 /* If in FSM mode, just vote for it */ 976 if (val & PLL_VOTE_FSM_ENA) { 977 ret = clk_enable_regmap(hw); 978 if (ret) 979 return ret; 980 return wait_for_pll_enable_active(pll); 981 } 982 983 /* Set operation mode to RUN */ 984 regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); 985 986 ret = wait_for_pll_enable_lock(pll); 987 if (ret) 988 return ret; 989 990 /* Enable the PLL outputs */ 991 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), 992 PLL_OUT_MASK, PLL_OUT_MASK); 993 if (ret) 994 return ret; 995 996 /* Enable the global PLL outputs */ 997 return regmap_update_bits(regmap, PLL_MODE(pll), 998 PLL_OUTCTRL, PLL_OUTCTRL); 999 } 1000 1001 static void clk_trion_pll_disable(struct clk_hw *hw) 1002 { 1003 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1004 struct regmap *regmap = pll->clkr.regmap; 1005 u32 val; 1006 int ret; 1007 1008 ret = regmap_read(regmap, PLL_MODE(pll), &val); 1009 if (ret) 1010 return; 1011 1012 /* If in FSM mode, just unvote it */ 1013 if (val & PLL_VOTE_FSM_ENA) { 1014 clk_disable_regmap(hw); 1015 return; 1016 } 1017 1018 /* Disable the global PLL output */ 1019 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 1020 if (ret) 1021 return; 1022 1023 /* Disable the PLL outputs */ 1024 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), 1025 PLL_OUT_MASK, 0); 1026 if (ret) 1027 return; 1028 1029 /* Place the PLL mode in STANDBY */ 1030 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 1031 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 1032 } 1033 1034 static unsigned long 1035 clk_trion_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 1036 { 1037 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1038 u32 l, frac, alpha_width = pll_alpha_width(pll); 1039 1040 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); 1041 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &frac); 1042 1043 return alpha_pll_calc_rate(parent_rate, l, frac, alpha_width); 1044 } 1045 1046 const struct clk_ops clk_alpha_pll_fixed_ops = { 1047 .enable = clk_alpha_pll_enable, 1048 .disable = clk_alpha_pll_disable, 1049 .is_enabled = clk_alpha_pll_is_enabled, 1050 .recalc_rate = clk_alpha_pll_recalc_rate, 1051 }; 1052 EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_ops); 1053 1054 const struct clk_ops clk_alpha_pll_ops = { 1055 .enable = clk_alpha_pll_enable, 1056 .disable = clk_alpha_pll_disable, 1057 .is_enabled = clk_alpha_pll_is_enabled, 1058 .recalc_rate = clk_alpha_pll_recalc_rate, 1059 .round_rate = clk_alpha_pll_round_rate, 1060 .set_rate = clk_alpha_pll_set_rate, 1061 }; 1062 EXPORT_SYMBOL_GPL(clk_alpha_pll_ops); 1063 1064 const struct clk_ops clk_alpha_pll_huayra_ops = { 1065 .enable = clk_alpha_pll_enable, 1066 .disable = clk_alpha_pll_disable, 1067 .is_enabled = clk_alpha_pll_is_enabled, 1068 .recalc_rate = alpha_pll_huayra_recalc_rate, 1069 .round_rate = alpha_pll_huayra_round_rate, 1070 .set_rate = alpha_pll_huayra_set_rate, 1071 }; 1072 EXPORT_SYMBOL_GPL(clk_alpha_pll_huayra_ops); 1073 1074 const struct clk_ops clk_alpha_pll_hwfsm_ops = { 1075 .enable = clk_alpha_pll_hwfsm_enable, 1076 .disable = clk_alpha_pll_hwfsm_disable, 1077 .is_enabled = clk_alpha_pll_hwfsm_is_enabled, 1078 .recalc_rate = clk_alpha_pll_recalc_rate, 1079 .round_rate = clk_alpha_pll_round_rate, 1080 .set_rate = clk_alpha_pll_hwfsm_set_rate, 1081 }; 1082 EXPORT_SYMBOL_GPL(clk_alpha_pll_hwfsm_ops); 1083 1084 const struct clk_ops clk_alpha_pll_fixed_trion_ops = { 1085 .enable = clk_trion_pll_enable, 1086 .disable = clk_trion_pll_disable, 1087 .is_enabled = clk_trion_pll_is_enabled, 1088 .recalc_rate = clk_trion_pll_recalc_rate, 1089 .round_rate = clk_alpha_pll_round_rate, 1090 }; 1091 EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_trion_ops); 1092 1093 static unsigned long 1094 clk_alpha_pll_postdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 1095 { 1096 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1097 u32 ctl; 1098 1099 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); 1100 1101 ctl >>= PLL_POST_DIV_SHIFT; 1102 ctl &= PLL_POST_DIV_MASK(pll); 1103 1104 return parent_rate >> fls(ctl); 1105 } 1106 1107 static const struct clk_div_table clk_alpha_div_table[] = { 1108 { 0x0, 1 }, 1109 { 0x1, 2 }, 1110 { 0x3, 4 }, 1111 { 0x7, 8 }, 1112 { 0xf, 16 }, 1113 { } 1114 }; 1115 1116 static const struct clk_div_table clk_alpha_2bit_div_table[] = { 1117 { 0x0, 1 }, 1118 { 0x1, 2 }, 1119 { 0x3, 4 }, 1120 { } 1121 }; 1122 1123 static long 1124 clk_alpha_pll_postdiv_round_rate(struct clk_hw *hw, unsigned long rate, 1125 unsigned long *prate) 1126 { 1127 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1128 const struct clk_div_table *table; 1129 1130 if (pll->width == 2) 1131 table = clk_alpha_2bit_div_table; 1132 else 1133 table = clk_alpha_div_table; 1134 1135 return divider_round_rate(hw, rate, prate, table, 1136 pll->width, CLK_DIVIDER_POWER_OF_TWO); 1137 } 1138 1139 static long 1140 clk_alpha_pll_postdiv_round_ro_rate(struct clk_hw *hw, unsigned long rate, 1141 unsigned long *prate) 1142 { 1143 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1144 u32 ctl, div; 1145 1146 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); 1147 1148 ctl >>= PLL_POST_DIV_SHIFT; 1149 ctl &= BIT(pll->width) - 1; 1150 div = 1 << fls(ctl); 1151 1152 if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) 1153 *prate = clk_hw_round_rate(clk_hw_get_parent(hw), div * rate); 1154 1155 return DIV_ROUND_UP_ULL((u64)*prate, div); 1156 } 1157 1158 static int clk_alpha_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, 1159 unsigned long parent_rate) 1160 { 1161 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1162 int div; 1163 1164 /* 16 -> 0xf, 8 -> 0x7, 4 -> 0x3, 2 -> 0x1, 1 -> 0x0 */ 1165 div = DIV_ROUND_UP_ULL(parent_rate, rate) - 1; 1166 1167 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 1168 PLL_POST_DIV_MASK(pll) << PLL_POST_DIV_SHIFT, 1169 div << PLL_POST_DIV_SHIFT); 1170 } 1171 1172 const struct clk_ops clk_alpha_pll_postdiv_ops = { 1173 .recalc_rate = clk_alpha_pll_postdiv_recalc_rate, 1174 .round_rate = clk_alpha_pll_postdiv_round_rate, 1175 .set_rate = clk_alpha_pll_postdiv_set_rate, 1176 }; 1177 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_ops); 1178 1179 const struct clk_ops clk_alpha_pll_postdiv_ro_ops = { 1180 .round_rate = clk_alpha_pll_postdiv_round_ro_rate, 1181 .recalc_rate = clk_alpha_pll_postdiv_recalc_rate, 1182 }; 1183 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_ro_ops); 1184 1185 void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 1186 const struct alpha_pll_config *config) 1187 { 1188 u32 val, mask; 1189 1190 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); 1191 clk_alpha_pll_write_config(regmap, PLL_FRAC(pll), config->alpha); 1192 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), 1193 config->config_ctl_val); 1194 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), 1195 config->config_ctl_hi_val); 1196 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), 1197 config->user_ctl_val); 1198 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), 1199 config->user_ctl_hi_val); 1200 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), 1201 config->test_ctl_val); 1202 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), 1203 config->test_ctl_hi_val); 1204 1205 if (config->post_div_mask) { 1206 mask = config->post_div_mask; 1207 val = config->post_div_val; 1208 regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val); 1209 } 1210 1211 if (pll->flags & SUPPORTS_FSM_LEGACY_MODE) 1212 regmap_update_bits(regmap, PLL_MODE(pll), PLL_FSM_LEGACY_MODE, 1213 PLL_FSM_LEGACY_MODE); 1214 1215 regmap_update_bits(regmap, PLL_MODE(pll), PLL_UPDATE_BYPASS, 1216 PLL_UPDATE_BYPASS); 1217 1218 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 1219 } 1220 EXPORT_SYMBOL_GPL(clk_fabia_pll_configure); 1221 1222 static int alpha_pll_fabia_enable(struct clk_hw *hw) 1223 { 1224 int ret; 1225 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1226 u32 val, opmode_val; 1227 struct regmap *regmap = pll->clkr.regmap; 1228 1229 ret = regmap_read(regmap, PLL_MODE(pll), &val); 1230 if (ret) 1231 return ret; 1232 1233 /* If in FSM mode, just vote for it */ 1234 if (val & PLL_VOTE_FSM_ENA) { 1235 ret = clk_enable_regmap(hw); 1236 if (ret) 1237 return ret; 1238 return wait_for_pll_enable_active(pll); 1239 } 1240 1241 ret = regmap_read(regmap, PLL_OPMODE(pll), &opmode_val); 1242 if (ret) 1243 return ret; 1244 1245 /* Skip If PLL is already running */ 1246 if ((opmode_val & PLL_RUN) && (val & PLL_OUTCTRL)) 1247 return 0; 1248 1249 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 1250 if (ret) 1251 return ret; 1252 1253 ret = regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 1254 if (ret) 1255 return ret; 1256 1257 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, 1258 PLL_RESET_N); 1259 if (ret) 1260 return ret; 1261 1262 ret = regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); 1263 if (ret) 1264 return ret; 1265 1266 ret = wait_for_pll_enable_lock(pll); 1267 if (ret) 1268 return ret; 1269 1270 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), 1271 PLL_OUT_MASK, PLL_OUT_MASK); 1272 if (ret) 1273 return ret; 1274 1275 return regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 1276 PLL_OUTCTRL); 1277 } 1278 1279 static void alpha_pll_fabia_disable(struct clk_hw *hw) 1280 { 1281 int ret; 1282 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1283 u32 val; 1284 struct regmap *regmap = pll->clkr.regmap; 1285 1286 ret = regmap_read(regmap, PLL_MODE(pll), &val); 1287 if (ret) 1288 return; 1289 1290 /* If in FSM mode, just unvote it */ 1291 if (val & PLL_FSM_ENA) { 1292 clk_disable_regmap(hw); 1293 return; 1294 } 1295 1296 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 1297 if (ret) 1298 return; 1299 1300 /* Disable main outputs */ 1301 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0); 1302 if (ret) 1303 return; 1304 1305 /* Place the PLL in STANDBY */ 1306 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 1307 } 1308 1309 static unsigned long alpha_pll_fabia_recalc_rate(struct clk_hw *hw, 1310 unsigned long parent_rate) 1311 { 1312 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1313 u32 l, frac, alpha_width = pll_alpha_width(pll); 1314 1315 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); 1316 regmap_read(pll->clkr.regmap, PLL_FRAC(pll), &frac); 1317 1318 return alpha_pll_calc_rate(parent_rate, l, frac, alpha_width); 1319 } 1320 1321 /* 1322 * Due to limited number of bits for fractional rate programming, the 1323 * rounded up rate could be marginally higher than the requested rate. 1324 */ 1325 static int alpha_pll_check_rate_margin(struct clk_hw *hw, 1326 unsigned long rrate, unsigned long rate) 1327 { 1328 unsigned long rate_margin = rate + PLL_RATE_MARGIN; 1329 1330 if (rrate > rate_margin || rrate < rate) { 1331 pr_err("%s: Rounded rate %lu not within range [%lu, %lu)\n", 1332 clk_hw_get_name(hw), rrate, rate, rate_margin); 1333 return -EINVAL; 1334 } 1335 1336 return 0; 1337 } 1338 1339 static int alpha_pll_fabia_set_rate(struct clk_hw *hw, unsigned long rate, 1340 unsigned long prate) 1341 { 1342 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1343 u32 l, alpha_width = pll_alpha_width(pll); 1344 unsigned long rrate; 1345 int ret; 1346 u64 a; 1347 1348 rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width); 1349 1350 ret = alpha_pll_check_rate_margin(hw, rrate, rate); 1351 if (ret < 0) 1352 return ret; 1353 1354 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 1355 regmap_write(pll->clkr.regmap, PLL_FRAC(pll), a); 1356 1357 return __clk_alpha_pll_update_latch(pll); 1358 } 1359 1360 static int alpha_pll_fabia_prepare(struct clk_hw *hw) 1361 { 1362 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1363 const struct pll_vco *vco; 1364 struct clk_hw *parent_hw; 1365 unsigned long cal_freq, rrate; 1366 u32 cal_l, val, alpha_width = pll_alpha_width(pll); 1367 const char *name = clk_hw_get_name(hw); 1368 u64 a; 1369 int ret; 1370 1371 /* Check if calibration needs to be done i.e. PLL is in reset */ 1372 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 1373 if (ret) 1374 return ret; 1375 1376 /* Return early if calibration is not needed. */ 1377 if (val & PLL_RESET_N) 1378 return 0; 1379 1380 vco = alpha_pll_find_vco(pll, clk_hw_get_rate(hw)); 1381 if (!vco) { 1382 pr_err("%s: alpha pll not in a valid vco range\n", name); 1383 return -EINVAL; 1384 } 1385 1386 cal_freq = DIV_ROUND_CLOSEST((pll->vco_table[0].min_freq + 1387 pll->vco_table[0].max_freq) * 54, 100); 1388 1389 parent_hw = clk_hw_get_parent(hw); 1390 if (!parent_hw) 1391 return -EINVAL; 1392 1393 rrate = alpha_pll_round_rate(cal_freq, clk_hw_get_rate(parent_hw), 1394 &cal_l, &a, alpha_width); 1395 1396 ret = alpha_pll_check_rate_margin(hw, rrate, cal_freq); 1397 if (ret < 0) 1398 return ret; 1399 1400 /* Setup PLL for calibration frequency */ 1401 regmap_write(pll->clkr.regmap, PLL_CAL_L_VAL(pll), cal_l); 1402 1403 /* Bringup the PLL at calibration frequency */ 1404 ret = clk_alpha_pll_enable(hw); 1405 if (ret) { 1406 pr_err("%s: alpha pll calibration failed\n", name); 1407 return ret; 1408 } 1409 1410 clk_alpha_pll_disable(hw); 1411 1412 return 0; 1413 } 1414 1415 const struct clk_ops clk_alpha_pll_fabia_ops = { 1416 .prepare = alpha_pll_fabia_prepare, 1417 .enable = alpha_pll_fabia_enable, 1418 .disable = alpha_pll_fabia_disable, 1419 .is_enabled = clk_alpha_pll_is_enabled, 1420 .set_rate = alpha_pll_fabia_set_rate, 1421 .recalc_rate = alpha_pll_fabia_recalc_rate, 1422 .round_rate = clk_alpha_pll_round_rate, 1423 }; 1424 EXPORT_SYMBOL_GPL(clk_alpha_pll_fabia_ops); 1425 1426 const struct clk_ops clk_alpha_pll_fixed_fabia_ops = { 1427 .enable = alpha_pll_fabia_enable, 1428 .disable = alpha_pll_fabia_disable, 1429 .is_enabled = clk_alpha_pll_is_enabled, 1430 .recalc_rate = alpha_pll_fabia_recalc_rate, 1431 .round_rate = clk_alpha_pll_round_rate, 1432 }; 1433 EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_fabia_ops); 1434 1435 static unsigned long clk_alpha_pll_postdiv_fabia_recalc_rate(struct clk_hw *hw, 1436 unsigned long parent_rate) 1437 { 1438 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1439 u32 i, div = 1, val; 1440 int ret; 1441 1442 ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val); 1443 if (ret) 1444 return ret; 1445 1446 val >>= pll->post_div_shift; 1447 val &= BIT(pll->width) - 1; 1448 1449 for (i = 0; i < pll->num_post_div; i++) { 1450 if (pll->post_div_table[i].val == val) { 1451 div = pll->post_div_table[i].div; 1452 break; 1453 } 1454 } 1455 1456 return (parent_rate / div); 1457 } 1458 1459 static unsigned long 1460 clk_trion_pll_postdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 1461 { 1462 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1463 struct regmap *regmap = pll->clkr.regmap; 1464 u32 i, div = 1, val; 1465 1466 regmap_read(regmap, PLL_USER_CTL(pll), &val); 1467 1468 val >>= pll->post_div_shift; 1469 val &= PLL_POST_DIV_MASK(pll); 1470 1471 for (i = 0; i < pll->num_post_div; i++) { 1472 if (pll->post_div_table[i].val == val) { 1473 div = pll->post_div_table[i].div; 1474 break; 1475 } 1476 } 1477 1478 return (parent_rate / div); 1479 } 1480 1481 static long 1482 clk_trion_pll_postdiv_round_rate(struct clk_hw *hw, unsigned long rate, 1483 unsigned long *prate) 1484 { 1485 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1486 1487 return divider_round_rate(hw, rate, prate, pll->post_div_table, 1488 pll->width, CLK_DIVIDER_ROUND_CLOSEST); 1489 }; 1490 1491 static int 1492 clk_trion_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, 1493 unsigned long parent_rate) 1494 { 1495 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1496 struct regmap *regmap = pll->clkr.regmap; 1497 int i, val = 0, div; 1498 1499 div = DIV_ROUND_UP_ULL(parent_rate, rate); 1500 for (i = 0; i < pll->num_post_div; i++) { 1501 if (pll->post_div_table[i].div == div) { 1502 val = pll->post_div_table[i].val; 1503 break; 1504 } 1505 } 1506 1507 return regmap_update_bits(regmap, PLL_USER_CTL(pll), 1508 PLL_POST_DIV_MASK(pll) << pll->post_div_shift, 1509 val << pll->post_div_shift); 1510 } 1511 1512 const struct clk_ops clk_alpha_pll_postdiv_trion_ops = { 1513 .recalc_rate = clk_trion_pll_postdiv_recalc_rate, 1514 .round_rate = clk_trion_pll_postdiv_round_rate, 1515 .set_rate = clk_trion_pll_postdiv_set_rate, 1516 }; 1517 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_trion_ops); 1518 1519 static long clk_alpha_pll_postdiv_fabia_round_rate(struct clk_hw *hw, 1520 unsigned long rate, unsigned long *prate) 1521 { 1522 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1523 1524 return divider_round_rate(hw, rate, prate, pll->post_div_table, 1525 pll->width, CLK_DIVIDER_ROUND_CLOSEST); 1526 } 1527 1528 static int clk_alpha_pll_postdiv_fabia_set_rate(struct clk_hw *hw, 1529 unsigned long rate, unsigned long parent_rate) 1530 { 1531 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1532 int i, val = 0, div, ret; 1533 1534 /* 1535 * If the PLL is in FSM mode, then treat set_rate callback as a 1536 * no-operation. 1537 */ 1538 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 1539 if (ret) 1540 return ret; 1541 1542 if (val & PLL_VOTE_FSM_ENA) 1543 return 0; 1544 1545 div = DIV_ROUND_UP_ULL(parent_rate, rate); 1546 for (i = 0; i < pll->num_post_div; i++) { 1547 if (pll->post_div_table[i].div == div) { 1548 val = pll->post_div_table[i].val; 1549 break; 1550 } 1551 } 1552 1553 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 1554 (BIT(pll->width) - 1) << pll->post_div_shift, 1555 val << pll->post_div_shift); 1556 } 1557 1558 const struct clk_ops clk_alpha_pll_postdiv_fabia_ops = { 1559 .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate, 1560 .round_rate = clk_alpha_pll_postdiv_fabia_round_rate, 1561 .set_rate = clk_alpha_pll_postdiv_fabia_set_rate, 1562 }; 1563 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_fabia_ops); 1564 1565 /** 1566 * clk_trion_pll_configure - configure the trion pll 1567 * 1568 * @pll: clk alpha pll 1569 * @regmap: register map 1570 * @config: configuration to apply for pll 1571 */ 1572 void clk_trion_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 1573 const struct alpha_pll_config *config) 1574 { 1575 /* 1576 * If the bootloader left the PLL enabled it's likely that there are 1577 * RCGs that will lock up if we disable the PLL below. 1578 */ 1579 if (trion_pll_is_enabled(pll, regmap)) { 1580 pr_debug("Trion PLL is already enabled, skipping configuration\n"); 1581 return; 1582 } 1583 1584 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); 1585 regmap_write(regmap, PLL_CAL_L_VAL(pll), TRION_PLL_CAL_VAL); 1586 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); 1587 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), 1588 config->config_ctl_val); 1589 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), 1590 config->config_ctl_hi_val); 1591 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), 1592 config->config_ctl_hi1_val); 1593 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), 1594 config->user_ctl_val); 1595 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), 1596 config->user_ctl_hi_val); 1597 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll), 1598 config->user_ctl_hi1_val); 1599 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), 1600 config->test_ctl_val); 1601 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), 1602 config->test_ctl_hi_val); 1603 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), 1604 config->test_ctl_hi1_val); 1605 1606 regmap_update_bits(regmap, PLL_MODE(pll), PLL_UPDATE_BYPASS, 1607 PLL_UPDATE_BYPASS); 1608 1609 /* Disable PLL output */ 1610 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 1611 1612 /* Set operation mode to OFF */ 1613 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 1614 1615 /* Place the PLL in STANDBY mode */ 1616 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 1617 } 1618 EXPORT_SYMBOL_GPL(clk_trion_pll_configure); 1619 1620 /* 1621 * The TRION PLL requires a power-on self-calibration which happens when the 1622 * PLL comes out of reset. Calibrate in case it is not completed. 1623 */ 1624 static int __alpha_pll_trion_prepare(struct clk_hw *hw, u32 pcal_done) 1625 { 1626 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1627 u32 val; 1628 int ret; 1629 1630 /* Return early if calibration is not needed. */ 1631 regmap_read(pll->clkr.regmap, PLL_STATUS(pll), &val); 1632 if (val & pcal_done) 1633 return 0; 1634 1635 /* On/off to calibrate */ 1636 ret = clk_trion_pll_enable(hw); 1637 if (!ret) 1638 clk_trion_pll_disable(hw); 1639 1640 return ret; 1641 } 1642 1643 static int alpha_pll_trion_prepare(struct clk_hw *hw) 1644 { 1645 return __alpha_pll_trion_prepare(hw, TRION_PCAL_DONE); 1646 } 1647 1648 static int alpha_pll_lucid_prepare(struct clk_hw *hw) 1649 { 1650 return __alpha_pll_trion_prepare(hw, LUCID_PCAL_DONE); 1651 } 1652 1653 static int __alpha_pll_trion_set_rate(struct clk_hw *hw, unsigned long rate, 1654 unsigned long prate, u32 latch_bit, u32 latch_ack) 1655 { 1656 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1657 unsigned long rrate; 1658 u32 val, l, alpha_width = pll_alpha_width(pll); 1659 u64 a; 1660 int ret; 1661 1662 rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width); 1663 1664 ret = alpha_pll_check_rate_margin(hw, rrate, rate); 1665 if (ret < 0) 1666 return ret; 1667 1668 regmap_update_bits(pll->clkr.regmap, PLL_L_VAL(pll), LUCID_EVO_PLL_L_VAL_MASK, l); 1669 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); 1670 1671 /* Latch the PLL input */ 1672 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), latch_bit, latch_bit); 1673 if (ret) 1674 return ret; 1675 1676 /* Wait for 2 reference cycles before checking the ACK bit. */ 1677 udelay(1); 1678 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 1679 if (!(val & latch_ack)) { 1680 pr_err("Lucid PLL latch failed. Output may be unstable!\n"); 1681 return -EINVAL; 1682 } 1683 1684 /* Return the latch input to 0 */ 1685 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), latch_bit, 0); 1686 if (ret) 1687 return ret; 1688 1689 if (clk_hw_is_enabled(hw)) { 1690 ret = wait_for_pll_enable_lock(pll); 1691 if (ret) 1692 return ret; 1693 } 1694 1695 /* Wait for PLL output to stabilize */ 1696 udelay(100); 1697 return 0; 1698 } 1699 1700 static int alpha_pll_trion_set_rate(struct clk_hw *hw, unsigned long rate, 1701 unsigned long prate) 1702 { 1703 return __alpha_pll_trion_set_rate(hw, rate, prate, PLL_UPDATE, ALPHA_PLL_ACK_LATCH); 1704 } 1705 1706 const struct clk_ops clk_alpha_pll_trion_ops = { 1707 .prepare = alpha_pll_trion_prepare, 1708 .enable = clk_trion_pll_enable, 1709 .disable = clk_trion_pll_disable, 1710 .is_enabled = clk_trion_pll_is_enabled, 1711 .recalc_rate = clk_trion_pll_recalc_rate, 1712 .round_rate = clk_alpha_pll_round_rate, 1713 .set_rate = alpha_pll_trion_set_rate, 1714 }; 1715 EXPORT_SYMBOL_GPL(clk_alpha_pll_trion_ops); 1716 1717 const struct clk_ops clk_alpha_pll_lucid_ops = { 1718 .prepare = alpha_pll_lucid_prepare, 1719 .enable = clk_trion_pll_enable, 1720 .disable = clk_trion_pll_disable, 1721 .is_enabled = clk_trion_pll_is_enabled, 1722 .recalc_rate = clk_trion_pll_recalc_rate, 1723 .round_rate = clk_alpha_pll_round_rate, 1724 .set_rate = alpha_pll_trion_set_rate, 1725 }; 1726 EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_ops); 1727 1728 const struct clk_ops clk_alpha_pll_postdiv_lucid_ops = { 1729 .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate, 1730 .round_rate = clk_alpha_pll_postdiv_fabia_round_rate, 1731 .set_rate = clk_alpha_pll_postdiv_fabia_set_rate, 1732 }; 1733 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_ops); 1734 1735 void clk_agera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 1736 const struct alpha_pll_config *config) 1737 { 1738 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); 1739 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); 1740 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), 1741 config->user_ctl_val); 1742 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), 1743 config->config_ctl_val); 1744 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), 1745 config->config_ctl_hi_val); 1746 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), 1747 config->test_ctl_val); 1748 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), 1749 config->test_ctl_hi_val); 1750 } 1751 EXPORT_SYMBOL_GPL(clk_agera_pll_configure); 1752 1753 static int clk_alpha_pll_agera_set_rate(struct clk_hw *hw, unsigned long rate, 1754 unsigned long prate) 1755 { 1756 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1757 u32 l, alpha_width = pll_alpha_width(pll); 1758 int ret; 1759 unsigned long rrate; 1760 u64 a; 1761 1762 rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width); 1763 ret = alpha_pll_check_rate_margin(hw, rrate, rate); 1764 if (ret < 0) 1765 return ret; 1766 1767 /* change L_VAL without having to go through the power on sequence */ 1768 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 1769 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); 1770 1771 if (clk_hw_is_enabled(hw)) 1772 return wait_for_pll_enable_lock(pll); 1773 1774 return 0; 1775 } 1776 1777 const struct clk_ops clk_alpha_pll_agera_ops = { 1778 .enable = clk_alpha_pll_enable, 1779 .disable = clk_alpha_pll_disable, 1780 .is_enabled = clk_alpha_pll_is_enabled, 1781 .recalc_rate = alpha_pll_fabia_recalc_rate, 1782 .round_rate = clk_alpha_pll_round_rate, 1783 .set_rate = clk_alpha_pll_agera_set_rate, 1784 }; 1785 EXPORT_SYMBOL_GPL(clk_alpha_pll_agera_ops); 1786 1787 /** 1788 * clk_lucid_5lpe_pll_configure - configure the lucid 5lpe pll 1789 * 1790 * @pll: clk alpha pll 1791 * @regmap: register map 1792 * @config: configuration to apply for pll 1793 */ 1794 void clk_lucid_5lpe_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 1795 const struct alpha_pll_config *config) 1796 { 1797 /* 1798 * If the bootloader left the PLL enabled it's likely that there are 1799 * RCGs that will lock up if we disable the PLL below. 1800 */ 1801 if (trion_pll_is_enabled(pll, regmap)) { 1802 pr_debug("Lucid 5LPE PLL is already enabled, skipping configuration\n"); 1803 return; 1804 } 1805 1806 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); 1807 regmap_write(regmap, PLL_CAL_L_VAL(pll), TRION_PLL_CAL_VAL); 1808 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); 1809 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), 1810 config->config_ctl_val); 1811 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), 1812 config->config_ctl_hi_val); 1813 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), 1814 config->config_ctl_hi1_val); 1815 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), 1816 config->user_ctl_val); 1817 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), 1818 config->user_ctl_hi_val); 1819 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll), 1820 config->user_ctl_hi1_val); 1821 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), 1822 config->test_ctl_val); 1823 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), 1824 config->test_ctl_hi_val); 1825 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), 1826 config->test_ctl_hi1_val); 1827 1828 /* Disable PLL output */ 1829 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 1830 1831 /* Set operation mode to OFF */ 1832 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 1833 1834 /* Place the PLL in STANDBY mode */ 1835 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 1836 } 1837 EXPORT_SYMBOL_GPL(clk_lucid_5lpe_pll_configure); 1838 1839 static int alpha_pll_lucid_5lpe_enable(struct clk_hw *hw) 1840 { 1841 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1842 u32 val; 1843 int ret; 1844 1845 ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val); 1846 if (ret) 1847 return ret; 1848 1849 /* If in FSM mode, just vote for it */ 1850 if (val & LUCID_5LPE_ENABLE_VOTE_RUN) { 1851 ret = clk_enable_regmap(hw); 1852 if (ret) 1853 return ret; 1854 return wait_for_pll_enable_lock(pll); 1855 } 1856 1857 /* Check if PLL is already enabled, return if enabled */ 1858 ret = trion_pll_is_enabled(pll, pll->clkr.regmap); 1859 if (ret < 0) 1860 return ret; 1861 1862 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 1863 if (ret) 1864 return ret; 1865 1866 regmap_write(pll->clkr.regmap, PLL_OPMODE(pll), PLL_RUN); 1867 1868 ret = wait_for_pll_enable_lock(pll); 1869 if (ret) 1870 return ret; 1871 1872 /* Enable the PLL outputs */ 1873 ret = regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, PLL_OUT_MASK); 1874 if (ret) 1875 return ret; 1876 1877 /* Enable the global PLL outputs */ 1878 return regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL); 1879 } 1880 1881 static void alpha_pll_lucid_5lpe_disable(struct clk_hw *hw) 1882 { 1883 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1884 u32 val; 1885 int ret; 1886 1887 ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val); 1888 if (ret) 1889 return; 1890 1891 /* If in FSM mode, just unvote it */ 1892 if (val & LUCID_5LPE_ENABLE_VOTE_RUN) { 1893 clk_disable_regmap(hw); 1894 return; 1895 } 1896 1897 /* Disable the global PLL output */ 1898 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 1899 if (ret) 1900 return; 1901 1902 /* Disable the PLL outputs */ 1903 ret = regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0); 1904 if (ret) 1905 return; 1906 1907 /* Place the PLL mode in STANDBY */ 1908 regmap_write(pll->clkr.regmap, PLL_OPMODE(pll), PLL_STANDBY); 1909 } 1910 1911 /* 1912 * The Lucid 5LPE PLL requires a power-on self-calibration which happens 1913 * when the PLL comes out of reset. Calibrate in case it is not completed. 1914 */ 1915 static int alpha_pll_lucid_5lpe_prepare(struct clk_hw *hw) 1916 { 1917 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1918 struct clk_hw *p; 1919 u32 val = 0; 1920 int ret; 1921 1922 /* Return early if calibration is not needed. */ 1923 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 1924 if (val & LUCID_5LPE_PCAL_DONE) 1925 return 0; 1926 1927 p = clk_hw_get_parent(hw); 1928 if (!p) 1929 return -EINVAL; 1930 1931 ret = alpha_pll_lucid_5lpe_enable(hw); 1932 if (ret) 1933 return ret; 1934 1935 alpha_pll_lucid_5lpe_disable(hw); 1936 1937 return 0; 1938 } 1939 1940 static int alpha_pll_lucid_5lpe_set_rate(struct clk_hw *hw, unsigned long rate, 1941 unsigned long prate) 1942 { 1943 return __alpha_pll_trion_set_rate(hw, rate, prate, 1944 LUCID_5LPE_PLL_LATCH_INPUT, 1945 LUCID_5LPE_ALPHA_PLL_ACK_LATCH); 1946 } 1947 1948 static int __clk_lucid_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, 1949 unsigned long parent_rate, 1950 unsigned long enable_vote_run) 1951 { 1952 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1953 struct regmap *regmap = pll->clkr.regmap; 1954 int i, val, div, ret; 1955 u32 mask; 1956 1957 /* 1958 * If the PLL is in FSM mode, then treat set_rate callback as a 1959 * no-operation. 1960 */ 1961 ret = regmap_read(regmap, PLL_USER_CTL(pll), &val); 1962 if (ret) 1963 return ret; 1964 1965 if (val & enable_vote_run) 1966 return 0; 1967 1968 if (!pll->post_div_table) { 1969 pr_err("Missing the post_div_table for the %s PLL\n", 1970 clk_hw_get_name(&pll->clkr.hw)); 1971 return -EINVAL; 1972 } 1973 1974 div = DIV_ROUND_UP_ULL((u64)parent_rate, rate); 1975 for (i = 0; i < pll->num_post_div; i++) { 1976 if (pll->post_div_table[i].div == div) { 1977 val = pll->post_div_table[i].val; 1978 break; 1979 } 1980 } 1981 1982 mask = GENMASK(pll->width + pll->post_div_shift - 1, pll->post_div_shift); 1983 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 1984 mask, val << pll->post_div_shift); 1985 } 1986 1987 static int clk_lucid_5lpe_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, 1988 unsigned long parent_rate) 1989 { 1990 return __clk_lucid_pll_postdiv_set_rate(hw, rate, parent_rate, LUCID_5LPE_ENABLE_VOTE_RUN); 1991 } 1992 1993 const struct clk_ops clk_alpha_pll_lucid_5lpe_ops = { 1994 .prepare = alpha_pll_lucid_5lpe_prepare, 1995 .enable = alpha_pll_lucid_5lpe_enable, 1996 .disable = alpha_pll_lucid_5lpe_disable, 1997 .is_enabled = clk_trion_pll_is_enabled, 1998 .recalc_rate = clk_trion_pll_recalc_rate, 1999 .round_rate = clk_alpha_pll_round_rate, 2000 .set_rate = alpha_pll_lucid_5lpe_set_rate, 2001 }; 2002 EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_5lpe_ops); 2003 2004 const struct clk_ops clk_alpha_pll_fixed_lucid_5lpe_ops = { 2005 .enable = alpha_pll_lucid_5lpe_enable, 2006 .disable = alpha_pll_lucid_5lpe_disable, 2007 .is_enabled = clk_trion_pll_is_enabled, 2008 .recalc_rate = clk_trion_pll_recalc_rate, 2009 .round_rate = clk_alpha_pll_round_rate, 2010 }; 2011 EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_lucid_5lpe_ops); 2012 2013 const struct clk_ops clk_alpha_pll_postdiv_lucid_5lpe_ops = { 2014 .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate, 2015 .round_rate = clk_alpha_pll_postdiv_fabia_round_rate, 2016 .set_rate = clk_lucid_5lpe_pll_postdiv_set_rate, 2017 }; 2018 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_5lpe_ops); 2019 2020 void clk_zonda_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 2021 const struct alpha_pll_config *config) 2022 { 2023 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); 2024 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); 2025 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); 2026 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); 2027 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); 2028 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val); 2029 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val); 2030 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll), config->user_ctl_hi1_val); 2031 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); 2032 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); 2033 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val); 2034 2035 regmap_update_bits(regmap, PLL_MODE(pll), PLL_BYPASSNL, 0); 2036 2037 /* Disable PLL output */ 2038 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 2039 2040 /* Set operation mode to OFF */ 2041 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 2042 2043 /* Place the PLL in STANDBY mode */ 2044 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 2045 } 2046 EXPORT_SYMBOL_GPL(clk_zonda_pll_configure); 2047 2048 static int clk_zonda_pll_enable(struct clk_hw *hw) 2049 { 2050 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2051 struct regmap *regmap = pll->clkr.regmap; 2052 u32 val; 2053 int ret; 2054 2055 regmap_read(regmap, PLL_MODE(pll), &val); 2056 2057 /* If in FSM mode, just vote for it */ 2058 if (val & PLL_VOTE_FSM_ENA) { 2059 ret = clk_enable_regmap(hw); 2060 if (ret) 2061 return ret; 2062 return wait_for_pll_enable_active(pll); 2063 } 2064 2065 /* Get the PLL out of bypass mode */ 2066 regmap_update_bits(regmap, PLL_MODE(pll), PLL_BYPASSNL, PLL_BYPASSNL); 2067 2068 /* 2069 * H/W requires a 1us delay between disabling the bypass and 2070 * de-asserting the reset. 2071 */ 2072 udelay(1); 2073 2074 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 2075 2076 /* Set operation mode to RUN */ 2077 regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); 2078 2079 regmap_read(regmap, PLL_TEST_CTL(pll), &val); 2080 2081 /* If cfa mode then poll for freq lock */ 2082 if (val & ZONDA_STAY_IN_CFA) 2083 ret = wait_for_zonda_pll_freq_lock(pll); 2084 else 2085 ret = wait_for_pll_enable_lock(pll); 2086 if (ret) 2087 return ret; 2088 2089 /* Enable the PLL outputs */ 2090 regmap_update_bits(regmap, PLL_USER_CTL(pll), ZONDA_PLL_OUT_MASK, ZONDA_PLL_OUT_MASK); 2091 2092 /* Enable the global PLL outputs */ 2093 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL); 2094 2095 return 0; 2096 } 2097 2098 static void clk_zonda_pll_disable(struct clk_hw *hw) 2099 { 2100 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2101 struct regmap *regmap = pll->clkr.regmap; 2102 u32 val; 2103 2104 regmap_read(regmap, PLL_MODE(pll), &val); 2105 2106 /* If in FSM mode, just unvote it */ 2107 if (val & PLL_VOTE_FSM_ENA) { 2108 clk_disable_regmap(hw); 2109 return; 2110 } 2111 2112 /* Disable the global PLL output */ 2113 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 2114 2115 /* Disable the PLL outputs */ 2116 regmap_update_bits(regmap, PLL_USER_CTL(pll), ZONDA_PLL_OUT_MASK, 0); 2117 2118 /* Put the PLL in bypass and reset */ 2119 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N | PLL_BYPASSNL, 0); 2120 2121 /* Place the PLL mode in OFF state */ 2122 regmap_write(regmap, PLL_OPMODE(pll), 0x0); 2123 } 2124 2125 static int clk_zonda_pll_set_rate(struct clk_hw *hw, unsigned long rate, 2126 unsigned long prate) 2127 { 2128 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2129 unsigned long rrate; 2130 u32 test_ctl_val; 2131 u32 l, alpha_width = pll_alpha_width(pll); 2132 u64 a; 2133 int ret; 2134 2135 rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width); 2136 2137 ret = alpha_pll_check_rate_margin(hw, rrate, rate); 2138 if (ret < 0) 2139 return ret; 2140 2141 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); 2142 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 2143 2144 /* Wait before polling for the frequency latch */ 2145 udelay(5); 2146 2147 /* Read stay in cfa mode */ 2148 regmap_read(pll->clkr.regmap, PLL_TEST_CTL(pll), &test_ctl_val); 2149 2150 /* If cfa mode then poll for freq lock */ 2151 if (test_ctl_val & ZONDA_STAY_IN_CFA) 2152 ret = wait_for_zonda_pll_freq_lock(pll); 2153 else 2154 ret = wait_for_pll_enable_lock(pll); 2155 if (ret) 2156 return ret; 2157 2158 /* Wait for PLL output to stabilize */ 2159 udelay(100); 2160 return 0; 2161 } 2162 2163 const struct clk_ops clk_alpha_pll_zonda_ops = { 2164 .enable = clk_zonda_pll_enable, 2165 .disable = clk_zonda_pll_disable, 2166 .is_enabled = clk_trion_pll_is_enabled, 2167 .recalc_rate = clk_trion_pll_recalc_rate, 2168 .round_rate = clk_alpha_pll_round_rate, 2169 .set_rate = clk_zonda_pll_set_rate, 2170 }; 2171 EXPORT_SYMBOL_GPL(clk_alpha_pll_zonda_ops); 2172 2173 void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 2174 const struct alpha_pll_config *config) 2175 { 2176 u32 lval = config->l; 2177 2178 lval |= TRION_PLL_CAL_VAL << LUCID_EVO_PLL_CAL_L_VAL_SHIFT; 2179 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), lval); 2180 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); 2181 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); 2182 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); 2183 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); 2184 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val); 2185 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val); 2186 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); 2187 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); 2188 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val); 2189 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U2(pll), config->test_ctl_hi2_val); 2190 2191 /* Disable PLL output */ 2192 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 2193 2194 /* Set operation mode to STANDBY and de-assert the reset */ 2195 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 2196 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 2197 } 2198 EXPORT_SYMBOL_GPL(clk_lucid_evo_pll_configure); 2199 2200 static int alpha_pll_lucid_evo_enable(struct clk_hw *hw) 2201 { 2202 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2203 struct regmap *regmap = pll->clkr.regmap; 2204 u32 val; 2205 int ret; 2206 2207 ret = regmap_read(regmap, PLL_USER_CTL(pll), &val); 2208 if (ret) 2209 return ret; 2210 2211 /* If in FSM mode, just vote for it */ 2212 if (val & LUCID_EVO_ENABLE_VOTE_RUN) { 2213 ret = clk_enable_regmap(hw); 2214 if (ret) 2215 return ret; 2216 return wait_for_pll_enable_lock(pll); 2217 } 2218 2219 /* Check if PLL is already enabled */ 2220 ret = trion_pll_is_enabled(pll, regmap); 2221 if (ret < 0) { 2222 return ret; 2223 } else if (ret) { 2224 pr_warn("%s PLL is already enabled\n", clk_hw_get_name(&pll->clkr.hw)); 2225 return 0; 2226 } 2227 2228 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 2229 if (ret) 2230 return ret; 2231 2232 /* Set operation mode to RUN */ 2233 regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); 2234 2235 ret = wait_for_pll_enable_lock(pll); 2236 if (ret) 2237 return ret; 2238 2239 /* Enable the PLL outputs */ 2240 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, PLL_OUT_MASK); 2241 if (ret) 2242 return ret; 2243 2244 /* Enable the global PLL outputs */ 2245 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL); 2246 if (ret) 2247 return ret; 2248 2249 /* Ensure that the write above goes through before returning. */ 2250 mb(); 2251 return ret; 2252 } 2253 2254 static void _alpha_pll_lucid_evo_disable(struct clk_hw *hw, bool reset) 2255 { 2256 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2257 struct regmap *regmap = pll->clkr.regmap; 2258 u32 val; 2259 int ret; 2260 2261 ret = regmap_read(regmap, PLL_USER_CTL(pll), &val); 2262 if (ret) 2263 return; 2264 2265 /* If in FSM mode, just unvote it */ 2266 if (val & LUCID_EVO_ENABLE_VOTE_RUN) { 2267 clk_disable_regmap(hw); 2268 return; 2269 } 2270 2271 /* Disable the global PLL output */ 2272 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 2273 if (ret) 2274 return; 2275 2276 /* Disable the PLL outputs */ 2277 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0); 2278 if (ret) 2279 return; 2280 2281 /* Place the PLL mode in STANDBY */ 2282 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 2283 2284 if (reset) 2285 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, 0); 2286 } 2287 2288 static int _alpha_pll_lucid_evo_prepare(struct clk_hw *hw, bool reset) 2289 { 2290 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2291 struct clk_hw *p; 2292 u32 val = 0; 2293 int ret; 2294 2295 /* Return early if calibration is not needed. */ 2296 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 2297 if (!(val & LUCID_EVO_PCAL_NOT_DONE)) 2298 return 0; 2299 2300 p = clk_hw_get_parent(hw); 2301 if (!p) 2302 return -EINVAL; 2303 2304 ret = alpha_pll_lucid_evo_enable(hw); 2305 if (ret) 2306 return ret; 2307 2308 _alpha_pll_lucid_evo_disable(hw, reset); 2309 2310 return 0; 2311 } 2312 2313 static void alpha_pll_lucid_evo_disable(struct clk_hw *hw) 2314 { 2315 _alpha_pll_lucid_evo_disable(hw, false); 2316 } 2317 2318 static int alpha_pll_lucid_evo_prepare(struct clk_hw *hw) 2319 { 2320 return _alpha_pll_lucid_evo_prepare(hw, false); 2321 } 2322 2323 static void alpha_pll_reset_lucid_evo_disable(struct clk_hw *hw) 2324 { 2325 _alpha_pll_lucid_evo_disable(hw, true); 2326 } 2327 2328 static int alpha_pll_reset_lucid_evo_prepare(struct clk_hw *hw) 2329 { 2330 return _alpha_pll_lucid_evo_prepare(hw, true); 2331 } 2332 2333 static unsigned long alpha_pll_lucid_evo_recalc_rate(struct clk_hw *hw, 2334 unsigned long parent_rate) 2335 { 2336 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2337 struct regmap *regmap = pll->clkr.regmap; 2338 u32 l, frac; 2339 2340 regmap_read(regmap, PLL_L_VAL(pll), &l); 2341 l &= LUCID_EVO_PLL_L_VAL_MASK; 2342 regmap_read(regmap, PLL_ALPHA_VAL(pll), &frac); 2343 2344 return alpha_pll_calc_rate(parent_rate, l, frac, pll_alpha_width(pll)); 2345 } 2346 2347 static int clk_lucid_evo_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, 2348 unsigned long parent_rate) 2349 { 2350 return __clk_lucid_pll_postdiv_set_rate(hw, rate, parent_rate, LUCID_EVO_ENABLE_VOTE_RUN); 2351 } 2352 2353 const struct clk_ops clk_alpha_pll_fixed_lucid_evo_ops = { 2354 .enable = alpha_pll_lucid_evo_enable, 2355 .disable = alpha_pll_lucid_evo_disable, 2356 .is_enabled = clk_trion_pll_is_enabled, 2357 .recalc_rate = alpha_pll_lucid_evo_recalc_rate, 2358 .round_rate = clk_alpha_pll_round_rate, 2359 }; 2360 EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_lucid_evo_ops); 2361 2362 const struct clk_ops clk_alpha_pll_postdiv_lucid_evo_ops = { 2363 .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate, 2364 .round_rate = clk_alpha_pll_postdiv_fabia_round_rate, 2365 .set_rate = clk_lucid_evo_pll_postdiv_set_rate, 2366 }; 2367 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_evo_ops); 2368 2369 const struct clk_ops clk_alpha_pll_lucid_evo_ops = { 2370 .prepare = alpha_pll_lucid_evo_prepare, 2371 .enable = alpha_pll_lucid_evo_enable, 2372 .disable = alpha_pll_lucid_evo_disable, 2373 .is_enabled = clk_trion_pll_is_enabled, 2374 .recalc_rate = alpha_pll_lucid_evo_recalc_rate, 2375 .round_rate = clk_alpha_pll_round_rate, 2376 .set_rate = alpha_pll_lucid_5lpe_set_rate, 2377 }; 2378 EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_evo_ops); 2379 2380 const struct clk_ops clk_alpha_pll_reset_lucid_evo_ops = { 2381 .prepare = alpha_pll_reset_lucid_evo_prepare, 2382 .enable = alpha_pll_lucid_evo_enable, 2383 .disable = alpha_pll_reset_lucid_evo_disable, 2384 .is_enabled = clk_trion_pll_is_enabled, 2385 .recalc_rate = alpha_pll_lucid_evo_recalc_rate, 2386 .round_rate = clk_alpha_pll_round_rate, 2387 .set_rate = alpha_pll_lucid_5lpe_set_rate, 2388 }; 2389 EXPORT_SYMBOL_GPL(clk_alpha_pll_reset_lucid_evo_ops); 2390 2391 void clk_rivian_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 2392 const struct alpha_pll_config *config) 2393 { 2394 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); 2395 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); 2396 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); 2397 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); 2398 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); 2399 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); 2400 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val); 2401 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val); 2402 2403 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 2404 2405 regmap_update_bits(regmap, PLL_MODE(pll), 2406 PLL_RESET_N | PLL_BYPASSNL | PLL_OUTCTRL, 2407 PLL_RESET_N | PLL_BYPASSNL); 2408 } 2409 EXPORT_SYMBOL_GPL(clk_rivian_evo_pll_configure); 2410 2411 static unsigned long clk_rivian_evo_pll_recalc_rate(struct clk_hw *hw, 2412 unsigned long parent_rate) 2413 { 2414 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2415 u32 l; 2416 2417 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); 2418 2419 return parent_rate * l; 2420 } 2421 2422 static long clk_rivian_evo_pll_round_rate(struct clk_hw *hw, unsigned long rate, 2423 unsigned long *prate) 2424 { 2425 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2426 unsigned long min_freq, max_freq; 2427 u32 l; 2428 u64 a; 2429 2430 rate = alpha_pll_round_rate(rate, *prate, &l, &a, 0); 2431 if (!pll->vco_table || alpha_pll_find_vco(pll, rate)) 2432 return rate; 2433 2434 min_freq = pll->vco_table[0].min_freq; 2435 max_freq = pll->vco_table[pll->num_vco - 1].max_freq; 2436 2437 return clamp(rate, min_freq, max_freq); 2438 } 2439 2440 const struct clk_ops clk_alpha_pll_rivian_evo_ops = { 2441 .enable = alpha_pll_lucid_5lpe_enable, 2442 .disable = alpha_pll_lucid_5lpe_disable, 2443 .is_enabled = clk_trion_pll_is_enabled, 2444 .recalc_rate = clk_rivian_evo_pll_recalc_rate, 2445 .round_rate = clk_rivian_evo_pll_round_rate, 2446 }; 2447 EXPORT_SYMBOL_GPL(clk_alpha_pll_rivian_evo_ops); 2448 2449 void clk_stromer_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 2450 const struct alpha_pll_config *config) 2451 { 2452 u32 val, val_u, mask, mask_u; 2453 2454 regmap_write(regmap, PLL_L_VAL(pll), config->l); 2455 regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha); 2456 regmap_write(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); 2457 2458 if (pll_has_64bit_config(pll)) 2459 regmap_write(regmap, PLL_CONFIG_CTL_U(pll), 2460 config->config_ctl_hi_val); 2461 2462 if (pll_alpha_width(pll) > 32) 2463 regmap_write(regmap, PLL_ALPHA_VAL_U(pll), config->alpha_hi); 2464 2465 val = config->main_output_mask; 2466 val |= config->aux_output_mask; 2467 val |= config->aux2_output_mask; 2468 val |= config->early_output_mask; 2469 val |= config->pre_div_val; 2470 val |= config->post_div_val; 2471 val |= config->vco_val; 2472 val |= config->alpha_en_mask; 2473 val |= config->alpha_mode_mask; 2474 2475 mask = config->main_output_mask; 2476 mask |= config->aux_output_mask; 2477 mask |= config->aux2_output_mask; 2478 mask |= config->early_output_mask; 2479 mask |= config->pre_div_mask; 2480 mask |= config->post_div_mask; 2481 mask |= config->vco_mask; 2482 mask |= config->alpha_en_mask; 2483 mask |= config->alpha_mode_mask; 2484 2485 regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val); 2486 2487 /* Stromer APSS PLL does not enable LOCK_DET by default, so enable it */ 2488 val_u = config->status_val << ALPHA_PLL_STATUS_REG_SHIFT; 2489 val_u |= config->lock_det; 2490 2491 mask_u = config->status_mask; 2492 mask_u |= config->lock_det; 2493 2494 regmap_update_bits(regmap, PLL_USER_CTL_U(pll), mask_u, val_u); 2495 regmap_write(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); 2496 regmap_write(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); 2497 2498 if (pll->flags & SUPPORTS_FSM_MODE) 2499 qcom_pll_set_fsm_mode(regmap, PLL_MODE(pll), 6, 0); 2500 } 2501 EXPORT_SYMBOL_GPL(clk_stromer_pll_configure); 2502 2503 static int clk_alpha_pll_stromer_determine_rate(struct clk_hw *hw, 2504 struct clk_rate_request *req) 2505 { 2506 u32 l; 2507 u64 a; 2508 2509 req->rate = alpha_pll_round_rate(req->rate, req->best_parent_rate, 2510 &l, &a, ALPHA_REG_BITWIDTH); 2511 2512 return 0; 2513 } 2514 2515 static int clk_alpha_pll_stromer_set_rate(struct clk_hw *hw, unsigned long rate, 2516 unsigned long prate) 2517 { 2518 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2519 int ret; 2520 u32 l; 2521 u64 a; 2522 2523 rate = alpha_pll_round_rate(rate, prate, &l, &a, ALPHA_REG_BITWIDTH); 2524 2525 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 2526 2527 a <<= ALPHA_REG_BITWIDTH - ALPHA_BITWIDTH; 2528 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); 2529 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), 2530 a >> ALPHA_BITWIDTH); 2531 2532 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 2533 PLL_ALPHA_EN, PLL_ALPHA_EN); 2534 2535 if (!clk_hw_is_enabled(hw)) 2536 return 0; 2537 2538 /* 2539 * Stromer PLL supports Dynamic programming. 2540 * It allows the PLL frequency to be changed on-the-fly without first 2541 * execution of a shutdown procedure followed by a bring up procedure. 2542 */ 2543 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE, 2544 PLL_UPDATE); 2545 2546 ret = wait_for_pll_update(pll); 2547 if (ret) 2548 return ret; 2549 2550 return wait_for_pll_enable_lock(pll); 2551 } 2552 2553 const struct clk_ops clk_alpha_pll_stromer_ops = { 2554 .enable = clk_alpha_pll_enable, 2555 .disable = clk_alpha_pll_disable, 2556 .is_enabled = clk_alpha_pll_is_enabled, 2557 .recalc_rate = clk_alpha_pll_recalc_rate, 2558 .determine_rate = clk_alpha_pll_stromer_determine_rate, 2559 .set_rate = clk_alpha_pll_stromer_set_rate, 2560 }; 2561 EXPORT_SYMBOL_GPL(clk_alpha_pll_stromer_ops); 2562 2563 static int clk_alpha_pll_stromer_plus_set_rate(struct clk_hw *hw, 2564 unsigned long rate, 2565 unsigned long prate) 2566 { 2567 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2568 u32 l, alpha_width = pll_alpha_width(pll); 2569 int ret, pll_mode; 2570 u64 a; 2571 2572 rate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width); 2573 2574 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &pll_mode); 2575 if (ret) 2576 return ret; 2577 2578 regmap_write(pll->clkr.regmap, PLL_MODE(pll), 0); 2579 2580 /* Delay of 2 output clock ticks required until output is disabled */ 2581 udelay(1); 2582 2583 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 2584 2585 if (alpha_width > ALPHA_BITWIDTH) 2586 a <<= alpha_width - ALPHA_BITWIDTH; 2587 2588 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); 2589 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), 2590 a >> ALPHA_BITWIDTH); 2591 2592 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 2593 PLL_ALPHA_EN, PLL_ALPHA_EN); 2594 2595 regmap_write(pll->clkr.regmap, PLL_MODE(pll), PLL_BYPASSNL); 2596 2597 /* Wait five micro seconds or more */ 2598 udelay(5); 2599 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_RESET_N, 2600 PLL_RESET_N); 2601 2602 /* The lock time should be less than 50 micro seconds worst case */ 2603 usleep_range(50, 60); 2604 2605 ret = wait_for_pll_enable_lock(pll); 2606 if (ret) { 2607 pr_err("Wait for PLL enable lock failed [%s] %d\n", 2608 clk_hw_get_name(hw), ret); 2609 return ret; 2610 } 2611 2612 if (pll_mode & PLL_OUTCTRL) 2613 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL, 2614 PLL_OUTCTRL); 2615 2616 return 0; 2617 } 2618 2619 const struct clk_ops clk_alpha_pll_stromer_plus_ops = { 2620 .prepare = clk_alpha_pll_enable, 2621 .unprepare = clk_alpha_pll_disable, 2622 .is_enabled = clk_alpha_pll_is_enabled, 2623 .recalc_rate = clk_alpha_pll_recalc_rate, 2624 .determine_rate = clk_alpha_pll_stromer_determine_rate, 2625 .set_rate = clk_alpha_pll_stromer_plus_set_rate, 2626 }; 2627 EXPORT_SYMBOL_GPL(clk_alpha_pll_stromer_plus_ops); 2628