1*a5e3f372SJacky Huang /* SPDX-License-Identifier: GPL-2.0-only */ 2*a5e3f372SJacky Huang /* 3*a5e3f372SJacky Huang * Copyright (C) 2023 Nuvoton Technology Corp. 4*a5e3f372SJacky Huang * Author: Chi-Fang Li <cfli0@nuvoton.com> 5*a5e3f372SJacky Huang */ 6*a5e3f372SJacky Huang 7*a5e3f372SJacky Huang #ifndef __DRV_CLK_NUVOTON_MA35D1_H 8*a5e3f372SJacky Huang #define __DRV_CLK_NUVOTON_MA35D1_H 9*a5e3f372SJacky Huang 10*a5e3f372SJacky Huang struct clk_hw *ma35d1_reg_clk_pll(struct device *dev, u32 id, u8 u8mode, const char *name, 11*a5e3f372SJacky Huang struct clk_hw *parent_hw, void __iomem *base); 12*a5e3f372SJacky Huang 13*a5e3f372SJacky Huang struct clk_hw *ma35d1_reg_adc_clkdiv(struct device *dev, const char *name, 14*a5e3f372SJacky Huang struct clk_hw *parent_hw, spinlock_t *lock, 15*a5e3f372SJacky Huang unsigned long flags, void __iomem *reg, 16*a5e3f372SJacky Huang u8 shift, u8 width, u32 mask_bit); 17*a5e3f372SJacky Huang 18*a5e3f372SJacky Huang #endif /* __DRV_CLK_NUVOTON_MA35D1_H */ 19