1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2020 MediaTek Inc. 4 * Copyright (c) 2020 BayLibre, SAS 5 * Author: James Liao <jamesjj.liao@mediatek.com> 6 * Fabien Parent <fparent@baylibre.com> 7 */ 8 9 #include <linux/clk-provider.h> 10 #include <linux/of.h> 11 #include <linux/of_address.h> 12 #include <linux/of_device.h> 13 #include <linux/platform_device.h> 14 15 #include "clk-mtk.h" 16 #include "clk-gate.h" 17 18 #include <dt-bindings/clock/mt8167-clk.h> 19 20 static const struct mtk_gate_regs vdec0_cg_regs = { 21 .set_ofs = 0x0, 22 .clr_ofs = 0x4, 23 .sta_ofs = 0x0, 24 }; 25 26 static const struct mtk_gate_regs vdec1_cg_regs = { 27 .set_ofs = 0x8, 28 .clr_ofs = 0xc, 29 .sta_ofs = 0x8, 30 }; 31 32 #define GATE_VDEC0_I(_id, _name, _parent, _shift) { \ 33 .id = _id, \ 34 .name = _name, \ 35 .parent_name = _parent, \ 36 .regs = &vdec0_cg_regs, \ 37 .shift = _shift, \ 38 .ops = &mtk_clk_gate_ops_setclr_inv, \ 39 } 40 41 #define GATE_VDEC1_I(_id, _name, _parent, _shift) { \ 42 .id = _id, \ 43 .name = _name, \ 44 .parent_name = _parent, \ 45 .regs = &vdec1_cg_regs, \ 46 .shift = _shift, \ 47 .ops = &mtk_clk_gate_ops_setclr_inv, \ 48 } 49 50 static const struct mtk_gate vdec_clks[] = { 51 /* VDEC0 */ 52 GATE_VDEC0_I(CLK_VDEC_CKEN, "vdec_cken", "rg_vdec", 0), 53 /* VDEC1 */ 54 GATE_VDEC1_I(CLK_VDEC_LARB1_CKEN, "vdec_larb1_cken", "smi_mm", 0), 55 }; 56 57 static const struct mtk_clk_desc vdec_desc = { 58 .clks = vdec_clks, 59 .num_clks = ARRAY_SIZE(vdec_clks), 60 }; 61 62 static const struct of_device_id of_match_clk_mt8167_vdec[] = { 63 { .compatible = "mediatek,mt8167-vdecsys", .data = &vdec_desc }, 64 { /* sentinel */ } 65 }; 66 67 static struct platform_driver clk_mt8167_vdec_drv = { 68 .probe = mtk_clk_simple_probe, 69 .remove = mtk_clk_simple_remove, 70 .driver = { 71 .name = "clk-mt8167-vdecsys", 72 .of_match_table = of_match_clk_mt8167_vdec, 73 }, 74 }; 75 module_platform_driver(clk_mt8167_vdec_drv); 76