1*e2f744a8Sweiyi.lu@mediatek.com /* 2*e2f744a8Sweiyi.lu@mediatek.com * Copyright (c) 2017 MediaTek Inc. 3*e2f744a8Sweiyi.lu@mediatek.com * Author: Weiyi Lu <weiyi.lu@mediatek.com> 4*e2f744a8Sweiyi.lu@mediatek.com * 5*e2f744a8Sweiyi.lu@mediatek.com * This program is free software; you can redistribute it and/or modify 6*e2f744a8Sweiyi.lu@mediatek.com * it under the terms of the GNU General Public License version 2 as 7*e2f744a8Sweiyi.lu@mediatek.com * published by the Free Software Foundation. 8*e2f744a8Sweiyi.lu@mediatek.com * 9*e2f744a8Sweiyi.lu@mediatek.com * This program is distributed in the hope that it will be useful, 10*e2f744a8Sweiyi.lu@mediatek.com * but WITHOUT ANY WARRANTY; without even the implied warranty of 11*e2f744a8Sweiyi.lu@mediatek.com * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12*e2f744a8Sweiyi.lu@mediatek.com * GNU General Public License for more details. 13*e2f744a8Sweiyi.lu@mediatek.com */ 14*e2f744a8Sweiyi.lu@mediatek.com 15*e2f744a8Sweiyi.lu@mediatek.com #include <linux/clk-provider.h> 16*e2f744a8Sweiyi.lu@mediatek.com #include <linux/platform_device.h> 17*e2f744a8Sweiyi.lu@mediatek.com 18*e2f744a8Sweiyi.lu@mediatek.com #include "clk-mtk.h" 19*e2f744a8Sweiyi.lu@mediatek.com #include "clk-gate.h" 20*e2f744a8Sweiyi.lu@mediatek.com 21*e2f744a8Sweiyi.lu@mediatek.com #include <dt-bindings/clock/mt2712-clk.h> 22*e2f744a8Sweiyi.lu@mediatek.com 23*e2f744a8Sweiyi.lu@mediatek.com static const struct mtk_gate_regs venc_cg_regs = { 24*e2f744a8Sweiyi.lu@mediatek.com .set_ofs = 0x4, 25*e2f744a8Sweiyi.lu@mediatek.com .clr_ofs = 0x8, 26*e2f744a8Sweiyi.lu@mediatek.com .sta_ofs = 0x0, 27*e2f744a8Sweiyi.lu@mediatek.com }; 28*e2f744a8Sweiyi.lu@mediatek.com 29*e2f744a8Sweiyi.lu@mediatek.com #define GATE_VENC(_id, _name, _parent, _shift) { \ 30*e2f744a8Sweiyi.lu@mediatek.com .id = _id, \ 31*e2f744a8Sweiyi.lu@mediatek.com .name = _name, \ 32*e2f744a8Sweiyi.lu@mediatek.com .parent_name = _parent, \ 33*e2f744a8Sweiyi.lu@mediatek.com .regs = &venc_cg_regs, \ 34*e2f744a8Sweiyi.lu@mediatek.com .shift = _shift, \ 35*e2f744a8Sweiyi.lu@mediatek.com .ops = &mtk_clk_gate_ops_setclr_inv, \ 36*e2f744a8Sweiyi.lu@mediatek.com } 37*e2f744a8Sweiyi.lu@mediatek.com 38*e2f744a8Sweiyi.lu@mediatek.com static const struct mtk_gate venc_clks[] = { 39*e2f744a8Sweiyi.lu@mediatek.com GATE_VENC(CLK_VENC_SMI_COMMON_CON, "venc_smi", "mm_sel", 0), 40*e2f744a8Sweiyi.lu@mediatek.com GATE_VENC(CLK_VENC_VENC, "venc_venc", "venc_sel", 4), 41*e2f744a8Sweiyi.lu@mediatek.com GATE_VENC(CLK_VENC_SMI_LARB6, "venc_smi_larb6", "jpgdec_sel", 12), 42*e2f744a8Sweiyi.lu@mediatek.com }; 43*e2f744a8Sweiyi.lu@mediatek.com 44*e2f744a8Sweiyi.lu@mediatek.com static int clk_mt2712_venc_probe(struct platform_device *pdev) 45*e2f744a8Sweiyi.lu@mediatek.com { 46*e2f744a8Sweiyi.lu@mediatek.com struct clk_onecell_data *clk_data; 47*e2f744a8Sweiyi.lu@mediatek.com int r; 48*e2f744a8Sweiyi.lu@mediatek.com struct device_node *node = pdev->dev.of_node; 49*e2f744a8Sweiyi.lu@mediatek.com 50*e2f744a8Sweiyi.lu@mediatek.com clk_data = mtk_alloc_clk_data(CLK_VENC_NR_CLK); 51*e2f744a8Sweiyi.lu@mediatek.com 52*e2f744a8Sweiyi.lu@mediatek.com mtk_clk_register_gates(node, venc_clks, ARRAY_SIZE(venc_clks), 53*e2f744a8Sweiyi.lu@mediatek.com clk_data); 54*e2f744a8Sweiyi.lu@mediatek.com 55*e2f744a8Sweiyi.lu@mediatek.com r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); 56*e2f744a8Sweiyi.lu@mediatek.com 57*e2f744a8Sweiyi.lu@mediatek.com if (r != 0) 58*e2f744a8Sweiyi.lu@mediatek.com pr_err("%s(): could not register clock provider: %d\n", 59*e2f744a8Sweiyi.lu@mediatek.com __func__, r); 60*e2f744a8Sweiyi.lu@mediatek.com 61*e2f744a8Sweiyi.lu@mediatek.com return r; 62*e2f744a8Sweiyi.lu@mediatek.com } 63*e2f744a8Sweiyi.lu@mediatek.com 64*e2f744a8Sweiyi.lu@mediatek.com static const struct of_device_id of_match_clk_mt2712_venc[] = { 65*e2f744a8Sweiyi.lu@mediatek.com { .compatible = "mediatek,mt2712-vencsys", }, 66*e2f744a8Sweiyi.lu@mediatek.com {} 67*e2f744a8Sweiyi.lu@mediatek.com }; 68*e2f744a8Sweiyi.lu@mediatek.com 69*e2f744a8Sweiyi.lu@mediatek.com static struct platform_driver clk_mt2712_venc_drv = { 70*e2f744a8Sweiyi.lu@mediatek.com .probe = clk_mt2712_venc_probe, 71*e2f744a8Sweiyi.lu@mediatek.com .driver = { 72*e2f744a8Sweiyi.lu@mediatek.com .name = "clk-mt2712-venc", 73*e2f744a8Sweiyi.lu@mediatek.com .of_match_table = of_match_clk_mt2712_venc, 74*e2f744a8Sweiyi.lu@mediatek.com }, 75*e2f744a8Sweiyi.lu@mediatek.com }; 76*e2f744a8Sweiyi.lu@mediatek.com 77*e2f744a8Sweiyi.lu@mediatek.com builtin_platform_driver(clk_mt2712_venc_drv); 78