1*036a4b4bSJacky Bai // SPDX-License-Identifier: GPL-2.0+ 2*036a4b4bSJacky Bai /* 3*036a4b4bSJacky Bai * Copyright 2019~2020 NXP 4*036a4b4bSJacky Bai */ 5*036a4b4bSJacky Bai 6*036a4b4bSJacky Bai #include <dt-bindings/firmware/imx/rsrc.h> 7*036a4b4bSJacky Bai 8*036a4b4bSJacky Bai #include "clk-scu.h" 9*036a4b4bSJacky Bai 10*036a4b4bSJacky Bai /* Keep sorted in the ascending order */ 11*036a4b4bSJacky Bai static u32 imx8dxl_clk_scu_rsrc_table[] = { 12*036a4b4bSJacky Bai IMX_SC_R_SPI_0, 13*036a4b4bSJacky Bai IMX_SC_R_SPI_1, 14*036a4b4bSJacky Bai IMX_SC_R_SPI_2, 15*036a4b4bSJacky Bai IMX_SC_R_SPI_3, 16*036a4b4bSJacky Bai IMX_SC_R_UART_0, 17*036a4b4bSJacky Bai IMX_SC_R_UART_1, 18*036a4b4bSJacky Bai IMX_SC_R_UART_2, 19*036a4b4bSJacky Bai IMX_SC_R_UART_3, 20*036a4b4bSJacky Bai IMX_SC_R_I2C_0, 21*036a4b4bSJacky Bai IMX_SC_R_I2C_1, 22*036a4b4bSJacky Bai IMX_SC_R_I2C_2, 23*036a4b4bSJacky Bai IMX_SC_R_I2C_3, 24*036a4b4bSJacky Bai IMX_SC_R_ADC_0, 25*036a4b4bSJacky Bai IMX_SC_R_FTM_0, 26*036a4b4bSJacky Bai IMX_SC_R_FTM_1, 27*036a4b4bSJacky Bai IMX_SC_R_CAN_0, 28*036a4b4bSJacky Bai IMX_SC_R_LCD_0, 29*036a4b4bSJacky Bai IMX_SC_R_LCD_0_PWM_0, 30*036a4b4bSJacky Bai IMX_SC_R_PWM_0, 31*036a4b4bSJacky Bai IMX_SC_R_PWM_1, 32*036a4b4bSJacky Bai IMX_SC_R_PWM_2, 33*036a4b4bSJacky Bai IMX_SC_R_PWM_3, 34*036a4b4bSJacky Bai IMX_SC_R_PWM_4, 35*036a4b4bSJacky Bai IMX_SC_R_PWM_5, 36*036a4b4bSJacky Bai IMX_SC_R_PWM_6, 37*036a4b4bSJacky Bai IMX_SC_R_PWM_7, 38*036a4b4bSJacky Bai IMX_SC_R_GPT_0, 39*036a4b4bSJacky Bai IMX_SC_R_GPT_1, 40*036a4b4bSJacky Bai IMX_SC_R_GPT_2, 41*036a4b4bSJacky Bai IMX_SC_R_GPT_3, 42*036a4b4bSJacky Bai IMX_SC_R_GPT_4, 43*036a4b4bSJacky Bai IMX_SC_R_FSPI_0, 44*036a4b4bSJacky Bai IMX_SC_R_FSPI_1, 45*036a4b4bSJacky Bai IMX_SC_R_SDHC_0, 46*036a4b4bSJacky Bai IMX_SC_R_SDHC_1, 47*036a4b4bSJacky Bai IMX_SC_R_SDHC_2, 48*036a4b4bSJacky Bai IMX_SC_R_ENET_0, 49*036a4b4bSJacky Bai IMX_SC_R_ENET_1, 50*036a4b4bSJacky Bai IMX_SC_R_MLB_0, 51*036a4b4bSJacky Bai IMX_SC_R_USB_1, 52*036a4b4bSJacky Bai IMX_SC_R_NAND, 53*036a4b4bSJacky Bai IMX_SC_R_M4_0_I2C, 54*036a4b4bSJacky Bai IMX_SC_R_M4_0_UART, 55*036a4b4bSJacky Bai IMX_SC_R_ELCDIF_PLL, 56*036a4b4bSJacky Bai IMX_SC_R_AUDIO_PLL_0, 57*036a4b4bSJacky Bai IMX_SC_R_AUDIO_PLL_1, 58*036a4b4bSJacky Bai IMX_SC_R_AUDIO_CLK_0, 59*036a4b4bSJacky Bai IMX_SC_R_AUDIO_CLK_1, 60*036a4b4bSJacky Bai IMX_SC_R_A35 61*036a4b4bSJacky Bai }; 62*036a4b4bSJacky Bai 63*036a4b4bSJacky Bai const struct imx_clk_scu_rsrc_table imx_clk_scu_rsrc_imx8dxl = { 64*036a4b4bSJacky Bai .rsrc = imx8dxl_clk_scu_rsrc_table, 65*036a4b4bSJacky Bai .num = ARRAY_SIZE(imx8dxl_clk_scu_rsrc_table), 66*036a4b4bSJacky Bai }; 67