1*11f68120SShawn Guo /* 2*11f68120SShawn Guo * Copyright (C) 2013 Freescale Semiconductor, Inc. 3*11f68120SShawn Guo * 4*11f68120SShawn Guo * The code contained herein is licensed under the GNU General Public 5*11f68120SShawn Guo * License. You may obtain a copy of the GNU General Public License 6*11f68120SShawn Guo * Version 2 or later at the following locations: 7*11f68120SShawn Guo * 8*11f68120SShawn Guo * http://www.opensource.org/licenses/gpl-license.html 9*11f68120SShawn Guo * http://www.gnu.org/copyleft/gpl.html 10*11f68120SShawn Guo */ 11*11f68120SShawn Guo 12*11f68120SShawn Guo #include <linux/clk-provider.h> 13*11f68120SShawn Guo #include <linux/err.h> 14*11f68120SShawn Guo #include <linux/io.h> 15*11f68120SShawn Guo #include <linux/slab.h> 16*11f68120SShawn Guo #include "clk.h" 17*11f68120SShawn Guo 18*11f68120SShawn Guo #define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw) 19*11f68120SShawn Guo 20*11f68120SShawn Guo /** 21*11f68120SShawn Guo * struct clk_fixup_mux - imx integer fixup multiplexer clock 22*11f68120SShawn Guo * @mux: the parent class 23*11f68120SShawn Guo * @ops: pointer to clk_ops of parent class 24*11f68120SShawn Guo * @fixup: a hook to fixup the write value 25*11f68120SShawn Guo * 26*11f68120SShawn Guo * The imx fixup multiplexer clock is a subclass of basic clk_mux 27*11f68120SShawn Guo * with an addtional fixup hook. 28*11f68120SShawn Guo */ 29*11f68120SShawn Guo struct clk_fixup_mux { 30*11f68120SShawn Guo struct clk_mux mux; 31*11f68120SShawn Guo const struct clk_ops *ops; 32*11f68120SShawn Guo void (*fixup)(u32 *val); 33*11f68120SShawn Guo }; 34*11f68120SShawn Guo 35*11f68120SShawn Guo static inline struct clk_fixup_mux *to_clk_fixup_mux(struct clk_hw *hw) 36*11f68120SShawn Guo { 37*11f68120SShawn Guo struct clk_mux *mux = to_clk_mux(hw); 38*11f68120SShawn Guo 39*11f68120SShawn Guo return container_of(mux, struct clk_fixup_mux, mux); 40*11f68120SShawn Guo } 41*11f68120SShawn Guo 42*11f68120SShawn Guo static u8 clk_fixup_mux_get_parent(struct clk_hw *hw) 43*11f68120SShawn Guo { 44*11f68120SShawn Guo struct clk_fixup_mux *fixup_mux = to_clk_fixup_mux(hw); 45*11f68120SShawn Guo 46*11f68120SShawn Guo return fixup_mux->ops->get_parent(&fixup_mux->mux.hw); 47*11f68120SShawn Guo } 48*11f68120SShawn Guo 49*11f68120SShawn Guo static int clk_fixup_mux_set_parent(struct clk_hw *hw, u8 index) 50*11f68120SShawn Guo { 51*11f68120SShawn Guo struct clk_fixup_mux *fixup_mux = to_clk_fixup_mux(hw); 52*11f68120SShawn Guo struct clk_mux *mux = to_clk_mux(hw); 53*11f68120SShawn Guo unsigned long flags = 0; 54*11f68120SShawn Guo u32 val; 55*11f68120SShawn Guo 56*11f68120SShawn Guo spin_lock_irqsave(mux->lock, flags); 57*11f68120SShawn Guo 58*11f68120SShawn Guo val = readl(mux->reg); 59*11f68120SShawn Guo val &= ~(mux->mask << mux->shift); 60*11f68120SShawn Guo val |= index << mux->shift; 61*11f68120SShawn Guo fixup_mux->fixup(&val); 62*11f68120SShawn Guo writel(val, mux->reg); 63*11f68120SShawn Guo 64*11f68120SShawn Guo spin_unlock_irqrestore(mux->lock, flags); 65*11f68120SShawn Guo 66*11f68120SShawn Guo return 0; 67*11f68120SShawn Guo } 68*11f68120SShawn Guo 69*11f68120SShawn Guo static const struct clk_ops clk_fixup_mux_ops = { 70*11f68120SShawn Guo .get_parent = clk_fixup_mux_get_parent, 71*11f68120SShawn Guo .set_parent = clk_fixup_mux_set_parent, 72*11f68120SShawn Guo }; 73*11f68120SShawn Guo 74*11f68120SShawn Guo struct clk *imx_clk_fixup_mux(const char *name, void __iomem *reg, 75*11f68120SShawn Guo u8 shift, u8 width, const char **parents, 76*11f68120SShawn Guo int num_parents, void (*fixup)(u32 *val)) 77*11f68120SShawn Guo { 78*11f68120SShawn Guo struct clk_fixup_mux *fixup_mux; 79*11f68120SShawn Guo struct clk *clk; 80*11f68120SShawn Guo struct clk_init_data init; 81*11f68120SShawn Guo 82*11f68120SShawn Guo if (!fixup) 83*11f68120SShawn Guo return ERR_PTR(-EINVAL); 84*11f68120SShawn Guo 85*11f68120SShawn Guo fixup_mux = kzalloc(sizeof(*fixup_mux), GFP_KERNEL); 86*11f68120SShawn Guo if (!fixup_mux) 87*11f68120SShawn Guo return ERR_PTR(-ENOMEM); 88*11f68120SShawn Guo 89*11f68120SShawn Guo init.name = name; 90*11f68120SShawn Guo init.ops = &clk_fixup_mux_ops; 91*11f68120SShawn Guo init.parent_names = parents; 92*11f68120SShawn Guo init.num_parents = num_parents; 93*11f68120SShawn Guo init.flags = 0; 94*11f68120SShawn Guo 95*11f68120SShawn Guo fixup_mux->mux.reg = reg; 96*11f68120SShawn Guo fixup_mux->mux.shift = shift; 97*11f68120SShawn Guo fixup_mux->mux.mask = BIT(width) - 1; 98*11f68120SShawn Guo fixup_mux->mux.lock = &imx_ccm_lock; 99*11f68120SShawn Guo fixup_mux->mux.hw.init = &init; 100*11f68120SShawn Guo fixup_mux->ops = &clk_mux_ops; 101*11f68120SShawn Guo fixup_mux->fixup = fixup; 102*11f68120SShawn Guo 103*11f68120SShawn Guo clk = clk_register(NULL, &fixup_mux->mux.hw); 104*11f68120SShawn Guo if (IS_ERR(clk)) 105*11f68120SShawn Guo kfree(fixup_mux); 106*11f68120SShawn Guo 107*11f68120SShawn Guo return clk; 108*11f68120SShawn Guo } 109