xref: /openbmc/linux/drivers/clk/imgtec/clk-boston.c (revision 46fda5b5067a391912cf73bf3d32c26b6a22ad09)
16b0fd6c1SPaul Burton /*
26b0fd6c1SPaul Burton  * Copyright (C) 2016-2017 Imagination Technologies
3fb615d61SPaul Burton  * Author: Paul Burton <paul.burton@mips.com>
46b0fd6c1SPaul Burton  *
56b0fd6c1SPaul Burton  * This program is free software; you can redistribute it and/or modify it
66b0fd6c1SPaul Burton  * under the terms of the GNU General Public License as published by the
76b0fd6c1SPaul Burton  * Free Software Foundation;  either version 2 of the  License, or (at your
86b0fd6c1SPaul Burton  * option) any later version.
96b0fd6c1SPaul Burton  */
106b0fd6c1SPaul Burton 
116b0fd6c1SPaul Burton #define pr_fmt(fmt) "clk-boston: " fmt
126b0fd6c1SPaul Burton 
136b0fd6c1SPaul Burton #include <linux/clk-provider.h>
146b0fd6c1SPaul Burton #include <linux/kernel.h>
156b0fd6c1SPaul Burton #include <linux/of.h>
166b0fd6c1SPaul Burton #include <linux/regmap.h>
176b0fd6c1SPaul Burton #include <linux/slab.h>
186b0fd6c1SPaul Burton #include <linux/mfd/syscon.h>
196b0fd6c1SPaul Burton 
206b0fd6c1SPaul Burton #include <dt-bindings/clock/boston-clock.h>
216b0fd6c1SPaul Burton 
226b0fd6c1SPaul Burton #define BOSTON_PLAT_MMCMDIV		0x30
236b0fd6c1SPaul Burton # define BOSTON_PLAT_MMCMDIV_CLK0DIV	(0xff << 0)
246b0fd6c1SPaul Burton # define BOSTON_PLAT_MMCMDIV_INPUT	(0xff << 8)
256b0fd6c1SPaul Burton # define BOSTON_PLAT_MMCMDIV_MUL	(0xff << 16)
266b0fd6c1SPaul Burton # define BOSTON_PLAT_MMCMDIV_CLK1DIV	(0xff << 24)
276b0fd6c1SPaul Burton 
286b0fd6c1SPaul Burton #define BOSTON_CLK_COUNT 3
296b0fd6c1SPaul Burton 
306b0fd6c1SPaul Burton static u32 ext_field(u32 val, u32 mask)
316b0fd6c1SPaul Burton {
326b0fd6c1SPaul Burton 	return (val & mask) >> (ffs(mask) - 1);
336b0fd6c1SPaul Burton }
346b0fd6c1SPaul Burton 
356b0fd6c1SPaul Burton static void __init clk_boston_setup(struct device_node *np)
366b0fd6c1SPaul Burton {
376b0fd6c1SPaul Burton 	unsigned long in_freq, cpu_freq, sys_freq;
386b0fd6c1SPaul Burton 	uint mmcmdiv, mul, cpu_div, sys_div;
396b0fd6c1SPaul Burton 	struct clk_hw_onecell_data *onecell;
406b0fd6c1SPaul Burton 	struct regmap *regmap;
416b0fd6c1SPaul Burton 	struct clk_hw *hw;
426b0fd6c1SPaul Burton 	int err;
436b0fd6c1SPaul Burton 
446b0fd6c1SPaul Burton 	regmap = syscon_node_to_regmap(np->parent);
456b0fd6c1SPaul Burton 	if (IS_ERR(regmap)) {
466b0fd6c1SPaul Burton 		pr_err("failed to find regmap\n");
476b0fd6c1SPaul Burton 		return;
486b0fd6c1SPaul Burton 	}
496b0fd6c1SPaul Burton 
506b0fd6c1SPaul Burton 	err = regmap_read(regmap, BOSTON_PLAT_MMCMDIV, &mmcmdiv);
516b0fd6c1SPaul Burton 	if (err) {
526b0fd6c1SPaul Burton 		pr_err("failed to read mmcm_div register: %d\n", err);
536b0fd6c1SPaul Burton 		return;
546b0fd6c1SPaul Burton 	}
556b0fd6c1SPaul Burton 
566b0fd6c1SPaul Burton 	in_freq = ext_field(mmcmdiv, BOSTON_PLAT_MMCMDIV_INPUT) * 1000000;
576b0fd6c1SPaul Burton 	mul = ext_field(mmcmdiv, BOSTON_PLAT_MMCMDIV_MUL);
586b0fd6c1SPaul Burton 
596b0fd6c1SPaul Burton 	sys_div = ext_field(mmcmdiv, BOSTON_PLAT_MMCMDIV_CLK0DIV);
606b0fd6c1SPaul Burton 	sys_freq = mult_frac(in_freq, mul, sys_div);
616b0fd6c1SPaul Burton 
626b0fd6c1SPaul Burton 	cpu_div = ext_field(mmcmdiv, BOSTON_PLAT_MMCMDIV_CLK1DIV);
636b0fd6c1SPaul Burton 	cpu_freq = mult_frac(in_freq, mul, cpu_div);
646b0fd6c1SPaul Burton 
656b0fd6c1SPaul Burton 	onecell = kzalloc(sizeof(*onecell) +
666b0fd6c1SPaul Burton 			  (BOSTON_CLK_COUNT * sizeof(struct clk_hw *)),
676b0fd6c1SPaul Burton 			  GFP_KERNEL);
686b0fd6c1SPaul Burton 	if (!onecell)
696b0fd6c1SPaul Burton 		return;
706b0fd6c1SPaul Burton 
716b0fd6c1SPaul Burton 	onecell->num = BOSTON_CLK_COUNT;
726b0fd6c1SPaul Burton 
736b0fd6c1SPaul Burton 	hw = clk_hw_register_fixed_rate(NULL, "input", NULL, 0, in_freq);
746b0fd6c1SPaul Burton 	if (IS_ERR(hw)) {
756b0fd6c1SPaul Burton 		pr_err("failed to register input clock: %ld\n", PTR_ERR(hw));
76*46fda5b5SYi Wang 		goto error;
776b0fd6c1SPaul Burton 	}
786b0fd6c1SPaul Burton 	onecell->hws[BOSTON_CLK_INPUT] = hw;
796b0fd6c1SPaul Burton 
806b0fd6c1SPaul Burton 	hw = clk_hw_register_fixed_rate(NULL, "sys", "input", 0, sys_freq);
816b0fd6c1SPaul Burton 	if (IS_ERR(hw)) {
826b0fd6c1SPaul Burton 		pr_err("failed to register sys clock: %ld\n", PTR_ERR(hw));
83*46fda5b5SYi Wang 		goto error;
846b0fd6c1SPaul Burton 	}
856b0fd6c1SPaul Burton 	onecell->hws[BOSTON_CLK_SYS] = hw;
866b0fd6c1SPaul Burton 
876b0fd6c1SPaul Burton 	hw = clk_hw_register_fixed_rate(NULL, "cpu", "input", 0, cpu_freq);
886b0fd6c1SPaul Burton 	if (IS_ERR(hw)) {
896b0fd6c1SPaul Burton 		pr_err("failed to register cpu clock: %ld\n", PTR_ERR(hw));
90*46fda5b5SYi Wang 		goto error;
916b0fd6c1SPaul Burton 	}
926b0fd6c1SPaul Burton 	onecell->hws[BOSTON_CLK_CPU] = hw;
936b0fd6c1SPaul Burton 
946b0fd6c1SPaul Burton 	err = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, onecell);
956b0fd6c1SPaul Burton 	if (err)
966b0fd6c1SPaul Burton 		pr_err("failed to add DT provider: %d\n", err);
97*46fda5b5SYi Wang 
98*46fda5b5SYi Wang 	return;
99*46fda5b5SYi Wang 
100*46fda5b5SYi Wang error:
101*46fda5b5SYi Wang 	kfree(onecell);
1026b0fd6c1SPaul Burton }
1036b0fd6c1SPaul Burton 
1046b0fd6c1SPaul Burton /*
1056b0fd6c1SPaul Burton  * Use CLK_OF_DECLARE so that this driver is probed early enough to provide the
1066b0fd6c1SPaul Burton  * CPU frequency for use with the GIC or cop0 counters/timers.
1076b0fd6c1SPaul Burton  */
1086b0fd6c1SPaul Burton CLK_OF_DECLARE(clk_boston, "img,boston-clock", clk_boston_setup);
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