1*c942fddfSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */ 2707d33cbSJiancheng Xue /* 3707d33cbSJiancheng Xue * HiSilicon Clock and Reset Driver Header 4707d33cbSJiancheng Xue * 5707d33cbSJiancheng Xue * Copyright (c) 2016 HiSilicon Limited. 6707d33cbSJiancheng Xue */ 7707d33cbSJiancheng Xue 8707d33cbSJiancheng Xue #ifndef __HISI_CRG_H 9707d33cbSJiancheng Xue #define __HISI_CRG_H 10707d33cbSJiancheng Xue 11707d33cbSJiancheng Xue struct hisi_clock_data; 12707d33cbSJiancheng Xue struct hisi_reset_controller; 13707d33cbSJiancheng Xue 14707d33cbSJiancheng Xue struct hisi_crg_funcs { 15707d33cbSJiancheng Xue struct hisi_clock_data* (*register_clks)(struct platform_device *pdev); 16707d33cbSJiancheng Xue void (*unregister_clks)(struct platform_device *pdev); 17707d33cbSJiancheng Xue }; 18707d33cbSJiancheng Xue 19707d33cbSJiancheng Xue struct hisi_crg_dev { 20707d33cbSJiancheng Xue struct hisi_clock_data *clk_data; 21707d33cbSJiancheng Xue struct hisi_reset_controller *rstc; 22707d33cbSJiancheng Xue const struct hisi_crg_funcs *funcs; 23707d33cbSJiancheng Xue }; 24707d33cbSJiancheng Xue 25707d33cbSJiancheng Xue #endif /* __HISI_CRG_H */ 26