10aa0c95fSHaojian Zhuang /* 20aa0c95fSHaojian Zhuang * Hisilicon clock driver 30aa0c95fSHaojian Zhuang * 40aa0c95fSHaojian Zhuang * Copyright (c) 2012-2013 Hisilicon Limited. 50aa0c95fSHaojian Zhuang * Copyright (c) 2012-2013 Linaro Limited. 60aa0c95fSHaojian Zhuang * 70aa0c95fSHaojian Zhuang * Author: Haojian Zhuang <haojian.zhuang@linaro.org> 80aa0c95fSHaojian Zhuang * Xin Li <li.xin@linaro.org> 90aa0c95fSHaojian Zhuang * 100aa0c95fSHaojian Zhuang * This program is free software; you can redistribute it and/or modify 110aa0c95fSHaojian Zhuang * it under the terms of the GNU General Public License as published by 120aa0c95fSHaojian Zhuang * the Free Software Foundation; either version 2 of the License, or 130aa0c95fSHaojian Zhuang * (at your option) any later version. 140aa0c95fSHaojian Zhuang * 150aa0c95fSHaojian Zhuang * This program is distributed in the hope that it will be useful, 160aa0c95fSHaojian Zhuang * but WITHOUT ANY WARRANTY; without even the implied warranty of 170aa0c95fSHaojian Zhuang * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 180aa0c95fSHaojian Zhuang * GNU General Public License for more details. 190aa0c95fSHaojian Zhuang * 200aa0c95fSHaojian Zhuang * You should have received a copy of the GNU General Public License along 210aa0c95fSHaojian Zhuang * with this program; if not, write to the Free Software Foundation, Inc., 220aa0c95fSHaojian Zhuang * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 230aa0c95fSHaojian Zhuang * 240aa0c95fSHaojian Zhuang */ 250aa0c95fSHaojian Zhuang 260aa0c95fSHaojian Zhuang #include <linux/kernel.h> 270aa0c95fSHaojian Zhuang #include <linux/clk-provider.h> 280aa0c95fSHaojian Zhuang #include <linux/clkdev.h> 290aa0c95fSHaojian Zhuang #include <linux/delay.h> 300aa0c95fSHaojian Zhuang #include <linux/io.h> 310aa0c95fSHaojian Zhuang #include <linux/of.h> 320aa0c95fSHaojian Zhuang #include <linux/of_address.h> 330aa0c95fSHaojian Zhuang #include <linux/of_device.h> 340aa0c95fSHaojian Zhuang #include <linux/slab.h> 350aa0c95fSHaojian Zhuang #include <linux/clk.h> 360aa0c95fSHaojian Zhuang 370aa0c95fSHaojian Zhuang #include "clk.h" 380aa0c95fSHaojian Zhuang 390aa0c95fSHaojian Zhuang static DEFINE_SPINLOCK(hisi_clk_lock); 400aa0c95fSHaojian Zhuang 4175af25f5SHaojian Zhuang struct hisi_clock_data __init *hisi_clk_init(struct device_node *np, 4275af25f5SHaojian Zhuang int nr_clks) 430aa0c95fSHaojian Zhuang { 4475af25f5SHaojian Zhuang struct hisi_clock_data *clk_data; 4575af25f5SHaojian Zhuang struct clk **clk_table; 4675af25f5SHaojian Zhuang void __iomem *base; 4775af25f5SHaojian Zhuang 4875af25f5SHaojian Zhuang if (np) { 4975af25f5SHaojian Zhuang base = of_iomap(np, 0); 5075af25f5SHaojian Zhuang if (!base) { 5175af25f5SHaojian Zhuang pr_err("failed to map Hisilicon clock registers\n"); 5275af25f5SHaojian Zhuang goto err; 5375af25f5SHaojian Zhuang } 5475af25f5SHaojian Zhuang } else { 5575af25f5SHaojian Zhuang pr_err("failed to find Hisilicon clock node in DTS\n"); 5675af25f5SHaojian Zhuang goto err; 5775af25f5SHaojian Zhuang } 5875af25f5SHaojian Zhuang 5975af25f5SHaojian Zhuang clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL); 6075af25f5SHaojian Zhuang if (!clk_data) { 6175af25f5SHaojian Zhuang pr_err("%s: could not allocate clock data\n", __func__); 6275af25f5SHaojian Zhuang goto err; 6375af25f5SHaojian Zhuang } 6475af25f5SHaojian Zhuang clk_data->base = base; 6575af25f5SHaojian Zhuang 660aa0c95fSHaojian Zhuang clk_table = kzalloc(sizeof(struct clk *) * nr_clks, GFP_KERNEL); 670aa0c95fSHaojian Zhuang if (!clk_table) { 680aa0c95fSHaojian Zhuang pr_err("%s: could not allocate clock lookup table\n", __func__); 6975af25f5SHaojian Zhuang goto err_data; 700aa0c95fSHaojian Zhuang } 7175af25f5SHaojian Zhuang clk_data->clk_data.clks = clk_table; 7275af25f5SHaojian Zhuang clk_data->clk_data.clk_num = nr_clks; 7375af25f5SHaojian Zhuang of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data->clk_data); 7475af25f5SHaojian Zhuang return clk_data; 7575af25f5SHaojian Zhuang err_data: 7675af25f5SHaojian Zhuang kfree(clk_data); 7775af25f5SHaojian Zhuang err: 7875af25f5SHaojian Zhuang return NULL; 790aa0c95fSHaojian Zhuang } 800aa0c95fSHaojian Zhuang 810aa0c95fSHaojian Zhuang void __init hisi_clk_register_fixed_rate(struct hisi_fixed_rate_clock *clks, 8275af25f5SHaojian Zhuang int nums, struct hisi_clock_data *data) 830aa0c95fSHaojian Zhuang { 840aa0c95fSHaojian Zhuang struct clk *clk; 850aa0c95fSHaojian Zhuang int i; 860aa0c95fSHaojian Zhuang 870aa0c95fSHaojian Zhuang for (i = 0; i < nums; i++) { 880aa0c95fSHaojian Zhuang clk = clk_register_fixed_rate(NULL, clks[i].name, 890aa0c95fSHaojian Zhuang clks[i].parent_name, 900aa0c95fSHaojian Zhuang clks[i].flags, 910aa0c95fSHaojian Zhuang clks[i].fixed_rate); 920aa0c95fSHaojian Zhuang if (IS_ERR(clk)) { 930aa0c95fSHaojian Zhuang pr_err("%s: failed to register clock %s\n", 940aa0c95fSHaojian Zhuang __func__, clks[i].name); 950aa0c95fSHaojian Zhuang continue; 960aa0c95fSHaojian Zhuang } 9775af25f5SHaojian Zhuang data->clk_data.clks[clks[i].id] = clk; 980aa0c95fSHaojian Zhuang } 990aa0c95fSHaojian Zhuang } 1000aa0c95fSHaojian Zhuang 1010aa0c95fSHaojian Zhuang void __init hisi_clk_register_fixed_factor(struct hisi_fixed_factor_clock *clks, 10275af25f5SHaojian Zhuang int nums, 10375af25f5SHaojian Zhuang struct hisi_clock_data *data) 1040aa0c95fSHaojian Zhuang { 1050aa0c95fSHaojian Zhuang struct clk *clk; 1060aa0c95fSHaojian Zhuang int i; 1070aa0c95fSHaojian Zhuang 1080aa0c95fSHaojian Zhuang for (i = 0; i < nums; i++) { 1090aa0c95fSHaojian Zhuang clk = clk_register_fixed_factor(NULL, clks[i].name, 1100aa0c95fSHaojian Zhuang clks[i].parent_name, 1110aa0c95fSHaojian Zhuang clks[i].flags, clks[i].mult, 1120aa0c95fSHaojian Zhuang clks[i].div); 1130aa0c95fSHaojian Zhuang if (IS_ERR(clk)) { 1140aa0c95fSHaojian Zhuang pr_err("%s: failed to register clock %s\n", 1150aa0c95fSHaojian Zhuang __func__, clks[i].name); 1160aa0c95fSHaojian Zhuang continue; 1170aa0c95fSHaojian Zhuang } 11875af25f5SHaojian Zhuang data->clk_data.clks[clks[i].id] = clk; 1190aa0c95fSHaojian Zhuang } 1200aa0c95fSHaojian Zhuang } 1210aa0c95fSHaojian Zhuang 1220aa0c95fSHaojian Zhuang void __init hisi_clk_register_mux(struct hisi_mux_clock *clks, 12375af25f5SHaojian Zhuang int nums, struct hisi_clock_data *data) 1240aa0c95fSHaojian Zhuang { 1250aa0c95fSHaojian Zhuang struct clk *clk; 12675af25f5SHaojian Zhuang void __iomem *base = data->base; 1270aa0c95fSHaojian Zhuang int i; 1280aa0c95fSHaojian Zhuang 1290aa0c95fSHaojian Zhuang for (i = 0; i < nums; i++) { 130156342a1SZhangfei Gao u32 mask = BIT(clks[i].width) - 1; 131156342a1SZhangfei Gao 132156342a1SZhangfei Gao clk = clk_register_mux_table(NULL, clks[i].name, 133156342a1SZhangfei Gao clks[i].parent_names, 1340aa0c95fSHaojian Zhuang clks[i].num_parents, clks[i].flags, 1350aa0c95fSHaojian Zhuang base + clks[i].offset, clks[i].shift, 136156342a1SZhangfei Gao mask, clks[i].mux_flags, 137156342a1SZhangfei Gao clks[i].table, &hisi_clk_lock); 1380aa0c95fSHaojian Zhuang if (IS_ERR(clk)) { 1390aa0c95fSHaojian Zhuang pr_err("%s: failed to register clock %s\n", 1400aa0c95fSHaojian Zhuang __func__, clks[i].name); 1410aa0c95fSHaojian Zhuang continue; 1420aa0c95fSHaojian Zhuang } 1430aa0c95fSHaojian Zhuang 1440aa0c95fSHaojian Zhuang if (clks[i].alias) 1450aa0c95fSHaojian Zhuang clk_register_clkdev(clk, clks[i].alias, NULL); 1460aa0c95fSHaojian Zhuang 14775af25f5SHaojian Zhuang data->clk_data.clks[clks[i].id] = clk; 1480aa0c95fSHaojian Zhuang } 1490aa0c95fSHaojian Zhuang } 1500aa0c95fSHaojian Zhuang 1510aa0c95fSHaojian Zhuang void __init hisi_clk_register_divider(struct hisi_divider_clock *clks, 15275af25f5SHaojian Zhuang int nums, struct hisi_clock_data *data) 1530aa0c95fSHaojian Zhuang { 1540aa0c95fSHaojian Zhuang struct clk *clk; 15575af25f5SHaojian Zhuang void __iomem *base = data->base; 1560aa0c95fSHaojian Zhuang int i; 1570aa0c95fSHaojian Zhuang 1580aa0c95fSHaojian Zhuang for (i = 0; i < nums; i++) { 1590aa0c95fSHaojian Zhuang clk = clk_register_divider_table(NULL, clks[i].name, 1600aa0c95fSHaojian Zhuang clks[i].parent_name, 1610aa0c95fSHaojian Zhuang clks[i].flags, 1620aa0c95fSHaojian Zhuang base + clks[i].offset, 1630aa0c95fSHaojian Zhuang clks[i].shift, clks[i].width, 1640aa0c95fSHaojian Zhuang clks[i].div_flags, 1650aa0c95fSHaojian Zhuang clks[i].table, 1660aa0c95fSHaojian Zhuang &hisi_clk_lock); 1670aa0c95fSHaojian Zhuang if (IS_ERR(clk)) { 1680aa0c95fSHaojian Zhuang pr_err("%s: failed to register clock %s\n", 1690aa0c95fSHaojian Zhuang __func__, clks[i].name); 1700aa0c95fSHaojian Zhuang continue; 1710aa0c95fSHaojian Zhuang } 1720aa0c95fSHaojian Zhuang 1730aa0c95fSHaojian Zhuang if (clks[i].alias) 1740aa0c95fSHaojian Zhuang clk_register_clkdev(clk, clks[i].alias, NULL); 1750aa0c95fSHaojian Zhuang 17675af25f5SHaojian Zhuang data->clk_data.clks[clks[i].id] = clk; 1770aa0c95fSHaojian Zhuang } 1780aa0c95fSHaojian Zhuang } 1790aa0c95fSHaojian Zhuang 1808b9dcb6cSZhangfei Gao void __init hisi_clk_register_gate(struct hisi_gate_clock *clks, 1818b9dcb6cSZhangfei Gao int nums, struct hisi_clock_data *data) 1828b9dcb6cSZhangfei Gao { 1838b9dcb6cSZhangfei Gao struct clk *clk; 1848b9dcb6cSZhangfei Gao void __iomem *base = data->base; 1858b9dcb6cSZhangfei Gao int i; 1868b9dcb6cSZhangfei Gao 1878b9dcb6cSZhangfei Gao for (i = 0; i < nums; i++) { 1888b9dcb6cSZhangfei Gao clk = clk_register_gate(NULL, clks[i].name, 1898b9dcb6cSZhangfei Gao clks[i].parent_name, 1908b9dcb6cSZhangfei Gao clks[i].flags, 1918b9dcb6cSZhangfei Gao base + clks[i].offset, 1928b9dcb6cSZhangfei Gao clks[i].bit_idx, 1938b9dcb6cSZhangfei Gao clks[i].gate_flags, 1948b9dcb6cSZhangfei Gao &hisi_clk_lock); 1958b9dcb6cSZhangfei Gao if (IS_ERR(clk)) { 1968b9dcb6cSZhangfei Gao pr_err("%s: failed to register clock %s\n", 1978b9dcb6cSZhangfei Gao __func__, clks[i].name); 1988b9dcb6cSZhangfei Gao continue; 1998b9dcb6cSZhangfei Gao } 2008b9dcb6cSZhangfei Gao 2018b9dcb6cSZhangfei Gao if (clks[i].alias) 2028b9dcb6cSZhangfei Gao clk_register_clkdev(clk, clks[i].alias, NULL); 2038b9dcb6cSZhangfei Gao 2048b9dcb6cSZhangfei Gao data->clk_data.clks[clks[i].id] = clk; 2058b9dcb6cSZhangfei Gao } 2068b9dcb6cSZhangfei Gao } 2078b9dcb6cSZhangfei Gao 2080aa0c95fSHaojian Zhuang void __init hisi_clk_register_gate_sep(struct hisi_gate_clock *clks, 20975af25f5SHaojian Zhuang int nums, struct hisi_clock_data *data) 2100aa0c95fSHaojian Zhuang { 2110aa0c95fSHaojian Zhuang struct clk *clk; 21275af25f5SHaojian Zhuang void __iomem *base = data->base; 2130aa0c95fSHaojian Zhuang int i; 2140aa0c95fSHaojian Zhuang 2150aa0c95fSHaojian Zhuang for (i = 0; i < nums; i++) { 2160aa0c95fSHaojian Zhuang clk = hisi_register_clkgate_sep(NULL, clks[i].name, 2170aa0c95fSHaojian Zhuang clks[i].parent_name, 2180aa0c95fSHaojian Zhuang clks[i].flags, 2190aa0c95fSHaojian Zhuang base + clks[i].offset, 2200aa0c95fSHaojian Zhuang clks[i].bit_idx, 2210aa0c95fSHaojian Zhuang clks[i].gate_flags, 2220aa0c95fSHaojian Zhuang &hisi_clk_lock); 2230aa0c95fSHaojian Zhuang if (IS_ERR(clk)) { 2240aa0c95fSHaojian Zhuang pr_err("%s: failed to register clock %s\n", 2250aa0c95fSHaojian Zhuang __func__, clks[i].name); 2260aa0c95fSHaojian Zhuang continue; 2270aa0c95fSHaojian Zhuang } 2280aa0c95fSHaojian Zhuang 2290aa0c95fSHaojian Zhuang if (clks[i].alias) 2300aa0c95fSHaojian Zhuang clk_register_clkdev(clk, clks[i].alias, NULL); 2310aa0c95fSHaojian Zhuang 23275af25f5SHaojian Zhuang data->clk_data.clks[clks[i].id] = clk; 2330aa0c95fSHaojian Zhuang } 2340aa0c95fSHaojian Zhuang } 235*72ea4861SBintian Wang 236*72ea4861SBintian Wang void __init hi6220_clk_register_divider(struct hi6220_divider_clock *clks, 237*72ea4861SBintian Wang int nums, struct hisi_clock_data *data) 238*72ea4861SBintian Wang { 239*72ea4861SBintian Wang struct clk *clk; 240*72ea4861SBintian Wang void __iomem *base = data->base; 241*72ea4861SBintian Wang int i; 242*72ea4861SBintian Wang 243*72ea4861SBintian Wang for (i = 0; i < nums; i++) { 244*72ea4861SBintian Wang clk = hi6220_register_clkdiv(NULL, clks[i].name, 245*72ea4861SBintian Wang clks[i].parent_name, 246*72ea4861SBintian Wang clks[i].flags, 247*72ea4861SBintian Wang base + clks[i].offset, 248*72ea4861SBintian Wang clks[i].shift, 249*72ea4861SBintian Wang clks[i].width, 250*72ea4861SBintian Wang clks[i].mask_bit, 251*72ea4861SBintian Wang &hisi_clk_lock); 252*72ea4861SBintian Wang if (IS_ERR(clk)) { 253*72ea4861SBintian Wang pr_err("%s: failed to register clock %s\n", 254*72ea4861SBintian Wang __func__, clks[i].name); 255*72ea4861SBintian Wang continue; 256*72ea4861SBintian Wang } 257*72ea4861SBintian Wang 258*72ea4861SBintian Wang if (clks[i].alias) 259*72ea4861SBintian Wang clk_register_clkdev(clk, clks[i].alias, NULL); 260*72ea4861SBintian Wang 261*72ea4861SBintian Wang data->clk_data.clks[clks[i].id] = clk; 262*72ea4861SBintian Wang } 263*72ea4861SBintian Wang } 264