1*16216333SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later
2d3e6573cSHaojian Zhuang /*
3d3e6573cSHaojian Zhuang * Hisilicon HiP04 clock driver
4d3e6573cSHaojian Zhuang *
5d3e6573cSHaojian Zhuang * Copyright (c) 2013-2014 Hisilicon Limited.
6d3e6573cSHaojian Zhuang * Copyright (c) 2013-2014 Linaro Limited.
7d3e6573cSHaojian Zhuang *
8d3e6573cSHaojian Zhuang * Author: Haojian Zhuang <haojian.zhuang@linaro.org>
9d3e6573cSHaojian Zhuang */
10d3e6573cSHaojian Zhuang
11d3e6573cSHaojian Zhuang #include <linux/kernel.h>
12d3e6573cSHaojian Zhuang #include <linux/clk-provider.h>
13d3e6573cSHaojian Zhuang #include <linux/io.h>
14d3e6573cSHaojian Zhuang #include <linux/slab.h>
15d3e6573cSHaojian Zhuang
16d3e6573cSHaojian Zhuang #include <dt-bindings/clock/hip04-clock.h>
17d3e6573cSHaojian Zhuang
18d3e6573cSHaojian Zhuang #include "clk.h"
19d3e6573cSHaojian Zhuang
20d3e6573cSHaojian Zhuang /* fixed rate clocks */
21d3e6573cSHaojian Zhuang static struct hisi_fixed_rate_clock hip04_fixed_rate_clks[] __initdata = {
22f61990f3SStephen Boyd { HIP04_OSC50M, "osc50m", NULL, 0, 50000000, },
23f61990f3SStephen Boyd { HIP04_CLK_50M, "clk50m", NULL, 0, 50000000, },
24f61990f3SStephen Boyd { HIP04_CLK_168M, "clk168m", NULL, 0, 168750000, },
25d3e6573cSHaojian Zhuang };
26d3e6573cSHaojian Zhuang
hip04_clk_init(struct device_node * np)27d3e6573cSHaojian Zhuang static void __init hip04_clk_init(struct device_node *np)
28d3e6573cSHaojian Zhuang {
2975af25f5SHaojian Zhuang struct hisi_clock_data *clk_data;
3075af25f5SHaojian Zhuang
3175af25f5SHaojian Zhuang clk_data = hisi_clk_init(np, HIP04_NR_CLKS);
3275af25f5SHaojian Zhuang if (!clk_data)
3375af25f5SHaojian Zhuang return;
34d3e6573cSHaojian Zhuang
35d3e6573cSHaojian Zhuang hisi_clk_register_fixed_rate(hip04_fixed_rate_clks,
36d3e6573cSHaojian Zhuang ARRAY_SIZE(hip04_fixed_rate_clks),
3775af25f5SHaojian Zhuang clk_data);
38d3e6573cSHaojian Zhuang }
39d3e6573cSHaojian Zhuang CLK_OF_DECLARE(hip04_clk, "hisilicon,hip04-clock", hip04_clk_init);
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