1 // SPDX-License-Identifier: GPL-2.0+ 2 3 #define pr_fmt(fmt) "clk-aspeed: " fmt 4 5 #include <linux/clk-provider.h> 6 #include <linux/mfd/syscon.h> 7 #include <linux/of_address.h> 8 #include <linux/of_device.h> 9 #include <linux/platform_device.h> 10 #include <linux/regmap.h> 11 #include <linux/reset-controller.h> 12 #include <linux/slab.h> 13 #include <linux/spinlock.h> 14 15 #include <dt-bindings/clock/aspeed-clock.h> 16 17 #define ASPEED_NUM_CLKS 35 18 19 #define ASPEED_RESET2_OFFSET 32 20 21 #define ASPEED_RESET_CTRL 0x04 22 #define ASPEED_CLK_SELECTION 0x08 23 #define ASPEED_CLK_STOP_CTRL 0x0c 24 #define ASPEED_MPLL_PARAM 0x20 25 #define ASPEED_HPLL_PARAM 0x24 26 #define AST2500_HPLL_BYPASS_EN BIT(20) 27 #define AST2400_HPLL_STRAPPED BIT(18) 28 #define AST2400_HPLL_BYPASS_EN BIT(17) 29 #define ASPEED_MISC_CTRL 0x2c 30 #define UART_DIV13_EN BIT(12) 31 #define ASPEED_STRAP 0x70 32 #define CLKIN_25MHZ_EN BIT(23) 33 #define AST2400_CLK_SOURCE_SEL BIT(18) 34 #define ASPEED_CLK_SELECTION_2 0xd8 35 #define ASPEED_RESET_CTRL2 0xd4 36 37 /* Globally visible clocks */ 38 static DEFINE_SPINLOCK(aspeed_clk_lock); 39 40 /* Keeps track of all clocks */ 41 static struct clk_hw_onecell_data *aspeed_clk_data; 42 43 static void __iomem *scu_base; 44 45 /** 46 * struct aspeed_gate_data - Aspeed gated clocks 47 * @clock_idx: bit used to gate this clock in the clock register 48 * @reset_idx: bit used to reset this IP in the reset register. -1 if no 49 * reset is required when enabling the clock 50 * @name: the clock name 51 * @parent_name: the name of the parent clock 52 * @flags: standard clock framework flags 53 */ 54 struct aspeed_gate_data { 55 u8 clock_idx; 56 s8 reset_idx; 57 const char *name; 58 const char *parent_name; 59 unsigned long flags; 60 }; 61 62 /** 63 * struct aspeed_clk_gate - Aspeed specific clk_gate structure 64 * @hw: handle between common and hardware-specific interfaces 65 * @reg: register controlling gate 66 * @clock_idx: bit used to gate this clock in the clock register 67 * @reset_idx: bit used to reset this IP in the reset register. -1 if no 68 * reset is required when enabling the clock 69 * @flags: hardware-specific flags 70 * @lock: register lock 71 * 72 * Some of the clocks in the Aspeed SoC must be put in reset before enabling. 73 * This modified version of clk_gate allows an optional reset bit to be 74 * specified. 75 */ 76 struct aspeed_clk_gate { 77 struct clk_hw hw; 78 struct regmap *map; 79 u8 clock_idx; 80 s8 reset_idx; 81 u8 flags; 82 spinlock_t *lock; 83 }; 84 85 #define to_aspeed_clk_gate(_hw) container_of(_hw, struct aspeed_clk_gate, hw) 86 87 /* TODO: ask Aspeed about the actual parent data */ 88 static const struct aspeed_gate_data aspeed_gates[] = { 89 /* clk rst name parent flags */ 90 [ASPEED_CLK_GATE_ECLK] = { 0, -1, "eclk-gate", "eclk", 0 }, /* Video Engine */ 91 [ASPEED_CLK_GATE_GCLK] = { 1, 7, "gclk-gate", NULL, 0 }, /* 2D engine */ 92 [ASPEED_CLK_GATE_MCLK] = { 2, -1, "mclk-gate", "mpll", CLK_IS_CRITICAL }, /* SDRAM */ 93 [ASPEED_CLK_GATE_VCLK] = { 3, 6, "vclk-gate", NULL, 0 }, /* Video Capture */ 94 [ASPEED_CLK_GATE_BCLK] = { 4, 10, "bclk-gate", "bclk", 0 }, /* PCIe/PCI */ 95 [ASPEED_CLK_GATE_DCLK] = { 5, -1, "dclk-gate", NULL, 0 }, /* DAC */ 96 [ASPEED_CLK_GATE_REFCLK] = { 6, -1, "refclk-gate", "clkin", CLK_IS_CRITICAL }, 97 [ASPEED_CLK_GATE_USBPORT2CLK] = { 7, 3, "usb-port2-gate", NULL, 0 }, /* USB2.0 Host port 2 */ 98 [ASPEED_CLK_GATE_LCLK] = { 8, 5, "lclk-gate", NULL, 0 }, /* LPC */ 99 [ASPEED_CLK_GATE_USBUHCICLK] = { 9, 15, "usb-uhci-gate", NULL, 0 }, /* USB1.1 (requires port 2 enabled) */ 100 [ASPEED_CLK_GATE_D1CLK] = { 10, 13, "d1clk-gate", NULL, 0 }, /* GFX CRT */ 101 [ASPEED_CLK_GATE_YCLK] = { 13, 4, "yclk-gate", NULL, 0 }, /* HAC */ 102 [ASPEED_CLK_GATE_USBPORT1CLK] = { 14, 14, "usb-port1-gate", NULL, 0 }, /* USB2 hub/USB2 host port 1/USB1.1 dev */ 103 [ASPEED_CLK_GATE_UART1CLK] = { 15, -1, "uart1clk-gate", "uart", 0 }, /* UART1 */ 104 [ASPEED_CLK_GATE_UART2CLK] = { 16, -1, "uart2clk-gate", "uart", 0 }, /* UART2 */ 105 [ASPEED_CLK_GATE_UART5CLK] = { 17, -1, "uart5clk-gate", "uart", 0 }, /* UART5 */ 106 [ASPEED_CLK_GATE_ESPICLK] = { 19, -1, "espiclk-gate", NULL, 0 }, /* eSPI */ 107 [ASPEED_CLK_GATE_MAC1CLK] = { 20, 11, "mac1clk-gate", "mac", 0 }, /* MAC1 */ 108 [ASPEED_CLK_GATE_MAC2CLK] = { 21, 12, "mac2clk-gate", "mac", 0 }, /* MAC2 */ 109 [ASPEED_CLK_GATE_RSACLK] = { 24, -1, "rsaclk-gate", NULL, 0 }, /* RSA */ 110 [ASPEED_CLK_GATE_UART3CLK] = { 25, -1, "uart3clk-gate", "uart", 0 }, /* UART3 */ 111 [ASPEED_CLK_GATE_UART4CLK] = { 26, -1, "uart4clk-gate", "uart", 0 }, /* UART4 */ 112 [ASPEED_CLK_GATE_SDCLKCLK] = { 27, 16, "sdclk-gate", NULL, 0 }, /* SDIO/SD */ 113 [ASPEED_CLK_GATE_LHCCLK] = { 28, -1, "lhclk-gate", "lhclk", 0 }, /* LPC master/LPC+ */ 114 }; 115 116 static const struct clk_div_table ast2500_mac_div_table[] = { 117 { 0x0, 4 }, /* Yep, really. Aspeed confirmed this is correct */ 118 { 0x1, 4 }, 119 { 0x2, 6 }, 120 { 0x3, 8 }, 121 { 0x4, 10 }, 122 { 0x5, 12 }, 123 { 0x6, 14 }, 124 { 0x7, 16 }, 125 { 0 } 126 }; 127 128 static const struct clk_div_table ast2400_div_table[] = { 129 { 0x0, 2 }, 130 { 0x1, 4 }, 131 { 0x2, 6 }, 132 { 0x3, 8 }, 133 { 0x4, 10 }, 134 { 0x5, 12 }, 135 { 0x6, 14 }, 136 { 0x7, 16 }, 137 { 0 } 138 }; 139 140 static const struct clk_div_table ast2500_div_table[] = { 141 { 0x0, 4 }, 142 { 0x1, 8 }, 143 { 0x2, 12 }, 144 { 0x3, 16 }, 145 { 0x4, 20 }, 146 { 0x5, 24 }, 147 { 0x6, 28 }, 148 { 0x7, 32 }, 149 { 0 } 150 }; 151 152 static struct clk_hw *aspeed_ast2400_calc_pll(const char *name, u32 val) 153 { 154 unsigned int mult, div; 155 156 if (val & AST2400_HPLL_BYPASS_EN) { 157 /* Pass through mode */ 158 mult = div = 1; 159 } else { 160 /* F = 24Mhz * (2-OD) * [(N + 2) / (D + 1)] */ 161 u32 n = (val >> 5) & 0x3f; 162 u32 od = (val >> 4) & 0x1; 163 u32 d = val & 0xf; 164 165 mult = (2 - od) * (n + 2); 166 div = d + 1; 167 } 168 return clk_hw_register_fixed_factor(NULL, name, "clkin", 0, 169 mult, div); 170 }; 171 172 static struct clk_hw *aspeed_ast2500_calc_pll(const char *name, u32 val) 173 { 174 unsigned int mult, div; 175 176 if (val & AST2500_HPLL_BYPASS_EN) { 177 /* Pass through mode */ 178 mult = div = 1; 179 } else { 180 /* F = clkin * [(M+1) / (N+1)] / (P + 1) */ 181 u32 p = (val >> 13) & 0x3f; 182 u32 m = (val >> 5) & 0xff; 183 u32 n = val & 0x1f; 184 185 mult = (m + 1) / (n + 1); 186 div = p + 1; 187 } 188 189 return clk_hw_register_fixed_factor(NULL, name, "clkin", 0, 190 mult, div); 191 } 192 193 struct aspeed_clk_soc_data { 194 const struct clk_div_table *div_table; 195 const struct clk_div_table *mac_div_table; 196 struct clk_hw *(*calc_pll)(const char *name, u32 val); 197 }; 198 199 static const struct aspeed_clk_soc_data ast2500_data = { 200 .div_table = ast2500_div_table, 201 .mac_div_table = ast2500_mac_div_table, 202 .calc_pll = aspeed_ast2500_calc_pll, 203 }; 204 205 static const struct aspeed_clk_soc_data ast2400_data = { 206 .div_table = ast2400_div_table, 207 .mac_div_table = ast2400_div_table, 208 .calc_pll = aspeed_ast2400_calc_pll, 209 }; 210 211 static int aspeed_clk_is_enabled(struct clk_hw *hw) 212 { 213 struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw); 214 u32 clk = BIT(gate->clock_idx); 215 u32 enval = (gate->flags & CLK_GATE_SET_TO_DISABLE) ? 0 : clk; 216 u32 reg; 217 218 regmap_read(gate->map, ASPEED_CLK_STOP_CTRL, ®); 219 220 return ((reg & clk) == enval) ? 1 : 0; 221 } 222 223 static int aspeed_clk_enable(struct clk_hw *hw) 224 { 225 struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw); 226 unsigned long flags; 227 u32 clk = BIT(gate->clock_idx); 228 u32 rst = BIT(gate->reset_idx); 229 u32 enval; 230 231 spin_lock_irqsave(gate->lock, flags); 232 233 if (aspeed_clk_is_enabled(hw)) { 234 spin_unlock_irqrestore(gate->lock, flags); 235 return 0; 236 } 237 238 if (gate->reset_idx >= 0) { 239 /* Put IP in reset */ 240 regmap_update_bits(gate->map, ASPEED_RESET_CTRL, rst, rst); 241 242 /* Delay 100us */ 243 udelay(100); 244 } 245 246 /* Enable clock */ 247 enval = (gate->flags & CLK_GATE_SET_TO_DISABLE) ? 0 : clk; 248 regmap_update_bits(gate->map, ASPEED_CLK_STOP_CTRL, clk, enval); 249 250 if (gate->reset_idx >= 0) { 251 /* A delay of 10ms is specified by the ASPEED docs */ 252 mdelay(10); 253 254 /* Take IP out of reset */ 255 regmap_update_bits(gate->map, ASPEED_RESET_CTRL, rst, 0); 256 } 257 258 spin_unlock_irqrestore(gate->lock, flags); 259 260 return 0; 261 } 262 263 static void aspeed_clk_disable(struct clk_hw *hw) 264 { 265 struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw); 266 unsigned long flags; 267 u32 clk = BIT(gate->clock_idx); 268 u32 enval; 269 270 spin_lock_irqsave(gate->lock, flags); 271 272 enval = (gate->flags & CLK_GATE_SET_TO_DISABLE) ? clk : 0; 273 regmap_update_bits(gate->map, ASPEED_CLK_STOP_CTRL, clk, enval); 274 275 spin_unlock_irqrestore(gate->lock, flags); 276 } 277 278 static const struct clk_ops aspeed_clk_gate_ops = { 279 .enable = aspeed_clk_enable, 280 .disable = aspeed_clk_disable, 281 .is_enabled = aspeed_clk_is_enabled, 282 }; 283 284 /** 285 * struct aspeed_reset - Aspeed reset controller 286 * @map: regmap to access the containing system controller 287 * @rcdev: reset controller device 288 */ 289 struct aspeed_reset { 290 struct regmap *map; 291 struct reset_controller_dev rcdev; 292 }; 293 294 #define to_aspeed_reset(p) container_of((p), struct aspeed_reset, rcdev) 295 296 static const u8 aspeed_resets[] = { 297 /* SCU04 resets */ 298 [ASPEED_RESET_XDMA] = 25, 299 [ASPEED_RESET_MCTP] = 24, 300 [ASPEED_RESET_ADC] = 23, 301 [ASPEED_RESET_JTAG_MASTER] = 22, 302 [ASPEED_RESET_MIC] = 18, 303 [ASPEED_RESET_PWM] = 9, 304 [ASPEED_RESET_PCIVGA] = 8, 305 [ASPEED_RESET_I2C] = 2, 306 [ASPEED_RESET_AHB] = 1, 307 308 /* 309 * SCUD4 resets start at an offset to separate them from 310 * the SCU04 resets. 311 */ 312 [ASPEED_RESET_CRT1] = ASPEED_RESET2_OFFSET + 5, 313 }; 314 315 static int aspeed_reset_deassert(struct reset_controller_dev *rcdev, 316 unsigned long id) 317 { 318 struct aspeed_reset *ar = to_aspeed_reset(rcdev); 319 u32 reg = ASPEED_RESET_CTRL; 320 u32 bit = aspeed_resets[id]; 321 322 if (bit >= ASPEED_RESET2_OFFSET) { 323 bit -= ASPEED_RESET2_OFFSET; 324 reg = ASPEED_RESET_CTRL2; 325 } 326 327 return regmap_update_bits(ar->map, reg, BIT(bit), 0); 328 } 329 330 static int aspeed_reset_assert(struct reset_controller_dev *rcdev, 331 unsigned long id) 332 { 333 struct aspeed_reset *ar = to_aspeed_reset(rcdev); 334 u32 reg = ASPEED_RESET_CTRL; 335 u32 bit = aspeed_resets[id]; 336 337 if (bit >= ASPEED_RESET2_OFFSET) { 338 bit -= ASPEED_RESET2_OFFSET; 339 reg = ASPEED_RESET_CTRL2; 340 } 341 342 return regmap_update_bits(ar->map, reg, BIT(bit), BIT(bit)); 343 } 344 345 static int aspeed_reset_status(struct reset_controller_dev *rcdev, 346 unsigned long id) 347 { 348 struct aspeed_reset *ar = to_aspeed_reset(rcdev); 349 u32 reg = ASPEED_RESET_CTRL; 350 u32 bit = aspeed_resets[id]; 351 int ret, val; 352 353 if (bit >= ASPEED_RESET2_OFFSET) { 354 bit -= ASPEED_RESET2_OFFSET; 355 reg = ASPEED_RESET_CTRL2; 356 } 357 358 ret = regmap_read(ar->map, reg, &val); 359 if (ret) 360 return ret; 361 362 return !!(val & BIT(bit)); 363 } 364 365 static const struct reset_control_ops aspeed_reset_ops = { 366 .assert = aspeed_reset_assert, 367 .deassert = aspeed_reset_deassert, 368 .status = aspeed_reset_status, 369 }; 370 371 static struct clk_hw *aspeed_clk_hw_register_gate(struct device *dev, 372 const char *name, const char *parent_name, unsigned long flags, 373 struct regmap *map, u8 clock_idx, u8 reset_idx, 374 u8 clk_gate_flags, spinlock_t *lock) 375 { 376 struct aspeed_clk_gate *gate; 377 struct clk_init_data init; 378 struct clk_hw *hw; 379 int ret; 380 381 gate = kzalloc(sizeof(*gate), GFP_KERNEL); 382 if (!gate) 383 return ERR_PTR(-ENOMEM); 384 385 init.name = name; 386 init.ops = &aspeed_clk_gate_ops; 387 init.flags = flags; 388 init.parent_names = parent_name ? &parent_name : NULL; 389 init.num_parents = parent_name ? 1 : 0; 390 391 gate->map = map; 392 gate->clock_idx = clock_idx; 393 gate->reset_idx = reset_idx; 394 gate->flags = clk_gate_flags; 395 gate->lock = lock; 396 gate->hw.init = &init; 397 398 hw = &gate->hw; 399 ret = clk_hw_register(dev, hw); 400 if (ret) { 401 kfree(gate); 402 hw = ERR_PTR(ret); 403 } 404 405 return hw; 406 } 407 408 static int aspeed_clk_probe(struct platform_device *pdev) 409 { 410 const struct aspeed_clk_soc_data *soc_data; 411 struct device *dev = &pdev->dev; 412 struct aspeed_reset *ar; 413 struct regmap *map; 414 struct clk_hw *hw; 415 u32 val, rate; 416 int i, ret; 417 418 map = syscon_node_to_regmap(dev->of_node); 419 if (IS_ERR(map)) { 420 dev_err(dev, "no syscon regmap\n"); 421 return PTR_ERR(map); 422 } 423 424 ar = devm_kzalloc(dev, sizeof(*ar), GFP_KERNEL); 425 if (!ar) 426 return -ENOMEM; 427 428 ar->map = map; 429 ar->rcdev.owner = THIS_MODULE; 430 ar->rcdev.nr_resets = ARRAY_SIZE(aspeed_resets); 431 ar->rcdev.ops = &aspeed_reset_ops; 432 ar->rcdev.of_node = dev->of_node; 433 434 ret = devm_reset_controller_register(dev, &ar->rcdev); 435 if (ret) { 436 dev_err(dev, "could not register reset controller\n"); 437 return ret; 438 } 439 440 /* SoC generations share common layouts but have different divisors */ 441 soc_data = of_device_get_match_data(dev); 442 if (!soc_data) { 443 dev_err(dev, "no match data for platform\n"); 444 return -EINVAL; 445 } 446 447 /* UART clock div13 setting */ 448 regmap_read(map, ASPEED_MISC_CTRL, &val); 449 if (val & UART_DIV13_EN) 450 rate = 24000000 / 13; 451 else 452 rate = 24000000; 453 /* TODO: Find the parent data for the uart clock */ 454 hw = clk_hw_register_fixed_rate(dev, "uart", NULL, 0, rate); 455 if (IS_ERR(hw)) 456 return PTR_ERR(hw); 457 aspeed_clk_data->hws[ASPEED_CLK_UART] = hw; 458 459 /* 460 * Memory controller (M-PLL) PLL. This clock is configured by the 461 * bootloader, and is exposed to Linux as a read-only clock rate. 462 */ 463 regmap_read(map, ASPEED_MPLL_PARAM, &val); 464 hw = soc_data->calc_pll("mpll", val); 465 if (IS_ERR(hw)) 466 return PTR_ERR(hw); 467 aspeed_clk_data->hws[ASPEED_CLK_MPLL] = hw; 468 469 /* SD/SDIO clock divider (TODO: There's a gate too) */ 470 hw = clk_hw_register_divider_table(dev, "sdio", "hpll", 0, 471 scu_base + ASPEED_CLK_SELECTION, 12, 3, 0, 472 soc_data->div_table, 473 &aspeed_clk_lock); 474 if (IS_ERR(hw)) 475 return PTR_ERR(hw); 476 aspeed_clk_data->hws[ASPEED_CLK_SDIO] = hw; 477 478 /* MAC AHB bus clock divider */ 479 hw = clk_hw_register_divider_table(dev, "mac", "hpll", 0, 480 scu_base + ASPEED_CLK_SELECTION, 16, 3, 0, 481 soc_data->mac_div_table, 482 &aspeed_clk_lock); 483 if (IS_ERR(hw)) 484 return PTR_ERR(hw); 485 aspeed_clk_data->hws[ASPEED_CLK_MAC] = hw; 486 487 /* LPC Host (LHCLK) clock divider */ 488 hw = clk_hw_register_divider_table(dev, "lhclk", "hpll", 0, 489 scu_base + ASPEED_CLK_SELECTION, 20, 3, 0, 490 soc_data->div_table, 491 &aspeed_clk_lock); 492 if (IS_ERR(hw)) 493 return PTR_ERR(hw); 494 aspeed_clk_data->hws[ASPEED_CLK_LHCLK] = hw; 495 496 /* P-Bus (BCLK) clock divider */ 497 hw = clk_hw_register_divider_table(dev, "bclk", "hpll", 0, 498 scu_base + ASPEED_CLK_SELECTION_2, 0, 2, 0, 499 soc_data->div_table, 500 &aspeed_clk_lock); 501 if (IS_ERR(hw)) 502 return PTR_ERR(hw); 503 aspeed_clk_data->hws[ASPEED_CLK_BCLK] = hw; 504 505 /* 506 * TODO: There are a number of clocks that not included in this driver 507 * as more information is required: 508 * D2-PLL 509 * D-PLL 510 * YCLK 511 * RGMII 512 * RMII 513 * UART[1..5] clock source mux 514 * Video Engine (ECLK) mux and clock divider 515 */ 516 517 for (i = 0; i < ARRAY_SIZE(aspeed_gates); i++) { 518 const struct aspeed_gate_data *gd = &aspeed_gates[i]; 519 u32 gate_flags; 520 521 /* Special case: the USB port 1 clock (bit 14) is always 522 * working the opposite way from the other ones. 523 */ 524 gate_flags = (gd->clock_idx == 14) ? 0 : CLK_GATE_SET_TO_DISABLE; 525 hw = aspeed_clk_hw_register_gate(dev, 526 gd->name, 527 gd->parent_name, 528 gd->flags, 529 map, 530 gd->clock_idx, 531 gd->reset_idx, 532 gate_flags, 533 &aspeed_clk_lock); 534 if (IS_ERR(hw)) 535 return PTR_ERR(hw); 536 aspeed_clk_data->hws[i] = hw; 537 } 538 539 return 0; 540 }; 541 542 static const struct of_device_id aspeed_clk_dt_ids[] = { 543 { .compatible = "aspeed,ast2400-scu", .data = &ast2400_data }, 544 { .compatible = "aspeed,ast2500-scu", .data = &ast2500_data }, 545 { } 546 }; 547 548 static struct platform_driver aspeed_clk_driver = { 549 .probe = aspeed_clk_probe, 550 .driver = { 551 .name = "aspeed-clk", 552 .of_match_table = aspeed_clk_dt_ids, 553 .suppress_bind_attrs = true, 554 }, 555 }; 556 builtin_platform_driver(aspeed_clk_driver); 557 558 static void __init aspeed_ast2400_cc(struct regmap *map) 559 { 560 struct clk_hw *hw; 561 u32 val, freq, div; 562 563 /* 564 * CLKIN is the crystal oscillator, 24, 48 or 25MHz selected by 565 * strapping 566 */ 567 regmap_read(map, ASPEED_STRAP, &val); 568 if (val & CLKIN_25MHZ_EN) 569 freq = 25000000; 570 else if (val & AST2400_CLK_SOURCE_SEL) 571 freq = 48000000; 572 else 573 freq = 24000000; 574 hw = clk_hw_register_fixed_rate(NULL, "clkin", NULL, 0, freq); 575 pr_debug("clkin @%u MHz\n", freq / 1000000); 576 577 /* 578 * High-speed PLL clock derived from the crystal. This the CPU clock, 579 * and we assume that it is enabled 580 */ 581 regmap_read(map, ASPEED_HPLL_PARAM, &val); 582 WARN(val & AST2400_HPLL_STRAPPED, "hpll is strapped not configured"); 583 aspeed_clk_data->hws[ASPEED_CLK_HPLL] = aspeed_ast2400_calc_pll("hpll", val); 584 585 /* 586 * Strap bits 11:10 define the CPU/AHB clock frequency ratio (aka HCLK) 587 * 00: Select CPU:AHB = 1:1 588 * 01: Select CPU:AHB = 2:1 589 * 10: Select CPU:AHB = 4:1 590 * 11: Select CPU:AHB = 3:1 591 */ 592 regmap_read(map, ASPEED_STRAP, &val); 593 val = (val >> 10) & 0x3; 594 div = val + 1; 595 if (div == 3) 596 div = 4; 597 else if (div == 4) 598 div = 3; 599 hw = clk_hw_register_fixed_factor(NULL, "ahb", "hpll", 0, 1, div); 600 aspeed_clk_data->hws[ASPEED_CLK_AHB] = hw; 601 602 /* APB clock clock selection register SCU08 (aka PCLK) */ 603 hw = clk_hw_register_divider_table(NULL, "apb", "hpll", 0, 604 scu_base + ASPEED_CLK_SELECTION, 23, 3, 0, 605 ast2400_div_table, 606 &aspeed_clk_lock); 607 aspeed_clk_data->hws[ASPEED_CLK_APB] = hw; 608 } 609 610 static void __init aspeed_ast2500_cc(struct regmap *map) 611 { 612 struct clk_hw *hw; 613 u32 val, freq, div; 614 615 /* CLKIN is the crystal oscillator, 24 or 25MHz selected by strapping */ 616 regmap_read(map, ASPEED_STRAP, &val); 617 if (val & CLKIN_25MHZ_EN) 618 freq = 25000000; 619 else 620 freq = 24000000; 621 hw = clk_hw_register_fixed_rate(NULL, "clkin", NULL, 0, freq); 622 pr_debug("clkin @%u MHz\n", freq / 1000000); 623 624 /* 625 * High-speed PLL clock derived from the crystal. This the CPU clock, 626 * and we assume that it is enabled 627 */ 628 regmap_read(map, ASPEED_HPLL_PARAM, &val); 629 aspeed_clk_data->hws[ASPEED_CLK_HPLL] = aspeed_ast2500_calc_pll("hpll", val); 630 631 /* Strap bits 11:9 define the AXI/AHB clock frequency ratio (aka HCLK)*/ 632 regmap_read(map, ASPEED_STRAP, &val); 633 val = (val >> 9) & 0x7; 634 WARN(val == 0, "strapping is zero: cannot determine ahb clock"); 635 div = 2 * (val + 1); 636 hw = clk_hw_register_fixed_factor(NULL, "ahb", "hpll", 0, 1, div); 637 aspeed_clk_data->hws[ASPEED_CLK_AHB] = hw; 638 639 /* APB clock clock selection register SCU08 (aka PCLK) */ 640 regmap_read(map, ASPEED_CLK_SELECTION, &val); 641 val = (val >> 23) & 0x7; 642 div = 4 * (val + 1); 643 hw = clk_hw_register_fixed_factor(NULL, "apb", "hpll", 0, 1, div); 644 aspeed_clk_data->hws[ASPEED_CLK_APB] = hw; 645 }; 646 647 static void __init aspeed_cc_init(struct device_node *np) 648 { 649 struct regmap *map; 650 u32 val; 651 int ret; 652 int i; 653 654 scu_base = of_iomap(np, 0); 655 if (!scu_base) 656 return; 657 658 aspeed_clk_data = kzalloc(sizeof(*aspeed_clk_data) + 659 sizeof(*aspeed_clk_data->hws) * ASPEED_NUM_CLKS, 660 GFP_KERNEL); 661 if (!aspeed_clk_data) 662 return; 663 664 /* 665 * This way all clocks fetched before the platform device probes, 666 * except those we assign here for early use, will be deferred. 667 */ 668 for (i = 0; i < ASPEED_NUM_CLKS; i++) 669 aspeed_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER); 670 671 map = syscon_node_to_regmap(np); 672 if (IS_ERR(map)) { 673 pr_err("no syscon regmap\n"); 674 return; 675 } 676 /* 677 * We check that the regmap works on this very first access, 678 * but as this is an MMIO-backed regmap, subsequent regmap 679 * access is not going to fail and we skip error checks from 680 * this point. 681 */ 682 ret = regmap_read(map, ASPEED_STRAP, &val); 683 if (ret) { 684 pr_err("failed to read strapping register\n"); 685 return; 686 } 687 688 if (of_device_is_compatible(np, "aspeed,ast2400-scu")) 689 aspeed_ast2400_cc(map); 690 else if (of_device_is_compatible(np, "aspeed,ast2500-scu")) 691 aspeed_ast2500_cc(map); 692 else 693 pr_err("unknown platform, failed to add clocks\n"); 694 695 aspeed_clk_data->num = ASPEED_NUM_CLKS; 696 ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, aspeed_clk_data); 697 if (ret) 698 pr_err("failed to add DT provider: %d\n", ret); 699 }; 700 CLK_OF_DECLARE_DRIVER(aspeed_cc_g5, "aspeed,ast2500-scu", aspeed_cc_init); 701 CLK_OF_DECLARE_DRIVER(aspeed_cc_g4, "aspeed,ast2400-scu", aspeed_cc_init); 702