1 /* 2 * Copyright (C) 2014 Broadcom Corporation 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License as 6 * published by the Free Software Foundation version 2. 7 * 8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 9 * kind, whether express or implied; without even the implied warranty 10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14 #include <linux/kernel.h> 15 #include <linux/err.h> 16 #include <linux/clk-provider.h> 17 #include <linux/io.h> 18 #include <linux/of.h> 19 #include <linux/clkdev.h> 20 #include <linux/of_address.h> 21 #include <linux/delay.h> 22 23 #include "clk-iproc.h" 24 25 #define PLL_VCO_HIGH_SHIFT 19 26 #define PLL_VCO_LOW_SHIFT 30 27 28 /* number of delay loops waiting for PLL to lock */ 29 #define LOCK_DELAY 100 30 31 /* number of VCO frequency bands */ 32 #define NUM_FREQ_BANDS 8 33 34 #define NUM_KP_BANDS 3 35 enum kp_band { 36 KP_BAND_MID = 0, 37 KP_BAND_HIGH, 38 KP_BAND_HIGH_HIGH 39 }; 40 41 static const unsigned int kp_table[NUM_KP_BANDS][NUM_FREQ_BANDS] = { 42 { 5, 6, 6, 7, 7, 8, 9, 10 }, 43 { 4, 4, 5, 5, 6, 7, 8, 9 }, 44 { 4, 5, 5, 6, 7, 8, 9, 10 }, 45 }; 46 47 static const unsigned long ref_freq_table[NUM_FREQ_BANDS][2] = { 48 { 10000000, 12500000 }, 49 { 12500000, 15000000 }, 50 { 15000000, 20000000 }, 51 { 20000000, 25000000 }, 52 { 25000000, 50000000 }, 53 { 50000000, 75000000 }, 54 { 75000000, 100000000 }, 55 { 100000000, 125000000 }, 56 }; 57 58 enum vco_freq_range { 59 VCO_LOW = 700000000U, 60 VCO_MID = 1200000000U, 61 VCO_HIGH = 2200000000U, 62 VCO_HIGH_HIGH = 3100000000U, 63 VCO_MAX = 4000000000U, 64 }; 65 66 struct iproc_pll; 67 68 struct iproc_clk { 69 struct clk_hw hw; 70 const char *name; 71 struct iproc_pll *pll; 72 unsigned long rate; 73 const struct iproc_clk_ctrl *ctrl; 74 }; 75 76 struct iproc_pll { 77 void __iomem *pll_base; 78 void __iomem *pwr_base; 79 void __iomem *asiu_base; 80 81 const struct iproc_pll_ctrl *ctrl; 82 const struct iproc_pll_vco_param *vco_param; 83 unsigned int num_vco_entries; 84 85 struct clk_onecell_data clk_data; 86 struct iproc_clk *clks; 87 }; 88 89 #define to_iproc_clk(hw) container_of(hw, struct iproc_clk, hw) 90 91 /* 92 * Based on the target frequency, find a match from the VCO frequency parameter 93 * table and return its index 94 */ 95 static int pll_get_rate_index(struct iproc_pll *pll, unsigned int target_rate) 96 { 97 int i; 98 99 for (i = 0; i < pll->num_vco_entries; i++) 100 if (target_rate == pll->vco_param[i].rate) 101 break; 102 103 if (i >= pll->num_vco_entries) 104 return -EINVAL; 105 106 return i; 107 } 108 109 static int get_kp(unsigned long ref_freq, enum kp_band kp_index) 110 { 111 int i; 112 113 if (ref_freq < ref_freq_table[0][0]) 114 return -EINVAL; 115 116 for (i = 0; i < NUM_FREQ_BANDS; i++) { 117 if (ref_freq >= ref_freq_table[i][0] && 118 ref_freq < ref_freq_table[i][1]) 119 return kp_table[kp_index][i]; 120 } 121 return -EINVAL; 122 } 123 124 static int pll_wait_for_lock(struct iproc_pll *pll) 125 { 126 int i; 127 const struct iproc_pll_ctrl *ctrl = pll->ctrl; 128 129 for (i = 0; i < LOCK_DELAY; i++) { 130 u32 val = readl(pll->pll_base + ctrl->status.offset); 131 132 if (val & (1 << ctrl->status.shift)) 133 return 0; 134 udelay(10); 135 } 136 137 return -EIO; 138 } 139 140 static void iproc_pll_write(const struct iproc_pll *pll, void __iomem *base, 141 const u32 offset, u32 val) 142 { 143 const struct iproc_pll_ctrl *ctrl = pll->ctrl; 144 145 writel(val, base + offset); 146 147 if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK && 148 base == pll->pll_base)) 149 val = readl(base + offset); 150 } 151 152 static void __pll_disable(struct iproc_pll *pll) 153 { 154 const struct iproc_pll_ctrl *ctrl = pll->ctrl; 155 u32 val; 156 157 if (ctrl->flags & IPROC_CLK_PLL_ASIU) { 158 val = readl(pll->asiu_base + ctrl->asiu.offset); 159 val &= ~(1 << ctrl->asiu.en_shift); 160 iproc_pll_write(pll, pll->asiu_base, ctrl->asiu.offset, val); 161 } 162 163 if (ctrl->flags & IPROC_CLK_EMBED_PWRCTRL) { 164 val = readl(pll->pll_base + ctrl->aon.offset); 165 val |= bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift; 166 iproc_pll_write(pll, pll->pll_base, ctrl->aon.offset, val); 167 } 168 169 if (pll->pwr_base) { 170 /* latch input value so core power can be shut down */ 171 val = readl(pll->pwr_base + ctrl->aon.offset); 172 val |= 1 << ctrl->aon.iso_shift; 173 iproc_pll_write(pll, pll->pwr_base, ctrl->aon.offset, val); 174 175 /* power down the core */ 176 val &= ~(bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift); 177 iproc_pll_write(pll, pll->pwr_base, ctrl->aon.offset, val); 178 } 179 } 180 181 static int __pll_enable(struct iproc_pll *pll) 182 { 183 const struct iproc_pll_ctrl *ctrl = pll->ctrl; 184 u32 val; 185 186 if (ctrl->flags & IPROC_CLK_EMBED_PWRCTRL) { 187 val = readl(pll->pll_base + ctrl->aon.offset); 188 val &= ~(bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift); 189 iproc_pll_write(pll, pll->pll_base, ctrl->aon.offset, val); 190 } 191 192 if (pll->pwr_base) { 193 /* power up the PLL and make sure it's not latched */ 194 val = readl(pll->pwr_base + ctrl->aon.offset); 195 val |= bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift; 196 val &= ~(1 << ctrl->aon.iso_shift); 197 iproc_pll_write(pll, pll->pwr_base, ctrl->aon.offset, val); 198 } 199 200 /* certain PLLs also need to be ungated from the ASIU top level */ 201 if (ctrl->flags & IPROC_CLK_PLL_ASIU) { 202 val = readl(pll->asiu_base + ctrl->asiu.offset); 203 val |= (1 << ctrl->asiu.en_shift); 204 iproc_pll_write(pll, pll->asiu_base, ctrl->asiu.offset, val); 205 } 206 207 return 0; 208 } 209 210 static void __pll_put_in_reset(struct iproc_pll *pll) 211 { 212 u32 val; 213 const struct iproc_pll_ctrl *ctrl = pll->ctrl; 214 const struct iproc_pll_reset_ctrl *reset = &ctrl->reset; 215 216 val = readl(pll->pll_base + reset->offset); 217 val &= ~(1 << reset->reset_shift | 1 << reset->p_reset_shift); 218 iproc_pll_write(pll, pll->pll_base, reset->offset, val); 219 } 220 221 static void __pll_bring_out_reset(struct iproc_pll *pll, unsigned int kp, 222 unsigned int ka, unsigned int ki) 223 { 224 u32 val; 225 const struct iproc_pll_ctrl *ctrl = pll->ctrl; 226 const struct iproc_pll_reset_ctrl *reset = &ctrl->reset; 227 228 val = readl(pll->pll_base + reset->offset); 229 val &= ~(bit_mask(reset->ki_width) << reset->ki_shift | 230 bit_mask(reset->kp_width) << reset->kp_shift | 231 bit_mask(reset->ka_width) << reset->ka_shift); 232 val |= ki << reset->ki_shift | kp << reset->kp_shift | 233 ka << reset->ka_shift; 234 val |= 1 << reset->reset_shift | 1 << reset->p_reset_shift; 235 iproc_pll_write(pll, pll->pll_base, reset->offset, val); 236 } 237 238 static int pll_set_rate(struct iproc_clk *clk, unsigned int rate_index, 239 unsigned long parent_rate) 240 { 241 struct iproc_pll *pll = clk->pll; 242 const struct iproc_pll_vco_param *vco = &pll->vco_param[rate_index]; 243 const struct iproc_pll_ctrl *ctrl = pll->ctrl; 244 int ka = 0, ki, kp, ret; 245 unsigned long rate = vco->rate; 246 u32 val; 247 enum kp_band kp_index; 248 unsigned long ref_freq; 249 250 /* 251 * reference frequency = parent frequency / PDIV 252 * If PDIV = 0, then it becomes a multiplier (x2) 253 */ 254 if (vco->pdiv == 0) 255 ref_freq = parent_rate * 2; 256 else 257 ref_freq = parent_rate / vco->pdiv; 258 259 /* determine Ki and Kp index based on target VCO frequency */ 260 if (rate >= VCO_LOW && rate < VCO_HIGH) { 261 ki = 4; 262 kp_index = KP_BAND_MID; 263 } else if (rate >= VCO_HIGH && rate && rate < VCO_HIGH_HIGH) { 264 ki = 3; 265 kp_index = KP_BAND_HIGH; 266 } else if (rate >= VCO_HIGH_HIGH && rate < VCO_MAX) { 267 ki = 3; 268 kp_index = KP_BAND_HIGH_HIGH; 269 } else { 270 pr_err("%s: pll: %s has invalid rate: %lu\n", __func__, 271 clk->name, rate); 272 return -EINVAL; 273 } 274 275 kp = get_kp(ref_freq, kp_index); 276 if (kp < 0) { 277 pr_err("%s: pll: %s has invalid kp\n", __func__, clk->name); 278 return kp; 279 } 280 281 ret = __pll_enable(pll); 282 if (ret) { 283 pr_err("%s: pll: %s fails to enable\n", __func__, clk->name); 284 return ret; 285 } 286 287 /* put PLL in reset */ 288 __pll_put_in_reset(pll); 289 290 iproc_pll_write(pll, pll->pll_base, ctrl->vco_ctrl.u_offset, 0); 291 292 val = readl(pll->pll_base + ctrl->vco_ctrl.l_offset); 293 294 if (rate >= VCO_LOW && rate < VCO_MID) 295 val |= (1 << PLL_VCO_LOW_SHIFT); 296 297 if (rate < VCO_HIGH) 298 val &= ~(1 << PLL_VCO_HIGH_SHIFT); 299 else 300 val |= (1 << PLL_VCO_HIGH_SHIFT); 301 302 iproc_pll_write(pll, pll->pll_base, ctrl->vco_ctrl.l_offset, val); 303 304 /* program integer part of NDIV */ 305 val = readl(pll->pll_base + ctrl->ndiv_int.offset); 306 val &= ~(bit_mask(ctrl->ndiv_int.width) << ctrl->ndiv_int.shift); 307 val |= vco->ndiv_int << ctrl->ndiv_int.shift; 308 iproc_pll_write(pll, pll->pll_base, ctrl->ndiv_int.offset, val); 309 310 /* program fractional part of NDIV */ 311 if (ctrl->flags & IPROC_CLK_PLL_HAS_NDIV_FRAC) { 312 val = readl(pll->pll_base + ctrl->ndiv_frac.offset); 313 val &= ~(bit_mask(ctrl->ndiv_frac.width) << 314 ctrl->ndiv_frac.shift); 315 val |= vco->ndiv_frac << ctrl->ndiv_frac.shift; 316 iproc_pll_write(pll, pll->pll_base, ctrl->ndiv_frac.offset, 317 val); 318 } 319 320 /* program PDIV */ 321 val = readl(pll->pll_base + ctrl->pdiv.offset); 322 val &= ~(bit_mask(ctrl->pdiv.width) << ctrl->pdiv.shift); 323 val |= vco->pdiv << ctrl->pdiv.shift; 324 iproc_pll_write(pll, pll->pll_base, ctrl->pdiv.offset, val); 325 326 __pll_bring_out_reset(pll, kp, ka, ki); 327 328 ret = pll_wait_for_lock(pll); 329 if (ret < 0) { 330 pr_err("%s: pll: %s failed to lock\n", __func__, clk->name); 331 return ret; 332 } 333 334 return 0; 335 } 336 337 static int iproc_pll_enable(struct clk_hw *hw) 338 { 339 struct iproc_clk *clk = to_iproc_clk(hw); 340 struct iproc_pll *pll = clk->pll; 341 342 return __pll_enable(pll); 343 } 344 345 static void iproc_pll_disable(struct clk_hw *hw) 346 { 347 struct iproc_clk *clk = to_iproc_clk(hw); 348 struct iproc_pll *pll = clk->pll; 349 const struct iproc_pll_ctrl *ctrl = pll->ctrl; 350 351 if (ctrl->flags & IPROC_CLK_AON) 352 return; 353 354 __pll_disable(pll); 355 } 356 357 static unsigned long iproc_pll_recalc_rate(struct clk_hw *hw, 358 unsigned long parent_rate) 359 { 360 struct iproc_clk *clk = to_iproc_clk(hw); 361 struct iproc_pll *pll = clk->pll; 362 const struct iproc_pll_ctrl *ctrl = pll->ctrl; 363 u32 val; 364 u64 ndiv; 365 unsigned int ndiv_int, ndiv_frac, pdiv; 366 367 if (parent_rate == 0) 368 return 0; 369 370 /* PLL needs to be locked */ 371 val = readl(pll->pll_base + ctrl->status.offset); 372 if ((val & (1 << ctrl->status.shift)) == 0) { 373 clk->rate = 0; 374 return 0; 375 } 376 377 /* 378 * PLL output frequency = 379 * 380 * ((ndiv_int + ndiv_frac / 2^20) * (parent clock rate / pdiv) 381 */ 382 val = readl(pll->pll_base + ctrl->ndiv_int.offset); 383 ndiv_int = (val >> ctrl->ndiv_int.shift) & 384 bit_mask(ctrl->ndiv_int.width); 385 ndiv = (u64)ndiv_int << ctrl->ndiv_int.shift; 386 387 if (ctrl->flags & IPROC_CLK_PLL_HAS_NDIV_FRAC) { 388 val = readl(pll->pll_base + ctrl->ndiv_frac.offset); 389 ndiv_frac = (val >> ctrl->ndiv_frac.shift) & 390 bit_mask(ctrl->ndiv_frac.width); 391 392 if (ndiv_frac != 0) 393 ndiv = ((u64)ndiv_int << ctrl->ndiv_int.shift) | 394 ndiv_frac; 395 } 396 397 val = readl(pll->pll_base + ctrl->pdiv.offset); 398 pdiv = (val >> ctrl->pdiv.shift) & bit_mask(ctrl->pdiv.width); 399 400 clk->rate = (ndiv * parent_rate) >> ctrl->ndiv_int.shift; 401 402 if (pdiv == 0) 403 clk->rate *= 2; 404 else 405 clk->rate /= pdiv; 406 407 return clk->rate; 408 } 409 410 static long iproc_pll_round_rate(struct clk_hw *hw, unsigned long rate, 411 unsigned long *parent_rate) 412 { 413 unsigned i; 414 struct iproc_clk *clk = to_iproc_clk(hw); 415 struct iproc_pll *pll = clk->pll; 416 417 if (rate == 0 || *parent_rate == 0 || !pll->vco_param) 418 return -EINVAL; 419 420 for (i = 0; i < pll->num_vco_entries; i++) { 421 if (rate <= pll->vco_param[i].rate) 422 break; 423 } 424 425 if (i == pll->num_vco_entries) 426 i--; 427 428 return pll->vco_param[i].rate; 429 } 430 431 static int iproc_pll_set_rate(struct clk_hw *hw, unsigned long rate, 432 unsigned long parent_rate) 433 { 434 struct iproc_clk *clk = to_iproc_clk(hw); 435 struct iproc_pll *pll = clk->pll; 436 int rate_index, ret; 437 438 rate_index = pll_get_rate_index(pll, rate); 439 if (rate_index < 0) 440 return rate_index; 441 442 ret = pll_set_rate(clk, rate_index, parent_rate); 443 return ret; 444 } 445 446 static const struct clk_ops iproc_pll_ops = { 447 .enable = iproc_pll_enable, 448 .disable = iproc_pll_disable, 449 .recalc_rate = iproc_pll_recalc_rate, 450 .round_rate = iproc_pll_round_rate, 451 .set_rate = iproc_pll_set_rate, 452 }; 453 454 static int iproc_clk_enable(struct clk_hw *hw) 455 { 456 struct iproc_clk *clk = to_iproc_clk(hw); 457 const struct iproc_clk_ctrl *ctrl = clk->ctrl; 458 struct iproc_pll *pll = clk->pll; 459 u32 val; 460 461 /* channel enable is active low */ 462 val = readl(pll->pll_base + ctrl->enable.offset); 463 val &= ~(1 << ctrl->enable.enable_shift); 464 iproc_pll_write(pll, pll->pll_base, ctrl->enable.offset, val); 465 466 /* also make sure channel is not held */ 467 val = readl(pll->pll_base + ctrl->enable.offset); 468 val &= ~(1 << ctrl->enable.hold_shift); 469 iproc_pll_write(pll, pll->pll_base, ctrl->enable.offset, val); 470 471 return 0; 472 } 473 474 static void iproc_clk_disable(struct clk_hw *hw) 475 { 476 struct iproc_clk *clk = to_iproc_clk(hw); 477 const struct iproc_clk_ctrl *ctrl = clk->ctrl; 478 struct iproc_pll *pll = clk->pll; 479 u32 val; 480 481 if (ctrl->flags & IPROC_CLK_AON) 482 return; 483 484 val = readl(pll->pll_base + ctrl->enable.offset); 485 val |= 1 << ctrl->enable.enable_shift; 486 iproc_pll_write(pll, pll->pll_base, ctrl->enable.offset, val); 487 } 488 489 static unsigned long iproc_clk_recalc_rate(struct clk_hw *hw, 490 unsigned long parent_rate) 491 { 492 struct iproc_clk *clk = to_iproc_clk(hw); 493 const struct iproc_clk_ctrl *ctrl = clk->ctrl; 494 struct iproc_pll *pll = clk->pll; 495 u32 val; 496 unsigned int mdiv; 497 498 if (parent_rate == 0) 499 return 0; 500 501 val = readl(pll->pll_base + ctrl->mdiv.offset); 502 mdiv = (val >> ctrl->mdiv.shift) & bit_mask(ctrl->mdiv.width); 503 if (mdiv == 0) 504 mdiv = 256; 505 506 clk->rate = parent_rate / mdiv; 507 508 return clk->rate; 509 } 510 511 static long iproc_clk_round_rate(struct clk_hw *hw, unsigned long rate, 512 unsigned long *parent_rate) 513 { 514 unsigned int div; 515 516 if (rate == 0 || *parent_rate == 0) 517 return -EINVAL; 518 519 if (rate == *parent_rate) 520 return *parent_rate; 521 522 div = DIV_ROUND_UP(*parent_rate, rate); 523 if (div < 2) 524 return *parent_rate; 525 526 if (div > 256) 527 div = 256; 528 529 return *parent_rate / div; 530 } 531 532 static int iproc_clk_set_rate(struct clk_hw *hw, unsigned long rate, 533 unsigned long parent_rate) 534 { 535 struct iproc_clk *clk = to_iproc_clk(hw); 536 const struct iproc_clk_ctrl *ctrl = clk->ctrl; 537 struct iproc_pll *pll = clk->pll; 538 u32 val; 539 unsigned int div; 540 541 if (rate == 0 || parent_rate == 0) 542 return -EINVAL; 543 544 div = DIV_ROUND_UP(parent_rate, rate); 545 if (div > 256) 546 return -EINVAL; 547 548 val = readl(pll->pll_base + ctrl->mdiv.offset); 549 if (div == 256) { 550 val &= ~(bit_mask(ctrl->mdiv.width) << ctrl->mdiv.shift); 551 } else { 552 val &= ~(bit_mask(ctrl->mdiv.width) << ctrl->mdiv.shift); 553 val |= div << ctrl->mdiv.shift; 554 } 555 iproc_pll_write(pll, pll->pll_base, ctrl->mdiv.offset, val); 556 clk->rate = parent_rate / div; 557 558 return 0; 559 } 560 561 static const struct clk_ops iproc_clk_ops = { 562 .enable = iproc_clk_enable, 563 .disable = iproc_clk_disable, 564 .recalc_rate = iproc_clk_recalc_rate, 565 .round_rate = iproc_clk_round_rate, 566 .set_rate = iproc_clk_set_rate, 567 }; 568 569 /** 570 * Some PLLs require the PLL SW override bit to be set before changes can be 571 * applied to the PLL 572 */ 573 static void iproc_pll_sw_cfg(struct iproc_pll *pll) 574 { 575 const struct iproc_pll_ctrl *ctrl = pll->ctrl; 576 577 if (ctrl->flags & IPROC_CLK_PLL_NEEDS_SW_CFG) { 578 u32 val; 579 580 val = readl(pll->pll_base + ctrl->sw_ctrl.offset); 581 val |= BIT(ctrl->sw_ctrl.shift); 582 iproc_pll_write(pll, pll->pll_base, ctrl->sw_ctrl.offset, val); 583 } 584 } 585 586 void __init iproc_pll_clk_setup(struct device_node *node, 587 const struct iproc_pll_ctrl *pll_ctrl, 588 const struct iproc_pll_vco_param *vco, 589 unsigned int num_vco_entries, 590 const struct iproc_clk_ctrl *clk_ctrl, 591 unsigned int num_clks) 592 { 593 int i, ret; 594 struct clk *clk; 595 struct iproc_pll *pll; 596 struct iproc_clk *iclk; 597 struct clk_init_data init; 598 const char *parent_name; 599 600 if (WARN_ON(!pll_ctrl) || WARN_ON(!clk_ctrl)) 601 return; 602 603 pll = kzalloc(sizeof(*pll), GFP_KERNEL); 604 if (WARN_ON(!pll)) 605 return; 606 607 pll->clk_data.clk_num = num_clks; 608 pll->clk_data.clks = kcalloc(num_clks, sizeof(*pll->clk_data.clks), 609 GFP_KERNEL); 610 if (WARN_ON(!pll->clk_data.clks)) 611 goto err_clk_data; 612 613 pll->clks = kcalloc(num_clks, sizeof(*pll->clks), GFP_KERNEL); 614 if (WARN_ON(!pll->clks)) 615 goto err_clks; 616 617 pll->pll_base = of_iomap(node, 0); 618 if (WARN_ON(!pll->pll_base)) 619 goto err_pll_iomap; 620 621 /* Some SoCs do not require the pwr_base, thus failing is not fatal */ 622 pll->pwr_base = of_iomap(node, 1); 623 624 /* some PLLs require gating control at the top ASIU level */ 625 if (pll_ctrl->flags & IPROC_CLK_PLL_ASIU) { 626 pll->asiu_base = of_iomap(node, 2); 627 if (WARN_ON(!pll->asiu_base)) 628 goto err_asiu_iomap; 629 } 630 631 /* initialize and register the PLL itself */ 632 pll->ctrl = pll_ctrl; 633 634 iclk = &pll->clks[0]; 635 iclk->pll = pll; 636 iclk->name = node->name; 637 638 init.name = node->name; 639 init.ops = &iproc_pll_ops; 640 init.flags = 0; 641 parent_name = of_clk_get_parent_name(node, 0); 642 init.parent_names = (parent_name ? &parent_name : NULL); 643 init.num_parents = (parent_name ? 1 : 0); 644 iclk->hw.init = &init; 645 646 if (vco) { 647 pll->num_vco_entries = num_vco_entries; 648 pll->vco_param = vco; 649 } 650 651 iproc_pll_sw_cfg(pll); 652 653 clk = clk_register(NULL, &iclk->hw); 654 if (WARN_ON(IS_ERR(clk))) 655 goto err_pll_register; 656 657 pll->clk_data.clks[0] = clk; 658 659 /* now initialize and register all leaf clocks */ 660 for (i = 1; i < num_clks; i++) { 661 const char *clk_name; 662 663 memset(&init, 0, sizeof(init)); 664 parent_name = node->name; 665 666 ret = of_property_read_string_index(node, "clock-output-names", 667 i, &clk_name); 668 if (WARN_ON(ret)) 669 goto err_clk_register; 670 671 iclk = &pll->clks[i]; 672 iclk->name = clk_name; 673 iclk->pll = pll; 674 iclk->ctrl = &clk_ctrl[i]; 675 676 init.name = clk_name; 677 init.ops = &iproc_clk_ops; 678 init.flags = 0; 679 init.parent_names = (parent_name ? &parent_name : NULL); 680 init.num_parents = (parent_name ? 1 : 0); 681 iclk->hw.init = &init; 682 683 clk = clk_register(NULL, &iclk->hw); 684 if (WARN_ON(IS_ERR(clk))) 685 goto err_clk_register; 686 687 pll->clk_data.clks[i] = clk; 688 } 689 690 ret = of_clk_add_provider(node, of_clk_src_onecell_get, &pll->clk_data); 691 if (WARN_ON(ret)) 692 goto err_clk_register; 693 694 return; 695 696 err_clk_register: 697 for (i = 0; i < num_clks; i++) 698 clk_unregister(pll->clk_data.clks[i]); 699 700 err_pll_register: 701 if (pll->asiu_base) 702 iounmap(pll->asiu_base); 703 704 err_asiu_iomap: 705 if (pll->pwr_base) 706 iounmap(pll->pwr_base); 707 708 iounmap(pll->pll_base); 709 710 err_pll_iomap: 711 kfree(pll->clks); 712 713 err_clks: 714 kfree(pll->clk_data.clks); 715 716 err_clk_data: 717 kfree(pll); 718 } 719