1 /* 2 * Copyright (C) 2014 Broadcom Corporation 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License as 6 * published by the Free Software Foundation version 2. 7 * 8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 9 * kind, whether express or implied; without even the implied warranty 10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14 #include <linux/kernel.h> 15 #include <linux/err.h> 16 #include <linux/clk-provider.h> 17 #include <linux/io.h> 18 #include <linux/of.h> 19 #include <linux/clkdev.h> 20 #include <linux/of_address.h> 21 #include <linux/delay.h> 22 23 #include "clk-iproc.h" 24 25 #define PLL_VCO_HIGH_SHIFT 19 26 #define PLL_VCO_LOW_SHIFT 30 27 28 /* number of delay loops waiting for PLL to lock */ 29 #define LOCK_DELAY 100 30 31 /* number of VCO frequency bands */ 32 #define NUM_FREQ_BANDS 8 33 34 #define NUM_KP_BANDS 3 35 enum kp_band { 36 KP_BAND_MID = 0, 37 KP_BAND_HIGH, 38 KP_BAND_HIGH_HIGH 39 }; 40 41 static const unsigned int kp_table[NUM_KP_BANDS][NUM_FREQ_BANDS] = { 42 { 5, 6, 6, 7, 7, 8, 9, 10 }, 43 { 4, 4, 5, 5, 6, 7, 8, 9 }, 44 { 4, 5, 5, 6, 7, 8, 9, 10 }, 45 }; 46 47 static const unsigned long ref_freq_table[NUM_FREQ_BANDS][2] = { 48 { 10000000, 12500000 }, 49 { 12500000, 15000000 }, 50 { 15000000, 20000000 }, 51 { 20000000, 25000000 }, 52 { 25000000, 50000000 }, 53 { 50000000, 75000000 }, 54 { 75000000, 100000000 }, 55 { 100000000, 125000000 }, 56 }; 57 58 enum vco_freq_range { 59 VCO_LOW = 700000000U, 60 VCO_MID = 1200000000U, 61 VCO_HIGH = 2200000000U, 62 VCO_HIGH_HIGH = 3100000000U, 63 VCO_MAX = 4000000000U, 64 }; 65 66 struct iproc_pll; 67 68 struct iproc_clk { 69 struct clk_hw hw; 70 const char *name; 71 struct iproc_pll *pll; 72 unsigned long rate; 73 const struct iproc_clk_ctrl *ctrl; 74 }; 75 76 struct iproc_pll { 77 void __iomem *pll_base; 78 void __iomem *pwr_base; 79 void __iomem *asiu_base; 80 81 const struct iproc_pll_ctrl *ctrl; 82 const struct iproc_pll_vco_param *vco_param; 83 unsigned int num_vco_entries; 84 85 struct clk_onecell_data clk_data; 86 struct iproc_clk *clks; 87 }; 88 89 #define to_iproc_clk(hw) container_of(hw, struct iproc_clk, hw) 90 91 /* 92 * Based on the target frequency, find a match from the VCO frequency parameter 93 * table and return its index 94 */ 95 static int pll_get_rate_index(struct iproc_pll *pll, unsigned int target_rate) 96 { 97 int i; 98 99 for (i = 0; i < pll->num_vco_entries; i++) 100 if (target_rate == pll->vco_param[i].rate) 101 break; 102 103 if (i >= pll->num_vco_entries) 104 return -EINVAL; 105 106 return i; 107 } 108 109 static int get_kp(unsigned long ref_freq, enum kp_band kp_index) 110 { 111 int i; 112 113 if (ref_freq < ref_freq_table[0][0]) 114 return -EINVAL; 115 116 for (i = 0; i < NUM_FREQ_BANDS; i++) { 117 if (ref_freq >= ref_freq_table[i][0] && 118 ref_freq < ref_freq_table[i][1]) 119 return kp_table[kp_index][i]; 120 } 121 return -EINVAL; 122 } 123 124 static int pll_wait_for_lock(struct iproc_pll *pll) 125 { 126 int i; 127 const struct iproc_pll_ctrl *ctrl = pll->ctrl; 128 129 for (i = 0; i < LOCK_DELAY; i++) { 130 u32 val = readl(pll->pll_base + ctrl->status.offset); 131 132 if (val & (1 << ctrl->status.shift)) 133 return 0; 134 udelay(10); 135 } 136 137 return -EIO; 138 } 139 140 static void __pll_disable(struct iproc_pll *pll) 141 { 142 const struct iproc_pll_ctrl *ctrl = pll->ctrl; 143 u32 val; 144 145 if (ctrl->flags & IPROC_CLK_PLL_ASIU) { 146 val = readl(pll->asiu_base + ctrl->asiu.offset); 147 val &= ~(1 << ctrl->asiu.en_shift); 148 writel(val, pll->asiu_base + ctrl->asiu.offset); 149 } 150 151 /* latch input value so core power can be shut down */ 152 val = readl(pll->pwr_base + ctrl->aon.offset); 153 val |= (1 << ctrl->aon.iso_shift); 154 writel(val, pll->pwr_base + ctrl->aon.offset); 155 156 /* power down the core */ 157 val &= ~(bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift); 158 writel(val, pll->pwr_base + ctrl->aon.offset); 159 } 160 161 static int __pll_enable(struct iproc_pll *pll) 162 { 163 const struct iproc_pll_ctrl *ctrl = pll->ctrl; 164 u32 val; 165 166 /* power up the PLL and make sure it's not latched */ 167 val = readl(pll->pwr_base + ctrl->aon.offset); 168 val |= bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift; 169 val &= ~(1 << ctrl->aon.iso_shift); 170 writel(val, pll->pwr_base + ctrl->aon.offset); 171 172 /* certain PLLs also need to be ungated from the ASIU top level */ 173 if (ctrl->flags & IPROC_CLK_PLL_ASIU) { 174 val = readl(pll->asiu_base + ctrl->asiu.offset); 175 val |= (1 << ctrl->asiu.en_shift); 176 writel(val, pll->asiu_base + ctrl->asiu.offset); 177 } 178 179 return 0; 180 } 181 182 static void __pll_put_in_reset(struct iproc_pll *pll) 183 { 184 u32 val; 185 const struct iproc_pll_ctrl *ctrl = pll->ctrl; 186 const struct iproc_pll_reset_ctrl *reset = &ctrl->reset; 187 188 val = readl(pll->pll_base + reset->offset); 189 val &= ~(1 << reset->reset_shift | 1 << reset->p_reset_shift); 190 writel(val, pll->pll_base + reset->offset); 191 if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK)) 192 readl(pll->pll_base + reset->offset); 193 } 194 195 static void __pll_bring_out_reset(struct iproc_pll *pll, unsigned int kp, 196 unsigned int ka, unsigned int ki) 197 { 198 u32 val; 199 const struct iproc_pll_ctrl *ctrl = pll->ctrl; 200 const struct iproc_pll_reset_ctrl *reset = &ctrl->reset; 201 202 val = readl(pll->pll_base + reset->offset); 203 val &= ~(bit_mask(reset->ki_width) << reset->ki_shift | 204 bit_mask(reset->kp_width) << reset->kp_shift | 205 bit_mask(reset->ka_width) << reset->ka_shift); 206 val |= ki << reset->ki_shift | kp << reset->kp_shift | 207 ka << reset->ka_shift; 208 val |= 1 << reset->reset_shift | 1 << reset->p_reset_shift; 209 writel(val, pll->pll_base + reset->offset); 210 if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK)) 211 readl(pll->pll_base + reset->offset); 212 } 213 214 static int pll_set_rate(struct iproc_clk *clk, unsigned int rate_index, 215 unsigned long parent_rate) 216 { 217 struct iproc_pll *pll = clk->pll; 218 const struct iproc_pll_vco_param *vco = &pll->vco_param[rate_index]; 219 const struct iproc_pll_ctrl *ctrl = pll->ctrl; 220 int ka = 0, ki, kp, ret; 221 unsigned long rate = vco->rate; 222 u32 val; 223 enum kp_band kp_index; 224 unsigned long ref_freq; 225 226 /* 227 * reference frequency = parent frequency / PDIV 228 * If PDIV = 0, then it becomes a multiplier (x2) 229 */ 230 if (vco->pdiv == 0) 231 ref_freq = parent_rate * 2; 232 else 233 ref_freq = parent_rate / vco->pdiv; 234 235 /* determine Ki and Kp index based on target VCO frequency */ 236 if (rate >= VCO_LOW && rate < VCO_HIGH) { 237 ki = 4; 238 kp_index = KP_BAND_MID; 239 } else if (rate >= VCO_HIGH && rate && rate < VCO_HIGH_HIGH) { 240 ki = 3; 241 kp_index = KP_BAND_HIGH; 242 } else if (rate >= VCO_HIGH_HIGH && rate < VCO_MAX) { 243 ki = 3; 244 kp_index = KP_BAND_HIGH_HIGH; 245 } else { 246 pr_err("%s: pll: %s has invalid rate: %lu\n", __func__, 247 clk->name, rate); 248 return -EINVAL; 249 } 250 251 kp = get_kp(ref_freq, kp_index); 252 if (kp < 0) { 253 pr_err("%s: pll: %s has invalid kp\n", __func__, clk->name); 254 return kp; 255 } 256 257 ret = __pll_enable(pll); 258 if (ret) { 259 pr_err("%s: pll: %s fails to enable\n", __func__, clk->name); 260 return ret; 261 } 262 263 /* put PLL in reset */ 264 __pll_put_in_reset(pll); 265 266 writel(0, pll->pll_base + ctrl->vco_ctrl.u_offset); 267 if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK)) 268 readl(pll->pll_base + ctrl->vco_ctrl.u_offset); 269 val = readl(pll->pll_base + ctrl->vco_ctrl.l_offset); 270 271 if (rate >= VCO_LOW && rate < VCO_MID) 272 val |= (1 << PLL_VCO_LOW_SHIFT); 273 274 if (rate < VCO_HIGH) 275 val &= ~(1 << PLL_VCO_HIGH_SHIFT); 276 else 277 val |= (1 << PLL_VCO_HIGH_SHIFT); 278 279 writel(val, pll->pll_base + ctrl->vco_ctrl.l_offset); 280 if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK)) 281 readl(pll->pll_base + ctrl->vco_ctrl.l_offset); 282 283 /* program integer part of NDIV */ 284 val = readl(pll->pll_base + ctrl->ndiv_int.offset); 285 val &= ~(bit_mask(ctrl->ndiv_int.width) << ctrl->ndiv_int.shift); 286 val |= vco->ndiv_int << ctrl->ndiv_int.shift; 287 writel(val, pll->pll_base + ctrl->ndiv_int.offset); 288 if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK)) 289 readl(pll->pll_base + ctrl->ndiv_int.offset); 290 291 /* program fractional part of NDIV */ 292 if (ctrl->flags & IPROC_CLK_PLL_HAS_NDIV_FRAC) { 293 val = readl(pll->pll_base + ctrl->ndiv_frac.offset); 294 val &= ~(bit_mask(ctrl->ndiv_frac.width) << 295 ctrl->ndiv_frac.shift); 296 val |= vco->ndiv_frac << ctrl->ndiv_frac.shift; 297 writel(val, pll->pll_base + ctrl->ndiv_frac.offset); 298 if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK)) 299 readl(pll->pll_base + ctrl->ndiv_frac.offset); 300 } 301 302 /* program PDIV */ 303 val = readl(pll->pll_base + ctrl->pdiv.offset); 304 val &= ~(bit_mask(ctrl->pdiv.width) << ctrl->pdiv.shift); 305 val |= vco->pdiv << ctrl->pdiv.shift; 306 writel(val, pll->pll_base + ctrl->pdiv.offset); 307 if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK)) 308 readl(pll->pll_base + ctrl->pdiv.offset); 309 310 __pll_bring_out_reset(pll, kp, ka, ki); 311 312 ret = pll_wait_for_lock(pll); 313 if (ret < 0) { 314 pr_err("%s: pll: %s failed to lock\n", __func__, clk->name); 315 return ret; 316 } 317 318 return 0; 319 } 320 321 static int iproc_pll_enable(struct clk_hw *hw) 322 { 323 struct iproc_clk *clk = to_iproc_clk(hw); 324 struct iproc_pll *pll = clk->pll; 325 326 return __pll_enable(pll); 327 } 328 329 static void iproc_pll_disable(struct clk_hw *hw) 330 { 331 struct iproc_clk *clk = to_iproc_clk(hw); 332 struct iproc_pll *pll = clk->pll; 333 const struct iproc_pll_ctrl *ctrl = pll->ctrl; 334 335 if (ctrl->flags & IPROC_CLK_AON) 336 return; 337 338 __pll_disable(pll); 339 } 340 341 static unsigned long iproc_pll_recalc_rate(struct clk_hw *hw, 342 unsigned long parent_rate) 343 { 344 struct iproc_clk *clk = to_iproc_clk(hw); 345 struct iproc_pll *pll = clk->pll; 346 const struct iproc_pll_ctrl *ctrl = pll->ctrl; 347 u32 val; 348 u64 ndiv, ndiv_int, ndiv_frac; 349 unsigned int pdiv; 350 351 if (parent_rate == 0) 352 return 0; 353 354 /* PLL needs to be locked */ 355 val = readl(pll->pll_base + ctrl->status.offset); 356 if ((val & (1 << ctrl->status.shift)) == 0) { 357 clk->rate = 0; 358 return 0; 359 } 360 361 /* 362 * PLL output frequency = 363 * 364 * ((ndiv_int + ndiv_frac / 2^20) * (parent clock rate / pdiv) 365 */ 366 val = readl(pll->pll_base + ctrl->ndiv_int.offset); 367 ndiv_int = (val >> ctrl->ndiv_int.shift) & 368 bit_mask(ctrl->ndiv_int.width); 369 ndiv = ndiv_int << 20; 370 371 if (ctrl->flags & IPROC_CLK_PLL_HAS_NDIV_FRAC) { 372 val = readl(pll->pll_base + ctrl->ndiv_frac.offset); 373 ndiv_frac = (val >> ctrl->ndiv_frac.shift) & 374 bit_mask(ctrl->ndiv_frac.width); 375 ndiv += ndiv_frac; 376 } 377 378 val = readl(pll->pll_base + ctrl->pdiv.offset); 379 pdiv = (val >> ctrl->pdiv.shift) & bit_mask(ctrl->pdiv.width); 380 381 clk->rate = (ndiv * parent_rate) >> 20; 382 383 if (pdiv == 0) 384 clk->rate *= 2; 385 else 386 clk->rate /= pdiv; 387 388 return clk->rate; 389 } 390 391 static long iproc_pll_round_rate(struct clk_hw *hw, unsigned long rate, 392 unsigned long *parent_rate) 393 { 394 unsigned i; 395 struct iproc_clk *clk = to_iproc_clk(hw); 396 struct iproc_pll *pll = clk->pll; 397 398 if (rate == 0 || *parent_rate == 0 || !pll->vco_param) 399 return -EINVAL; 400 401 for (i = 0; i < pll->num_vco_entries; i++) { 402 if (rate <= pll->vco_param[i].rate) 403 break; 404 } 405 406 if (i == pll->num_vco_entries) 407 i--; 408 409 return pll->vco_param[i].rate; 410 } 411 412 static int iproc_pll_set_rate(struct clk_hw *hw, unsigned long rate, 413 unsigned long parent_rate) 414 { 415 struct iproc_clk *clk = to_iproc_clk(hw); 416 struct iproc_pll *pll = clk->pll; 417 int rate_index, ret; 418 419 rate_index = pll_get_rate_index(pll, rate); 420 if (rate_index < 0) 421 return rate_index; 422 423 ret = pll_set_rate(clk, rate_index, parent_rate); 424 return ret; 425 } 426 427 static const struct clk_ops iproc_pll_ops = { 428 .enable = iproc_pll_enable, 429 .disable = iproc_pll_disable, 430 .recalc_rate = iproc_pll_recalc_rate, 431 .round_rate = iproc_pll_round_rate, 432 .set_rate = iproc_pll_set_rate, 433 }; 434 435 static int iproc_clk_enable(struct clk_hw *hw) 436 { 437 struct iproc_clk *clk = to_iproc_clk(hw); 438 const struct iproc_clk_ctrl *ctrl = clk->ctrl; 439 struct iproc_pll *pll = clk->pll; 440 u32 val; 441 442 /* channel enable is active low */ 443 val = readl(pll->pll_base + ctrl->enable.offset); 444 val &= ~(1 << ctrl->enable.enable_shift); 445 writel(val, pll->pll_base + ctrl->enable.offset); 446 447 /* also make sure channel is not held */ 448 val = readl(pll->pll_base + ctrl->enable.offset); 449 val &= ~(1 << ctrl->enable.hold_shift); 450 writel(val, pll->pll_base + ctrl->enable.offset); 451 if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK)) 452 readl(pll->pll_base + ctrl->enable.offset); 453 454 return 0; 455 } 456 457 static void iproc_clk_disable(struct clk_hw *hw) 458 { 459 struct iproc_clk *clk = to_iproc_clk(hw); 460 const struct iproc_clk_ctrl *ctrl = clk->ctrl; 461 struct iproc_pll *pll = clk->pll; 462 u32 val; 463 464 if (ctrl->flags & IPROC_CLK_AON) 465 return; 466 467 val = readl(pll->pll_base + ctrl->enable.offset); 468 val |= 1 << ctrl->enable.enable_shift; 469 writel(val, pll->pll_base + ctrl->enable.offset); 470 if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK)) 471 readl(pll->pll_base + ctrl->enable.offset); 472 } 473 474 static unsigned long iproc_clk_recalc_rate(struct clk_hw *hw, 475 unsigned long parent_rate) 476 { 477 struct iproc_clk *clk = to_iproc_clk(hw); 478 const struct iproc_clk_ctrl *ctrl = clk->ctrl; 479 struct iproc_pll *pll = clk->pll; 480 u32 val; 481 unsigned int mdiv; 482 483 if (parent_rate == 0) 484 return 0; 485 486 val = readl(pll->pll_base + ctrl->mdiv.offset); 487 mdiv = (val >> ctrl->mdiv.shift) & bit_mask(ctrl->mdiv.width); 488 if (mdiv == 0) 489 mdiv = 256; 490 491 clk->rate = parent_rate / mdiv; 492 493 return clk->rate; 494 } 495 496 static long iproc_clk_round_rate(struct clk_hw *hw, unsigned long rate, 497 unsigned long *parent_rate) 498 { 499 unsigned int div; 500 501 if (rate == 0 || *parent_rate == 0) 502 return -EINVAL; 503 504 if (rate == *parent_rate) 505 return *parent_rate; 506 507 div = DIV_ROUND_UP(*parent_rate, rate); 508 if (div < 2) 509 return *parent_rate; 510 511 if (div > 256) 512 div = 256; 513 514 return *parent_rate / div; 515 } 516 517 static int iproc_clk_set_rate(struct clk_hw *hw, unsigned long rate, 518 unsigned long parent_rate) 519 { 520 struct iproc_clk *clk = to_iproc_clk(hw); 521 const struct iproc_clk_ctrl *ctrl = clk->ctrl; 522 struct iproc_pll *pll = clk->pll; 523 u32 val; 524 unsigned int div; 525 526 if (rate == 0 || parent_rate == 0) 527 return -EINVAL; 528 529 div = DIV_ROUND_UP(parent_rate, rate); 530 if (div > 256) 531 return -EINVAL; 532 533 val = readl(pll->pll_base + ctrl->mdiv.offset); 534 if (div == 256) { 535 val &= ~(bit_mask(ctrl->mdiv.width) << ctrl->mdiv.shift); 536 } else { 537 val &= ~(bit_mask(ctrl->mdiv.width) << ctrl->mdiv.shift); 538 val |= div << ctrl->mdiv.shift; 539 } 540 writel(val, pll->pll_base + ctrl->mdiv.offset); 541 if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK)) 542 readl(pll->pll_base + ctrl->mdiv.offset); 543 clk->rate = parent_rate / div; 544 545 return 0; 546 } 547 548 static const struct clk_ops iproc_clk_ops = { 549 .enable = iproc_clk_enable, 550 .disable = iproc_clk_disable, 551 .recalc_rate = iproc_clk_recalc_rate, 552 .round_rate = iproc_clk_round_rate, 553 .set_rate = iproc_clk_set_rate, 554 }; 555 556 /** 557 * Some PLLs require the PLL SW override bit to be set before changes can be 558 * applied to the PLL 559 */ 560 static void iproc_pll_sw_cfg(struct iproc_pll *pll) 561 { 562 const struct iproc_pll_ctrl *ctrl = pll->ctrl; 563 564 if (ctrl->flags & IPROC_CLK_PLL_NEEDS_SW_CFG) { 565 u32 val; 566 567 val = readl(pll->pll_base + ctrl->sw_ctrl.offset); 568 val |= BIT(ctrl->sw_ctrl.shift); 569 writel(val, pll->pll_base + ctrl->sw_ctrl.offset); 570 if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK)) 571 readl(pll->pll_base + ctrl->sw_ctrl.offset); 572 } 573 } 574 575 void __init iproc_pll_clk_setup(struct device_node *node, 576 const struct iproc_pll_ctrl *pll_ctrl, 577 const struct iproc_pll_vco_param *vco, 578 unsigned int num_vco_entries, 579 const struct iproc_clk_ctrl *clk_ctrl, 580 unsigned int num_clks) 581 { 582 int i, ret; 583 struct clk *clk; 584 struct iproc_pll *pll; 585 struct iproc_clk *iclk; 586 struct clk_init_data init; 587 const char *parent_name; 588 589 if (WARN_ON(!pll_ctrl) || WARN_ON(!clk_ctrl)) 590 return; 591 592 pll = kzalloc(sizeof(*pll), GFP_KERNEL); 593 if (WARN_ON(!pll)) 594 return; 595 596 pll->clk_data.clk_num = num_clks; 597 pll->clk_data.clks = kcalloc(num_clks, sizeof(*pll->clk_data.clks), 598 GFP_KERNEL); 599 if (WARN_ON(!pll->clk_data.clks)) 600 goto err_clk_data; 601 602 pll->clks = kcalloc(num_clks, sizeof(*pll->clks), GFP_KERNEL); 603 if (WARN_ON(!pll->clks)) 604 goto err_clks; 605 606 pll->pll_base = of_iomap(node, 0); 607 if (WARN_ON(!pll->pll_base)) 608 goto err_pll_iomap; 609 610 pll->pwr_base = of_iomap(node, 1); 611 if (WARN_ON(!pll->pwr_base)) 612 goto err_pwr_iomap; 613 614 /* some PLLs require gating control at the top ASIU level */ 615 if (pll_ctrl->flags & IPROC_CLK_PLL_ASIU) { 616 pll->asiu_base = of_iomap(node, 2); 617 if (WARN_ON(!pll->asiu_base)) 618 goto err_asiu_iomap; 619 } 620 621 /* initialize and register the PLL itself */ 622 pll->ctrl = pll_ctrl; 623 624 iclk = &pll->clks[0]; 625 iclk->pll = pll; 626 iclk->name = node->name; 627 628 init.name = node->name; 629 init.ops = &iproc_pll_ops; 630 init.flags = 0; 631 parent_name = of_clk_get_parent_name(node, 0); 632 init.parent_names = (parent_name ? &parent_name : NULL); 633 init.num_parents = (parent_name ? 1 : 0); 634 iclk->hw.init = &init; 635 636 if (vco) { 637 pll->num_vco_entries = num_vco_entries; 638 pll->vco_param = vco; 639 } 640 641 iproc_pll_sw_cfg(pll); 642 643 clk = clk_register(NULL, &iclk->hw); 644 if (WARN_ON(IS_ERR(clk))) 645 goto err_pll_register; 646 647 pll->clk_data.clks[0] = clk; 648 649 /* now initialize and register all leaf clocks */ 650 for (i = 1; i < num_clks; i++) { 651 const char *clk_name; 652 653 memset(&init, 0, sizeof(init)); 654 parent_name = node->name; 655 656 ret = of_property_read_string_index(node, "clock-output-names", 657 i, &clk_name); 658 if (WARN_ON(ret)) 659 goto err_clk_register; 660 661 iclk = &pll->clks[i]; 662 iclk->name = clk_name; 663 iclk->pll = pll; 664 iclk->ctrl = &clk_ctrl[i]; 665 666 init.name = clk_name; 667 init.ops = &iproc_clk_ops; 668 init.flags = 0; 669 init.parent_names = (parent_name ? &parent_name : NULL); 670 init.num_parents = (parent_name ? 1 : 0); 671 iclk->hw.init = &init; 672 673 clk = clk_register(NULL, &iclk->hw); 674 if (WARN_ON(IS_ERR(clk))) 675 goto err_clk_register; 676 677 pll->clk_data.clks[i] = clk; 678 } 679 680 ret = of_clk_add_provider(node, of_clk_src_onecell_get, &pll->clk_data); 681 if (WARN_ON(ret)) 682 goto err_clk_register; 683 684 return; 685 686 err_clk_register: 687 for (i = 0; i < num_clks; i++) 688 clk_unregister(pll->clk_data.clks[i]); 689 690 err_pll_register: 691 if (pll->asiu_base) 692 iounmap(pll->asiu_base); 693 694 err_asiu_iomap: 695 iounmap(pll->pwr_base); 696 697 err_pwr_iomap: 698 iounmap(pll->pll_base); 699 700 err_pll_iomap: 701 kfree(pll->clks); 702 703 err_clks: 704 kfree(pll->clk_data.clks); 705 706 err_clk_data: 707 kfree(pll); 708 } 709