1b7d950b9SSerge Semin /* SPDX-License-Identifier: GPL-2.0-only */ 2b7d950b9SSerge Semin /* 3b7d950b9SSerge Semin * Copyright (C) 2020 BAIKAL ELECTRONICS, JSC 4b7d950b9SSerge Semin * 5b7d950b9SSerge Semin * Baikal-T1 CCU PLL interface driver 6b7d950b9SSerge Semin */ 7b7d950b9SSerge Semin #ifndef __CLK_BT1_CCU_PLL_H__ 8b7d950b9SSerge Semin #define __CLK_BT1_CCU_PLL_H__ 9b7d950b9SSerge Semin 10b7d950b9SSerge Semin #include <linux/clk-provider.h> 11b7d950b9SSerge Semin #include <linux/spinlock.h> 12b7d950b9SSerge Semin #include <linux/regmap.h> 13b7d950b9SSerge Semin #include <linux/bits.h> 14b7d950b9SSerge Semin #include <linux/of.h> 15b7d950b9SSerge Semin 16b7d950b9SSerge Semin /* 17*c4e05443SSerge Semin * CCU PLL private flags 18*c4e05443SSerge Semin * @CCU_PLL_BASIC: Basic PLL required by the kernel as early as possible. 19*c4e05443SSerge Semin */ 20*c4e05443SSerge Semin #define CCU_PLL_BASIC BIT(0) 21*c4e05443SSerge Semin 22*c4e05443SSerge Semin /* 23b7d950b9SSerge Semin * struct ccu_pll_init_data - CCU PLL initialization data 24b7d950b9SSerge Semin * @id: Clock private identifier. 25b7d950b9SSerge Semin * @name: Clocks name. 26b7d950b9SSerge Semin * @parent_name: Clocks parent name in a fw node. 27b7d950b9SSerge Semin * @base: PLL registers base address with respect to the sys_regs base. 28b7d950b9SSerge Semin * @sys_regs: Baikal-T1 System Controller registers map. 29b7d950b9SSerge Semin * @np: Pointer to the node describing the CCU PLLs. 30b7d950b9SSerge Semin * @flags: PLL clock flags. 31*c4e05443SSerge Semin * @features: PLL private features. 32b7d950b9SSerge Semin */ 33b7d950b9SSerge Semin struct ccu_pll_init_data { 34b7d950b9SSerge Semin unsigned int id; 35b7d950b9SSerge Semin const char *name; 36b7d950b9SSerge Semin const char *parent_name; 37b7d950b9SSerge Semin unsigned int base; 38b7d950b9SSerge Semin struct regmap *sys_regs; 39b7d950b9SSerge Semin struct device_node *np; 40b7d950b9SSerge Semin unsigned long flags; 41*c4e05443SSerge Semin unsigned long features; 42b7d950b9SSerge Semin }; 43b7d950b9SSerge Semin 44b7d950b9SSerge Semin /* 45b7d950b9SSerge Semin * struct ccu_pll - CCU PLL descriptor 46b7d950b9SSerge Semin * @hw: clk_hw of the PLL. 47b7d950b9SSerge Semin * @id: Clock private identifier. 48b7d950b9SSerge Semin * @reg_ctl: PLL control register base. 49b7d950b9SSerge Semin * @reg_ctl1: PLL control1 register base. 50b7d950b9SSerge Semin * @sys_regs: Baikal-T1 System Controller registers map. 51b7d950b9SSerge Semin * @lock: PLL state change spin-lock. 52b7d950b9SSerge Semin */ 53b7d950b9SSerge Semin struct ccu_pll { 54b7d950b9SSerge Semin struct clk_hw hw; 55b7d950b9SSerge Semin unsigned int id; 56b7d950b9SSerge Semin unsigned int reg_ctl; 57b7d950b9SSerge Semin unsigned int reg_ctl1; 58b7d950b9SSerge Semin struct regmap *sys_regs; 59b7d950b9SSerge Semin spinlock_t lock; 60b7d950b9SSerge Semin }; 61b7d950b9SSerge Semin #define to_ccu_pll(_hw) container_of(_hw, struct ccu_pll, hw) 62b7d950b9SSerge Semin ccu_pll_get_clk_hw(struct ccu_pll * pll)63b7d950b9SSerge Seminstatic inline struct clk_hw *ccu_pll_get_clk_hw(struct ccu_pll *pll) 64b7d950b9SSerge Semin { 65b7d950b9SSerge Semin return pll ? &pll->hw : NULL; 66b7d950b9SSerge Semin } 67b7d950b9SSerge Semin 68b7d950b9SSerge Semin struct ccu_pll *ccu_pll_hw_register(const struct ccu_pll_init_data *init); 69b7d950b9SSerge Semin 70b7d950b9SSerge Semin void ccu_pll_hw_unregister(struct ccu_pll *pll); 71b7d950b9SSerge Semin 72b7d950b9SSerge Semin #endif /* __CLK_BT1_CCU_PLL_H__ */ 73