xref: /openbmc/linux/drivers/clk/actions/owl-reset.c (revision 3eb66e91a25497065c5322b1268cbc3953642227)
1*09dbde01SManivannan Sadhasivam // SPDX-License-Identifier: GPL-2.0-or-later
2*09dbde01SManivannan Sadhasivam //
3*09dbde01SManivannan Sadhasivam // Actions Semi Owl SoCs Reset Management Unit driver
4*09dbde01SManivannan Sadhasivam //
5*09dbde01SManivannan Sadhasivam // Copyright (c) 2018 Linaro Ltd.
6*09dbde01SManivannan Sadhasivam // Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
7*09dbde01SManivannan Sadhasivam 
8*09dbde01SManivannan Sadhasivam #include <linux/delay.h>
9*09dbde01SManivannan Sadhasivam #include <linux/regmap.h>
10*09dbde01SManivannan Sadhasivam #include <linux/reset-controller.h>
11*09dbde01SManivannan Sadhasivam 
12*09dbde01SManivannan Sadhasivam #include "owl-reset.h"
13*09dbde01SManivannan Sadhasivam 
owl_reset_assert(struct reset_controller_dev * rcdev,unsigned long id)14*09dbde01SManivannan Sadhasivam static int owl_reset_assert(struct reset_controller_dev *rcdev,
15*09dbde01SManivannan Sadhasivam 			    unsigned long id)
16*09dbde01SManivannan Sadhasivam {
17*09dbde01SManivannan Sadhasivam 	struct owl_reset *reset = to_owl_reset(rcdev);
18*09dbde01SManivannan Sadhasivam 	const struct owl_reset_map *map = &reset->reset_map[id];
19*09dbde01SManivannan Sadhasivam 
20*09dbde01SManivannan Sadhasivam 	return regmap_update_bits(reset->regmap, map->reg, map->bit, 0);
21*09dbde01SManivannan Sadhasivam }
22*09dbde01SManivannan Sadhasivam 
owl_reset_deassert(struct reset_controller_dev * rcdev,unsigned long id)23*09dbde01SManivannan Sadhasivam static int owl_reset_deassert(struct reset_controller_dev *rcdev,
24*09dbde01SManivannan Sadhasivam 			      unsigned long id)
25*09dbde01SManivannan Sadhasivam {
26*09dbde01SManivannan Sadhasivam 	struct owl_reset *reset = to_owl_reset(rcdev);
27*09dbde01SManivannan Sadhasivam 	const struct owl_reset_map *map = &reset->reset_map[id];
28*09dbde01SManivannan Sadhasivam 
29*09dbde01SManivannan Sadhasivam 	return regmap_update_bits(reset->regmap, map->reg, map->bit, map->bit);
30*09dbde01SManivannan Sadhasivam }
31*09dbde01SManivannan Sadhasivam 
owl_reset_reset(struct reset_controller_dev * rcdev,unsigned long id)32*09dbde01SManivannan Sadhasivam static int owl_reset_reset(struct reset_controller_dev *rcdev,
33*09dbde01SManivannan Sadhasivam 			   unsigned long id)
34*09dbde01SManivannan Sadhasivam {
35*09dbde01SManivannan Sadhasivam 	owl_reset_assert(rcdev, id);
36*09dbde01SManivannan Sadhasivam 	udelay(1);
37*09dbde01SManivannan Sadhasivam 	owl_reset_deassert(rcdev, id);
38*09dbde01SManivannan Sadhasivam 
39*09dbde01SManivannan Sadhasivam 	return 0;
40*09dbde01SManivannan Sadhasivam }
41*09dbde01SManivannan Sadhasivam 
owl_reset_status(struct reset_controller_dev * rcdev,unsigned long id)42*09dbde01SManivannan Sadhasivam static int owl_reset_status(struct reset_controller_dev *rcdev,
43*09dbde01SManivannan Sadhasivam 			    unsigned long id)
44*09dbde01SManivannan Sadhasivam {
45*09dbde01SManivannan Sadhasivam 	struct owl_reset *reset = to_owl_reset(rcdev);
46*09dbde01SManivannan Sadhasivam 	const struct owl_reset_map *map = &reset->reset_map[id];
47*09dbde01SManivannan Sadhasivam 	u32 reg;
48*09dbde01SManivannan Sadhasivam 	int ret;
49*09dbde01SManivannan Sadhasivam 
50*09dbde01SManivannan Sadhasivam 	ret = regmap_read(reset->regmap, map->reg, &reg);
51*09dbde01SManivannan Sadhasivam 	if (ret)
52*09dbde01SManivannan Sadhasivam 		return ret;
53*09dbde01SManivannan Sadhasivam 
54*09dbde01SManivannan Sadhasivam 	/*
55*09dbde01SManivannan Sadhasivam 	 * The reset control API expects 0 if reset is not asserted,
56*09dbde01SManivannan Sadhasivam 	 * which is the opposite of what our hardware uses.
57*09dbde01SManivannan Sadhasivam 	 */
58*09dbde01SManivannan Sadhasivam 	return !(map->bit & reg);
59*09dbde01SManivannan Sadhasivam }
60*09dbde01SManivannan Sadhasivam 
61*09dbde01SManivannan Sadhasivam const struct reset_control_ops owl_reset_ops = {
62*09dbde01SManivannan Sadhasivam 	.assert		= owl_reset_assert,
63*09dbde01SManivannan Sadhasivam 	.deassert	= owl_reset_deassert,
64*09dbde01SManivannan Sadhasivam 	.reset		= owl_reset_reset,
65*09dbde01SManivannan Sadhasivam 	.status		= owl_reset_status,
66*09dbde01SManivannan Sadhasivam };
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