1*b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 2ce087150SDavid S. Miller /* n2rng.h: Niagara2 RNG defines. 3ce087150SDavid S. Miller * 4ce087150SDavid S. Miller * Copyright (C) 2008 David S. Miller <davem@davemloft.net> 5ce087150SDavid S. Miller */ 6ce087150SDavid S. Miller 7ce087150SDavid S. Miller #ifndef _N2RNG_H 8ce087150SDavid S. Miller #define _N2RNG_H 9ce087150SDavid S. Miller 1007e25d43SShannon Nelson /* ver1 devices - n2-rng, vf-rng, kt-rng */ 1107e25d43SShannon Nelson #define RNG_v1_CTL_WAIT 0x0000000001fffe00ULL /* Minimum wait time */ 1207e25d43SShannon Nelson #define RNG_v1_CTL_WAIT_SHIFT 9 1307e25d43SShannon Nelson #define RNG_v1_CTL_BYPASS 0x0000000000000100ULL /* VCO voltage source */ 1407e25d43SShannon Nelson #define RNG_v1_CTL_VCO 0x00000000000000c0ULL /* VCO rate control */ 1507e25d43SShannon Nelson #define RNG_v1_CTL_VCO_SHIFT 6 1607e25d43SShannon Nelson #define RNG_v1_CTL_ASEL 0x0000000000000030ULL /* Analog MUX select */ 1707e25d43SShannon Nelson #define RNG_v1_CTL_ASEL_SHIFT 4 1807e25d43SShannon Nelson #define RNG_v1_CTL_ASEL_NOOUT 2 1907e25d43SShannon Nelson 2007e25d43SShannon Nelson /* these are the same in v2 as in v1 */ 21ce087150SDavid S. Miller #define RNG_CTL_LFSR 0x0000000000000008ULL /* Use LFSR or plain shift */ 22ce087150SDavid S. Miller #define RNG_CTL_ES3 0x0000000000000004ULL /* Enable entropy source 3 */ 23ce087150SDavid S. Miller #define RNG_CTL_ES2 0x0000000000000002ULL /* Enable entropy source 2 */ 24ce087150SDavid S. Miller #define RNG_CTL_ES1 0x0000000000000001ULL /* Enable entropy source 1 */ 25ce087150SDavid S. Miller 2607e25d43SShannon Nelson /* ver2 devices - m4-rng, m7-rng */ 2707e25d43SShannon Nelson #define RNG_v2_CTL_WAIT 0x0000000007fff800ULL /* Minimum wait time */ 2807e25d43SShannon Nelson #define RNG_v2_CTL_WAIT_SHIFT 12 2907e25d43SShannon Nelson #define RNG_v2_CTL_BYPASS 0x0000000000000400ULL /* VCO voltage source */ 3007e25d43SShannon Nelson #define RNG_v2_CTL_VCO 0x0000000000000300ULL /* VCO rate control */ 3107e25d43SShannon Nelson #define RNG_v2_CTL_VCO_SHIFT 9 3207e25d43SShannon Nelson #define RNG_v2_CTL_PERF 0x0000000000000180ULL /* Perf */ 3307e25d43SShannon Nelson #define RNG_v2_CTL_ASEL 0x0000000000000070ULL /* Analog MUX select */ 3407e25d43SShannon Nelson #define RNG_v2_CTL_ASEL_SHIFT 4 3507e25d43SShannon Nelson #define RNG_v2_CTL_ASEL_NOOUT 7 3607e25d43SShannon Nelson 3707e25d43SShannon Nelson 38ce087150SDavid S. Miller #define HV_FAST_RNG_GET_DIAG_CTL 0x130 39ce087150SDavid S. Miller #define HV_FAST_RNG_CTL_READ 0x131 40ce087150SDavid S. Miller #define HV_FAST_RNG_CTL_WRITE 0x132 41ce087150SDavid S. Miller #define HV_FAST_RNG_DATA_READ_DIAG 0x133 42ce087150SDavid S. Miller #define HV_FAST_RNG_DATA_READ 0x134 43ce087150SDavid S. Miller 44ce087150SDavid S. Miller #define HV_RNG_STATE_UNCONFIGURED 0 45ce087150SDavid S. Miller #define HV_RNG_STATE_CONFIGURED 1 46ce087150SDavid S. Miller #define HV_RNG_STATE_HEALTHCHECK 2 47ce087150SDavid S. Miller #define HV_RNG_STATE_ERROR 3 48ce087150SDavid S. Miller 49ce087150SDavid S. Miller #define HV_RNG_NUM_CONTROL 4 50ce087150SDavid S. Miller 51ce087150SDavid S. Miller #ifndef __ASSEMBLY__ 52ce087150SDavid S. Miller extern unsigned long sun4v_rng_get_diag_ctl(void); 53ce087150SDavid S. Miller extern unsigned long sun4v_rng_ctl_read_v1(unsigned long ctl_regs_ra, 54ce087150SDavid S. Miller unsigned long *state, 55ce087150SDavid S. Miller unsigned long *tick_delta); 56ce087150SDavid S. Miller extern unsigned long sun4v_rng_ctl_read_v2(unsigned long ctl_regs_ra, 57ce087150SDavid S. Miller unsigned long unit, 58ce087150SDavid S. Miller unsigned long *state, 59ce087150SDavid S. Miller unsigned long *tick_delta, 60ce087150SDavid S. Miller unsigned long *watchdog, 61ce087150SDavid S. Miller unsigned long *write_status); 62ce087150SDavid S. Miller extern unsigned long sun4v_rng_ctl_write_v1(unsigned long ctl_regs_ra, 63ce087150SDavid S. Miller unsigned long state, 64ce087150SDavid S. Miller unsigned long write_timeout, 65ce087150SDavid S. Miller unsigned long *tick_delta); 66ce087150SDavid S. Miller extern unsigned long sun4v_rng_ctl_write_v2(unsigned long ctl_regs_ra, 67ce087150SDavid S. Miller unsigned long state, 68ce087150SDavid S. Miller unsigned long write_timeout, 69ce087150SDavid S. Miller unsigned long unit); 70ce087150SDavid S. Miller extern unsigned long sun4v_rng_data_read_diag_v1(unsigned long data_ra, 71ce087150SDavid S. Miller unsigned long len, 72ce087150SDavid S. Miller unsigned long *tick_delta); 73ce087150SDavid S. Miller extern unsigned long sun4v_rng_data_read_diag_v2(unsigned long data_ra, 74ce087150SDavid S. Miller unsigned long len, 75ce087150SDavid S. Miller unsigned long unit, 76ce087150SDavid S. Miller unsigned long *tick_delta); 77ce087150SDavid S. Miller extern unsigned long sun4v_rng_data_read(unsigned long data_ra, 78ce087150SDavid S. Miller unsigned long *tick_delta); 79ce087150SDavid S. Miller 80becbc494SShannon Nelson enum n2rng_compat_id { 81becbc494SShannon Nelson N2_n2_rng, 82becbc494SShannon Nelson N2_vf_rng, 83becbc494SShannon Nelson N2_kt_rng, 84becbc494SShannon Nelson N2_m4_rng, 85becbc494SShannon Nelson N2_m7_rng, 86becbc494SShannon Nelson }; 87becbc494SShannon Nelson 88becbc494SShannon Nelson struct n2rng_template { 89becbc494SShannon Nelson enum n2rng_compat_id id; 90becbc494SShannon Nelson int multi_capable; 91becbc494SShannon Nelson int chip_version; 92becbc494SShannon Nelson }; 93becbc494SShannon Nelson 94ce087150SDavid S. Miller struct n2rng_unit { 95ce087150SDavid S. Miller u64 control[HV_RNG_NUM_CONTROL]; 96ce087150SDavid S. Miller }; 97ce087150SDavid S. Miller 98ce087150SDavid S. Miller struct n2rng { 992dc11581SGrant Likely struct platform_device *op; 100ce087150SDavid S. Miller 101ce087150SDavid S. Miller unsigned long flags; 10224f14669SDavid S. Miller #define N2RNG_FLAG_MULTI 0x00000001 /* Multi-unit capable RNG */ 103ce087150SDavid S. Miller #define N2RNG_FLAG_CONTROL 0x00000002 /* Operating in control domain */ 104ce087150SDavid S. Miller #define N2RNG_FLAG_READY 0x00000008 /* Ready for hw-rng layer */ 105ce087150SDavid S. Miller #define N2RNG_FLAG_SHUTDOWN 0x00000010 /* Driver unregistering */ 106ce087150SDavid S. Miller #define N2RNG_FLAG_BUFFER_VALID 0x00000020 /* u32 buffer holds valid data */ 107ce087150SDavid S. Miller 108becbc494SShannon Nelson struct n2rng_template *data; 109ce087150SDavid S. Miller int num_units; 110ce087150SDavid S. Miller struct n2rng_unit *units; 111ce087150SDavid S. Miller 112ce087150SDavid S. Miller struct hwrng hwrng; 113ce087150SDavid S. Miller u32 buffer; 114ce087150SDavid S. Miller 115ce087150SDavid S. Miller /* Registered hypervisor group API major and minor version. */ 116ce087150SDavid S. Miller unsigned long hvapi_major; 117ce087150SDavid S. Miller unsigned long hvapi_minor; 118ce087150SDavid S. Miller 119ce087150SDavid S. Miller struct delayed_work work; 120ce087150SDavid S. Miller 121ce087150SDavid S. Miller unsigned long hv_state; /* HV_RNG_STATE_foo */ 122ce087150SDavid S. Miller 123ce087150SDavid S. Miller unsigned long health_check_sec; 124ce087150SDavid S. Miller unsigned long accum_cycles; 125ce087150SDavid S. Miller unsigned long wd_timeo; 126ce087150SDavid S. Miller #define N2RNG_HEALTH_CHECK_SEC_DEFAULT 0 127ce087150SDavid S. Miller #define N2RNG_ACCUM_CYCLES_DEFAULT 2048 128ce087150SDavid S. Miller #define N2RNG_WD_TIMEO_DEFAULT 0 129ce087150SDavid S. Miller 130ce087150SDavid S. Miller u64 scratch_control[HV_RNG_NUM_CONTROL]; 131ce087150SDavid S. Miller 13207e25d43SShannon Nelson #define RNG_v1_SELFTEST_TICKS 38859 13307e25d43SShannon Nelson #define RNG_v1_SELFTEST_VAL ((u64)0xB8820C7BD387E32C) 13407e25d43SShannon Nelson #define RNG_v2_SELFTEST_TICKS 64 13507e25d43SShannon Nelson #define RNG_v2_SELFTEST_VAL ((u64)0xffffffffffffffff) 136ce087150SDavid S. Miller #define SELFTEST_POLY ((u64)0x231DCEE91262B8A3) 137ce087150SDavid S. Miller #define SELFTEST_MATCH_GOAL 6 138ce087150SDavid S. Miller #define SELFTEST_LOOPS_MAX 40000 139ce087150SDavid S. Miller #define SELFTEST_BUFFER_WORDS 8 140ce087150SDavid S. Miller 141ce087150SDavid S. Miller u64 test_data; 142ce087150SDavid S. Miller u64 test_control[HV_RNG_NUM_CONTROL]; 143ce087150SDavid S. Miller u64 test_buffer[SELFTEST_BUFFER_WORDS]; 144ce087150SDavid S. Miller }; 145ce087150SDavid S. Miller 146ce087150SDavid S. Miller #define N2RNG_BLOCK_LIMIT 60000 147ce087150SDavid S. Miller #define N2RNG_BUSY_LIMIT 100 148ce087150SDavid S. Miller #define N2RNG_HCHECK_LIMIT 100 149ce087150SDavid S. Miller 150ce087150SDavid S. Miller #endif /* !(__ASSEMBLY__) */ 151ce087150SDavid S. Miller 152ce087150SDavid S. Miller #endif /* _N2RNG_H */ 153