1*a583ed31SHadar Gat /* SPDX-License-Identifier: GPL-2.0 */ 2*a583ed31SHadar Gat /* Copyright (C) 2019-2020 ARM Limited or its affiliates. */ 3*a583ed31SHadar Gat 4*a583ed31SHadar Gat #include <linux/bitops.h> 5*a583ed31SHadar Gat 6*a583ed31SHadar Gat #define POWER_DOWN_ENABLE 0x01 7*a583ed31SHadar Gat #define POWER_DOWN_DISABLE 0x00 8*a583ed31SHadar Gat 9*a583ed31SHadar Gat /* hwrng quality: bits of true entropy per 1024 bits of input */ 10*a583ed31SHadar Gat #define CC_TRNG_QUALITY 1024 11*a583ed31SHadar Gat 12*a583ed31SHadar Gat /* CryptoCell TRNG HW definitions */ 13*a583ed31SHadar Gat #define CC_TRNG_NUM_OF_ROSCS 4 14*a583ed31SHadar Gat /* The number of words generated in the entropy holding register (EHR) 15*a583ed31SHadar Gat * 6 words (192 bit) according to HW implementation 16*a583ed31SHadar Gat */ 17*a583ed31SHadar Gat #define CC_TRNG_EHR_IN_WORDS 6 18*a583ed31SHadar Gat #define CC_TRNG_EHR_IN_BITS (CC_TRNG_EHR_IN_WORDS * BITS_PER_TYPE(u32)) 19*a583ed31SHadar Gat 20*a583ed31SHadar Gat #define CC_HOST_RNG_IRQ_MASK BIT(CC_HOST_RGF_IRR_RNG_INT_BIT_SHIFT) 21*a583ed31SHadar Gat 22*a583ed31SHadar Gat /* RNG interrupt mask */ 23*a583ed31SHadar Gat #define CC_RNG_INT_MASK (BIT(CC_RNG_IMR_EHR_VALID_INT_MASK_BIT_SHIFT) | \ 24*a583ed31SHadar Gat BIT(CC_RNG_IMR_AUTOCORR_ERR_INT_MASK_BIT_SHIFT) | \ 25*a583ed31SHadar Gat BIT(CC_RNG_IMR_CRNGT_ERR_INT_MASK_BIT_SHIFT) | \ 26*a583ed31SHadar Gat BIT(CC_RNG_IMR_VN_ERR_INT_MASK_BIT_SHIFT) | \ 27*a583ed31SHadar Gat BIT(CC_RNG_IMR_WATCHDOG_INT_MASK_BIT_SHIFT)) 28*a583ed31SHadar Gat 29*a583ed31SHadar Gat // -------------------------------------- 30*a583ed31SHadar Gat // BLOCK: RNG 31*a583ed31SHadar Gat // -------------------------------------- 32*a583ed31SHadar Gat #define CC_RNG_IMR_REG_OFFSET 0x0100UL 33*a583ed31SHadar Gat #define CC_RNG_IMR_EHR_VALID_INT_MASK_BIT_SHIFT 0x0UL 34*a583ed31SHadar Gat #define CC_RNG_IMR_AUTOCORR_ERR_INT_MASK_BIT_SHIFT 0x1UL 35*a583ed31SHadar Gat #define CC_RNG_IMR_CRNGT_ERR_INT_MASK_BIT_SHIFT 0x2UL 36*a583ed31SHadar Gat #define CC_RNG_IMR_VN_ERR_INT_MASK_BIT_SHIFT 0x3UL 37*a583ed31SHadar Gat #define CC_RNG_IMR_WATCHDOG_INT_MASK_BIT_SHIFT 0x4UL 38*a583ed31SHadar Gat #define CC_RNG_ISR_REG_OFFSET 0x0104UL 39*a583ed31SHadar Gat #define CC_RNG_ISR_EHR_VALID_BIT_SHIFT 0x0UL 40*a583ed31SHadar Gat #define CC_RNG_ISR_EHR_VALID_BIT_SIZE 0x1UL 41*a583ed31SHadar Gat #define CC_RNG_ISR_AUTOCORR_ERR_BIT_SHIFT 0x1UL 42*a583ed31SHadar Gat #define CC_RNG_ISR_AUTOCORR_ERR_BIT_SIZE 0x1UL 43*a583ed31SHadar Gat #define CC_RNG_ISR_CRNGT_ERR_BIT_SHIFT 0x2UL 44*a583ed31SHadar Gat #define CC_RNG_ISR_CRNGT_ERR_BIT_SIZE 0x1UL 45*a583ed31SHadar Gat #define CC_RNG_ISR_WATCHDOG_BIT_SHIFT 0x4UL 46*a583ed31SHadar Gat #define CC_RNG_ISR_WATCHDOG_BIT_SIZE 0x1UL 47*a583ed31SHadar Gat #define CC_RNG_ICR_REG_OFFSET 0x0108UL 48*a583ed31SHadar Gat #define CC_TRNG_CONFIG_REG_OFFSET 0x010CUL 49*a583ed31SHadar Gat #define CC_EHR_DATA_0_REG_OFFSET 0x0114UL 50*a583ed31SHadar Gat #define CC_RND_SOURCE_ENABLE_REG_OFFSET 0x012CUL 51*a583ed31SHadar Gat #define CC_SAMPLE_CNT1_REG_OFFSET 0x0130UL 52*a583ed31SHadar Gat #define CC_TRNG_DEBUG_CONTROL_REG_OFFSET 0x0138UL 53*a583ed31SHadar Gat #define CC_RNG_SW_RESET_REG_OFFSET 0x0140UL 54*a583ed31SHadar Gat #define CC_RNG_CLK_ENABLE_REG_OFFSET 0x01C4UL 55*a583ed31SHadar Gat #define CC_RNG_DMA_ENABLE_REG_OFFSET 0x01C8UL 56*a583ed31SHadar Gat #define CC_RNG_WATCHDOG_VAL_REG_OFFSET 0x01D8UL 57*a583ed31SHadar Gat // -------------------------------------- 58*a583ed31SHadar Gat // BLOCK: SEC_HOST_RGF 59*a583ed31SHadar Gat // -------------------------------------- 60*a583ed31SHadar Gat #define CC_HOST_RGF_IRR_REG_OFFSET 0x0A00UL 61*a583ed31SHadar Gat #define CC_HOST_RGF_IRR_RNG_INT_BIT_SHIFT 0xAUL 62*a583ed31SHadar Gat #define CC_HOST_RGF_IMR_REG_OFFSET 0x0A04UL 63*a583ed31SHadar Gat #define CC_HOST_RGF_ICR_REG_OFFSET 0x0A08UL 64*a583ed31SHadar Gat 65*a583ed31SHadar Gat #define CC_HOST_POWER_DOWN_EN_REG_OFFSET 0x0A78UL 66*a583ed31SHadar Gat 67*a583ed31SHadar Gat // -------------------------------------- 68*a583ed31SHadar Gat // BLOCK: NVM 69*a583ed31SHadar Gat // -------------------------------------- 70*a583ed31SHadar Gat #define CC_NVM_IS_IDLE_REG_OFFSET 0x0F10UL 71*a583ed31SHadar Gat #define CC_NVM_IS_IDLE_VALUE_BIT_SHIFT 0x0UL 72*a583ed31SHadar Gat #define CC_NVM_IS_IDLE_VALUE_BIT_SIZE 0x1UL 73