1 /* 2 * Intel AGPGART routines. 3 */ 4 5 #include <linux/module.h> 6 #include <linux/pci.h> 7 #include <linux/init.h> 8 #include <linux/kernel.h> 9 #include <linux/pagemap.h> 10 #include <linux/agp_backend.h> 11 #include "agp.h" 12 13 #define PCI_DEVICE_ID_INTEL_82946GZ_HB 0x2970 14 #define PCI_DEVICE_ID_INTEL_82946GZ_IG 0x2972 15 #define PCI_DEVICE_ID_INTEL_82965G_1_HB 0x2980 16 #define PCI_DEVICE_ID_INTEL_82965G_1_IG 0x2982 17 #define PCI_DEVICE_ID_INTEL_82965Q_HB 0x2990 18 #define PCI_DEVICE_ID_INTEL_82965Q_IG 0x2992 19 #define PCI_DEVICE_ID_INTEL_82965G_HB 0x29A0 20 #define PCI_DEVICE_ID_INTEL_82965G_IG 0x29A2 21 #define PCI_DEVICE_ID_INTEL_82965GM_HB 0x2A00 22 #define PCI_DEVICE_ID_INTEL_82965GM_IG 0x2A02 23 #define PCI_DEVICE_ID_INTEL_82965GME_HB 0x2A10 24 #define PCI_DEVICE_ID_INTEL_82965GME_IG 0x2A12 25 #define PCI_DEVICE_ID_INTEL_82945GME_HB 0x27AC 26 #define PCI_DEVICE_ID_INTEL_82945GME_IG 0x27AE 27 #define PCI_DEVICE_ID_INTEL_G33_HB 0x29C0 28 #define PCI_DEVICE_ID_INTEL_G33_IG 0x29C2 29 #define PCI_DEVICE_ID_INTEL_Q35_HB 0x29B0 30 #define PCI_DEVICE_ID_INTEL_Q35_IG 0x29B2 31 #define PCI_DEVICE_ID_INTEL_Q33_HB 0x29D0 32 #define PCI_DEVICE_ID_INTEL_Q33_IG 0x29D2 33 34 #define IS_I965 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82946GZ_HB || \ 35 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965G_1_HB || \ 36 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965Q_HB || \ 37 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965G_HB || \ 38 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GM_HB || \ 39 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GME_HB) 40 41 #define IS_G33 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G33_HB || \ 42 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q35_HB || \ 43 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q33_HB) 44 45 extern int agp_memory_reserved; 46 47 48 /* Intel 815 register */ 49 #define INTEL_815_APCONT 0x51 50 #define INTEL_815_ATTBASE_MASK ~0x1FFFFFFF 51 52 /* Intel i820 registers */ 53 #define INTEL_I820_RDCR 0x51 54 #define INTEL_I820_ERRSTS 0xc8 55 56 /* Intel i840 registers */ 57 #define INTEL_I840_MCHCFG 0x50 58 #define INTEL_I840_ERRSTS 0xc8 59 60 /* Intel i850 registers */ 61 #define INTEL_I850_MCHCFG 0x50 62 #define INTEL_I850_ERRSTS 0xc8 63 64 /* intel 915G registers */ 65 #define I915_GMADDR 0x18 66 #define I915_MMADDR 0x10 67 #define I915_PTEADDR 0x1C 68 #define I915_GMCH_GMS_STOLEN_48M (0x6 << 4) 69 #define I915_GMCH_GMS_STOLEN_64M (0x7 << 4) 70 #define G33_GMCH_GMS_STOLEN_128M (0x8 << 4) 71 #define G33_GMCH_GMS_STOLEN_256M (0x9 << 4) 72 73 /* Intel 965G registers */ 74 #define I965_MSAC 0x62 75 76 /* Intel 7505 registers */ 77 #define INTEL_I7505_APSIZE 0x74 78 #define INTEL_I7505_NCAPID 0x60 79 #define INTEL_I7505_NISTAT 0x6c 80 #define INTEL_I7505_ATTBASE 0x78 81 #define INTEL_I7505_ERRSTS 0x42 82 #define INTEL_I7505_AGPCTRL 0x70 83 #define INTEL_I7505_MCHCFG 0x50 84 85 static const struct aper_size_info_fixed intel_i810_sizes[] = 86 { 87 {64, 16384, 4}, 88 /* The 32M mode still requires a 64k gatt */ 89 {32, 8192, 4} 90 }; 91 92 #define AGP_DCACHE_MEMORY 1 93 #define AGP_PHYS_MEMORY 2 94 #define INTEL_AGP_CACHED_MEMORY 3 95 96 static struct gatt_mask intel_i810_masks[] = 97 { 98 {.mask = I810_PTE_VALID, .type = 0}, 99 {.mask = (I810_PTE_VALID | I810_PTE_LOCAL), .type = AGP_DCACHE_MEMORY}, 100 {.mask = I810_PTE_VALID, .type = 0}, 101 {.mask = I810_PTE_VALID | I830_PTE_SYSTEM_CACHED, 102 .type = INTEL_AGP_CACHED_MEMORY} 103 }; 104 105 static struct _intel_private { 106 struct pci_dev *pcidev; /* device one */ 107 u8 __iomem *registers; 108 u32 __iomem *gtt; /* I915G */ 109 int num_dcache_entries; 110 /* gtt_entries is the number of gtt entries that are already mapped 111 * to stolen memory. Stolen memory is larger than the memory mapped 112 * through gtt_entries, as it includes some reserved space for the BIOS 113 * popup and for the GTT. 114 */ 115 int gtt_entries; /* i830+ */ 116 } intel_private; 117 118 static int intel_i810_fetch_size(void) 119 { 120 u32 smram_miscc; 121 struct aper_size_info_fixed *values; 122 123 pci_read_config_dword(agp_bridge->dev, I810_SMRAM_MISCC, &smram_miscc); 124 values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes); 125 126 if ((smram_miscc & I810_GMS) == I810_GMS_DISABLE) { 127 printk(KERN_WARNING PFX "i810 is disabled\n"); 128 return 0; 129 } 130 if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) == I810_GFX_MEM_WIN_32M) { 131 agp_bridge->previous_size = 132 agp_bridge->current_size = (void *) (values + 1); 133 agp_bridge->aperture_size_idx = 1; 134 return values[1].size; 135 } else { 136 agp_bridge->previous_size = 137 agp_bridge->current_size = (void *) (values); 138 agp_bridge->aperture_size_idx = 0; 139 return values[0].size; 140 } 141 142 return 0; 143 } 144 145 static int intel_i810_configure(void) 146 { 147 struct aper_size_info_fixed *current_size; 148 u32 temp; 149 int i; 150 151 current_size = A_SIZE_FIX(agp_bridge->current_size); 152 153 if (!intel_private.registers) { 154 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp); 155 temp &= 0xfff80000; 156 157 intel_private.registers = ioremap(temp, 128 * 4096); 158 if (!intel_private.registers) { 159 printk(KERN_ERR PFX "Unable to remap memory.\n"); 160 return -ENOMEM; 161 } 162 } 163 164 if ((readl(intel_private.registers+I810_DRAM_CTL) 165 & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) { 166 /* This will need to be dynamically assigned */ 167 printk(KERN_INFO PFX "detected 4MB dedicated video ram.\n"); 168 intel_private.num_dcache_entries = 1024; 169 } 170 pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp); 171 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 172 writel(agp_bridge->gatt_bus_addr | I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL); 173 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */ 174 175 if (agp_bridge->driver->needs_scratch_page) { 176 for (i = 0; i < current_size->num_entries; i++) { 177 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4)); 178 readl(intel_private.registers+I810_PTE_BASE+(i*4)); /* PCI posting. */ 179 } 180 } 181 global_cache_flush(); 182 return 0; 183 } 184 185 static void intel_i810_cleanup(void) 186 { 187 writel(0, intel_private.registers+I810_PGETBL_CTL); 188 readl(intel_private.registers); /* PCI Posting. */ 189 iounmap(intel_private.registers); 190 } 191 192 static void intel_i810_tlbflush(struct agp_memory *mem) 193 { 194 return; 195 } 196 197 static void intel_i810_agp_enable(struct agp_bridge_data *bridge, u32 mode) 198 { 199 return; 200 } 201 202 /* Exists to support ARGB cursors */ 203 static void *i8xx_alloc_pages(void) 204 { 205 struct page * page; 206 207 page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2); 208 if (page == NULL) 209 return NULL; 210 211 if (change_page_attr(page, 4, PAGE_KERNEL_NOCACHE) < 0) { 212 change_page_attr(page, 4, PAGE_KERNEL); 213 global_flush_tlb(); 214 __free_pages(page, 2); 215 return NULL; 216 } 217 global_flush_tlb(); 218 get_page(page); 219 atomic_inc(&agp_bridge->current_memory_agp); 220 return page_address(page); 221 } 222 223 static void i8xx_destroy_pages(void *addr) 224 { 225 struct page *page; 226 227 if (addr == NULL) 228 return; 229 230 page = virt_to_page(addr); 231 change_page_attr(page, 4, PAGE_KERNEL); 232 global_flush_tlb(); 233 put_page(page); 234 __free_pages(page, 2); 235 atomic_dec(&agp_bridge->current_memory_agp); 236 } 237 238 static int intel_i830_type_to_mask_type(struct agp_bridge_data *bridge, 239 int type) 240 { 241 if (type < AGP_USER_TYPES) 242 return type; 243 else if (type == AGP_USER_CACHED_MEMORY) 244 return INTEL_AGP_CACHED_MEMORY; 245 else 246 return 0; 247 } 248 249 static int intel_i810_insert_entries(struct agp_memory *mem, off_t pg_start, 250 int type) 251 { 252 int i, j, num_entries; 253 void *temp; 254 int ret = -EINVAL; 255 int mask_type; 256 257 if (mem->page_count == 0) 258 goto out; 259 260 temp = agp_bridge->current_size; 261 num_entries = A_SIZE_FIX(temp)->num_entries; 262 263 if ((pg_start + mem->page_count) > num_entries) 264 goto out_err; 265 266 267 for (j = pg_start; j < (pg_start + mem->page_count); j++) { 268 if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j))) { 269 ret = -EBUSY; 270 goto out_err; 271 } 272 } 273 274 if (type != mem->type) 275 goto out_err; 276 277 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type); 278 279 switch (mask_type) { 280 case AGP_DCACHE_MEMORY: 281 if (!mem->is_flushed) 282 global_cache_flush(); 283 for (i = pg_start; i < (pg_start + mem->page_count); i++) { 284 writel((i*4096)|I810_PTE_LOCAL|I810_PTE_VALID, 285 intel_private.registers+I810_PTE_BASE+(i*4)); 286 } 287 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); 288 break; 289 case AGP_PHYS_MEMORY: 290 case AGP_NORMAL_MEMORY: 291 if (!mem->is_flushed) 292 global_cache_flush(); 293 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { 294 writel(agp_bridge->driver->mask_memory(agp_bridge, 295 mem->memory[i], 296 mask_type), 297 intel_private.registers+I810_PTE_BASE+(j*4)); 298 } 299 readl(intel_private.registers+I810_PTE_BASE+((j-1)*4)); 300 break; 301 default: 302 goto out_err; 303 } 304 305 agp_bridge->driver->tlb_flush(mem); 306 out: 307 ret = 0; 308 out_err: 309 mem->is_flushed = 1; 310 return ret; 311 } 312 313 static int intel_i810_remove_entries(struct agp_memory *mem, off_t pg_start, 314 int type) 315 { 316 int i; 317 318 if (mem->page_count == 0) 319 return 0; 320 321 for (i = pg_start; i < (mem->page_count + pg_start); i++) { 322 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4)); 323 } 324 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); 325 326 agp_bridge->driver->tlb_flush(mem); 327 return 0; 328 } 329 330 /* 331 * The i810/i830 requires a physical address to program its mouse 332 * pointer into hardware. 333 * However the Xserver still writes to it through the agp aperture. 334 */ 335 static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type) 336 { 337 struct agp_memory *new; 338 void *addr; 339 340 switch (pg_count) { 341 case 1: addr = agp_bridge->driver->agp_alloc_page(agp_bridge); 342 global_flush_tlb(); 343 break; 344 case 4: 345 /* kludge to get 4 physical pages for ARGB cursor */ 346 addr = i8xx_alloc_pages(); 347 break; 348 default: 349 return NULL; 350 } 351 352 if (addr == NULL) 353 return NULL; 354 355 new = agp_create_memory(pg_count); 356 if (new == NULL) 357 return NULL; 358 359 new->memory[0] = virt_to_gart(addr); 360 if (pg_count == 4) { 361 /* kludge to get 4 physical pages for ARGB cursor */ 362 new->memory[1] = new->memory[0] + PAGE_SIZE; 363 new->memory[2] = new->memory[1] + PAGE_SIZE; 364 new->memory[3] = new->memory[2] + PAGE_SIZE; 365 } 366 new->page_count = pg_count; 367 new->num_scratch_pages = pg_count; 368 new->type = AGP_PHYS_MEMORY; 369 new->physical = new->memory[0]; 370 return new; 371 } 372 373 static struct agp_memory *intel_i810_alloc_by_type(size_t pg_count, int type) 374 { 375 struct agp_memory *new; 376 377 if (type == AGP_DCACHE_MEMORY) { 378 if (pg_count != intel_private.num_dcache_entries) 379 return NULL; 380 381 new = agp_create_memory(1); 382 if (new == NULL) 383 return NULL; 384 385 new->type = AGP_DCACHE_MEMORY; 386 new->page_count = pg_count; 387 new->num_scratch_pages = 0; 388 agp_free_page_array(new); 389 return new; 390 } 391 if (type == AGP_PHYS_MEMORY) 392 return alloc_agpphysmem_i8xx(pg_count, type); 393 return NULL; 394 } 395 396 static void intel_i810_free_by_type(struct agp_memory *curr) 397 { 398 agp_free_key(curr->key); 399 if (curr->type == AGP_PHYS_MEMORY) { 400 if (curr->page_count == 4) 401 i8xx_destroy_pages(gart_to_virt(curr->memory[0])); 402 else { 403 agp_bridge->driver->agp_destroy_page(gart_to_virt(curr->memory[0]), 404 AGP_PAGE_DESTROY_UNMAP); 405 global_flush_tlb(); 406 agp_bridge->driver->agp_destroy_page(gart_to_virt(curr->memory[0]), 407 AGP_PAGE_DESTROY_FREE); 408 } 409 agp_free_page_array(curr); 410 } 411 kfree(curr); 412 } 413 414 static unsigned long intel_i810_mask_memory(struct agp_bridge_data *bridge, 415 unsigned long addr, int type) 416 { 417 /* Type checking must be done elsewhere */ 418 return addr | bridge->driver->masks[type].mask; 419 } 420 421 static struct aper_size_info_fixed intel_i830_sizes[] = 422 { 423 {128, 32768, 5}, 424 /* The 64M mode still requires a 128k gatt */ 425 {64, 16384, 5}, 426 {256, 65536, 6}, 427 {512, 131072, 7}, 428 }; 429 430 static void intel_i830_init_gtt_entries(void) 431 { 432 u16 gmch_ctrl; 433 int gtt_entries; 434 u8 rdct; 435 int local = 0; 436 static const int ddt[4] = { 0, 16, 32, 64 }; 437 int size; /* reserved space (in kb) at the top of stolen memory */ 438 439 pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl); 440 441 if (IS_I965) { 442 u32 pgetbl_ctl; 443 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL); 444 445 /* The 965 has a field telling us the size of the GTT, 446 * which may be larger than what is necessary to map the 447 * aperture. 448 */ 449 switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) { 450 case I965_PGETBL_SIZE_128KB: 451 size = 128; 452 break; 453 case I965_PGETBL_SIZE_256KB: 454 size = 256; 455 break; 456 case I965_PGETBL_SIZE_512KB: 457 size = 512; 458 break; 459 default: 460 printk(KERN_INFO PFX "Unknown page table size, " 461 "assuming 512KB\n"); 462 size = 512; 463 } 464 size += 4; /* add in BIOS popup space */ 465 } else if (IS_G33) { 466 /* G33's GTT size defined in gmch_ctrl */ 467 switch (gmch_ctrl & G33_PGETBL_SIZE_MASK) { 468 case G33_PGETBL_SIZE_1M: 469 size = 1024; 470 break; 471 case G33_PGETBL_SIZE_2M: 472 size = 2048; 473 break; 474 default: 475 printk(KERN_INFO PFX "Unknown page table size 0x%x, " 476 "assuming 512KB\n", 477 (gmch_ctrl & G33_PGETBL_SIZE_MASK)); 478 size = 512; 479 } 480 size += 4; 481 } else { 482 /* On previous hardware, the GTT size was just what was 483 * required to map the aperture. 484 */ 485 size = agp_bridge->driver->fetch_size() + 4; 486 } 487 488 if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82830_HB || 489 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) { 490 switch (gmch_ctrl & I830_GMCH_GMS_MASK) { 491 case I830_GMCH_GMS_STOLEN_512: 492 gtt_entries = KB(512) - KB(size); 493 break; 494 case I830_GMCH_GMS_STOLEN_1024: 495 gtt_entries = MB(1) - KB(size); 496 break; 497 case I830_GMCH_GMS_STOLEN_8192: 498 gtt_entries = MB(8) - KB(size); 499 break; 500 case I830_GMCH_GMS_LOCAL: 501 rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE); 502 gtt_entries = (I830_RDRAM_ND(rdct) + 1) * 503 MB(ddt[I830_RDRAM_DDT(rdct)]); 504 local = 1; 505 break; 506 default: 507 gtt_entries = 0; 508 break; 509 } 510 } else { 511 switch (gmch_ctrl & I855_GMCH_GMS_MASK) { 512 case I855_GMCH_GMS_STOLEN_1M: 513 gtt_entries = MB(1) - KB(size); 514 break; 515 case I855_GMCH_GMS_STOLEN_4M: 516 gtt_entries = MB(4) - KB(size); 517 break; 518 case I855_GMCH_GMS_STOLEN_8M: 519 gtt_entries = MB(8) - KB(size); 520 break; 521 case I855_GMCH_GMS_STOLEN_16M: 522 gtt_entries = MB(16) - KB(size); 523 break; 524 case I855_GMCH_GMS_STOLEN_32M: 525 gtt_entries = MB(32) - KB(size); 526 break; 527 case I915_GMCH_GMS_STOLEN_48M: 528 /* Check it's really I915G */ 529 if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915G_HB || 530 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB || 531 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945G_HB || 532 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GM_HB || 533 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GME_HB || 534 IS_I965 || IS_G33) 535 gtt_entries = MB(48) - KB(size); 536 else 537 gtt_entries = 0; 538 break; 539 case I915_GMCH_GMS_STOLEN_64M: 540 /* Check it's really I915G */ 541 if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915G_HB || 542 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB || 543 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945G_HB || 544 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GM_HB || 545 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GME_HB || 546 IS_I965 || IS_G33) 547 gtt_entries = MB(64) - KB(size); 548 else 549 gtt_entries = 0; 550 break; 551 case G33_GMCH_GMS_STOLEN_128M: 552 if (IS_G33) 553 gtt_entries = MB(128) - KB(size); 554 else 555 gtt_entries = 0; 556 break; 557 case G33_GMCH_GMS_STOLEN_256M: 558 if (IS_G33) 559 gtt_entries = MB(256) - KB(size); 560 else 561 gtt_entries = 0; 562 break; 563 default: 564 gtt_entries = 0; 565 break; 566 } 567 } 568 if (gtt_entries > 0) 569 printk(KERN_INFO PFX "Detected %dK %s memory.\n", 570 gtt_entries / KB(1), local ? "local" : "stolen"); 571 else 572 printk(KERN_INFO PFX 573 "No pre-allocated video memory detected.\n"); 574 gtt_entries /= KB(4); 575 576 intel_private.gtt_entries = gtt_entries; 577 } 578 579 /* The intel i830 automatically initializes the agp aperture during POST. 580 * Use the memory already set aside for in the GTT. 581 */ 582 static int intel_i830_create_gatt_table(struct agp_bridge_data *bridge) 583 { 584 int page_order; 585 struct aper_size_info_fixed *size; 586 int num_entries; 587 u32 temp; 588 589 size = agp_bridge->current_size; 590 page_order = size->page_order; 591 num_entries = size->num_entries; 592 agp_bridge->gatt_table_real = NULL; 593 594 pci_read_config_dword(intel_private.pcidev,I810_MMADDR,&temp); 595 temp &= 0xfff80000; 596 597 intel_private.registers = ioremap(temp,128 * 4096); 598 if (!intel_private.registers) 599 return -ENOMEM; 600 601 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000; 602 global_cache_flush(); /* FIXME: ?? */ 603 604 /* we have to call this as early as possible after the MMIO base address is known */ 605 intel_i830_init_gtt_entries(); 606 607 agp_bridge->gatt_table = NULL; 608 609 agp_bridge->gatt_bus_addr = temp; 610 611 return 0; 612 } 613 614 /* Return the gatt table to a sane state. Use the top of stolen 615 * memory for the GTT. 616 */ 617 static int intel_i830_free_gatt_table(struct agp_bridge_data *bridge) 618 { 619 return 0; 620 } 621 622 static int intel_i830_fetch_size(void) 623 { 624 u16 gmch_ctrl; 625 struct aper_size_info_fixed *values; 626 627 values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes); 628 629 if (agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82830_HB && 630 agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82845G_HB) { 631 /* 855GM/852GM/865G has 128MB aperture size */ 632 agp_bridge->previous_size = agp_bridge->current_size = (void *) values; 633 agp_bridge->aperture_size_idx = 0; 634 return values[0].size; 635 } 636 637 pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl); 638 639 if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_128M) { 640 agp_bridge->previous_size = agp_bridge->current_size = (void *) values; 641 agp_bridge->aperture_size_idx = 0; 642 return values[0].size; 643 } else { 644 agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + 1); 645 agp_bridge->aperture_size_idx = 1; 646 return values[1].size; 647 } 648 649 return 0; 650 } 651 652 static int intel_i830_configure(void) 653 { 654 struct aper_size_info_fixed *current_size; 655 u32 temp; 656 u16 gmch_ctrl; 657 int i; 658 659 current_size = A_SIZE_FIX(agp_bridge->current_size); 660 661 pci_read_config_dword(intel_private.pcidev,I810_GMADDR,&temp); 662 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 663 664 pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl); 665 gmch_ctrl |= I830_GMCH_ENABLED; 666 pci_write_config_word(agp_bridge->dev,I830_GMCH_CTRL,gmch_ctrl); 667 668 writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL); 669 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */ 670 671 if (agp_bridge->driver->needs_scratch_page) { 672 for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) { 673 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4)); 674 readl(intel_private.registers+I810_PTE_BASE+(i*4)); /* PCI Posting. */ 675 } 676 } 677 678 global_cache_flush(); 679 return 0; 680 } 681 682 static void intel_i830_cleanup(void) 683 { 684 iounmap(intel_private.registers); 685 } 686 687 static int intel_i830_insert_entries(struct agp_memory *mem,off_t pg_start, int type) 688 { 689 int i,j,num_entries; 690 void *temp; 691 int ret = -EINVAL; 692 int mask_type; 693 694 if (mem->page_count == 0) 695 goto out; 696 697 temp = agp_bridge->current_size; 698 num_entries = A_SIZE_FIX(temp)->num_entries; 699 700 if (pg_start < intel_private.gtt_entries) { 701 printk (KERN_DEBUG PFX "pg_start == 0x%.8lx,intel_private.gtt_entries == 0x%.8x\n", 702 pg_start,intel_private.gtt_entries); 703 704 printk (KERN_INFO PFX "Trying to insert into local/stolen memory\n"); 705 goto out_err; 706 } 707 708 if ((pg_start + mem->page_count) > num_entries) 709 goto out_err; 710 711 /* The i830 can't check the GTT for entries since its read only, 712 * depend on the caller to make the correct offset decisions. 713 */ 714 715 if (type != mem->type) 716 goto out_err; 717 718 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type); 719 720 if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY && 721 mask_type != INTEL_AGP_CACHED_MEMORY) 722 goto out_err; 723 724 if (!mem->is_flushed) 725 global_cache_flush(); 726 727 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { 728 writel(agp_bridge->driver->mask_memory(agp_bridge, 729 mem->memory[i], mask_type), 730 intel_private.registers+I810_PTE_BASE+(j*4)); 731 } 732 readl(intel_private.registers+I810_PTE_BASE+((j-1)*4)); 733 agp_bridge->driver->tlb_flush(mem); 734 735 out: 736 ret = 0; 737 out_err: 738 mem->is_flushed = 1; 739 return ret; 740 } 741 742 static int intel_i830_remove_entries(struct agp_memory *mem,off_t pg_start, 743 int type) 744 { 745 int i; 746 747 if (mem->page_count == 0) 748 return 0; 749 750 if (pg_start < intel_private.gtt_entries) { 751 printk (KERN_INFO PFX "Trying to disable local/stolen memory\n"); 752 return -EINVAL; 753 } 754 755 for (i = pg_start; i < (mem->page_count + pg_start); i++) { 756 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4)); 757 } 758 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); 759 760 agp_bridge->driver->tlb_flush(mem); 761 return 0; 762 } 763 764 static struct agp_memory *intel_i830_alloc_by_type(size_t pg_count,int type) 765 { 766 if (type == AGP_PHYS_MEMORY) 767 return alloc_agpphysmem_i8xx(pg_count, type); 768 /* always return NULL for other allocation types for now */ 769 return NULL; 770 } 771 772 static int intel_i915_configure(void) 773 { 774 struct aper_size_info_fixed *current_size; 775 u32 temp; 776 u16 gmch_ctrl; 777 int i; 778 779 current_size = A_SIZE_FIX(agp_bridge->current_size); 780 781 pci_read_config_dword(intel_private.pcidev, I915_GMADDR, &temp); 782 783 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 784 785 pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl); 786 gmch_ctrl |= I830_GMCH_ENABLED; 787 pci_write_config_word(agp_bridge->dev,I830_GMCH_CTRL,gmch_ctrl); 788 789 writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL); 790 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */ 791 792 if (agp_bridge->driver->needs_scratch_page) { 793 for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) { 794 writel(agp_bridge->scratch_page, intel_private.gtt+i); 795 readl(intel_private.gtt+i); /* PCI Posting. */ 796 } 797 } 798 799 global_cache_flush(); 800 return 0; 801 } 802 803 static void intel_i915_cleanup(void) 804 { 805 iounmap(intel_private.gtt); 806 iounmap(intel_private.registers); 807 } 808 809 static int intel_i915_insert_entries(struct agp_memory *mem,off_t pg_start, 810 int type) 811 { 812 int i,j,num_entries; 813 void *temp; 814 int ret = -EINVAL; 815 int mask_type; 816 817 if (mem->page_count == 0) 818 goto out; 819 820 temp = agp_bridge->current_size; 821 num_entries = A_SIZE_FIX(temp)->num_entries; 822 823 if (pg_start < intel_private.gtt_entries) { 824 printk (KERN_DEBUG PFX "pg_start == 0x%.8lx,intel_private.gtt_entries == 0x%.8x\n", 825 pg_start,intel_private.gtt_entries); 826 827 printk (KERN_INFO PFX "Trying to insert into local/stolen memory\n"); 828 goto out_err; 829 } 830 831 if ((pg_start + mem->page_count) > num_entries) 832 goto out_err; 833 834 /* The i915 can't check the GTT for entries since its read only, 835 * depend on the caller to make the correct offset decisions. 836 */ 837 838 if (type != mem->type) 839 goto out_err; 840 841 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type); 842 843 if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY && 844 mask_type != INTEL_AGP_CACHED_MEMORY) 845 goto out_err; 846 847 if (!mem->is_flushed) 848 global_cache_flush(); 849 850 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { 851 writel(agp_bridge->driver->mask_memory(agp_bridge, 852 mem->memory[i], mask_type), intel_private.gtt+j); 853 } 854 855 readl(intel_private.gtt+j-1); 856 agp_bridge->driver->tlb_flush(mem); 857 858 out: 859 ret = 0; 860 out_err: 861 mem->is_flushed = 1; 862 return ret; 863 } 864 865 static int intel_i915_remove_entries(struct agp_memory *mem,off_t pg_start, 866 int type) 867 { 868 int i; 869 870 if (mem->page_count == 0) 871 return 0; 872 873 if (pg_start < intel_private.gtt_entries) { 874 printk (KERN_INFO PFX "Trying to disable local/stolen memory\n"); 875 return -EINVAL; 876 } 877 878 for (i = pg_start; i < (mem->page_count + pg_start); i++) { 879 writel(agp_bridge->scratch_page, intel_private.gtt+i); 880 } 881 readl(intel_private.gtt+i-1); 882 883 agp_bridge->driver->tlb_flush(mem); 884 return 0; 885 } 886 887 /* Return the aperture size by just checking the resource length. The effect 888 * described in the spec of the MSAC registers is just changing of the 889 * resource size. 890 */ 891 static int intel_i9xx_fetch_size(void) 892 { 893 int num_sizes = ARRAY_SIZE(intel_i830_sizes); 894 int aper_size; /* size in megabytes */ 895 int i; 896 897 aper_size = pci_resource_len(intel_private.pcidev, 2) / MB(1); 898 899 for (i = 0; i < num_sizes; i++) { 900 if (aper_size == intel_i830_sizes[i].size) { 901 agp_bridge->current_size = intel_i830_sizes + i; 902 agp_bridge->previous_size = agp_bridge->current_size; 903 return aper_size; 904 } 905 } 906 907 return 0; 908 } 909 910 /* The intel i915 automatically initializes the agp aperture during POST. 911 * Use the memory already set aside for in the GTT. 912 */ 913 static int intel_i915_create_gatt_table(struct agp_bridge_data *bridge) 914 { 915 int page_order; 916 struct aper_size_info_fixed *size; 917 int num_entries; 918 u32 temp, temp2; 919 int gtt_map_size = 256 * 1024; 920 921 size = agp_bridge->current_size; 922 page_order = size->page_order; 923 num_entries = size->num_entries; 924 agp_bridge->gatt_table_real = NULL; 925 926 pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp); 927 pci_read_config_dword(intel_private.pcidev, I915_PTEADDR,&temp2); 928 929 if (IS_G33) 930 gtt_map_size = 1024 * 1024; /* 1M on G33 */ 931 intel_private.gtt = ioremap(temp2, gtt_map_size); 932 if (!intel_private.gtt) 933 return -ENOMEM; 934 935 temp &= 0xfff80000; 936 937 intel_private.registers = ioremap(temp,128 * 4096); 938 if (!intel_private.registers) { 939 iounmap(intel_private.gtt); 940 return -ENOMEM; 941 } 942 943 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000; 944 global_cache_flush(); /* FIXME: ? */ 945 946 /* we have to call this as early as possible after the MMIO base address is known */ 947 intel_i830_init_gtt_entries(); 948 949 agp_bridge->gatt_table = NULL; 950 951 agp_bridge->gatt_bus_addr = temp; 952 953 return 0; 954 } 955 956 /* 957 * The i965 supports 36-bit physical addresses, but to keep 958 * the format of the GTT the same, the bits that don't fit 959 * in a 32-bit word are shifted down to bits 4..7. 960 * 961 * Gcc is smart enough to notice that "(addr >> 28) & 0xf0" 962 * is always zero on 32-bit architectures, so no need to make 963 * this conditional. 964 */ 965 static unsigned long intel_i965_mask_memory(struct agp_bridge_data *bridge, 966 unsigned long addr, int type) 967 { 968 /* Shift high bits down */ 969 addr |= (addr >> 28) & 0xf0; 970 971 /* Type checking must be done elsewhere */ 972 return addr | bridge->driver->masks[type].mask; 973 } 974 975 /* The intel i965 automatically initializes the agp aperture during POST. 976 * Use the memory already set aside for in the GTT. 977 */ 978 static int intel_i965_create_gatt_table(struct agp_bridge_data *bridge) 979 { 980 int page_order; 981 struct aper_size_info_fixed *size; 982 int num_entries; 983 u32 temp; 984 985 size = agp_bridge->current_size; 986 page_order = size->page_order; 987 num_entries = size->num_entries; 988 agp_bridge->gatt_table_real = NULL; 989 990 pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp); 991 992 temp &= 0xfff00000; 993 intel_private.gtt = ioremap((temp + (512 * 1024)) , 512 * 1024); 994 995 if (!intel_private.gtt) 996 return -ENOMEM; 997 998 999 intel_private.registers = ioremap(temp,128 * 4096); 1000 if (!intel_private.registers) { 1001 iounmap(intel_private.gtt); 1002 return -ENOMEM; 1003 } 1004 1005 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000; 1006 global_cache_flush(); /* FIXME: ? */ 1007 1008 /* we have to call this as early as possible after the MMIO base address is known */ 1009 intel_i830_init_gtt_entries(); 1010 1011 agp_bridge->gatt_table = NULL; 1012 1013 agp_bridge->gatt_bus_addr = temp; 1014 1015 return 0; 1016 } 1017 1018 1019 static int intel_fetch_size(void) 1020 { 1021 int i; 1022 u16 temp; 1023 struct aper_size_info_16 *values; 1024 1025 pci_read_config_word(agp_bridge->dev, INTEL_APSIZE, &temp); 1026 values = A_SIZE_16(agp_bridge->driver->aperture_sizes); 1027 1028 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) { 1029 if (temp == values[i].size_value) { 1030 agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + i); 1031 agp_bridge->aperture_size_idx = i; 1032 return values[i].size; 1033 } 1034 } 1035 1036 return 0; 1037 } 1038 1039 static int __intel_8xx_fetch_size(u8 temp) 1040 { 1041 int i; 1042 struct aper_size_info_8 *values; 1043 1044 values = A_SIZE_8(agp_bridge->driver->aperture_sizes); 1045 1046 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) { 1047 if (temp == values[i].size_value) { 1048 agp_bridge->previous_size = 1049 agp_bridge->current_size = (void *) (values + i); 1050 agp_bridge->aperture_size_idx = i; 1051 return values[i].size; 1052 } 1053 } 1054 return 0; 1055 } 1056 1057 static int intel_8xx_fetch_size(void) 1058 { 1059 u8 temp; 1060 1061 pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp); 1062 return __intel_8xx_fetch_size(temp); 1063 } 1064 1065 static int intel_815_fetch_size(void) 1066 { 1067 u8 temp; 1068 1069 /* Intel 815 chipsets have a _weird_ APSIZE register with only 1070 * one non-reserved bit, so mask the others out ... */ 1071 pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp); 1072 temp &= (1 << 3); 1073 1074 return __intel_8xx_fetch_size(temp); 1075 } 1076 1077 static void intel_tlbflush(struct agp_memory *mem) 1078 { 1079 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2200); 1080 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280); 1081 } 1082 1083 1084 static void intel_8xx_tlbflush(struct agp_memory *mem) 1085 { 1086 u32 temp; 1087 pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp); 1088 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp & ~(1 << 7)); 1089 pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp); 1090 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp | (1 << 7)); 1091 } 1092 1093 1094 static void intel_cleanup(void) 1095 { 1096 u16 temp; 1097 struct aper_size_info_16 *previous_size; 1098 1099 previous_size = A_SIZE_16(agp_bridge->previous_size); 1100 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp); 1101 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9)); 1102 pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value); 1103 } 1104 1105 1106 static void intel_8xx_cleanup(void) 1107 { 1108 u16 temp; 1109 struct aper_size_info_8 *previous_size; 1110 1111 previous_size = A_SIZE_8(agp_bridge->previous_size); 1112 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp); 1113 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9)); 1114 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value); 1115 } 1116 1117 1118 static int intel_configure(void) 1119 { 1120 u32 temp; 1121 u16 temp2; 1122 struct aper_size_info_16 *current_size; 1123 1124 current_size = A_SIZE_16(agp_bridge->current_size); 1125 1126 /* aperture size */ 1127 pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 1128 1129 /* address to map to */ 1130 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 1131 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1132 1133 /* attbase - aperture base */ 1134 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); 1135 1136 /* agpctrl */ 1137 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280); 1138 1139 /* paccfg/nbxcfg */ 1140 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2); 1141 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, 1142 (temp2 & ~(1 << 10)) | (1 << 9)); 1143 /* clear any possible error conditions */ 1144 pci_write_config_byte(agp_bridge->dev, INTEL_ERRSTS + 1, 7); 1145 return 0; 1146 } 1147 1148 static int intel_815_configure(void) 1149 { 1150 u32 temp, addr; 1151 u8 temp2; 1152 struct aper_size_info_8 *current_size; 1153 1154 /* attbase - aperture base */ 1155 /* the Intel 815 chipset spec. says that bits 29-31 in the 1156 * ATTBASE register are reserved -> try not to write them */ 1157 if (agp_bridge->gatt_bus_addr & INTEL_815_ATTBASE_MASK) { 1158 printk (KERN_EMERG PFX "gatt bus addr too high"); 1159 return -EINVAL; 1160 } 1161 1162 current_size = A_SIZE_8(agp_bridge->current_size); 1163 1164 /* aperture size */ 1165 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, 1166 current_size->size_value); 1167 1168 /* address to map to */ 1169 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 1170 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1171 1172 pci_read_config_dword(agp_bridge->dev, INTEL_ATTBASE, &addr); 1173 addr &= INTEL_815_ATTBASE_MASK; 1174 addr |= agp_bridge->gatt_bus_addr; 1175 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, addr); 1176 1177 /* agpctrl */ 1178 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); 1179 1180 /* apcont */ 1181 pci_read_config_byte(agp_bridge->dev, INTEL_815_APCONT, &temp2); 1182 pci_write_config_byte(agp_bridge->dev, INTEL_815_APCONT, temp2 | (1 << 1)); 1183 1184 /* clear any possible error conditions */ 1185 /* Oddness : this chipset seems to have no ERRSTS register ! */ 1186 return 0; 1187 } 1188 1189 static void intel_820_tlbflush(struct agp_memory *mem) 1190 { 1191 return; 1192 } 1193 1194 static void intel_820_cleanup(void) 1195 { 1196 u8 temp; 1197 struct aper_size_info_8 *previous_size; 1198 1199 previous_size = A_SIZE_8(agp_bridge->previous_size); 1200 pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp); 1201 pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR, 1202 temp & ~(1 << 1)); 1203 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, 1204 previous_size->size_value); 1205 } 1206 1207 1208 static int intel_820_configure(void) 1209 { 1210 u32 temp; 1211 u8 temp2; 1212 struct aper_size_info_8 *current_size; 1213 1214 current_size = A_SIZE_8(agp_bridge->current_size); 1215 1216 /* aperture size */ 1217 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 1218 1219 /* address to map to */ 1220 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 1221 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1222 1223 /* attbase - aperture base */ 1224 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); 1225 1226 /* agpctrl */ 1227 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); 1228 1229 /* global enable aperture access */ 1230 /* This flag is not accessed through MCHCFG register as in */ 1231 /* i850 chipset. */ 1232 pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp2); 1233 pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR, temp2 | (1 << 1)); 1234 /* clear any possible AGP-related error conditions */ 1235 pci_write_config_word(agp_bridge->dev, INTEL_I820_ERRSTS, 0x001c); 1236 return 0; 1237 } 1238 1239 static int intel_840_configure(void) 1240 { 1241 u32 temp; 1242 u16 temp2; 1243 struct aper_size_info_8 *current_size; 1244 1245 current_size = A_SIZE_8(agp_bridge->current_size); 1246 1247 /* aperture size */ 1248 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 1249 1250 /* address to map to */ 1251 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 1252 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1253 1254 /* attbase - aperture base */ 1255 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); 1256 1257 /* agpctrl */ 1258 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); 1259 1260 /* mcgcfg */ 1261 pci_read_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, &temp2); 1262 pci_write_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, temp2 | (1 << 9)); 1263 /* clear any possible error conditions */ 1264 pci_write_config_word(agp_bridge->dev, INTEL_I840_ERRSTS, 0xc000); 1265 return 0; 1266 } 1267 1268 static int intel_845_configure(void) 1269 { 1270 u32 temp; 1271 u8 temp2; 1272 struct aper_size_info_8 *current_size; 1273 1274 current_size = A_SIZE_8(agp_bridge->current_size); 1275 1276 /* aperture size */ 1277 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 1278 1279 if (agp_bridge->apbase_config != 0) { 1280 pci_write_config_dword(agp_bridge->dev, AGP_APBASE, 1281 agp_bridge->apbase_config); 1282 } else { 1283 /* address to map to */ 1284 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 1285 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1286 agp_bridge->apbase_config = temp; 1287 } 1288 1289 /* attbase - aperture base */ 1290 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); 1291 1292 /* agpctrl */ 1293 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); 1294 1295 /* agpm */ 1296 pci_read_config_byte(agp_bridge->dev, INTEL_I845_AGPM, &temp2); 1297 pci_write_config_byte(agp_bridge->dev, INTEL_I845_AGPM, temp2 | (1 << 1)); 1298 /* clear any possible error conditions */ 1299 pci_write_config_word(agp_bridge->dev, INTEL_I845_ERRSTS, 0x001c); 1300 return 0; 1301 } 1302 1303 static int intel_850_configure(void) 1304 { 1305 u32 temp; 1306 u16 temp2; 1307 struct aper_size_info_8 *current_size; 1308 1309 current_size = A_SIZE_8(agp_bridge->current_size); 1310 1311 /* aperture size */ 1312 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 1313 1314 /* address to map to */ 1315 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 1316 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1317 1318 /* attbase - aperture base */ 1319 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); 1320 1321 /* agpctrl */ 1322 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); 1323 1324 /* mcgcfg */ 1325 pci_read_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, &temp2); 1326 pci_write_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, temp2 | (1 << 9)); 1327 /* clear any possible AGP-related error conditions */ 1328 pci_write_config_word(agp_bridge->dev, INTEL_I850_ERRSTS, 0x001c); 1329 return 0; 1330 } 1331 1332 static int intel_860_configure(void) 1333 { 1334 u32 temp; 1335 u16 temp2; 1336 struct aper_size_info_8 *current_size; 1337 1338 current_size = A_SIZE_8(agp_bridge->current_size); 1339 1340 /* aperture size */ 1341 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 1342 1343 /* address to map to */ 1344 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 1345 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1346 1347 /* attbase - aperture base */ 1348 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); 1349 1350 /* agpctrl */ 1351 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); 1352 1353 /* mcgcfg */ 1354 pci_read_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, &temp2); 1355 pci_write_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, temp2 | (1 << 9)); 1356 /* clear any possible AGP-related error conditions */ 1357 pci_write_config_word(agp_bridge->dev, INTEL_I860_ERRSTS, 0xf700); 1358 return 0; 1359 } 1360 1361 static int intel_830mp_configure(void) 1362 { 1363 u32 temp; 1364 u16 temp2; 1365 struct aper_size_info_8 *current_size; 1366 1367 current_size = A_SIZE_8(agp_bridge->current_size); 1368 1369 /* aperture size */ 1370 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 1371 1372 /* address to map to */ 1373 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 1374 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1375 1376 /* attbase - aperture base */ 1377 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); 1378 1379 /* agpctrl */ 1380 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); 1381 1382 /* gmch */ 1383 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2); 1384 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp2 | (1 << 9)); 1385 /* clear any possible AGP-related error conditions */ 1386 pci_write_config_word(agp_bridge->dev, INTEL_I830_ERRSTS, 0x1c); 1387 return 0; 1388 } 1389 1390 static int intel_7505_configure(void) 1391 { 1392 u32 temp; 1393 u16 temp2; 1394 struct aper_size_info_8 *current_size; 1395 1396 current_size = A_SIZE_8(agp_bridge->current_size); 1397 1398 /* aperture size */ 1399 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 1400 1401 /* address to map to */ 1402 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 1403 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1404 1405 /* attbase - aperture base */ 1406 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); 1407 1408 /* agpctrl */ 1409 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); 1410 1411 /* mchcfg */ 1412 pci_read_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, &temp2); 1413 pci_write_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, temp2 | (1 << 9)); 1414 1415 return 0; 1416 } 1417 1418 /* Setup function */ 1419 static const struct gatt_mask intel_generic_masks[] = 1420 { 1421 {.mask = 0x00000017, .type = 0} 1422 }; 1423 1424 static const struct aper_size_info_8 intel_815_sizes[2] = 1425 { 1426 {64, 16384, 4, 0}, 1427 {32, 8192, 3, 8}, 1428 }; 1429 1430 static const struct aper_size_info_8 intel_8xx_sizes[7] = 1431 { 1432 {256, 65536, 6, 0}, 1433 {128, 32768, 5, 32}, 1434 {64, 16384, 4, 48}, 1435 {32, 8192, 3, 56}, 1436 {16, 4096, 2, 60}, 1437 {8, 2048, 1, 62}, 1438 {4, 1024, 0, 63} 1439 }; 1440 1441 static const struct aper_size_info_16 intel_generic_sizes[7] = 1442 { 1443 {256, 65536, 6, 0}, 1444 {128, 32768, 5, 32}, 1445 {64, 16384, 4, 48}, 1446 {32, 8192, 3, 56}, 1447 {16, 4096, 2, 60}, 1448 {8, 2048, 1, 62}, 1449 {4, 1024, 0, 63} 1450 }; 1451 1452 static const struct aper_size_info_8 intel_830mp_sizes[4] = 1453 { 1454 {256, 65536, 6, 0}, 1455 {128, 32768, 5, 32}, 1456 {64, 16384, 4, 48}, 1457 {32, 8192, 3, 56} 1458 }; 1459 1460 static const struct agp_bridge_driver intel_generic_driver = { 1461 .owner = THIS_MODULE, 1462 .aperture_sizes = intel_generic_sizes, 1463 .size_type = U16_APER_SIZE, 1464 .num_aperture_sizes = 7, 1465 .configure = intel_configure, 1466 .fetch_size = intel_fetch_size, 1467 .cleanup = intel_cleanup, 1468 .tlb_flush = intel_tlbflush, 1469 .mask_memory = agp_generic_mask_memory, 1470 .masks = intel_generic_masks, 1471 .agp_enable = agp_generic_enable, 1472 .cache_flush = global_cache_flush, 1473 .create_gatt_table = agp_generic_create_gatt_table, 1474 .free_gatt_table = agp_generic_free_gatt_table, 1475 .insert_memory = agp_generic_insert_memory, 1476 .remove_memory = agp_generic_remove_memory, 1477 .alloc_by_type = agp_generic_alloc_by_type, 1478 .free_by_type = agp_generic_free_by_type, 1479 .agp_alloc_page = agp_generic_alloc_page, 1480 .agp_destroy_page = agp_generic_destroy_page, 1481 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 1482 }; 1483 1484 static const struct agp_bridge_driver intel_810_driver = { 1485 .owner = THIS_MODULE, 1486 .aperture_sizes = intel_i810_sizes, 1487 .size_type = FIXED_APER_SIZE, 1488 .num_aperture_sizes = 2, 1489 .needs_scratch_page = TRUE, 1490 .configure = intel_i810_configure, 1491 .fetch_size = intel_i810_fetch_size, 1492 .cleanup = intel_i810_cleanup, 1493 .tlb_flush = intel_i810_tlbflush, 1494 .mask_memory = intel_i810_mask_memory, 1495 .masks = intel_i810_masks, 1496 .agp_enable = intel_i810_agp_enable, 1497 .cache_flush = global_cache_flush, 1498 .create_gatt_table = agp_generic_create_gatt_table, 1499 .free_gatt_table = agp_generic_free_gatt_table, 1500 .insert_memory = intel_i810_insert_entries, 1501 .remove_memory = intel_i810_remove_entries, 1502 .alloc_by_type = intel_i810_alloc_by_type, 1503 .free_by_type = intel_i810_free_by_type, 1504 .agp_alloc_page = agp_generic_alloc_page, 1505 .agp_destroy_page = agp_generic_destroy_page, 1506 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 1507 }; 1508 1509 static const struct agp_bridge_driver intel_815_driver = { 1510 .owner = THIS_MODULE, 1511 .aperture_sizes = intel_815_sizes, 1512 .size_type = U8_APER_SIZE, 1513 .num_aperture_sizes = 2, 1514 .configure = intel_815_configure, 1515 .fetch_size = intel_815_fetch_size, 1516 .cleanup = intel_8xx_cleanup, 1517 .tlb_flush = intel_8xx_tlbflush, 1518 .mask_memory = agp_generic_mask_memory, 1519 .masks = intel_generic_masks, 1520 .agp_enable = agp_generic_enable, 1521 .cache_flush = global_cache_flush, 1522 .create_gatt_table = agp_generic_create_gatt_table, 1523 .free_gatt_table = agp_generic_free_gatt_table, 1524 .insert_memory = agp_generic_insert_memory, 1525 .remove_memory = agp_generic_remove_memory, 1526 .alloc_by_type = agp_generic_alloc_by_type, 1527 .free_by_type = agp_generic_free_by_type, 1528 .agp_alloc_page = agp_generic_alloc_page, 1529 .agp_destroy_page = agp_generic_destroy_page, 1530 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 1531 }; 1532 1533 static const struct agp_bridge_driver intel_830_driver = { 1534 .owner = THIS_MODULE, 1535 .aperture_sizes = intel_i830_sizes, 1536 .size_type = FIXED_APER_SIZE, 1537 .num_aperture_sizes = 4, 1538 .needs_scratch_page = TRUE, 1539 .configure = intel_i830_configure, 1540 .fetch_size = intel_i830_fetch_size, 1541 .cleanup = intel_i830_cleanup, 1542 .tlb_flush = intel_i810_tlbflush, 1543 .mask_memory = intel_i810_mask_memory, 1544 .masks = intel_i810_masks, 1545 .agp_enable = intel_i810_agp_enable, 1546 .cache_flush = global_cache_flush, 1547 .create_gatt_table = intel_i830_create_gatt_table, 1548 .free_gatt_table = intel_i830_free_gatt_table, 1549 .insert_memory = intel_i830_insert_entries, 1550 .remove_memory = intel_i830_remove_entries, 1551 .alloc_by_type = intel_i830_alloc_by_type, 1552 .free_by_type = intel_i810_free_by_type, 1553 .agp_alloc_page = agp_generic_alloc_page, 1554 .agp_destroy_page = agp_generic_destroy_page, 1555 .agp_type_to_mask_type = intel_i830_type_to_mask_type, 1556 }; 1557 1558 static const struct agp_bridge_driver intel_820_driver = { 1559 .owner = THIS_MODULE, 1560 .aperture_sizes = intel_8xx_sizes, 1561 .size_type = U8_APER_SIZE, 1562 .num_aperture_sizes = 7, 1563 .configure = intel_820_configure, 1564 .fetch_size = intel_8xx_fetch_size, 1565 .cleanup = intel_820_cleanup, 1566 .tlb_flush = intel_820_tlbflush, 1567 .mask_memory = agp_generic_mask_memory, 1568 .masks = intel_generic_masks, 1569 .agp_enable = agp_generic_enable, 1570 .cache_flush = global_cache_flush, 1571 .create_gatt_table = agp_generic_create_gatt_table, 1572 .free_gatt_table = agp_generic_free_gatt_table, 1573 .insert_memory = agp_generic_insert_memory, 1574 .remove_memory = agp_generic_remove_memory, 1575 .alloc_by_type = agp_generic_alloc_by_type, 1576 .free_by_type = agp_generic_free_by_type, 1577 .agp_alloc_page = agp_generic_alloc_page, 1578 .agp_destroy_page = agp_generic_destroy_page, 1579 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 1580 }; 1581 1582 static const struct agp_bridge_driver intel_830mp_driver = { 1583 .owner = THIS_MODULE, 1584 .aperture_sizes = intel_830mp_sizes, 1585 .size_type = U8_APER_SIZE, 1586 .num_aperture_sizes = 4, 1587 .configure = intel_830mp_configure, 1588 .fetch_size = intel_8xx_fetch_size, 1589 .cleanup = intel_8xx_cleanup, 1590 .tlb_flush = intel_8xx_tlbflush, 1591 .mask_memory = agp_generic_mask_memory, 1592 .masks = intel_generic_masks, 1593 .agp_enable = agp_generic_enable, 1594 .cache_flush = global_cache_flush, 1595 .create_gatt_table = agp_generic_create_gatt_table, 1596 .free_gatt_table = agp_generic_free_gatt_table, 1597 .insert_memory = agp_generic_insert_memory, 1598 .remove_memory = agp_generic_remove_memory, 1599 .alloc_by_type = agp_generic_alloc_by_type, 1600 .free_by_type = agp_generic_free_by_type, 1601 .agp_alloc_page = agp_generic_alloc_page, 1602 .agp_destroy_page = agp_generic_destroy_page, 1603 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 1604 }; 1605 1606 static const struct agp_bridge_driver intel_840_driver = { 1607 .owner = THIS_MODULE, 1608 .aperture_sizes = intel_8xx_sizes, 1609 .size_type = U8_APER_SIZE, 1610 .num_aperture_sizes = 7, 1611 .configure = intel_840_configure, 1612 .fetch_size = intel_8xx_fetch_size, 1613 .cleanup = intel_8xx_cleanup, 1614 .tlb_flush = intel_8xx_tlbflush, 1615 .mask_memory = agp_generic_mask_memory, 1616 .masks = intel_generic_masks, 1617 .agp_enable = agp_generic_enable, 1618 .cache_flush = global_cache_flush, 1619 .create_gatt_table = agp_generic_create_gatt_table, 1620 .free_gatt_table = agp_generic_free_gatt_table, 1621 .insert_memory = agp_generic_insert_memory, 1622 .remove_memory = agp_generic_remove_memory, 1623 .alloc_by_type = agp_generic_alloc_by_type, 1624 .free_by_type = agp_generic_free_by_type, 1625 .agp_alloc_page = agp_generic_alloc_page, 1626 .agp_destroy_page = agp_generic_destroy_page, 1627 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 1628 }; 1629 1630 static const struct agp_bridge_driver intel_845_driver = { 1631 .owner = THIS_MODULE, 1632 .aperture_sizes = intel_8xx_sizes, 1633 .size_type = U8_APER_SIZE, 1634 .num_aperture_sizes = 7, 1635 .configure = intel_845_configure, 1636 .fetch_size = intel_8xx_fetch_size, 1637 .cleanup = intel_8xx_cleanup, 1638 .tlb_flush = intel_8xx_tlbflush, 1639 .mask_memory = agp_generic_mask_memory, 1640 .masks = intel_generic_masks, 1641 .agp_enable = agp_generic_enable, 1642 .cache_flush = global_cache_flush, 1643 .create_gatt_table = agp_generic_create_gatt_table, 1644 .free_gatt_table = agp_generic_free_gatt_table, 1645 .insert_memory = agp_generic_insert_memory, 1646 .remove_memory = agp_generic_remove_memory, 1647 .alloc_by_type = agp_generic_alloc_by_type, 1648 .free_by_type = agp_generic_free_by_type, 1649 .agp_alloc_page = agp_generic_alloc_page, 1650 .agp_destroy_page = agp_generic_destroy_page, 1651 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 1652 }; 1653 1654 static const struct agp_bridge_driver intel_850_driver = { 1655 .owner = THIS_MODULE, 1656 .aperture_sizes = intel_8xx_sizes, 1657 .size_type = U8_APER_SIZE, 1658 .num_aperture_sizes = 7, 1659 .configure = intel_850_configure, 1660 .fetch_size = intel_8xx_fetch_size, 1661 .cleanup = intel_8xx_cleanup, 1662 .tlb_flush = intel_8xx_tlbflush, 1663 .mask_memory = agp_generic_mask_memory, 1664 .masks = intel_generic_masks, 1665 .agp_enable = agp_generic_enable, 1666 .cache_flush = global_cache_flush, 1667 .create_gatt_table = agp_generic_create_gatt_table, 1668 .free_gatt_table = agp_generic_free_gatt_table, 1669 .insert_memory = agp_generic_insert_memory, 1670 .remove_memory = agp_generic_remove_memory, 1671 .alloc_by_type = agp_generic_alloc_by_type, 1672 .free_by_type = agp_generic_free_by_type, 1673 .agp_alloc_page = agp_generic_alloc_page, 1674 .agp_destroy_page = agp_generic_destroy_page, 1675 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 1676 }; 1677 1678 static const struct agp_bridge_driver intel_860_driver = { 1679 .owner = THIS_MODULE, 1680 .aperture_sizes = intel_8xx_sizes, 1681 .size_type = U8_APER_SIZE, 1682 .num_aperture_sizes = 7, 1683 .configure = intel_860_configure, 1684 .fetch_size = intel_8xx_fetch_size, 1685 .cleanup = intel_8xx_cleanup, 1686 .tlb_flush = intel_8xx_tlbflush, 1687 .mask_memory = agp_generic_mask_memory, 1688 .masks = intel_generic_masks, 1689 .agp_enable = agp_generic_enable, 1690 .cache_flush = global_cache_flush, 1691 .create_gatt_table = agp_generic_create_gatt_table, 1692 .free_gatt_table = agp_generic_free_gatt_table, 1693 .insert_memory = agp_generic_insert_memory, 1694 .remove_memory = agp_generic_remove_memory, 1695 .alloc_by_type = agp_generic_alloc_by_type, 1696 .free_by_type = agp_generic_free_by_type, 1697 .agp_alloc_page = agp_generic_alloc_page, 1698 .agp_destroy_page = agp_generic_destroy_page, 1699 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 1700 }; 1701 1702 static const struct agp_bridge_driver intel_915_driver = { 1703 .owner = THIS_MODULE, 1704 .aperture_sizes = intel_i830_sizes, 1705 .size_type = FIXED_APER_SIZE, 1706 .num_aperture_sizes = 4, 1707 .needs_scratch_page = TRUE, 1708 .configure = intel_i915_configure, 1709 .fetch_size = intel_i9xx_fetch_size, 1710 .cleanup = intel_i915_cleanup, 1711 .tlb_flush = intel_i810_tlbflush, 1712 .mask_memory = intel_i810_mask_memory, 1713 .masks = intel_i810_masks, 1714 .agp_enable = intel_i810_agp_enable, 1715 .cache_flush = global_cache_flush, 1716 .create_gatt_table = intel_i915_create_gatt_table, 1717 .free_gatt_table = intel_i830_free_gatt_table, 1718 .insert_memory = intel_i915_insert_entries, 1719 .remove_memory = intel_i915_remove_entries, 1720 .alloc_by_type = intel_i830_alloc_by_type, 1721 .free_by_type = intel_i810_free_by_type, 1722 .agp_alloc_page = agp_generic_alloc_page, 1723 .agp_destroy_page = agp_generic_destroy_page, 1724 .agp_type_to_mask_type = intel_i830_type_to_mask_type, 1725 }; 1726 1727 static const struct agp_bridge_driver intel_i965_driver = { 1728 .owner = THIS_MODULE, 1729 .aperture_sizes = intel_i830_sizes, 1730 .size_type = FIXED_APER_SIZE, 1731 .num_aperture_sizes = 4, 1732 .needs_scratch_page = TRUE, 1733 .configure = intel_i915_configure, 1734 .fetch_size = intel_i9xx_fetch_size, 1735 .cleanup = intel_i915_cleanup, 1736 .tlb_flush = intel_i810_tlbflush, 1737 .mask_memory = intel_i965_mask_memory, 1738 .masks = intel_i810_masks, 1739 .agp_enable = intel_i810_agp_enable, 1740 .cache_flush = global_cache_flush, 1741 .create_gatt_table = intel_i965_create_gatt_table, 1742 .free_gatt_table = intel_i830_free_gatt_table, 1743 .insert_memory = intel_i915_insert_entries, 1744 .remove_memory = intel_i915_remove_entries, 1745 .alloc_by_type = intel_i830_alloc_by_type, 1746 .free_by_type = intel_i810_free_by_type, 1747 .agp_alloc_page = agp_generic_alloc_page, 1748 .agp_destroy_page = agp_generic_destroy_page, 1749 .agp_type_to_mask_type = intel_i830_type_to_mask_type, 1750 }; 1751 1752 static const struct agp_bridge_driver intel_7505_driver = { 1753 .owner = THIS_MODULE, 1754 .aperture_sizes = intel_8xx_sizes, 1755 .size_type = U8_APER_SIZE, 1756 .num_aperture_sizes = 7, 1757 .configure = intel_7505_configure, 1758 .fetch_size = intel_8xx_fetch_size, 1759 .cleanup = intel_8xx_cleanup, 1760 .tlb_flush = intel_8xx_tlbflush, 1761 .mask_memory = agp_generic_mask_memory, 1762 .masks = intel_generic_masks, 1763 .agp_enable = agp_generic_enable, 1764 .cache_flush = global_cache_flush, 1765 .create_gatt_table = agp_generic_create_gatt_table, 1766 .free_gatt_table = agp_generic_free_gatt_table, 1767 .insert_memory = agp_generic_insert_memory, 1768 .remove_memory = agp_generic_remove_memory, 1769 .alloc_by_type = agp_generic_alloc_by_type, 1770 .free_by_type = agp_generic_free_by_type, 1771 .agp_alloc_page = agp_generic_alloc_page, 1772 .agp_destroy_page = agp_generic_destroy_page, 1773 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 1774 }; 1775 1776 static const struct agp_bridge_driver intel_g33_driver = { 1777 .owner = THIS_MODULE, 1778 .aperture_sizes = intel_i830_sizes, 1779 .size_type = FIXED_APER_SIZE, 1780 .num_aperture_sizes = 4, 1781 .needs_scratch_page = TRUE, 1782 .configure = intel_i915_configure, 1783 .fetch_size = intel_i9xx_fetch_size, 1784 .cleanup = intel_i915_cleanup, 1785 .tlb_flush = intel_i810_tlbflush, 1786 .mask_memory = intel_i965_mask_memory, 1787 .masks = intel_i810_masks, 1788 .agp_enable = intel_i810_agp_enable, 1789 .cache_flush = global_cache_flush, 1790 .create_gatt_table = intel_i915_create_gatt_table, 1791 .free_gatt_table = intel_i830_free_gatt_table, 1792 .insert_memory = intel_i915_insert_entries, 1793 .remove_memory = intel_i915_remove_entries, 1794 .alloc_by_type = intel_i830_alloc_by_type, 1795 .free_by_type = intel_i810_free_by_type, 1796 .agp_alloc_page = agp_generic_alloc_page, 1797 .agp_destroy_page = agp_generic_destroy_page, 1798 .agp_type_to_mask_type = intel_i830_type_to_mask_type, 1799 }; 1800 1801 static int find_gmch(u16 device) 1802 { 1803 struct pci_dev *gmch_device; 1804 1805 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL); 1806 if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) { 1807 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, 1808 device, gmch_device); 1809 } 1810 1811 if (!gmch_device) 1812 return 0; 1813 1814 intel_private.pcidev = gmch_device; 1815 return 1; 1816 } 1817 1818 /* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of 1819 * driver and gmch_driver must be non-null, and find_gmch will determine 1820 * which one should be used if a gmch_chip_id is present. 1821 */ 1822 static const struct intel_driver_description { 1823 unsigned int chip_id; 1824 unsigned int gmch_chip_id; 1825 unsigned int multi_gmch_chip; /* if we have more gfx chip type on this HB. */ 1826 char *name; 1827 const struct agp_bridge_driver *driver; 1828 const struct agp_bridge_driver *gmch_driver; 1829 } intel_agp_chipsets[] = { 1830 { PCI_DEVICE_ID_INTEL_82443LX_0, 0, 0, "440LX", &intel_generic_driver, NULL }, 1831 { PCI_DEVICE_ID_INTEL_82443BX_0, 0, 0, "440BX", &intel_generic_driver, NULL }, 1832 { PCI_DEVICE_ID_INTEL_82443GX_0, 0, 0, "440GX", &intel_generic_driver, NULL }, 1833 { PCI_DEVICE_ID_INTEL_82810_MC1, PCI_DEVICE_ID_INTEL_82810_IG1, 0, "i810", 1834 NULL, &intel_810_driver }, 1835 { PCI_DEVICE_ID_INTEL_82810_MC3, PCI_DEVICE_ID_INTEL_82810_IG3, 0, "i810", 1836 NULL, &intel_810_driver }, 1837 { PCI_DEVICE_ID_INTEL_82810E_MC, PCI_DEVICE_ID_INTEL_82810E_IG, 0, "i810", 1838 NULL, &intel_810_driver }, 1839 { PCI_DEVICE_ID_INTEL_82815_MC, PCI_DEVICE_ID_INTEL_82815_CGC, 0, "i815", 1840 &intel_815_driver, &intel_810_driver }, 1841 { PCI_DEVICE_ID_INTEL_82820_HB, 0, 0, "i820", &intel_820_driver, NULL }, 1842 { PCI_DEVICE_ID_INTEL_82820_UP_HB, 0, 0, "i820", &intel_820_driver, NULL }, 1843 { PCI_DEVICE_ID_INTEL_82830_HB, PCI_DEVICE_ID_INTEL_82830_CGC, 0, "830M", 1844 &intel_830mp_driver, &intel_830_driver }, 1845 { PCI_DEVICE_ID_INTEL_82840_HB, 0, 0, "i840", &intel_840_driver, NULL }, 1846 { PCI_DEVICE_ID_INTEL_82845_HB, 0, 0, "845G", &intel_845_driver, NULL }, 1847 { PCI_DEVICE_ID_INTEL_82845G_HB, PCI_DEVICE_ID_INTEL_82845G_IG, 0, "830M", 1848 &intel_845_driver, &intel_830_driver }, 1849 { PCI_DEVICE_ID_INTEL_82850_HB, 0, 0, "i850", &intel_850_driver, NULL }, 1850 { PCI_DEVICE_ID_INTEL_82855PM_HB, 0, 0, "855PM", &intel_845_driver, NULL }, 1851 { PCI_DEVICE_ID_INTEL_82855GM_HB, PCI_DEVICE_ID_INTEL_82855GM_IG, 0, "855GM", 1852 &intel_845_driver, &intel_830_driver }, 1853 { PCI_DEVICE_ID_INTEL_82860_HB, 0, 0, "i860", &intel_860_driver, NULL }, 1854 { PCI_DEVICE_ID_INTEL_82865_HB, PCI_DEVICE_ID_INTEL_82865_IG, 0, "865", 1855 &intel_845_driver, &intel_830_driver }, 1856 { PCI_DEVICE_ID_INTEL_82875_HB, 0, 0, "i875", &intel_845_driver, NULL }, 1857 { PCI_DEVICE_ID_INTEL_82915G_HB, PCI_DEVICE_ID_INTEL_82915G_IG, 0, "915G", 1858 NULL, &intel_915_driver }, 1859 { PCI_DEVICE_ID_INTEL_82915GM_HB, PCI_DEVICE_ID_INTEL_82915GM_IG, 0, "915GM", 1860 NULL, &intel_915_driver }, 1861 { PCI_DEVICE_ID_INTEL_82945G_HB, PCI_DEVICE_ID_INTEL_82945G_IG, 0, "945G", 1862 NULL, &intel_915_driver }, 1863 { PCI_DEVICE_ID_INTEL_82945GM_HB, PCI_DEVICE_ID_INTEL_82945GM_IG, 0, "945GM", 1864 NULL, &intel_915_driver }, 1865 { PCI_DEVICE_ID_INTEL_82945GME_HB, PCI_DEVICE_ID_INTEL_82945GME_IG, 0, "945GME", 1866 NULL, &intel_915_driver }, 1867 { PCI_DEVICE_ID_INTEL_82946GZ_HB, PCI_DEVICE_ID_INTEL_82946GZ_IG, 0, "946GZ", 1868 NULL, &intel_i965_driver }, 1869 { PCI_DEVICE_ID_INTEL_82965G_1_HB, PCI_DEVICE_ID_INTEL_82965G_1_IG, 0, "965G", 1870 NULL, &intel_i965_driver }, 1871 { PCI_DEVICE_ID_INTEL_82965Q_HB, PCI_DEVICE_ID_INTEL_82965Q_IG, 0, "965Q", 1872 NULL, &intel_i965_driver }, 1873 { PCI_DEVICE_ID_INTEL_82965G_HB, PCI_DEVICE_ID_INTEL_82965G_IG, 0, "965G", 1874 NULL, &intel_i965_driver }, 1875 { PCI_DEVICE_ID_INTEL_82965GM_HB, PCI_DEVICE_ID_INTEL_82965GM_IG, 0, "965GM", 1876 NULL, &intel_i965_driver }, 1877 { PCI_DEVICE_ID_INTEL_82965GME_HB, PCI_DEVICE_ID_INTEL_82965GME_IG, 0, "965GME/GLE", 1878 NULL, &intel_i965_driver }, 1879 { PCI_DEVICE_ID_INTEL_7505_0, 0, 0, "E7505", &intel_7505_driver, NULL }, 1880 { PCI_DEVICE_ID_INTEL_7205_0, 0, 0, "E7205", &intel_7505_driver, NULL }, 1881 { PCI_DEVICE_ID_INTEL_G33_HB, PCI_DEVICE_ID_INTEL_G33_IG, 0, "G33", 1882 NULL, &intel_g33_driver }, 1883 { PCI_DEVICE_ID_INTEL_Q35_HB, PCI_DEVICE_ID_INTEL_Q35_IG, 0, "Q35", 1884 NULL, &intel_g33_driver }, 1885 { PCI_DEVICE_ID_INTEL_Q33_HB, PCI_DEVICE_ID_INTEL_Q33_IG, 0, "Q33", 1886 NULL, &intel_g33_driver }, 1887 { 0, 0, 0, NULL, NULL, NULL } 1888 }; 1889 1890 static int __devinit agp_intel_probe(struct pci_dev *pdev, 1891 const struct pci_device_id *ent) 1892 { 1893 struct agp_bridge_data *bridge; 1894 u8 cap_ptr = 0; 1895 struct resource *r; 1896 int i; 1897 1898 cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP); 1899 1900 bridge = agp_alloc_bridge(); 1901 if (!bridge) 1902 return -ENOMEM; 1903 1904 for (i = 0; intel_agp_chipsets[i].name != NULL; i++) { 1905 /* In case that multiple models of gfx chip may 1906 stand on same host bridge type, this can be 1907 sure we detect the right IGD. */ 1908 if (pdev->device == intel_agp_chipsets[i].chip_id) { 1909 if ((intel_agp_chipsets[i].gmch_chip_id != 0) && 1910 find_gmch(intel_agp_chipsets[i].gmch_chip_id)) { 1911 bridge->driver = 1912 intel_agp_chipsets[i].gmch_driver; 1913 break; 1914 } else if (intel_agp_chipsets[i].multi_gmch_chip) { 1915 continue; 1916 } else { 1917 bridge->driver = intel_agp_chipsets[i].driver; 1918 break; 1919 } 1920 } 1921 } 1922 1923 if (intel_agp_chipsets[i].name == NULL) { 1924 if (cap_ptr) 1925 printk(KERN_WARNING PFX "Unsupported Intel chipset" 1926 "(device id: %04x)\n", pdev->device); 1927 agp_put_bridge(bridge); 1928 return -ENODEV; 1929 } 1930 1931 if (bridge->driver == NULL) { 1932 /* bridge has no AGP and no IGD detected */ 1933 if (cap_ptr) 1934 printk(KERN_WARNING PFX "Failed to find bridge device " 1935 "(chip_id: %04x)\n", 1936 intel_agp_chipsets[i].gmch_chip_id); 1937 agp_put_bridge(bridge); 1938 return -ENODEV; 1939 } 1940 1941 bridge->dev = pdev; 1942 bridge->capndx = cap_ptr; 1943 bridge->dev_private_data = &intel_private; 1944 1945 printk(KERN_INFO PFX "Detected an Intel %s Chipset.\n", 1946 intel_agp_chipsets[i].name); 1947 1948 /* 1949 * The following fixes the case where the BIOS has "forgotten" to 1950 * provide an address range for the GART. 1951 * 20030610 - hamish@zot.org 1952 */ 1953 r = &pdev->resource[0]; 1954 if (!r->start && r->end) { 1955 if (pci_assign_resource(pdev, 0)) { 1956 printk(KERN_ERR PFX "could not assign resource 0\n"); 1957 agp_put_bridge(bridge); 1958 return -ENODEV; 1959 } 1960 } 1961 1962 /* 1963 * If the device has not been properly setup, the following will catch 1964 * the problem and should stop the system from crashing. 1965 * 20030610 - hamish@zot.org 1966 */ 1967 if (pci_enable_device(pdev)) { 1968 printk(KERN_ERR PFX "Unable to Enable PCI device\n"); 1969 agp_put_bridge(bridge); 1970 return -ENODEV; 1971 } 1972 1973 /* Fill in the mode register */ 1974 if (cap_ptr) { 1975 pci_read_config_dword(pdev, 1976 bridge->capndx+PCI_AGP_STATUS, 1977 &bridge->mode); 1978 } 1979 1980 pci_set_drvdata(pdev, bridge); 1981 return agp_add_bridge(bridge); 1982 } 1983 1984 static void __devexit agp_intel_remove(struct pci_dev *pdev) 1985 { 1986 struct agp_bridge_data *bridge = pci_get_drvdata(pdev); 1987 1988 agp_remove_bridge(bridge); 1989 1990 if (intel_private.pcidev) 1991 pci_dev_put(intel_private.pcidev); 1992 1993 agp_put_bridge(bridge); 1994 } 1995 1996 #ifdef CONFIG_PM 1997 static int agp_intel_resume(struct pci_dev *pdev) 1998 { 1999 struct agp_bridge_data *bridge = pci_get_drvdata(pdev); 2000 2001 pci_restore_state(pdev); 2002 2003 /* We should restore our graphics device's config space, 2004 * as host bridge (00:00) resumes before graphics device (02:00), 2005 * then our access to its pci space can work right. 2006 */ 2007 if (intel_private.pcidev) 2008 pci_restore_state(intel_private.pcidev); 2009 2010 if (bridge->driver == &intel_generic_driver) 2011 intel_configure(); 2012 else if (bridge->driver == &intel_850_driver) 2013 intel_850_configure(); 2014 else if (bridge->driver == &intel_845_driver) 2015 intel_845_configure(); 2016 else if (bridge->driver == &intel_830mp_driver) 2017 intel_830mp_configure(); 2018 else if (bridge->driver == &intel_915_driver) 2019 intel_i915_configure(); 2020 else if (bridge->driver == &intel_830_driver) 2021 intel_i830_configure(); 2022 else if (bridge->driver == &intel_810_driver) 2023 intel_i810_configure(); 2024 else if (bridge->driver == &intel_i965_driver) 2025 intel_i915_configure(); 2026 2027 return 0; 2028 } 2029 #endif 2030 2031 static struct pci_device_id agp_intel_pci_table[] = { 2032 #define ID(x) \ 2033 { \ 2034 .class = (PCI_CLASS_BRIDGE_HOST << 8), \ 2035 .class_mask = ~0, \ 2036 .vendor = PCI_VENDOR_ID_INTEL, \ 2037 .device = x, \ 2038 .subvendor = PCI_ANY_ID, \ 2039 .subdevice = PCI_ANY_ID, \ 2040 } 2041 ID(PCI_DEVICE_ID_INTEL_82443LX_0), 2042 ID(PCI_DEVICE_ID_INTEL_82443BX_0), 2043 ID(PCI_DEVICE_ID_INTEL_82443GX_0), 2044 ID(PCI_DEVICE_ID_INTEL_82810_MC1), 2045 ID(PCI_DEVICE_ID_INTEL_82810_MC3), 2046 ID(PCI_DEVICE_ID_INTEL_82810E_MC), 2047 ID(PCI_DEVICE_ID_INTEL_82815_MC), 2048 ID(PCI_DEVICE_ID_INTEL_82820_HB), 2049 ID(PCI_DEVICE_ID_INTEL_82820_UP_HB), 2050 ID(PCI_DEVICE_ID_INTEL_82830_HB), 2051 ID(PCI_DEVICE_ID_INTEL_82840_HB), 2052 ID(PCI_DEVICE_ID_INTEL_82845_HB), 2053 ID(PCI_DEVICE_ID_INTEL_82845G_HB), 2054 ID(PCI_DEVICE_ID_INTEL_82850_HB), 2055 ID(PCI_DEVICE_ID_INTEL_82855PM_HB), 2056 ID(PCI_DEVICE_ID_INTEL_82855GM_HB), 2057 ID(PCI_DEVICE_ID_INTEL_82860_HB), 2058 ID(PCI_DEVICE_ID_INTEL_82865_HB), 2059 ID(PCI_DEVICE_ID_INTEL_82875_HB), 2060 ID(PCI_DEVICE_ID_INTEL_7505_0), 2061 ID(PCI_DEVICE_ID_INTEL_7205_0), 2062 ID(PCI_DEVICE_ID_INTEL_82915G_HB), 2063 ID(PCI_DEVICE_ID_INTEL_82915GM_HB), 2064 ID(PCI_DEVICE_ID_INTEL_82945G_HB), 2065 ID(PCI_DEVICE_ID_INTEL_82945GM_HB), 2066 ID(PCI_DEVICE_ID_INTEL_82945GME_HB), 2067 ID(PCI_DEVICE_ID_INTEL_82946GZ_HB), 2068 ID(PCI_DEVICE_ID_INTEL_82965G_1_HB), 2069 ID(PCI_DEVICE_ID_INTEL_82965Q_HB), 2070 ID(PCI_DEVICE_ID_INTEL_82965G_HB), 2071 ID(PCI_DEVICE_ID_INTEL_82965GM_HB), 2072 ID(PCI_DEVICE_ID_INTEL_82965GME_HB), 2073 ID(PCI_DEVICE_ID_INTEL_G33_HB), 2074 ID(PCI_DEVICE_ID_INTEL_Q35_HB), 2075 ID(PCI_DEVICE_ID_INTEL_Q33_HB), 2076 { } 2077 }; 2078 2079 MODULE_DEVICE_TABLE(pci, agp_intel_pci_table); 2080 2081 static struct pci_driver agp_intel_pci_driver = { 2082 .name = "agpgart-intel", 2083 .id_table = agp_intel_pci_table, 2084 .probe = agp_intel_probe, 2085 .remove = __devexit_p(agp_intel_remove), 2086 #ifdef CONFIG_PM 2087 .resume = agp_intel_resume, 2088 #endif 2089 }; 2090 2091 static int __init agp_intel_init(void) 2092 { 2093 if (agp_off) 2094 return -EINVAL; 2095 return pci_register_driver(&agp_intel_pci_driver); 2096 } 2097 2098 static void __exit agp_intel_cleanup(void) 2099 { 2100 pci_unregister_driver(&agp_intel_pci_driver); 2101 } 2102 2103 module_init(agp_intel_init); 2104 module_exit(agp_intel_cleanup); 2105 2106 MODULE_AUTHOR("Dave Jones <davej@codemonkey.org.uk>"); 2107 MODULE_LICENSE("GPL and additional rights"); 2108