1 /* 2 * Intel AGPGART routines. 3 */ 4 5 #include <linux/module.h> 6 #include <linux/pci.h> 7 #include <linux/init.h> 8 #include <linux/kernel.h> 9 #include <linux/pagemap.h> 10 #include <linux/agp_backend.h> 11 #include "agp.h" 12 13 /* 14 * If we have Intel graphics, we're not going to have anything other than 15 * an Intel IOMMU. So make the correct use of the PCI DMA API contingent 16 * on the Intel IOMMU support (CONFIG_DMAR). 17 * Only newer chipsets need to bother with this, of course. 18 */ 19 #ifdef CONFIG_DMAR 20 #define USE_PCI_DMA_API 1 21 #endif 22 23 #define PCI_DEVICE_ID_INTEL_E7221_HB 0x2588 24 #define PCI_DEVICE_ID_INTEL_E7221_IG 0x258a 25 #define PCI_DEVICE_ID_INTEL_82946GZ_HB 0x2970 26 #define PCI_DEVICE_ID_INTEL_82946GZ_IG 0x2972 27 #define PCI_DEVICE_ID_INTEL_82G35_HB 0x2980 28 #define PCI_DEVICE_ID_INTEL_82G35_IG 0x2982 29 #define PCI_DEVICE_ID_INTEL_82965Q_HB 0x2990 30 #define PCI_DEVICE_ID_INTEL_82965Q_IG 0x2992 31 #define PCI_DEVICE_ID_INTEL_82965G_HB 0x29A0 32 #define PCI_DEVICE_ID_INTEL_82965G_IG 0x29A2 33 #define PCI_DEVICE_ID_INTEL_82965GM_HB 0x2A00 34 #define PCI_DEVICE_ID_INTEL_82965GM_IG 0x2A02 35 #define PCI_DEVICE_ID_INTEL_82965GME_HB 0x2A10 36 #define PCI_DEVICE_ID_INTEL_82965GME_IG 0x2A12 37 #define PCI_DEVICE_ID_INTEL_82945GME_HB 0x27AC 38 #define PCI_DEVICE_ID_INTEL_82945GME_IG 0x27AE 39 #define PCI_DEVICE_ID_INTEL_IGDGM_HB 0xA010 40 #define PCI_DEVICE_ID_INTEL_IGDGM_IG 0xA011 41 #define PCI_DEVICE_ID_INTEL_IGDG_HB 0xA000 42 #define PCI_DEVICE_ID_INTEL_IGDG_IG 0xA001 43 #define PCI_DEVICE_ID_INTEL_G33_HB 0x29C0 44 #define PCI_DEVICE_ID_INTEL_G33_IG 0x29C2 45 #define PCI_DEVICE_ID_INTEL_Q35_HB 0x29B0 46 #define PCI_DEVICE_ID_INTEL_Q35_IG 0x29B2 47 #define PCI_DEVICE_ID_INTEL_Q33_HB 0x29D0 48 #define PCI_DEVICE_ID_INTEL_Q33_IG 0x29D2 49 #define PCI_DEVICE_ID_INTEL_GM45_HB 0x2A40 50 #define PCI_DEVICE_ID_INTEL_GM45_IG 0x2A42 51 #define PCI_DEVICE_ID_INTEL_IGD_E_HB 0x2E00 52 #define PCI_DEVICE_ID_INTEL_IGD_E_IG 0x2E02 53 #define PCI_DEVICE_ID_INTEL_Q45_HB 0x2E10 54 #define PCI_DEVICE_ID_INTEL_Q45_IG 0x2E12 55 #define PCI_DEVICE_ID_INTEL_G45_HB 0x2E20 56 #define PCI_DEVICE_ID_INTEL_G45_IG 0x2E22 57 #define PCI_DEVICE_ID_INTEL_G41_HB 0x2E30 58 #define PCI_DEVICE_ID_INTEL_G41_IG 0x2E32 59 #define PCI_DEVICE_ID_INTEL_IGDNG_D_HB 0x0040 60 #define PCI_DEVICE_ID_INTEL_IGDNG_D_IG 0x0042 61 #define PCI_DEVICE_ID_INTEL_IGDNG_M_HB 0x0044 62 #define PCI_DEVICE_ID_INTEL_IGDNG_M_IG 0x0046 63 64 /* cover 915 and 945 variants */ 65 #define IS_I915 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_E7221_HB || \ 66 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915G_HB || \ 67 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB || \ 68 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945G_HB || \ 69 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GM_HB || \ 70 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GME_HB) 71 72 #define IS_I965 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82946GZ_HB || \ 73 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82G35_HB || \ 74 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965Q_HB || \ 75 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965G_HB || \ 76 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GM_HB || \ 77 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GME_HB) 78 79 #define IS_G33 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G33_HB || \ 80 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q35_HB || \ 81 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q33_HB || \ 82 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDGM_HB || \ 83 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDG_HB) 84 85 #define IS_IGD (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDGM_HB || \ 86 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDG_HB) 87 88 #define IS_G4X (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGD_E_HB || \ 89 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q45_HB || \ 90 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G45_HB || \ 91 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_GM45_HB || \ 92 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G41_HB || \ 93 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDNG_D_HB || \ 94 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDNG_M_HB) 95 96 extern int agp_memory_reserved; 97 98 99 /* Intel 815 register */ 100 #define INTEL_815_APCONT 0x51 101 #define INTEL_815_ATTBASE_MASK ~0x1FFFFFFF 102 103 /* Intel i820 registers */ 104 #define INTEL_I820_RDCR 0x51 105 #define INTEL_I820_ERRSTS 0xc8 106 107 /* Intel i840 registers */ 108 #define INTEL_I840_MCHCFG 0x50 109 #define INTEL_I840_ERRSTS 0xc8 110 111 /* Intel i850 registers */ 112 #define INTEL_I850_MCHCFG 0x50 113 #define INTEL_I850_ERRSTS 0xc8 114 115 /* intel 915G registers */ 116 #define I915_GMADDR 0x18 117 #define I915_MMADDR 0x10 118 #define I915_PTEADDR 0x1C 119 #define I915_GMCH_GMS_STOLEN_48M (0x6 << 4) 120 #define I915_GMCH_GMS_STOLEN_64M (0x7 << 4) 121 #define G33_GMCH_GMS_STOLEN_128M (0x8 << 4) 122 #define G33_GMCH_GMS_STOLEN_256M (0x9 << 4) 123 #define INTEL_GMCH_GMS_STOLEN_96M (0xa << 4) 124 #define INTEL_GMCH_GMS_STOLEN_160M (0xb << 4) 125 #define INTEL_GMCH_GMS_STOLEN_224M (0xc << 4) 126 #define INTEL_GMCH_GMS_STOLEN_352M (0xd << 4) 127 128 #define I915_IFPADDR 0x60 129 130 /* Intel 965G registers */ 131 #define I965_MSAC 0x62 132 #define I965_IFPADDR 0x70 133 134 /* Intel 7505 registers */ 135 #define INTEL_I7505_APSIZE 0x74 136 #define INTEL_I7505_NCAPID 0x60 137 #define INTEL_I7505_NISTAT 0x6c 138 #define INTEL_I7505_ATTBASE 0x78 139 #define INTEL_I7505_ERRSTS 0x42 140 #define INTEL_I7505_AGPCTRL 0x70 141 #define INTEL_I7505_MCHCFG 0x50 142 143 static const struct aper_size_info_fixed intel_i810_sizes[] = 144 { 145 {64, 16384, 4}, 146 /* The 32M mode still requires a 64k gatt */ 147 {32, 8192, 4} 148 }; 149 150 #define AGP_DCACHE_MEMORY 1 151 #define AGP_PHYS_MEMORY 2 152 #define INTEL_AGP_CACHED_MEMORY 3 153 154 static struct gatt_mask intel_i810_masks[] = 155 { 156 {.mask = I810_PTE_VALID, .type = 0}, 157 {.mask = (I810_PTE_VALID | I810_PTE_LOCAL), .type = AGP_DCACHE_MEMORY}, 158 {.mask = I810_PTE_VALID, .type = 0}, 159 {.mask = I810_PTE_VALID | I830_PTE_SYSTEM_CACHED, 160 .type = INTEL_AGP_CACHED_MEMORY} 161 }; 162 163 static struct _intel_private { 164 struct pci_dev *pcidev; /* device one */ 165 u8 __iomem *registers; 166 u32 __iomem *gtt; /* I915G */ 167 int num_dcache_entries; 168 /* gtt_entries is the number of gtt entries that are already mapped 169 * to stolen memory. Stolen memory is larger than the memory mapped 170 * through gtt_entries, as it includes some reserved space for the BIOS 171 * popup and for the GTT. 172 */ 173 int gtt_entries; /* i830+ */ 174 union { 175 void __iomem *i9xx_flush_page; 176 void *i8xx_flush_page; 177 }; 178 struct page *i8xx_page; 179 struct resource ifp_resource; 180 int resource_valid; 181 } intel_private; 182 183 #ifdef USE_PCI_DMA_API 184 static int intel_agp_map_page(void *addr, dma_addr_t *ret) 185 { 186 *ret = pci_map_single(intel_private.pcidev, addr, 187 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 188 if (pci_dma_mapping_error(intel_private.pcidev, *ret)) 189 return -EINVAL; 190 return 0; 191 } 192 193 static void intel_agp_unmap_page(void *addr, dma_addr_t dma) 194 { 195 pci_unmap_single(intel_private.pcidev, dma, 196 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 197 } 198 199 static int intel_agp_map_memory(struct agp_memory *mem) 200 { 201 struct scatterlist *sg; 202 int i; 203 204 DBG("try mapping %lu pages\n", (unsigned long)mem->page_count); 205 206 if ((mem->page_count * sizeof(*mem->sg_list)) < 2*PAGE_SIZE) 207 mem->sg_list = kcalloc(mem->page_count, sizeof(*mem->sg_list), 208 GFP_KERNEL); 209 210 if (mem->sg_list == NULL) { 211 mem->sg_list = vmalloc(mem->page_count * sizeof(*mem->sg_list)); 212 mem->sg_vmalloc_flag = 1; 213 } 214 215 if (!mem->sg_list) { 216 mem->sg_vmalloc_flag = 0; 217 return -ENOMEM; 218 } 219 sg_init_table(mem->sg_list, mem->page_count); 220 221 sg = mem->sg_list; 222 for (i = 0 ; i < mem->page_count; i++, sg = sg_next(sg)) 223 sg_set_page(sg, mem->pages[i], PAGE_SIZE, 0); 224 225 mem->num_sg = pci_map_sg(intel_private.pcidev, mem->sg_list, 226 mem->page_count, PCI_DMA_BIDIRECTIONAL); 227 if (!mem->num_sg) { 228 if (mem->sg_vmalloc_flag) 229 vfree(mem->sg_list); 230 else 231 kfree(mem->sg_list); 232 mem->sg_list = NULL; 233 mem->sg_vmalloc_flag = 0; 234 return -ENOMEM; 235 } 236 return 0; 237 } 238 239 static void intel_agp_unmap_memory(struct agp_memory *mem) 240 { 241 DBG("try unmapping %lu pages\n", (unsigned long)mem->page_count); 242 243 pci_unmap_sg(intel_private.pcidev, mem->sg_list, 244 mem->page_count, PCI_DMA_BIDIRECTIONAL); 245 if (mem->sg_vmalloc_flag) 246 vfree(mem->sg_list); 247 else 248 kfree(mem->sg_list); 249 mem->sg_vmalloc_flag = 0; 250 mem->sg_list = NULL; 251 mem->num_sg = 0; 252 } 253 254 static void intel_agp_insert_sg_entries(struct agp_memory *mem, 255 off_t pg_start, int mask_type) 256 { 257 struct scatterlist *sg; 258 int i, j; 259 260 j = pg_start; 261 262 WARN_ON(!mem->num_sg); 263 264 if (mem->num_sg == mem->page_count) { 265 for_each_sg(mem->sg_list, sg, mem->page_count, i) { 266 writel(agp_bridge->driver->mask_memory(agp_bridge, 267 sg_dma_address(sg), mask_type), 268 intel_private.gtt+j); 269 j++; 270 } 271 } else { 272 /* sg may merge pages, but we have to seperate 273 * per-page addr for GTT */ 274 unsigned int len, m; 275 276 for_each_sg(mem->sg_list, sg, mem->num_sg, i) { 277 len = sg_dma_len(sg) / PAGE_SIZE; 278 for (m = 0; m < len; m++) { 279 writel(agp_bridge->driver->mask_memory(agp_bridge, 280 sg_dma_address(sg) + m * PAGE_SIZE, 281 mask_type), 282 intel_private.gtt+j); 283 j++; 284 } 285 } 286 } 287 readl(intel_private.gtt+j-1); 288 } 289 290 #else 291 292 static void intel_agp_insert_sg_entries(struct agp_memory *mem, 293 off_t pg_start, int mask_type) 294 { 295 int i, j; 296 297 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { 298 writel(agp_bridge->driver->mask_memory(agp_bridge, 299 phys_to_gart(page_to_phys(mem->pages[i])), mask_type), 300 intel_private.gtt+j); 301 } 302 303 readl(intel_private.gtt+j-1); 304 } 305 306 #endif 307 308 static int intel_i810_fetch_size(void) 309 { 310 u32 smram_miscc; 311 struct aper_size_info_fixed *values; 312 313 pci_read_config_dword(agp_bridge->dev, I810_SMRAM_MISCC, &smram_miscc); 314 values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes); 315 316 if ((smram_miscc & I810_GMS) == I810_GMS_DISABLE) { 317 dev_warn(&agp_bridge->dev->dev, "i810 is disabled\n"); 318 return 0; 319 } 320 if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) == I810_GFX_MEM_WIN_32M) { 321 agp_bridge->previous_size = 322 agp_bridge->current_size = (void *) (values + 1); 323 agp_bridge->aperture_size_idx = 1; 324 return values[1].size; 325 } else { 326 agp_bridge->previous_size = 327 agp_bridge->current_size = (void *) (values); 328 agp_bridge->aperture_size_idx = 0; 329 return values[0].size; 330 } 331 332 return 0; 333 } 334 335 static int intel_i810_configure(void) 336 { 337 struct aper_size_info_fixed *current_size; 338 u32 temp; 339 int i; 340 341 current_size = A_SIZE_FIX(agp_bridge->current_size); 342 343 if (!intel_private.registers) { 344 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp); 345 temp &= 0xfff80000; 346 347 intel_private.registers = ioremap(temp, 128 * 4096); 348 if (!intel_private.registers) { 349 dev_err(&intel_private.pcidev->dev, 350 "can't remap memory\n"); 351 return -ENOMEM; 352 } 353 } 354 355 if ((readl(intel_private.registers+I810_DRAM_CTL) 356 & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) { 357 /* This will need to be dynamically assigned */ 358 dev_info(&intel_private.pcidev->dev, 359 "detected 4MB dedicated video ram\n"); 360 intel_private.num_dcache_entries = 1024; 361 } 362 pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp); 363 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 364 writel(agp_bridge->gatt_bus_addr | I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL); 365 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */ 366 367 if (agp_bridge->driver->needs_scratch_page) { 368 for (i = 0; i < current_size->num_entries; i++) { 369 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4)); 370 } 371 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); /* PCI posting. */ 372 } 373 global_cache_flush(); 374 return 0; 375 } 376 377 static void intel_i810_cleanup(void) 378 { 379 writel(0, intel_private.registers+I810_PGETBL_CTL); 380 readl(intel_private.registers); /* PCI Posting. */ 381 iounmap(intel_private.registers); 382 } 383 384 static void intel_i810_tlbflush(struct agp_memory *mem) 385 { 386 return; 387 } 388 389 static void intel_i810_agp_enable(struct agp_bridge_data *bridge, u32 mode) 390 { 391 return; 392 } 393 394 /* Exists to support ARGB cursors */ 395 static struct page *i8xx_alloc_pages(void) 396 { 397 struct page *page; 398 399 page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2); 400 if (page == NULL) 401 return NULL; 402 403 if (set_pages_uc(page, 4) < 0) { 404 set_pages_wb(page, 4); 405 __free_pages(page, 2); 406 return NULL; 407 } 408 get_page(page); 409 atomic_inc(&agp_bridge->current_memory_agp); 410 return page; 411 } 412 413 static void i8xx_destroy_pages(struct page *page) 414 { 415 if (page == NULL) 416 return; 417 418 set_pages_wb(page, 4); 419 put_page(page); 420 __free_pages(page, 2); 421 atomic_dec(&agp_bridge->current_memory_agp); 422 } 423 424 static int intel_i830_type_to_mask_type(struct agp_bridge_data *bridge, 425 int type) 426 { 427 if (type < AGP_USER_TYPES) 428 return type; 429 else if (type == AGP_USER_CACHED_MEMORY) 430 return INTEL_AGP_CACHED_MEMORY; 431 else 432 return 0; 433 } 434 435 static int intel_i810_insert_entries(struct agp_memory *mem, off_t pg_start, 436 int type) 437 { 438 int i, j, num_entries; 439 void *temp; 440 int ret = -EINVAL; 441 int mask_type; 442 443 if (mem->page_count == 0) 444 goto out; 445 446 temp = agp_bridge->current_size; 447 num_entries = A_SIZE_FIX(temp)->num_entries; 448 449 if ((pg_start + mem->page_count) > num_entries) 450 goto out_err; 451 452 453 for (j = pg_start; j < (pg_start + mem->page_count); j++) { 454 if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j))) { 455 ret = -EBUSY; 456 goto out_err; 457 } 458 } 459 460 if (type != mem->type) 461 goto out_err; 462 463 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type); 464 465 switch (mask_type) { 466 case AGP_DCACHE_MEMORY: 467 if (!mem->is_flushed) 468 global_cache_flush(); 469 for (i = pg_start; i < (pg_start + mem->page_count); i++) { 470 writel((i*4096)|I810_PTE_LOCAL|I810_PTE_VALID, 471 intel_private.registers+I810_PTE_BASE+(i*4)); 472 } 473 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); 474 break; 475 case AGP_PHYS_MEMORY: 476 case AGP_NORMAL_MEMORY: 477 if (!mem->is_flushed) 478 global_cache_flush(); 479 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { 480 writel(agp_bridge->driver->mask_memory(agp_bridge, 481 phys_to_gart(page_to_phys(mem->pages[i])), 482 mask_type), 483 intel_private.registers+I810_PTE_BASE+(j*4)); 484 } 485 readl(intel_private.registers+I810_PTE_BASE+((j-1)*4)); 486 break; 487 default: 488 goto out_err; 489 } 490 491 agp_bridge->driver->tlb_flush(mem); 492 out: 493 ret = 0; 494 out_err: 495 mem->is_flushed = true; 496 return ret; 497 } 498 499 static int intel_i810_remove_entries(struct agp_memory *mem, off_t pg_start, 500 int type) 501 { 502 int i; 503 504 if (mem->page_count == 0) 505 return 0; 506 507 for (i = pg_start; i < (mem->page_count + pg_start); i++) { 508 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4)); 509 } 510 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); 511 512 agp_bridge->driver->tlb_flush(mem); 513 return 0; 514 } 515 516 /* 517 * The i810/i830 requires a physical address to program its mouse 518 * pointer into hardware. 519 * However the Xserver still writes to it through the agp aperture. 520 */ 521 static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type) 522 { 523 struct agp_memory *new; 524 struct page *page; 525 526 switch (pg_count) { 527 case 1: page = agp_bridge->driver->agp_alloc_page(agp_bridge); 528 break; 529 case 4: 530 /* kludge to get 4 physical pages for ARGB cursor */ 531 page = i8xx_alloc_pages(); 532 break; 533 default: 534 return NULL; 535 } 536 537 if (page == NULL) 538 return NULL; 539 540 new = agp_create_memory(pg_count); 541 if (new == NULL) 542 return NULL; 543 544 new->pages[0] = page; 545 if (pg_count == 4) { 546 /* kludge to get 4 physical pages for ARGB cursor */ 547 new->pages[1] = new->pages[0] + 1; 548 new->pages[2] = new->pages[1] + 1; 549 new->pages[3] = new->pages[2] + 1; 550 } 551 new->page_count = pg_count; 552 new->num_scratch_pages = pg_count; 553 new->type = AGP_PHYS_MEMORY; 554 new->physical = page_to_phys(new->pages[0]); 555 return new; 556 } 557 558 static struct agp_memory *intel_i810_alloc_by_type(size_t pg_count, int type) 559 { 560 struct agp_memory *new; 561 562 if (type == AGP_DCACHE_MEMORY) { 563 if (pg_count != intel_private.num_dcache_entries) 564 return NULL; 565 566 new = agp_create_memory(1); 567 if (new == NULL) 568 return NULL; 569 570 new->type = AGP_DCACHE_MEMORY; 571 new->page_count = pg_count; 572 new->num_scratch_pages = 0; 573 agp_free_page_array(new); 574 return new; 575 } 576 if (type == AGP_PHYS_MEMORY) 577 return alloc_agpphysmem_i8xx(pg_count, type); 578 return NULL; 579 } 580 581 static void intel_i810_free_by_type(struct agp_memory *curr) 582 { 583 agp_free_key(curr->key); 584 if (curr->type == AGP_PHYS_MEMORY) { 585 if (curr->page_count == 4) 586 i8xx_destroy_pages(curr->pages[0]); 587 else { 588 agp_bridge->driver->agp_destroy_page(curr->pages[0], 589 AGP_PAGE_DESTROY_UNMAP); 590 agp_bridge->driver->agp_destroy_page(curr->pages[0], 591 AGP_PAGE_DESTROY_FREE); 592 } 593 agp_free_page_array(curr); 594 } 595 kfree(curr); 596 } 597 598 static unsigned long intel_i810_mask_memory(struct agp_bridge_data *bridge, 599 dma_addr_t addr, int type) 600 { 601 /* Type checking must be done elsewhere */ 602 return addr | bridge->driver->masks[type].mask; 603 } 604 605 static struct aper_size_info_fixed intel_i830_sizes[] = 606 { 607 {128, 32768, 5}, 608 /* The 64M mode still requires a 128k gatt */ 609 {64, 16384, 5}, 610 {256, 65536, 6}, 611 {512, 131072, 7}, 612 }; 613 614 static void intel_i830_init_gtt_entries(void) 615 { 616 u16 gmch_ctrl; 617 int gtt_entries; 618 u8 rdct; 619 int local = 0; 620 static const int ddt[4] = { 0, 16, 32, 64 }; 621 int size; /* reserved space (in kb) at the top of stolen memory */ 622 623 pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl); 624 625 if (IS_I965) { 626 u32 pgetbl_ctl; 627 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL); 628 629 /* The 965 has a field telling us the size of the GTT, 630 * which may be larger than what is necessary to map the 631 * aperture. 632 */ 633 switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) { 634 case I965_PGETBL_SIZE_128KB: 635 size = 128; 636 break; 637 case I965_PGETBL_SIZE_256KB: 638 size = 256; 639 break; 640 case I965_PGETBL_SIZE_512KB: 641 size = 512; 642 break; 643 case I965_PGETBL_SIZE_1MB: 644 size = 1024; 645 break; 646 case I965_PGETBL_SIZE_2MB: 647 size = 2048; 648 break; 649 case I965_PGETBL_SIZE_1_5MB: 650 size = 1024 + 512; 651 break; 652 default: 653 dev_info(&intel_private.pcidev->dev, 654 "unknown page table size, assuming 512KB\n"); 655 size = 512; 656 } 657 size += 4; /* add in BIOS popup space */ 658 } else if (IS_G33 && !IS_IGD) { 659 /* G33's GTT size defined in gmch_ctrl */ 660 switch (gmch_ctrl & G33_PGETBL_SIZE_MASK) { 661 case G33_PGETBL_SIZE_1M: 662 size = 1024; 663 break; 664 case G33_PGETBL_SIZE_2M: 665 size = 2048; 666 break; 667 default: 668 dev_info(&agp_bridge->dev->dev, 669 "unknown page table size 0x%x, assuming 512KB\n", 670 (gmch_ctrl & G33_PGETBL_SIZE_MASK)); 671 size = 512; 672 } 673 size += 4; 674 } else if (IS_G4X || IS_IGD) { 675 /* On 4 series hardware, GTT stolen is separate from graphics 676 * stolen, ignore it in stolen gtt entries counting. However, 677 * 4KB of the stolen memory doesn't get mapped to the GTT. 678 */ 679 size = 4; 680 } else { 681 /* On previous hardware, the GTT size was just what was 682 * required to map the aperture. 683 */ 684 size = agp_bridge->driver->fetch_size() + 4; 685 } 686 687 if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82830_HB || 688 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) { 689 switch (gmch_ctrl & I830_GMCH_GMS_MASK) { 690 case I830_GMCH_GMS_STOLEN_512: 691 gtt_entries = KB(512) - KB(size); 692 break; 693 case I830_GMCH_GMS_STOLEN_1024: 694 gtt_entries = MB(1) - KB(size); 695 break; 696 case I830_GMCH_GMS_STOLEN_8192: 697 gtt_entries = MB(8) - KB(size); 698 break; 699 case I830_GMCH_GMS_LOCAL: 700 rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE); 701 gtt_entries = (I830_RDRAM_ND(rdct) + 1) * 702 MB(ddt[I830_RDRAM_DDT(rdct)]); 703 local = 1; 704 break; 705 default: 706 gtt_entries = 0; 707 break; 708 } 709 } else { 710 switch (gmch_ctrl & I855_GMCH_GMS_MASK) { 711 case I855_GMCH_GMS_STOLEN_1M: 712 gtt_entries = MB(1) - KB(size); 713 break; 714 case I855_GMCH_GMS_STOLEN_4M: 715 gtt_entries = MB(4) - KB(size); 716 break; 717 case I855_GMCH_GMS_STOLEN_8M: 718 gtt_entries = MB(8) - KB(size); 719 break; 720 case I855_GMCH_GMS_STOLEN_16M: 721 gtt_entries = MB(16) - KB(size); 722 break; 723 case I855_GMCH_GMS_STOLEN_32M: 724 gtt_entries = MB(32) - KB(size); 725 break; 726 case I915_GMCH_GMS_STOLEN_48M: 727 /* Check it's really I915G */ 728 if (IS_I915 || IS_I965 || IS_G33 || IS_G4X) 729 gtt_entries = MB(48) - KB(size); 730 else 731 gtt_entries = 0; 732 break; 733 case I915_GMCH_GMS_STOLEN_64M: 734 /* Check it's really I915G */ 735 if (IS_I915 || IS_I965 || IS_G33 || IS_G4X) 736 gtt_entries = MB(64) - KB(size); 737 else 738 gtt_entries = 0; 739 break; 740 case G33_GMCH_GMS_STOLEN_128M: 741 if (IS_G33 || IS_I965 || IS_G4X) 742 gtt_entries = MB(128) - KB(size); 743 else 744 gtt_entries = 0; 745 break; 746 case G33_GMCH_GMS_STOLEN_256M: 747 if (IS_G33 || IS_I965 || IS_G4X) 748 gtt_entries = MB(256) - KB(size); 749 else 750 gtt_entries = 0; 751 break; 752 case INTEL_GMCH_GMS_STOLEN_96M: 753 if (IS_I965 || IS_G4X) 754 gtt_entries = MB(96) - KB(size); 755 else 756 gtt_entries = 0; 757 break; 758 case INTEL_GMCH_GMS_STOLEN_160M: 759 if (IS_I965 || IS_G4X) 760 gtt_entries = MB(160) - KB(size); 761 else 762 gtt_entries = 0; 763 break; 764 case INTEL_GMCH_GMS_STOLEN_224M: 765 if (IS_I965 || IS_G4X) 766 gtt_entries = MB(224) - KB(size); 767 else 768 gtt_entries = 0; 769 break; 770 case INTEL_GMCH_GMS_STOLEN_352M: 771 if (IS_I965 || IS_G4X) 772 gtt_entries = MB(352) - KB(size); 773 else 774 gtt_entries = 0; 775 break; 776 default: 777 gtt_entries = 0; 778 break; 779 } 780 } 781 if (gtt_entries > 0) { 782 dev_info(&agp_bridge->dev->dev, "detected %dK %s memory\n", 783 gtt_entries / KB(1), local ? "local" : "stolen"); 784 gtt_entries /= KB(4); 785 } else { 786 dev_info(&agp_bridge->dev->dev, 787 "no pre-allocated video memory detected\n"); 788 gtt_entries = 0; 789 } 790 791 intel_private.gtt_entries = gtt_entries; 792 } 793 794 static void intel_i830_fini_flush(void) 795 { 796 kunmap(intel_private.i8xx_page); 797 intel_private.i8xx_flush_page = NULL; 798 unmap_page_from_agp(intel_private.i8xx_page); 799 800 __free_page(intel_private.i8xx_page); 801 intel_private.i8xx_page = NULL; 802 } 803 804 static void intel_i830_setup_flush(void) 805 { 806 /* return if we've already set the flush mechanism up */ 807 if (intel_private.i8xx_page) 808 return; 809 810 intel_private.i8xx_page = alloc_page(GFP_KERNEL | __GFP_ZERO | GFP_DMA32); 811 if (!intel_private.i8xx_page) 812 return; 813 814 /* make page uncached */ 815 map_page_into_agp(intel_private.i8xx_page); 816 817 intel_private.i8xx_flush_page = kmap(intel_private.i8xx_page); 818 if (!intel_private.i8xx_flush_page) 819 intel_i830_fini_flush(); 820 } 821 822 static void intel_i830_chipset_flush(struct agp_bridge_data *bridge) 823 { 824 unsigned int *pg = intel_private.i8xx_flush_page; 825 int i; 826 827 for (i = 0; i < 256; i += 2) 828 *(pg + i) = i; 829 830 wmb(); 831 } 832 833 /* The intel i830 automatically initializes the agp aperture during POST. 834 * Use the memory already set aside for in the GTT. 835 */ 836 static int intel_i830_create_gatt_table(struct agp_bridge_data *bridge) 837 { 838 int page_order; 839 struct aper_size_info_fixed *size; 840 int num_entries; 841 u32 temp; 842 843 size = agp_bridge->current_size; 844 page_order = size->page_order; 845 num_entries = size->num_entries; 846 agp_bridge->gatt_table_real = NULL; 847 848 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp); 849 temp &= 0xfff80000; 850 851 intel_private.registers = ioremap(temp, 128 * 4096); 852 if (!intel_private.registers) 853 return -ENOMEM; 854 855 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000; 856 global_cache_flush(); /* FIXME: ?? */ 857 858 /* we have to call this as early as possible after the MMIO base address is known */ 859 intel_i830_init_gtt_entries(); 860 861 agp_bridge->gatt_table = NULL; 862 863 agp_bridge->gatt_bus_addr = temp; 864 865 return 0; 866 } 867 868 /* Return the gatt table to a sane state. Use the top of stolen 869 * memory for the GTT. 870 */ 871 static int intel_i830_free_gatt_table(struct agp_bridge_data *bridge) 872 { 873 return 0; 874 } 875 876 static int intel_i830_fetch_size(void) 877 { 878 u16 gmch_ctrl; 879 struct aper_size_info_fixed *values; 880 881 values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes); 882 883 if (agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82830_HB && 884 agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82845G_HB) { 885 /* 855GM/852GM/865G has 128MB aperture size */ 886 agp_bridge->previous_size = agp_bridge->current_size = (void *) values; 887 agp_bridge->aperture_size_idx = 0; 888 return values[0].size; 889 } 890 891 pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl); 892 893 if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_128M) { 894 agp_bridge->previous_size = agp_bridge->current_size = (void *) values; 895 agp_bridge->aperture_size_idx = 0; 896 return values[0].size; 897 } else { 898 agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + 1); 899 agp_bridge->aperture_size_idx = 1; 900 return values[1].size; 901 } 902 903 return 0; 904 } 905 906 static int intel_i830_configure(void) 907 { 908 struct aper_size_info_fixed *current_size; 909 u32 temp; 910 u16 gmch_ctrl; 911 int i; 912 913 current_size = A_SIZE_FIX(agp_bridge->current_size); 914 915 pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp); 916 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 917 918 pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl); 919 gmch_ctrl |= I830_GMCH_ENABLED; 920 pci_write_config_word(agp_bridge->dev, I830_GMCH_CTRL, gmch_ctrl); 921 922 writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL); 923 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */ 924 925 if (agp_bridge->driver->needs_scratch_page) { 926 for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) { 927 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4)); 928 } 929 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); /* PCI Posting. */ 930 } 931 932 global_cache_flush(); 933 934 intel_i830_setup_flush(); 935 return 0; 936 } 937 938 static void intel_i830_cleanup(void) 939 { 940 iounmap(intel_private.registers); 941 } 942 943 static int intel_i830_insert_entries(struct agp_memory *mem, off_t pg_start, 944 int type) 945 { 946 int i, j, num_entries; 947 void *temp; 948 int ret = -EINVAL; 949 int mask_type; 950 951 if (mem->page_count == 0) 952 goto out; 953 954 temp = agp_bridge->current_size; 955 num_entries = A_SIZE_FIX(temp)->num_entries; 956 957 if (pg_start < intel_private.gtt_entries) { 958 dev_printk(KERN_DEBUG, &intel_private.pcidev->dev, 959 "pg_start == 0x%.8lx, intel_private.gtt_entries == 0x%.8x\n", 960 pg_start, intel_private.gtt_entries); 961 962 dev_info(&intel_private.pcidev->dev, 963 "trying to insert into local/stolen memory\n"); 964 goto out_err; 965 } 966 967 if ((pg_start + mem->page_count) > num_entries) 968 goto out_err; 969 970 /* The i830 can't check the GTT for entries since its read only, 971 * depend on the caller to make the correct offset decisions. 972 */ 973 974 if (type != mem->type) 975 goto out_err; 976 977 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type); 978 979 if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY && 980 mask_type != INTEL_AGP_CACHED_MEMORY) 981 goto out_err; 982 983 if (!mem->is_flushed) 984 global_cache_flush(); 985 986 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { 987 writel(agp_bridge->driver->mask_memory(agp_bridge, 988 phys_to_gart(page_to_phys(mem->pages[i])), mask_type), 989 intel_private.registers+I810_PTE_BASE+(j*4)); 990 } 991 readl(intel_private.registers+I810_PTE_BASE+((j-1)*4)); 992 agp_bridge->driver->tlb_flush(mem); 993 994 out: 995 ret = 0; 996 out_err: 997 mem->is_flushed = true; 998 return ret; 999 } 1000 1001 static int intel_i830_remove_entries(struct agp_memory *mem, off_t pg_start, 1002 int type) 1003 { 1004 int i; 1005 1006 if (mem->page_count == 0) 1007 return 0; 1008 1009 if (pg_start < intel_private.gtt_entries) { 1010 dev_info(&intel_private.pcidev->dev, 1011 "trying to disable local/stolen memory\n"); 1012 return -EINVAL; 1013 } 1014 1015 for (i = pg_start; i < (mem->page_count + pg_start); i++) { 1016 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4)); 1017 } 1018 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); 1019 1020 agp_bridge->driver->tlb_flush(mem); 1021 return 0; 1022 } 1023 1024 static struct agp_memory *intel_i830_alloc_by_type(size_t pg_count, int type) 1025 { 1026 if (type == AGP_PHYS_MEMORY) 1027 return alloc_agpphysmem_i8xx(pg_count, type); 1028 /* always return NULL for other allocation types for now */ 1029 return NULL; 1030 } 1031 1032 static int intel_alloc_chipset_flush_resource(void) 1033 { 1034 int ret; 1035 ret = pci_bus_alloc_resource(agp_bridge->dev->bus, &intel_private.ifp_resource, PAGE_SIZE, 1036 PAGE_SIZE, PCIBIOS_MIN_MEM, 0, 1037 pcibios_align_resource, agp_bridge->dev); 1038 1039 return ret; 1040 } 1041 1042 static void intel_i915_setup_chipset_flush(void) 1043 { 1044 int ret; 1045 u32 temp; 1046 1047 pci_read_config_dword(agp_bridge->dev, I915_IFPADDR, &temp); 1048 if (!(temp & 0x1)) { 1049 intel_alloc_chipset_flush_resource(); 1050 intel_private.resource_valid = 1; 1051 pci_write_config_dword(agp_bridge->dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1); 1052 } else { 1053 temp &= ~1; 1054 1055 intel_private.resource_valid = 1; 1056 intel_private.ifp_resource.start = temp; 1057 intel_private.ifp_resource.end = temp + PAGE_SIZE; 1058 ret = request_resource(&iomem_resource, &intel_private.ifp_resource); 1059 /* some BIOSes reserve this area in a pnp some don't */ 1060 if (ret) 1061 intel_private.resource_valid = 0; 1062 } 1063 } 1064 1065 static void intel_i965_g33_setup_chipset_flush(void) 1066 { 1067 u32 temp_hi, temp_lo; 1068 int ret; 1069 1070 pci_read_config_dword(agp_bridge->dev, I965_IFPADDR + 4, &temp_hi); 1071 pci_read_config_dword(agp_bridge->dev, I965_IFPADDR, &temp_lo); 1072 1073 if (!(temp_lo & 0x1)) { 1074 1075 intel_alloc_chipset_flush_resource(); 1076 1077 intel_private.resource_valid = 1; 1078 pci_write_config_dword(agp_bridge->dev, I965_IFPADDR + 4, 1079 upper_32_bits(intel_private.ifp_resource.start)); 1080 pci_write_config_dword(agp_bridge->dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1); 1081 } else { 1082 u64 l64; 1083 1084 temp_lo &= ~0x1; 1085 l64 = ((u64)temp_hi << 32) | temp_lo; 1086 1087 intel_private.resource_valid = 1; 1088 intel_private.ifp_resource.start = l64; 1089 intel_private.ifp_resource.end = l64 + PAGE_SIZE; 1090 ret = request_resource(&iomem_resource, &intel_private.ifp_resource); 1091 /* some BIOSes reserve this area in a pnp some don't */ 1092 if (ret) 1093 intel_private.resource_valid = 0; 1094 } 1095 } 1096 1097 static void intel_i9xx_setup_flush(void) 1098 { 1099 /* return if already configured */ 1100 if (intel_private.ifp_resource.start) 1101 return; 1102 1103 /* setup a resource for this object */ 1104 intel_private.ifp_resource.name = "Intel Flush Page"; 1105 intel_private.ifp_resource.flags = IORESOURCE_MEM; 1106 1107 /* Setup chipset flush for 915 */ 1108 if (IS_I965 || IS_G33 || IS_G4X) { 1109 intel_i965_g33_setup_chipset_flush(); 1110 } else { 1111 intel_i915_setup_chipset_flush(); 1112 } 1113 1114 if (intel_private.ifp_resource.start) { 1115 intel_private.i9xx_flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE); 1116 if (!intel_private.i9xx_flush_page) 1117 dev_info(&intel_private.pcidev->dev, "can't ioremap flush page - no chipset flushing"); 1118 } 1119 } 1120 1121 static int intel_i915_configure(void) 1122 { 1123 struct aper_size_info_fixed *current_size; 1124 u32 temp; 1125 u16 gmch_ctrl; 1126 int i; 1127 1128 current_size = A_SIZE_FIX(agp_bridge->current_size); 1129 1130 pci_read_config_dword(intel_private.pcidev, I915_GMADDR, &temp); 1131 1132 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1133 1134 pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl); 1135 gmch_ctrl |= I830_GMCH_ENABLED; 1136 pci_write_config_word(agp_bridge->dev, I830_GMCH_CTRL, gmch_ctrl); 1137 1138 writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL); 1139 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */ 1140 1141 if (agp_bridge->driver->needs_scratch_page) { 1142 for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) { 1143 writel(agp_bridge->scratch_page, intel_private.gtt+i); 1144 } 1145 readl(intel_private.gtt+i-1); /* PCI Posting. */ 1146 } 1147 1148 global_cache_flush(); 1149 1150 intel_i9xx_setup_flush(); 1151 1152 return 0; 1153 } 1154 1155 static void intel_i915_cleanup(void) 1156 { 1157 if (intel_private.i9xx_flush_page) 1158 iounmap(intel_private.i9xx_flush_page); 1159 if (intel_private.resource_valid) 1160 release_resource(&intel_private.ifp_resource); 1161 intel_private.ifp_resource.start = 0; 1162 intel_private.resource_valid = 0; 1163 iounmap(intel_private.gtt); 1164 iounmap(intel_private.registers); 1165 } 1166 1167 static void intel_i915_chipset_flush(struct agp_bridge_data *bridge) 1168 { 1169 if (intel_private.i9xx_flush_page) 1170 writel(1, intel_private.i9xx_flush_page); 1171 } 1172 1173 static int intel_i915_insert_entries(struct agp_memory *mem, off_t pg_start, 1174 int type) 1175 { 1176 int num_entries; 1177 void *temp; 1178 int ret = -EINVAL; 1179 int mask_type; 1180 1181 if (mem->page_count == 0) 1182 goto out; 1183 1184 temp = agp_bridge->current_size; 1185 num_entries = A_SIZE_FIX(temp)->num_entries; 1186 1187 if (pg_start < intel_private.gtt_entries) { 1188 dev_printk(KERN_DEBUG, &intel_private.pcidev->dev, 1189 "pg_start == 0x%.8lx, intel_private.gtt_entries == 0x%.8x\n", 1190 pg_start, intel_private.gtt_entries); 1191 1192 dev_info(&intel_private.pcidev->dev, 1193 "trying to insert into local/stolen memory\n"); 1194 goto out_err; 1195 } 1196 1197 if ((pg_start + mem->page_count) > num_entries) 1198 goto out_err; 1199 1200 /* The i915 can't check the GTT for entries since it's read only; 1201 * depend on the caller to make the correct offset decisions. 1202 */ 1203 1204 if (type != mem->type) 1205 goto out_err; 1206 1207 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type); 1208 1209 if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY && 1210 mask_type != INTEL_AGP_CACHED_MEMORY) 1211 goto out_err; 1212 1213 if (!mem->is_flushed) 1214 global_cache_flush(); 1215 1216 intel_agp_insert_sg_entries(mem, pg_start, mask_type); 1217 agp_bridge->driver->tlb_flush(mem); 1218 1219 out: 1220 ret = 0; 1221 out_err: 1222 mem->is_flushed = true; 1223 return ret; 1224 } 1225 1226 static int intel_i915_remove_entries(struct agp_memory *mem, off_t pg_start, 1227 int type) 1228 { 1229 int i; 1230 1231 if (mem->page_count == 0) 1232 return 0; 1233 1234 if (pg_start < intel_private.gtt_entries) { 1235 dev_info(&intel_private.pcidev->dev, 1236 "trying to disable local/stolen memory\n"); 1237 return -EINVAL; 1238 } 1239 1240 for (i = pg_start; i < (mem->page_count + pg_start); i++) 1241 writel(agp_bridge->scratch_page, intel_private.gtt+i); 1242 1243 readl(intel_private.gtt+i-1); 1244 1245 agp_bridge->driver->tlb_flush(mem); 1246 return 0; 1247 } 1248 1249 /* Return the aperture size by just checking the resource length. The effect 1250 * described in the spec of the MSAC registers is just changing of the 1251 * resource size. 1252 */ 1253 static int intel_i9xx_fetch_size(void) 1254 { 1255 int num_sizes = ARRAY_SIZE(intel_i830_sizes); 1256 int aper_size; /* size in megabytes */ 1257 int i; 1258 1259 aper_size = pci_resource_len(intel_private.pcidev, 2) / MB(1); 1260 1261 for (i = 0; i < num_sizes; i++) { 1262 if (aper_size == intel_i830_sizes[i].size) { 1263 agp_bridge->current_size = intel_i830_sizes + i; 1264 agp_bridge->previous_size = agp_bridge->current_size; 1265 return aper_size; 1266 } 1267 } 1268 1269 return 0; 1270 } 1271 1272 /* The intel i915 automatically initializes the agp aperture during POST. 1273 * Use the memory already set aside for in the GTT. 1274 */ 1275 static int intel_i915_create_gatt_table(struct agp_bridge_data *bridge) 1276 { 1277 int page_order; 1278 struct aper_size_info_fixed *size; 1279 int num_entries; 1280 u32 temp, temp2; 1281 int gtt_map_size = 256 * 1024; 1282 1283 size = agp_bridge->current_size; 1284 page_order = size->page_order; 1285 num_entries = size->num_entries; 1286 agp_bridge->gatt_table_real = NULL; 1287 1288 pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp); 1289 pci_read_config_dword(intel_private.pcidev, I915_PTEADDR, &temp2); 1290 1291 if (IS_G33) 1292 gtt_map_size = 1024 * 1024; /* 1M on G33 */ 1293 intel_private.gtt = ioremap(temp2, gtt_map_size); 1294 if (!intel_private.gtt) 1295 return -ENOMEM; 1296 1297 temp &= 0xfff80000; 1298 1299 intel_private.registers = ioremap(temp, 128 * 4096); 1300 if (!intel_private.registers) { 1301 iounmap(intel_private.gtt); 1302 return -ENOMEM; 1303 } 1304 1305 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000; 1306 global_cache_flush(); /* FIXME: ? */ 1307 1308 /* we have to call this as early as possible after the MMIO base address is known */ 1309 intel_i830_init_gtt_entries(); 1310 1311 agp_bridge->gatt_table = NULL; 1312 1313 agp_bridge->gatt_bus_addr = temp; 1314 1315 return 0; 1316 } 1317 1318 /* 1319 * The i965 supports 36-bit physical addresses, but to keep 1320 * the format of the GTT the same, the bits that don't fit 1321 * in a 32-bit word are shifted down to bits 4..7. 1322 * 1323 * Gcc is smart enough to notice that "(addr >> 28) & 0xf0" 1324 * is always zero on 32-bit architectures, so no need to make 1325 * this conditional. 1326 */ 1327 static unsigned long intel_i965_mask_memory(struct agp_bridge_data *bridge, 1328 dma_addr_t addr, int type) 1329 { 1330 /* Shift high bits down */ 1331 addr |= (addr >> 28) & 0xf0; 1332 1333 /* Type checking must be done elsewhere */ 1334 return addr | bridge->driver->masks[type].mask; 1335 } 1336 1337 static void intel_i965_get_gtt_range(int *gtt_offset, int *gtt_size) 1338 { 1339 switch (agp_bridge->dev->device) { 1340 case PCI_DEVICE_ID_INTEL_GM45_HB: 1341 case PCI_DEVICE_ID_INTEL_IGD_E_HB: 1342 case PCI_DEVICE_ID_INTEL_Q45_HB: 1343 case PCI_DEVICE_ID_INTEL_G45_HB: 1344 case PCI_DEVICE_ID_INTEL_G41_HB: 1345 case PCI_DEVICE_ID_INTEL_IGDNG_D_HB: 1346 case PCI_DEVICE_ID_INTEL_IGDNG_M_HB: 1347 *gtt_offset = *gtt_size = MB(2); 1348 break; 1349 default: 1350 *gtt_offset = *gtt_size = KB(512); 1351 } 1352 } 1353 1354 /* The intel i965 automatically initializes the agp aperture during POST. 1355 * Use the memory already set aside for in the GTT. 1356 */ 1357 static int intel_i965_create_gatt_table(struct agp_bridge_data *bridge) 1358 { 1359 int page_order; 1360 struct aper_size_info_fixed *size; 1361 int num_entries; 1362 u32 temp; 1363 int gtt_offset, gtt_size; 1364 1365 size = agp_bridge->current_size; 1366 page_order = size->page_order; 1367 num_entries = size->num_entries; 1368 agp_bridge->gatt_table_real = NULL; 1369 1370 pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp); 1371 1372 temp &= 0xfff00000; 1373 1374 intel_i965_get_gtt_range(>t_offset, >t_size); 1375 1376 intel_private.gtt = ioremap((temp + gtt_offset) , gtt_size); 1377 1378 if (!intel_private.gtt) 1379 return -ENOMEM; 1380 1381 intel_private.registers = ioremap(temp, 128 * 4096); 1382 if (!intel_private.registers) { 1383 iounmap(intel_private.gtt); 1384 return -ENOMEM; 1385 } 1386 1387 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000; 1388 global_cache_flush(); /* FIXME: ? */ 1389 1390 /* we have to call this as early as possible after the MMIO base address is known */ 1391 intel_i830_init_gtt_entries(); 1392 1393 agp_bridge->gatt_table = NULL; 1394 1395 agp_bridge->gatt_bus_addr = temp; 1396 1397 return 0; 1398 } 1399 1400 1401 static int intel_fetch_size(void) 1402 { 1403 int i; 1404 u16 temp; 1405 struct aper_size_info_16 *values; 1406 1407 pci_read_config_word(agp_bridge->dev, INTEL_APSIZE, &temp); 1408 values = A_SIZE_16(agp_bridge->driver->aperture_sizes); 1409 1410 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) { 1411 if (temp == values[i].size_value) { 1412 agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + i); 1413 agp_bridge->aperture_size_idx = i; 1414 return values[i].size; 1415 } 1416 } 1417 1418 return 0; 1419 } 1420 1421 static int __intel_8xx_fetch_size(u8 temp) 1422 { 1423 int i; 1424 struct aper_size_info_8 *values; 1425 1426 values = A_SIZE_8(agp_bridge->driver->aperture_sizes); 1427 1428 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) { 1429 if (temp == values[i].size_value) { 1430 agp_bridge->previous_size = 1431 agp_bridge->current_size = (void *) (values + i); 1432 agp_bridge->aperture_size_idx = i; 1433 return values[i].size; 1434 } 1435 } 1436 return 0; 1437 } 1438 1439 static int intel_8xx_fetch_size(void) 1440 { 1441 u8 temp; 1442 1443 pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp); 1444 return __intel_8xx_fetch_size(temp); 1445 } 1446 1447 static int intel_815_fetch_size(void) 1448 { 1449 u8 temp; 1450 1451 /* Intel 815 chipsets have a _weird_ APSIZE register with only 1452 * one non-reserved bit, so mask the others out ... */ 1453 pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp); 1454 temp &= (1 << 3); 1455 1456 return __intel_8xx_fetch_size(temp); 1457 } 1458 1459 static void intel_tlbflush(struct agp_memory *mem) 1460 { 1461 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2200); 1462 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280); 1463 } 1464 1465 1466 static void intel_8xx_tlbflush(struct agp_memory *mem) 1467 { 1468 u32 temp; 1469 pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp); 1470 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp & ~(1 << 7)); 1471 pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp); 1472 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp | (1 << 7)); 1473 } 1474 1475 1476 static void intel_cleanup(void) 1477 { 1478 u16 temp; 1479 struct aper_size_info_16 *previous_size; 1480 1481 previous_size = A_SIZE_16(agp_bridge->previous_size); 1482 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp); 1483 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9)); 1484 pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value); 1485 } 1486 1487 1488 static void intel_8xx_cleanup(void) 1489 { 1490 u16 temp; 1491 struct aper_size_info_8 *previous_size; 1492 1493 previous_size = A_SIZE_8(agp_bridge->previous_size); 1494 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp); 1495 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9)); 1496 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value); 1497 } 1498 1499 1500 static int intel_configure(void) 1501 { 1502 u32 temp; 1503 u16 temp2; 1504 struct aper_size_info_16 *current_size; 1505 1506 current_size = A_SIZE_16(agp_bridge->current_size); 1507 1508 /* aperture size */ 1509 pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 1510 1511 /* address to map to */ 1512 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 1513 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1514 1515 /* attbase - aperture base */ 1516 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); 1517 1518 /* agpctrl */ 1519 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280); 1520 1521 /* paccfg/nbxcfg */ 1522 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2); 1523 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, 1524 (temp2 & ~(1 << 10)) | (1 << 9)); 1525 /* clear any possible error conditions */ 1526 pci_write_config_byte(agp_bridge->dev, INTEL_ERRSTS + 1, 7); 1527 return 0; 1528 } 1529 1530 static int intel_815_configure(void) 1531 { 1532 u32 temp, addr; 1533 u8 temp2; 1534 struct aper_size_info_8 *current_size; 1535 1536 /* attbase - aperture base */ 1537 /* the Intel 815 chipset spec. says that bits 29-31 in the 1538 * ATTBASE register are reserved -> try not to write them */ 1539 if (agp_bridge->gatt_bus_addr & INTEL_815_ATTBASE_MASK) { 1540 dev_emerg(&agp_bridge->dev->dev, "gatt bus addr too high"); 1541 return -EINVAL; 1542 } 1543 1544 current_size = A_SIZE_8(agp_bridge->current_size); 1545 1546 /* aperture size */ 1547 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, 1548 current_size->size_value); 1549 1550 /* address to map to */ 1551 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 1552 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1553 1554 pci_read_config_dword(agp_bridge->dev, INTEL_ATTBASE, &addr); 1555 addr &= INTEL_815_ATTBASE_MASK; 1556 addr |= agp_bridge->gatt_bus_addr; 1557 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, addr); 1558 1559 /* agpctrl */ 1560 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); 1561 1562 /* apcont */ 1563 pci_read_config_byte(agp_bridge->dev, INTEL_815_APCONT, &temp2); 1564 pci_write_config_byte(agp_bridge->dev, INTEL_815_APCONT, temp2 | (1 << 1)); 1565 1566 /* clear any possible error conditions */ 1567 /* Oddness : this chipset seems to have no ERRSTS register ! */ 1568 return 0; 1569 } 1570 1571 static void intel_820_tlbflush(struct agp_memory *mem) 1572 { 1573 return; 1574 } 1575 1576 static void intel_820_cleanup(void) 1577 { 1578 u8 temp; 1579 struct aper_size_info_8 *previous_size; 1580 1581 previous_size = A_SIZE_8(agp_bridge->previous_size); 1582 pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp); 1583 pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR, 1584 temp & ~(1 << 1)); 1585 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, 1586 previous_size->size_value); 1587 } 1588 1589 1590 static int intel_820_configure(void) 1591 { 1592 u32 temp; 1593 u8 temp2; 1594 struct aper_size_info_8 *current_size; 1595 1596 current_size = A_SIZE_8(agp_bridge->current_size); 1597 1598 /* aperture size */ 1599 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 1600 1601 /* address to map to */ 1602 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 1603 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1604 1605 /* attbase - aperture base */ 1606 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); 1607 1608 /* agpctrl */ 1609 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); 1610 1611 /* global enable aperture access */ 1612 /* This flag is not accessed through MCHCFG register as in */ 1613 /* i850 chipset. */ 1614 pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp2); 1615 pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR, temp2 | (1 << 1)); 1616 /* clear any possible AGP-related error conditions */ 1617 pci_write_config_word(agp_bridge->dev, INTEL_I820_ERRSTS, 0x001c); 1618 return 0; 1619 } 1620 1621 static int intel_840_configure(void) 1622 { 1623 u32 temp; 1624 u16 temp2; 1625 struct aper_size_info_8 *current_size; 1626 1627 current_size = A_SIZE_8(agp_bridge->current_size); 1628 1629 /* aperture size */ 1630 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 1631 1632 /* address to map to */ 1633 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 1634 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1635 1636 /* attbase - aperture base */ 1637 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); 1638 1639 /* agpctrl */ 1640 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); 1641 1642 /* mcgcfg */ 1643 pci_read_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, &temp2); 1644 pci_write_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, temp2 | (1 << 9)); 1645 /* clear any possible error conditions */ 1646 pci_write_config_word(agp_bridge->dev, INTEL_I840_ERRSTS, 0xc000); 1647 return 0; 1648 } 1649 1650 static int intel_845_configure(void) 1651 { 1652 u32 temp; 1653 u8 temp2; 1654 struct aper_size_info_8 *current_size; 1655 1656 current_size = A_SIZE_8(agp_bridge->current_size); 1657 1658 /* aperture size */ 1659 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 1660 1661 if (agp_bridge->apbase_config != 0) { 1662 pci_write_config_dword(agp_bridge->dev, AGP_APBASE, 1663 agp_bridge->apbase_config); 1664 } else { 1665 /* address to map to */ 1666 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 1667 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1668 agp_bridge->apbase_config = temp; 1669 } 1670 1671 /* attbase - aperture base */ 1672 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); 1673 1674 /* agpctrl */ 1675 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); 1676 1677 /* agpm */ 1678 pci_read_config_byte(agp_bridge->dev, INTEL_I845_AGPM, &temp2); 1679 pci_write_config_byte(agp_bridge->dev, INTEL_I845_AGPM, temp2 | (1 << 1)); 1680 /* clear any possible error conditions */ 1681 pci_write_config_word(agp_bridge->dev, INTEL_I845_ERRSTS, 0x001c); 1682 1683 intel_i830_setup_flush(); 1684 return 0; 1685 } 1686 1687 static int intel_850_configure(void) 1688 { 1689 u32 temp; 1690 u16 temp2; 1691 struct aper_size_info_8 *current_size; 1692 1693 current_size = A_SIZE_8(agp_bridge->current_size); 1694 1695 /* aperture size */ 1696 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 1697 1698 /* address to map to */ 1699 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 1700 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1701 1702 /* attbase - aperture base */ 1703 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); 1704 1705 /* agpctrl */ 1706 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); 1707 1708 /* mcgcfg */ 1709 pci_read_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, &temp2); 1710 pci_write_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, temp2 | (1 << 9)); 1711 /* clear any possible AGP-related error conditions */ 1712 pci_write_config_word(agp_bridge->dev, INTEL_I850_ERRSTS, 0x001c); 1713 return 0; 1714 } 1715 1716 static int intel_860_configure(void) 1717 { 1718 u32 temp; 1719 u16 temp2; 1720 struct aper_size_info_8 *current_size; 1721 1722 current_size = A_SIZE_8(agp_bridge->current_size); 1723 1724 /* aperture size */ 1725 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 1726 1727 /* address to map to */ 1728 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 1729 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1730 1731 /* attbase - aperture base */ 1732 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); 1733 1734 /* agpctrl */ 1735 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); 1736 1737 /* mcgcfg */ 1738 pci_read_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, &temp2); 1739 pci_write_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, temp2 | (1 << 9)); 1740 /* clear any possible AGP-related error conditions */ 1741 pci_write_config_word(agp_bridge->dev, INTEL_I860_ERRSTS, 0xf700); 1742 return 0; 1743 } 1744 1745 static int intel_830mp_configure(void) 1746 { 1747 u32 temp; 1748 u16 temp2; 1749 struct aper_size_info_8 *current_size; 1750 1751 current_size = A_SIZE_8(agp_bridge->current_size); 1752 1753 /* aperture size */ 1754 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 1755 1756 /* address to map to */ 1757 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 1758 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1759 1760 /* attbase - aperture base */ 1761 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); 1762 1763 /* agpctrl */ 1764 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); 1765 1766 /* gmch */ 1767 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2); 1768 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp2 | (1 << 9)); 1769 /* clear any possible AGP-related error conditions */ 1770 pci_write_config_word(agp_bridge->dev, INTEL_I830_ERRSTS, 0x1c); 1771 return 0; 1772 } 1773 1774 static int intel_7505_configure(void) 1775 { 1776 u32 temp; 1777 u16 temp2; 1778 struct aper_size_info_8 *current_size; 1779 1780 current_size = A_SIZE_8(agp_bridge->current_size); 1781 1782 /* aperture size */ 1783 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 1784 1785 /* address to map to */ 1786 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 1787 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1788 1789 /* attbase - aperture base */ 1790 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); 1791 1792 /* agpctrl */ 1793 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); 1794 1795 /* mchcfg */ 1796 pci_read_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, &temp2); 1797 pci_write_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, temp2 | (1 << 9)); 1798 1799 return 0; 1800 } 1801 1802 /* Setup function */ 1803 static const struct gatt_mask intel_generic_masks[] = 1804 { 1805 {.mask = 0x00000017, .type = 0} 1806 }; 1807 1808 static const struct aper_size_info_8 intel_815_sizes[2] = 1809 { 1810 {64, 16384, 4, 0}, 1811 {32, 8192, 3, 8}, 1812 }; 1813 1814 static const struct aper_size_info_8 intel_8xx_sizes[7] = 1815 { 1816 {256, 65536, 6, 0}, 1817 {128, 32768, 5, 32}, 1818 {64, 16384, 4, 48}, 1819 {32, 8192, 3, 56}, 1820 {16, 4096, 2, 60}, 1821 {8, 2048, 1, 62}, 1822 {4, 1024, 0, 63} 1823 }; 1824 1825 static const struct aper_size_info_16 intel_generic_sizes[7] = 1826 { 1827 {256, 65536, 6, 0}, 1828 {128, 32768, 5, 32}, 1829 {64, 16384, 4, 48}, 1830 {32, 8192, 3, 56}, 1831 {16, 4096, 2, 60}, 1832 {8, 2048, 1, 62}, 1833 {4, 1024, 0, 63} 1834 }; 1835 1836 static const struct aper_size_info_8 intel_830mp_sizes[4] = 1837 { 1838 {256, 65536, 6, 0}, 1839 {128, 32768, 5, 32}, 1840 {64, 16384, 4, 48}, 1841 {32, 8192, 3, 56} 1842 }; 1843 1844 static const struct agp_bridge_driver intel_generic_driver = { 1845 .owner = THIS_MODULE, 1846 .aperture_sizes = intel_generic_sizes, 1847 .size_type = U16_APER_SIZE, 1848 .num_aperture_sizes = 7, 1849 .configure = intel_configure, 1850 .fetch_size = intel_fetch_size, 1851 .cleanup = intel_cleanup, 1852 .tlb_flush = intel_tlbflush, 1853 .mask_memory = agp_generic_mask_memory, 1854 .masks = intel_generic_masks, 1855 .agp_enable = agp_generic_enable, 1856 .cache_flush = global_cache_flush, 1857 .create_gatt_table = agp_generic_create_gatt_table, 1858 .free_gatt_table = agp_generic_free_gatt_table, 1859 .insert_memory = agp_generic_insert_memory, 1860 .remove_memory = agp_generic_remove_memory, 1861 .alloc_by_type = agp_generic_alloc_by_type, 1862 .free_by_type = agp_generic_free_by_type, 1863 .agp_alloc_page = agp_generic_alloc_page, 1864 .agp_alloc_pages = agp_generic_alloc_pages, 1865 .agp_destroy_page = agp_generic_destroy_page, 1866 .agp_destroy_pages = agp_generic_destroy_pages, 1867 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 1868 }; 1869 1870 static const struct agp_bridge_driver intel_810_driver = { 1871 .owner = THIS_MODULE, 1872 .aperture_sizes = intel_i810_sizes, 1873 .size_type = FIXED_APER_SIZE, 1874 .num_aperture_sizes = 2, 1875 .needs_scratch_page = true, 1876 .configure = intel_i810_configure, 1877 .fetch_size = intel_i810_fetch_size, 1878 .cleanup = intel_i810_cleanup, 1879 .tlb_flush = intel_i810_tlbflush, 1880 .mask_memory = intel_i810_mask_memory, 1881 .masks = intel_i810_masks, 1882 .agp_enable = intel_i810_agp_enable, 1883 .cache_flush = global_cache_flush, 1884 .create_gatt_table = agp_generic_create_gatt_table, 1885 .free_gatt_table = agp_generic_free_gatt_table, 1886 .insert_memory = intel_i810_insert_entries, 1887 .remove_memory = intel_i810_remove_entries, 1888 .alloc_by_type = intel_i810_alloc_by_type, 1889 .free_by_type = intel_i810_free_by_type, 1890 .agp_alloc_page = agp_generic_alloc_page, 1891 .agp_alloc_pages = agp_generic_alloc_pages, 1892 .agp_destroy_page = agp_generic_destroy_page, 1893 .agp_destroy_pages = agp_generic_destroy_pages, 1894 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 1895 }; 1896 1897 static const struct agp_bridge_driver intel_815_driver = { 1898 .owner = THIS_MODULE, 1899 .aperture_sizes = intel_815_sizes, 1900 .size_type = U8_APER_SIZE, 1901 .num_aperture_sizes = 2, 1902 .configure = intel_815_configure, 1903 .fetch_size = intel_815_fetch_size, 1904 .cleanup = intel_8xx_cleanup, 1905 .tlb_flush = intel_8xx_tlbflush, 1906 .mask_memory = agp_generic_mask_memory, 1907 .masks = intel_generic_masks, 1908 .agp_enable = agp_generic_enable, 1909 .cache_flush = global_cache_flush, 1910 .create_gatt_table = agp_generic_create_gatt_table, 1911 .free_gatt_table = agp_generic_free_gatt_table, 1912 .insert_memory = agp_generic_insert_memory, 1913 .remove_memory = agp_generic_remove_memory, 1914 .alloc_by_type = agp_generic_alloc_by_type, 1915 .free_by_type = agp_generic_free_by_type, 1916 .agp_alloc_page = agp_generic_alloc_page, 1917 .agp_alloc_pages = agp_generic_alloc_pages, 1918 .agp_destroy_page = agp_generic_destroy_page, 1919 .agp_destroy_pages = agp_generic_destroy_pages, 1920 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 1921 }; 1922 1923 static const struct agp_bridge_driver intel_830_driver = { 1924 .owner = THIS_MODULE, 1925 .aperture_sizes = intel_i830_sizes, 1926 .size_type = FIXED_APER_SIZE, 1927 .num_aperture_sizes = 4, 1928 .needs_scratch_page = true, 1929 .configure = intel_i830_configure, 1930 .fetch_size = intel_i830_fetch_size, 1931 .cleanup = intel_i830_cleanup, 1932 .tlb_flush = intel_i810_tlbflush, 1933 .mask_memory = intel_i810_mask_memory, 1934 .masks = intel_i810_masks, 1935 .agp_enable = intel_i810_agp_enable, 1936 .cache_flush = global_cache_flush, 1937 .create_gatt_table = intel_i830_create_gatt_table, 1938 .free_gatt_table = intel_i830_free_gatt_table, 1939 .insert_memory = intel_i830_insert_entries, 1940 .remove_memory = intel_i830_remove_entries, 1941 .alloc_by_type = intel_i830_alloc_by_type, 1942 .free_by_type = intel_i810_free_by_type, 1943 .agp_alloc_page = agp_generic_alloc_page, 1944 .agp_alloc_pages = agp_generic_alloc_pages, 1945 .agp_destroy_page = agp_generic_destroy_page, 1946 .agp_destroy_pages = agp_generic_destroy_pages, 1947 .agp_type_to_mask_type = intel_i830_type_to_mask_type, 1948 .chipset_flush = intel_i830_chipset_flush, 1949 }; 1950 1951 static const struct agp_bridge_driver intel_820_driver = { 1952 .owner = THIS_MODULE, 1953 .aperture_sizes = intel_8xx_sizes, 1954 .size_type = U8_APER_SIZE, 1955 .num_aperture_sizes = 7, 1956 .configure = intel_820_configure, 1957 .fetch_size = intel_8xx_fetch_size, 1958 .cleanup = intel_820_cleanup, 1959 .tlb_flush = intel_820_tlbflush, 1960 .mask_memory = agp_generic_mask_memory, 1961 .masks = intel_generic_masks, 1962 .agp_enable = agp_generic_enable, 1963 .cache_flush = global_cache_flush, 1964 .create_gatt_table = agp_generic_create_gatt_table, 1965 .free_gatt_table = agp_generic_free_gatt_table, 1966 .insert_memory = agp_generic_insert_memory, 1967 .remove_memory = agp_generic_remove_memory, 1968 .alloc_by_type = agp_generic_alloc_by_type, 1969 .free_by_type = agp_generic_free_by_type, 1970 .agp_alloc_page = agp_generic_alloc_page, 1971 .agp_alloc_pages = agp_generic_alloc_pages, 1972 .agp_destroy_page = agp_generic_destroy_page, 1973 .agp_destroy_pages = agp_generic_destroy_pages, 1974 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 1975 }; 1976 1977 static const struct agp_bridge_driver intel_830mp_driver = { 1978 .owner = THIS_MODULE, 1979 .aperture_sizes = intel_830mp_sizes, 1980 .size_type = U8_APER_SIZE, 1981 .num_aperture_sizes = 4, 1982 .configure = intel_830mp_configure, 1983 .fetch_size = intel_8xx_fetch_size, 1984 .cleanup = intel_8xx_cleanup, 1985 .tlb_flush = intel_8xx_tlbflush, 1986 .mask_memory = agp_generic_mask_memory, 1987 .masks = intel_generic_masks, 1988 .agp_enable = agp_generic_enable, 1989 .cache_flush = global_cache_flush, 1990 .create_gatt_table = agp_generic_create_gatt_table, 1991 .free_gatt_table = agp_generic_free_gatt_table, 1992 .insert_memory = agp_generic_insert_memory, 1993 .remove_memory = agp_generic_remove_memory, 1994 .alloc_by_type = agp_generic_alloc_by_type, 1995 .free_by_type = agp_generic_free_by_type, 1996 .agp_alloc_page = agp_generic_alloc_page, 1997 .agp_alloc_pages = agp_generic_alloc_pages, 1998 .agp_destroy_page = agp_generic_destroy_page, 1999 .agp_destroy_pages = agp_generic_destroy_pages, 2000 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 2001 }; 2002 2003 static const struct agp_bridge_driver intel_840_driver = { 2004 .owner = THIS_MODULE, 2005 .aperture_sizes = intel_8xx_sizes, 2006 .size_type = U8_APER_SIZE, 2007 .num_aperture_sizes = 7, 2008 .configure = intel_840_configure, 2009 .fetch_size = intel_8xx_fetch_size, 2010 .cleanup = intel_8xx_cleanup, 2011 .tlb_flush = intel_8xx_tlbflush, 2012 .mask_memory = agp_generic_mask_memory, 2013 .masks = intel_generic_masks, 2014 .agp_enable = agp_generic_enable, 2015 .cache_flush = global_cache_flush, 2016 .create_gatt_table = agp_generic_create_gatt_table, 2017 .free_gatt_table = agp_generic_free_gatt_table, 2018 .insert_memory = agp_generic_insert_memory, 2019 .remove_memory = agp_generic_remove_memory, 2020 .alloc_by_type = agp_generic_alloc_by_type, 2021 .free_by_type = agp_generic_free_by_type, 2022 .agp_alloc_page = agp_generic_alloc_page, 2023 .agp_alloc_pages = agp_generic_alloc_pages, 2024 .agp_destroy_page = agp_generic_destroy_page, 2025 .agp_destroy_pages = agp_generic_destroy_pages, 2026 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 2027 }; 2028 2029 static const struct agp_bridge_driver intel_845_driver = { 2030 .owner = THIS_MODULE, 2031 .aperture_sizes = intel_8xx_sizes, 2032 .size_type = U8_APER_SIZE, 2033 .num_aperture_sizes = 7, 2034 .configure = intel_845_configure, 2035 .fetch_size = intel_8xx_fetch_size, 2036 .cleanup = intel_8xx_cleanup, 2037 .tlb_flush = intel_8xx_tlbflush, 2038 .mask_memory = agp_generic_mask_memory, 2039 .masks = intel_generic_masks, 2040 .agp_enable = agp_generic_enable, 2041 .cache_flush = global_cache_flush, 2042 .create_gatt_table = agp_generic_create_gatt_table, 2043 .free_gatt_table = agp_generic_free_gatt_table, 2044 .insert_memory = agp_generic_insert_memory, 2045 .remove_memory = agp_generic_remove_memory, 2046 .alloc_by_type = agp_generic_alloc_by_type, 2047 .free_by_type = agp_generic_free_by_type, 2048 .agp_alloc_page = agp_generic_alloc_page, 2049 .agp_alloc_pages = agp_generic_alloc_pages, 2050 .agp_destroy_page = agp_generic_destroy_page, 2051 .agp_destroy_pages = agp_generic_destroy_pages, 2052 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 2053 .chipset_flush = intel_i830_chipset_flush, 2054 }; 2055 2056 static const struct agp_bridge_driver intel_850_driver = { 2057 .owner = THIS_MODULE, 2058 .aperture_sizes = intel_8xx_sizes, 2059 .size_type = U8_APER_SIZE, 2060 .num_aperture_sizes = 7, 2061 .configure = intel_850_configure, 2062 .fetch_size = intel_8xx_fetch_size, 2063 .cleanup = intel_8xx_cleanup, 2064 .tlb_flush = intel_8xx_tlbflush, 2065 .mask_memory = agp_generic_mask_memory, 2066 .masks = intel_generic_masks, 2067 .agp_enable = agp_generic_enable, 2068 .cache_flush = global_cache_flush, 2069 .create_gatt_table = agp_generic_create_gatt_table, 2070 .free_gatt_table = agp_generic_free_gatt_table, 2071 .insert_memory = agp_generic_insert_memory, 2072 .remove_memory = agp_generic_remove_memory, 2073 .alloc_by_type = agp_generic_alloc_by_type, 2074 .free_by_type = agp_generic_free_by_type, 2075 .agp_alloc_page = agp_generic_alloc_page, 2076 .agp_alloc_pages = agp_generic_alloc_pages, 2077 .agp_destroy_page = agp_generic_destroy_page, 2078 .agp_destroy_pages = agp_generic_destroy_pages, 2079 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 2080 }; 2081 2082 static const struct agp_bridge_driver intel_860_driver = { 2083 .owner = THIS_MODULE, 2084 .aperture_sizes = intel_8xx_sizes, 2085 .size_type = U8_APER_SIZE, 2086 .num_aperture_sizes = 7, 2087 .configure = intel_860_configure, 2088 .fetch_size = intel_8xx_fetch_size, 2089 .cleanup = intel_8xx_cleanup, 2090 .tlb_flush = intel_8xx_tlbflush, 2091 .mask_memory = agp_generic_mask_memory, 2092 .masks = intel_generic_masks, 2093 .agp_enable = agp_generic_enable, 2094 .cache_flush = global_cache_flush, 2095 .create_gatt_table = agp_generic_create_gatt_table, 2096 .free_gatt_table = agp_generic_free_gatt_table, 2097 .insert_memory = agp_generic_insert_memory, 2098 .remove_memory = agp_generic_remove_memory, 2099 .alloc_by_type = agp_generic_alloc_by_type, 2100 .free_by_type = agp_generic_free_by_type, 2101 .agp_alloc_page = agp_generic_alloc_page, 2102 .agp_alloc_pages = agp_generic_alloc_pages, 2103 .agp_destroy_page = agp_generic_destroy_page, 2104 .agp_destroy_pages = agp_generic_destroy_pages, 2105 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 2106 }; 2107 2108 static const struct agp_bridge_driver intel_915_driver = { 2109 .owner = THIS_MODULE, 2110 .aperture_sizes = intel_i830_sizes, 2111 .size_type = FIXED_APER_SIZE, 2112 .num_aperture_sizes = 4, 2113 .needs_scratch_page = true, 2114 .configure = intel_i915_configure, 2115 .fetch_size = intel_i9xx_fetch_size, 2116 .cleanup = intel_i915_cleanup, 2117 .tlb_flush = intel_i810_tlbflush, 2118 .mask_memory = intel_i810_mask_memory, 2119 .masks = intel_i810_masks, 2120 .agp_enable = intel_i810_agp_enable, 2121 .cache_flush = global_cache_flush, 2122 .create_gatt_table = intel_i915_create_gatt_table, 2123 .free_gatt_table = intel_i830_free_gatt_table, 2124 .insert_memory = intel_i915_insert_entries, 2125 .remove_memory = intel_i915_remove_entries, 2126 .alloc_by_type = intel_i830_alloc_by_type, 2127 .free_by_type = intel_i810_free_by_type, 2128 .agp_alloc_page = agp_generic_alloc_page, 2129 .agp_alloc_pages = agp_generic_alloc_pages, 2130 .agp_destroy_page = agp_generic_destroy_page, 2131 .agp_destroy_pages = agp_generic_destroy_pages, 2132 .agp_type_to_mask_type = intel_i830_type_to_mask_type, 2133 .chipset_flush = intel_i915_chipset_flush, 2134 #ifdef USE_PCI_DMA_API 2135 .agp_map_page = intel_agp_map_page, 2136 .agp_unmap_page = intel_agp_unmap_page, 2137 .agp_map_memory = intel_agp_map_memory, 2138 .agp_unmap_memory = intel_agp_unmap_memory, 2139 #endif 2140 }; 2141 2142 static const struct agp_bridge_driver intel_i965_driver = { 2143 .owner = THIS_MODULE, 2144 .aperture_sizes = intel_i830_sizes, 2145 .size_type = FIXED_APER_SIZE, 2146 .num_aperture_sizes = 4, 2147 .needs_scratch_page = true, 2148 .configure = intel_i915_configure, 2149 .fetch_size = intel_i9xx_fetch_size, 2150 .cleanup = intel_i915_cleanup, 2151 .tlb_flush = intel_i810_tlbflush, 2152 .mask_memory = intel_i965_mask_memory, 2153 .masks = intel_i810_masks, 2154 .agp_enable = intel_i810_agp_enable, 2155 .cache_flush = global_cache_flush, 2156 .create_gatt_table = intel_i965_create_gatt_table, 2157 .free_gatt_table = intel_i830_free_gatt_table, 2158 .insert_memory = intel_i915_insert_entries, 2159 .remove_memory = intel_i915_remove_entries, 2160 .alloc_by_type = intel_i830_alloc_by_type, 2161 .free_by_type = intel_i810_free_by_type, 2162 .agp_alloc_page = agp_generic_alloc_page, 2163 .agp_alloc_pages = agp_generic_alloc_pages, 2164 .agp_destroy_page = agp_generic_destroy_page, 2165 .agp_destroy_pages = agp_generic_destroy_pages, 2166 .agp_type_to_mask_type = intel_i830_type_to_mask_type, 2167 .chipset_flush = intel_i915_chipset_flush, 2168 #ifdef USE_PCI_DMA_API 2169 .agp_map_page = intel_agp_map_page, 2170 .agp_unmap_page = intel_agp_unmap_page, 2171 .agp_map_memory = intel_agp_map_memory, 2172 .agp_unmap_memory = intel_agp_unmap_memory, 2173 #endif 2174 }; 2175 2176 static const struct agp_bridge_driver intel_7505_driver = { 2177 .owner = THIS_MODULE, 2178 .aperture_sizes = intel_8xx_sizes, 2179 .size_type = U8_APER_SIZE, 2180 .num_aperture_sizes = 7, 2181 .configure = intel_7505_configure, 2182 .fetch_size = intel_8xx_fetch_size, 2183 .cleanup = intel_8xx_cleanup, 2184 .tlb_flush = intel_8xx_tlbflush, 2185 .mask_memory = agp_generic_mask_memory, 2186 .masks = intel_generic_masks, 2187 .agp_enable = agp_generic_enable, 2188 .cache_flush = global_cache_flush, 2189 .create_gatt_table = agp_generic_create_gatt_table, 2190 .free_gatt_table = agp_generic_free_gatt_table, 2191 .insert_memory = agp_generic_insert_memory, 2192 .remove_memory = agp_generic_remove_memory, 2193 .alloc_by_type = agp_generic_alloc_by_type, 2194 .free_by_type = agp_generic_free_by_type, 2195 .agp_alloc_page = agp_generic_alloc_page, 2196 .agp_alloc_pages = agp_generic_alloc_pages, 2197 .agp_destroy_page = agp_generic_destroy_page, 2198 .agp_destroy_pages = agp_generic_destroy_pages, 2199 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 2200 }; 2201 2202 static const struct agp_bridge_driver intel_g33_driver = { 2203 .owner = THIS_MODULE, 2204 .aperture_sizes = intel_i830_sizes, 2205 .size_type = FIXED_APER_SIZE, 2206 .num_aperture_sizes = 4, 2207 .needs_scratch_page = true, 2208 .configure = intel_i915_configure, 2209 .fetch_size = intel_i9xx_fetch_size, 2210 .cleanup = intel_i915_cleanup, 2211 .tlb_flush = intel_i810_tlbflush, 2212 .mask_memory = intel_i965_mask_memory, 2213 .masks = intel_i810_masks, 2214 .agp_enable = intel_i810_agp_enable, 2215 .cache_flush = global_cache_flush, 2216 .create_gatt_table = intel_i915_create_gatt_table, 2217 .free_gatt_table = intel_i830_free_gatt_table, 2218 .insert_memory = intel_i915_insert_entries, 2219 .remove_memory = intel_i915_remove_entries, 2220 .alloc_by_type = intel_i830_alloc_by_type, 2221 .free_by_type = intel_i810_free_by_type, 2222 .agp_alloc_page = agp_generic_alloc_page, 2223 .agp_alloc_pages = agp_generic_alloc_pages, 2224 .agp_destroy_page = agp_generic_destroy_page, 2225 .agp_destroy_pages = agp_generic_destroy_pages, 2226 .agp_type_to_mask_type = intel_i830_type_to_mask_type, 2227 .chipset_flush = intel_i915_chipset_flush, 2228 #ifdef USE_PCI_DMA_API 2229 .agp_map_page = intel_agp_map_page, 2230 .agp_unmap_page = intel_agp_unmap_page, 2231 .agp_map_memory = intel_agp_map_memory, 2232 .agp_unmap_memory = intel_agp_unmap_memory, 2233 #endif 2234 }; 2235 2236 static int find_gmch(u16 device) 2237 { 2238 struct pci_dev *gmch_device; 2239 2240 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL); 2241 if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) { 2242 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, 2243 device, gmch_device); 2244 } 2245 2246 if (!gmch_device) 2247 return 0; 2248 2249 intel_private.pcidev = gmch_device; 2250 return 1; 2251 } 2252 2253 /* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of 2254 * driver and gmch_driver must be non-null, and find_gmch will determine 2255 * which one should be used if a gmch_chip_id is present. 2256 */ 2257 static const struct intel_driver_description { 2258 unsigned int chip_id; 2259 unsigned int gmch_chip_id; 2260 unsigned int multi_gmch_chip; /* if we have more gfx chip type on this HB. */ 2261 char *name; 2262 const struct agp_bridge_driver *driver; 2263 const struct agp_bridge_driver *gmch_driver; 2264 } intel_agp_chipsets[] = { 2265 { PCI_DEVICE_ID_INTEL_82443LX_0, 0, 0, "440LX", &intel_generic_driver, NULL }, 2266 { PCI_DEVICE_ID_INTEL_82443BX_0, 0, 0, "440BX", &intel_generic_driver, NULL }, 2267 { PCI_DEVICE_ID_INTEL_82443GX_0, 0, 0, "440GX", &intel_generic_driver, NULL }, 2268 { PCI_DEVICE_ID_INTEL_82810_MC1, PCI_DEVICE_ID_INTEL_82810_IG1, 0, "i810", 2269 NULL, &intel_810_driver }, 2270 { PCI_DEVICE_ID_INTEL_82810_MC3, PCI_DEVICE_ID_INTEL_82810_IG3, 0, "i810", 2271 NULL, &intel_810_driver }, 2272 { PCI_DEVICE_ID_INTEL_82810E_MC, PCI_DEVICE_ID_INTEL_82810E_IG, 0, "i810", 2273 NULL, &intel_810_driver }, 2274 { PCI_DEVICE_ID_INTEL_82815_MC, PCI_DEVICE_ID_INTEL_82815_CGC, 0, "i815", 2275 &intel_815_driver, &intel_810_driver }, 2276 { PCI_DEVICE_ID_INTEL_82820_HB, 0, 0, "i820", &intel_820_driver, NULL }, 2277 { PCI_DEVICE_ID_INTEL_82820_UP_HB, 0, 0, "i820", &intel_820_driver, NULL }, 2278 { PCI_DEVICE_ID_INTEL_82830_HB, PCI_DEVICE_ID_INTEL_82830_CGC, 0, "830M", 2279 &intel_830mp_driver, &intel_830_driver }, 2280 { PCI_DEVICE_ID_INTEL_82840_HB, 0, 0, "i840", &intel_840_driver, NULL }, 2281 { PCI_DEVICE_ID_INTEL_82845_HB, 0, 0, "845G", &intel_845_driver, NULL }, 2282 { PCI_DEVICE_ID_INTEL_82845G_HB, PCI_DEVICE_ID_INTEL_82845G_IG, 0, "830M", 2283 &intel_845_driver, &intel_830_driver }, 2284 { PCI_DEVICE_ID_INTEL_82850_HB, 0, 0, "i850", &intel_850_driver, NULL }, 2285 { PCI_DEVICE_ID_INTEL_82854_HB, PCI_DEVICE_ID_INTEL_82854_IG, 0, "854", 2286 &intel_845_driver, &intel_830_driver }, 2287 { PCI_DEVICE_ID_INTEL_82855PM_HB, 0, 0, "855PM", &intel_845_driver, NULL }, 2288 { PCI_DEVICE_ID_INTEL_82855GM_HB, PCI_DEVICE_ID_INTEL_82855GM_IG, 0, "855GM", 2289 &intel_845_driver, &intel_830_driver }, 2290 { PCI_DEVICE_ID_INTEL_82860_HB, 0, 0, "i860", &intel_860_driver, NULL }, 2291 { PCI_DEVICE_ID_INTEL_82865_HB, PCI_DEVICE_ID_INTEL_82865_IG, 0, "865", 2292 &intel_845_driver, &intel_830_driver }, 2293 { PCI_DEVICE_ID_INTEL_82875_HB, 0, 0, "i875", &intel_845_driver, NULL }, 2294 { PCI_DEVICE_ID_INTEL_E7221_HB, PCI_DEVICE_ID_INTEL_E7221_IG, 0, "E7221 (i915)", 2295 NULL, &intel_915_driver }, 2296 { PCI_DEVICE_ID_INTEL_82915G_HB, PCI_DEVICE_ID_INTEL_82915G_IG, 0, "915G", 2297 NULL, &intel_915_driver }, 2298 { PCI_DEVICE_ID_INTEL_82915GM_HB, PCI_DEVICE_ID_INTEL_82915GM_IG, 0, "915GM", 2299 NULL, &intel_915_driver }, 2300 { PCI_DEVICE_ID_INTEL_82945G_HB, PCI_DEVICE_ID_INTEL_82945G_IG, 0, "945G", 2301 NULL, &intel_915_driver }, 2302 { PCI_DEVICE_ID_INTEL_82945GM_HB, PCI_DEVICE_ID_INTEL_82945GM_IG, 0, "945GM", 2303 NULL, &intel_915_driver }, 2304 { PCI_DEVICE_ID_INTEL_82945GME_HB, PCI_DEVICE_ID_INTEL_82945GME_IG, 0, "945GME", 2305 NULL, &intel_915_driver }, 2306 { PCI_DEVICE_ID_INTEL_82946GZ_HB, PCI_DEVICE_ID_INTEL_82946GZ_IG, 0, "946GZ", 2307 NULL, &intel_i965_driver }, 2308 { PCI_DEVICE_ID_INTEL_82G35_HB, PCI_DEVICE_ID_INTEL_82G35_IG, 0, "G35", 2309 NULL, &intel_i965_driver }, 2310 { PCI_DEVICE_ID_INTEL_82965Q_HB, PCI_DEVICE_ID_INTEL_82965Q_IG, 0, "965Q", 2311 NULL, &intel_i965_driver }, 2312 { PCI_DEVICE_ID_INTEL_82965G_HB, PCI_DEVICE_ID_INTEL_82965G_IG, 0, "965G", 2313 NULL, &intel_i965_driver }, 2314 { PCI_DEVICE_ID_INTEL_82965GM_HB, PCI_DEVICE_ID_INTEL_82965GM_IG, 0, "965GM", 2315 NULL, &intel_i965_driver }, 2316 { PCI_DEVICE_ID_INTEL_82965GME_HB, PCI_DEVICE_ID_INTEL_82965GME_IG, 0, "965GME/GLE", 2317 NULL, &intel_i965_driver }, 2318 { PCI_DEVICE_ID_INTEL_7505_0, 0, 0, "E7505", &intel_7505_driver, NULL }, 2319 { PCI_DEVICE_ID_INTEL_7205_0, 0, 0, "E7205", &intel_7505_driver, NULL }, 2320 { PCI_DEVICE_ID_INTEL_G33_HB, PCI_DEVICE_ID_INTEL_G33_IG, 0, "G33", 2321 NULL, &intel_g33_driver }, 2322 { PCI_DEVICE_ID_INTEL_Q35_HB, PCI_DEVICE_ID_INTEL_Q35_IG, 0, "Q35", 2323 NULL, &intel_g33_driver }, 2324 { PCI_DEVICE_ID_INTEL_Q33_HB, PCI_DEVICE_ID_INTEL_Q33_IG, 0, "Q33", 2325 NULL, &intel_g33_driver }, 2326 { PCI_DEVICE_ID_INTEL_IGDGM_HB, PCI_DEVICE_ID_INTEL_IGDGM_IG, 0, "IGD", 2327 NULL, &intel_g33_driver }, 2328 { PCI_DEVICE_ID_INTEL_IGDG_HB, PCI_DEVICE_ID_INTEL_IGDG_IG, 0, "IGD", 2329 NULL, &intel_g33_driver }, 2330 { PCI_DEVICE_ID_INTEL_GM45_HB, PCI_DEVICE_ID_INTEL_GM45_IG, 0, 2331 "Mobile Intel® GM45 Express", NULL, &intel_i965_driver }, 2332 { PCI_DEVICE_ID_INTEL_IGD_E_HB, PCI_DEVICE_ID_INTEL_IGD_E_IG, 0, 2333 "Intel Integrated Graphics Device", NULL, &intel_i965_driver }, 2334 { PCI_DEVICE_ID_INTEL_Q45_HB, PCI_DEVICE_ID_INTEL_Q45_IG, 0, 2335 "Q45/Q43", NULL, &intel_i965_driver }, 2336 { PCI_DEVICE_ID_INTEL_G45_HB, PCI_DEVICE_ID_INTEL_G45_IG, 0, 2337 "G45/G43", NULL, &intel_i965_driver }, 2338 { PCI_DEVICE_ID_INTEL_G41_HB, PCI_DEVICE_ID_INTEL_G41_IG, 0, 2339 "G41", NULL, &intel_i965_driver }, 2340 { PCI_DEVICE_ID_INTEL_IGDNG_D_HB, PCI_DEVICE_ID_INTEL_IGDNG_D_IG, 0, 2341 "IGDNG/D", NULL, &intel_i965_driver }, 2342 { PCI_DEVICE_ID_INTEL_IGDNG_M_HB, PCI_DEVICE_ID_INTEL_IGDNG_M_IG, 0, 2343 "IGDNG/M", NULL, &intel_i965_driver }, 2344 { 0, 0, 0, NULL, NULL, NULL } 2345 }; 2346 2347 static int __devinit agp_intel_probe(struct pci_dev *pdev, 2348 const struct pci_device_id *ent) 2349 { 2350 struct agp_bridge_data *bridge; 2351 u8 cap_ptr = 0; 2352 struct resource *r; 2353 int i; 2354 2355 cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP); 2356 2357 bridge = agp_alloc_bridge(); 2358 if (!bridge) 2359 return -ENOMEM; 2360 2361 for (i = 0; intel_agp_chipsets[i].name != NULL; i++) { 2362 /* In case that multiple models of gfx chip may 2363 stand on same host bridge type, this can be 2364 sure we detect the right IGD. */ 2365 if (pdev->device == intel_agp_chipsets[i].chip_id) { 2366 if ((intel_agp_chipsets[i].gmch_chip_id != 0) && 2367 find_gmch(intel_agp_chipsets[i].gmch_chip_id)) { 2368 bridge->driver = 2369 intel_agp_chipsets[i].gmch_driver; 2370 break; 2371 } else if (intel_agp_chipsets[i].multi_gmch_chip) { 2372 continue; 2373 } else { 2374 bridge->driver = intel_agp_chipsets[i].driver; 2375 break; 2376 } 2377 } 2378 } 2379 2380 if (intel_agp_chipsets[i].name == NULL) { 2381 if (cap_ptr) 2382 dev_warn(&pdev->dev, "unsupported Intel chipset [%04x/%04x]\n", 2383 pdev->vendor, pdev->device); 2384 agp_put_bridge(bridge); 2385 return -ENODEV; 2386 } 2387 2388 if (bridge->driver == NULL) { 2389 /* bridge has no AGP and no IGD detected */ 2390 if (cap_ptr) 2391 dev_warn(&pdev->dev, "can't find bridge device (chip_id: %04x)\n", 2392 intel_agp_chipsets[i].gmch_chip_id); 2393 agp_put_bridge(bridge); 2394 return -ENODEV; 2395 } 2396 2397 bridge->dev = pdev; 2398 bridge->capndx = cap_ptr; 2399 bridge->dev_private_data = &intel_private; 2400 2401 dev_info(&pdev->dev, "Intel %s Chipset\n", intel_agp_chipsets[i].name); 2402 2403 /* 2404 * The following fixes the case where the BIOS has "forgotten" to 2405 * provide an address range for the GART. 2406 * 20030610 - hamish@zot.org 2407 */ 2408 r = &pdev->resource[0]; 2409 if (!r->start && r->end) { 2410 if (pci_assign_resource(pdev, 0)) { 2411 dev_err(&pdev->dev, "can't assign resource 0\n"); 2412 agp_put_bridge(bridge); 2413 return -ENODEV; 2414 } 2415 } 2416 2417 /* 2418 * If the device has not been properly setup, the following will catch 2419 * the problem and should stop the system from crashing. 2420 * 20030610 - hamish@zot.org 2421 */ 2422 if (pci_enable_device(pdev)) { 2423 dev_err(&pdev->dev, "can't enable PCI device\n"); 2424 agp_put_bridge(bridge); 2425 return -ENODEV; 2426 } 2427 2428 /* Fill in the mode register */ 2429 if (cap_ptr) { 2430 pci_read_config_dword(pdev, 2431 bridge->capndx+PCI_AGP_STATUS, 2432 &bridge->mode); 2433 } 2434 2435 pci_set_drvdata(pdev, bridge); 2436 return agp_add_bridge(bridge); 2437 } 2438 2439 static void __devexit agp_intel_remove(struct pci_dev *pdev) 2440 { 2441 struct agp_bridge_data *bridge = pci_get_drvdata(pdev); 2442 2443 agp_remove_bridge(bridge); 2444 2445 if (intel_private.pcidev) 2446 pci_dev_put(intel_private.pcidev); 2447 2448 agp_put_bridge(bridge); 2449 } 2450 2451 #ifdef CONFIG_PM 2452 static int agp_intel_resume(struct pci_dev *pdev) 2453 { 2454 struct agp_bridge_data *bridge = pci_get_drvdata(pdev); 2455 int ret_val; 2456 2457 pci_restore_state(pdev); 2458 2459 /* We should restore our graphics device's config space, 2460 * as host bridge (00:00) resumes before graphics device (02:00), 2461 * then our access to its pci space can work right. 2462 */ 2463 if (intel_private.pcidev) 2464 pci_restore_state(intel_private.pcidev); 2465 2466 if (bridge->driver == &intel_generic_driver) 2467 intel_configure(); 2468 else if (bridge->driver == &intel_850_driver) 2469 intel_850_configure(); 2470 else if (bridge->driver == &intel_845_driver) 2471 intel_845_configure(); 2472 else if (bridge->driver == &intel_830mp_driver) 2473 intel_830mp_configure(); 2474 else if (bridge->driver == &intel_915_driver) 2475 intel_i915_configure(); 2476 else if (bridge->driver == &intel_830_driver) 2477 intel_i830_configure(); 2478 else if (bridge->driver == &intel_810_driver) 2479 intel_i810_configure(); 2480 else if (bridge->driver == &intel_i965_driver) 2481 intel_i915_configure(); 2482 2483 ret_val = agp_rebind_memory(); 2484 if (ret_val != 0) 2485 return ret_val; 2486 2487 return 0; 2488 } 2489 #endif 2490 2491 static struct pci_device_id agp_intel_pci_table[] = { 2492 #define ID(x) \ 2493 { \ 2494 .class = (PCI_CLASS_BRIDGE_HOST << 8), \ 2495 .class_mask = ~0, \ 2496 .vendor = PCI_VENDOR_ID_INTEL, \ 2497 .device = x, \ 2498 .subvendor = PCI_ANY_ID, \ 2499 .subdevice = PCI_ANY_ID, \ 2500 } 2501 ID(PCI_DEVICE_ID_INTEL_82443LX_0), 2502 ID(PCI_DEVICE_ID_INTEL_82443BX_0), 2503 ID(PCI_DEVICE_ID_INTEL_82443GX_0), 2504 ID(PCI_DEVICE_ID_INTEL_82810_MC1), 2505 ID(PCI_DEVICE_ID_INTEL_82810_MC3), 2506 ID(PCI_DEVICE_ID_INTEL_82810E_MC), 2507 ID(PCI_DEVICE_ID_INTEL_82815_MC), 2508 ID(PCI_DEVICE_ID_INTEL_82820_HB), 2509 ID(PCI_DEVICE_ID_INTEL_82820_UP_HB), 2510 ID(PCI_DEVICE_ID_INTEL_82830_HB), 2511 ID(PCI_DEVICE_ID_INTEL_82840_HB), 2512 ID(PCI_DEVICE_ID_INTEL_82845_HB), 2513 ID(PCI_DEVICE_ID_INTEL_82845G_HB), 2514 ID(PCI_DEVICE_ID_INTEL_82850_HB), 2515 ID(PCI_DEVICE_ID_INTEL_82854_HB), 2516 ID(PCI_DEVICE_ID_INTEL_82855PM_HB), 2517 ID(PCI_DEVICE_ID_INTEL_82855GM_HB), 2518 ID(PCI_DEVICE_ID_INTEL_82860_HB), 2519 ID(PCI_DEVICE_ID_INTEL_82865_HB), 2520 ID(PCI_DEVICE_ID_INTEL_82875_HB), 2521 ID(PCI_DEVICE_ID_INTEL_7505_0), 2522 ID(PCI_DEVICE_ID_INTEL_7205_0), 2523 ID(PCI_DEVICE_ID_INTEL_E7221_HB), 2524 ID(PCI_DEVICE_ID_INTEL_82915G_HB), 2525 ID(PCI_DEVICE_ID_INTEL_82915GM_HB), 2526 ID(PCI_DEVICE_ID_INTEL_82945G_HB), 2527 ID(PCI_DEVICE_ID_INTEL_82945GM_HB), 2528 ID(PCI_DEVICE_ID_INTEL_82945GME_HB), 2529 ID(PCI_DEVICE_ID_INTEL_IGDGM_HB), 2530 ID(PCI_DEVICE_ID_INTEL_IGDG_HB), 2531 ID(PCI_DEVICE_ID_INTEL_82946GZ_HB), 2532 ID(PCI_DEVICE_ID_INTEL_82G35_HB), 2533 ID(PCI_DEVICE_ID_INTEL_82965Q_HB), 2534 ID(PCI_DEVICE_ID_INTEL_82965G_HB), 2535 ID(PCI_DEVICE_ID_INTEL_82965GM_HB), 2536 ID(PCI_DEVICE_ID_INTEL_82965GME_HB), 2537 ID(PCI_DEVICE_ID_INTEL_G33_HB), 2538 ID(PCI_DEVICE_ID_INTEL_Q35_HB), 2539 ID(PCI_DEVICE_ID_INTEL_Q33_HB), 2540 ID(PCI_DEVICE_ID_INTEL_GM45_HB), 2541 ID(PCI_DEVICE_ID_INTEL_IGD_E_HB), 2542 ID(PCI_DEVICE_ID_INTEL_Q45_HB), 2543 ID(PCI_DEVICE_ID_INTEL_G45_HB), 2544 ID(PCI_DEVICE_ID_INTEL_G41_HB), 2545 ID(PCI_DEVICE_ID_INTEL_IGDNG_D_HB), 2546 ID(PCI_DEVICE_ID_INTEL_IGDNG_M_HB), 2547 { } 2548 }; 2549 2550 MODULE_DEVICE_TABLE(pci, agp_intel_pci_table); 2551 2552 static struct pci_driver agp_intel_pci_driver = { 2553 .name = "agpgart-intel", 2554 .id_table = agp_intel_pci_table, 2555 .probe = agp_intel_probe, 2556 .remove = __devexit_p(agp_intel_remove), 2557 #ifdef CONFIG_PM 2558 .resume = agp_intel_resume, 2559 #endif 2560 }; 2561 2562 static int __init agp_intel_init(void) 2563 { 2564 if (agp_off) 2565 return -EINVAL; 2566 return pci_register_driver(&agp_intel_pci_driver); 2567 } 2568 2569 static void __exit agp_intel_cleanup(void) 2570 { 2571 pci_unregister_driver(&agp_intel_pci_driver); 2572 } 2573 2574 module_init(agp_intel_init); 2575 module_exit(agp_intel_cleanup); 2576 2577 MODULE_AUTHOR("Dave Jones <davej@redhat.com>"); 2578 MODULE_LICENSE("GPL and additional rights"); 2579