1*99c926ceSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 2789221ecSBing Zhao /** 3789221ecSBing Zhao * Marvell BT-over-SDIO driver: SDIO interface related definitions 4789221ecSBing Zhao * 5789221ecSBing Zhao * Copyright (C) 2009, Marvell International Ltd. 6789221ecSBing Zhao **/ 7789221ecSBing Zhao 8789221ecSBing Zhao #define SDIO_HEADER_LEN 4 9789221ecSBing Zhao 10789221ecSBing Zhao /* SD block size can not bigger than 64 due to buf size limit in firmware */ 11789221ecSBing Zhao /* define SD block size for data Tx/Rx */ 12789221ecSBing Zhao #define SDIO_BLOCK_SIZE 64 13789221ecSBing Zhao 14789221ecSBing Zhao /* Number of blocks for firmware transfer */ 15789221ecSBing Zhao #define FIRMWARE_TRANSFER_NBLOCK 2 16789221ecSBing Zhao 17789221ecSBing Zhao /* This is for firmware specific length */ 18789221ecSBing Zhao #define FW_EXTRA_LEN 36 19789221ecSBing Zhao 20789221ecSBing Zhao #define MRVDRV_SIZE_OF_CMD_BUFFER (2 * 1024) 21789221ecSBing Zhao 22789221ecSBing Zhao #define MRVDRV_BT_RX_PACKET_BUFFER_SIZE \ 23789221ecSBing Zhao (HCI_MAX_FRAME_SIZE + FW_EXTRA_LEN) 24789221ecSBing Zhao 25789221ecSBing Zhao #define ALLOC_BUF_SIZE (((max_t (int, MRVDRV_BT_RX_PACKET_BUFFER_SIZE, \ 26789221ecSBing Zhao MRVDRV_SIZE_OF_CMD_BUFFER) + SDIO_HEADER_LEN \ 27789221ecSBing Zhao + SDIO_BLOCK_SIZE - 1) / SDIO_BLOCK_SIZE) \ 28789221ecSBing Zhao * SDIO_BLOCK_SIZE) 29789221ecSBing Zhao 30789221ecSBing Zhao /* The number of times to try when polling for status */ 31789221ecSBing Zhao #define MAX_POLL_TRIES 100 32789221ecSBing Zhao 33789221ecSBing Zhao /* Max retry number of CMD53 write */ 34789221ecSBing Zhao #define MAX_WRITE_IOMEM_RETRY 2 35789221ecSBing Zhao 369f72c1d9SKevin Gan /* register bitmasks */ 37789221ecSBing Zhao #define HOST_POWER_UP BIT(1) 38789221ecSBing Zhao #define HOST_CMD53_FIN BIT(2) 39789221ecSBing Zhao 40789221ecSBing Zhao #define HIM_DISABLE 0xff 41789221ecSBing Zhao #define HIM_ENABLE (BIT(0) | BIT(1)) 42789221ecSBing Zhao 43789221ecSBing Zhao #define UP_LD_HOST_INT_STATUS BIT(0) 44789221ecSBing Zhao #define DN_LD_HOST_INT_STATUS BIT(1) 45789221ecSBing Zhao 46789221ecSBing Zhao #define DN_LD_CARD_RDY BIT(0) 47789221ecSBing Zhao #define CARD_IO_READY BIT(3) 48789221ecSBing Zhao 49789221ecSBing Zhao #define FIRMWARE_READY 0xfedc 50789221ecSBing Zhao 51bb7f4f0bSXinming Hu struct btmrvl_plt_wake_cfg { 52bb7f4f0bSXinming Hu int irq_bt; 53bb7f4f0bSXinming Hu bool wake_by_bt; 54bb7f4f0bSXinming Hu }; 55789221ecSBing Zhao 569f72c1d9SKevin Gan struct btmrvl_sdio_card_reg { 579f72c1d9SKevin Gan u8 cfg; 589f72c1d9SKevin Gan u8 host_int_mask; 599f72c1d9SKevin Gan u8 host_intstatus; 609f72c1d9SKevin Gan u8 card_status; 619f72c1d9SKevin Gan u8 sq_read_base_addr_a0; 629f72c1d9SKevin Gan u8 sq_read_base_addr_a1; 639f72c1d9SKevin Gan u8 card_revision; 649f72c1d9SKevin Gan u8 card_fw_status0; 659f72c1d9SKevin Gan u8 card_fw_status1; 669f72c1d9SKevin Gan u8 card_rx_len; 679f72c1d9SKevin Gan u8 card_rx_unit; 689f72c1d9SKevin Gan u8 io_port_0; 699f72c1d9SKevin Gan u8 io_port_1; 709f72c1d9SKevin Gan u8 io_port_2; 710d367408SBing Zhao bool int_read_to_clear; 720d367408SBing Zhao u8 host_int_rsr; 730d367408SBing Zhao u8 card_misc_cfg; 74dc759613SXinming Hu u8 fw_dump_ctrl; 75dc759613SXinming Hu u8 fw_dump_start; 76dc759613SXinming Hu u8 fw_dump_end; 779f72c1d9SKevin Gan }; 78789221ecSBing Zhao 79789221ecSBing Zhao struct btmrvl_sdio_card { 80789221ecSBing Zhao struct sdio_func *func; 81789221ecSBing Zhao u32 ioport; 82789221ecSBing Zhao const char *helper; 83789221ecSBing Zhao const char *firmware; 849f72c1d9SKevin Gan const struct btmrvl_sdio_card_reg *reg; 854df82b59SBing Zhao bool support_pscan_win_report; 86dc759613SXinming Hu bool supports_fw_dump; 879f72c1d9SKevin Gan u16 sd_blksz_fw_dl; 88789221ecSBing Zhao u8 rx_unit; 89789221ecSBing Zhao struct btmrvl_private *priv; 90bb7f4f0bSXinming Hu struct device_node *plt_of_node; 91bb7f4f0bSXinming Hu struct btmrvl_plt_wake_cfg *plt_wake_cfg; 92789221ecSBing Zhao }; 93789221ecSBing Zhao 94789221ecSBing Zhao struct btmrvl_sdio_device { 95789221ecSBing Zhao const char *helper; 96789221ecSBing Zhao const char *firmware; 979f72c1d9SKevin Gan const struct btmrvl_sdio_card_reg *reg; 984df82b59SBing Zhao const bool support_pscan_win_report; 999f72c1d9SKevin Gan u16 sd_blksz_fw_dl; 100dc759613SXinming Hu bool supports_fw_dump; 101789221ecSBing Zhao }; 102789221ecSBing Zhao 103789221ecSBing Zhao 104789221ecSBing Zhao /* Platform specific DMA alignment */ 105789221ecSBing Zhao #define BTSDIO_DMA_ALIGN 8 106789221ecSBing Zhao 107789221ecSBing Zhao /* Macros for Data Alignment : size */ 108789221ecSBing Zhao #define ALIGN_SZ(p, a) \ 109789221ecSBing Zhao (((p) + ((a) - 1)) & ~((a) - 1)) 110789221ecSBing Zhao 111789221ecSBing Zhao /* Macros for Data Alignment : address */ 112789221ecSBing Zhao #define ALIGN_ADDR(p, a) \ 1133318b236SBing Zhao ((((unsigned long)(p)) + (((unsigned long)(a)) - 1)) & \ 1143318b236SBing Zhao ~(((unsigned long)(a)) - 1)) 115