1 /* 2 * Broadcom specific AMBA 3 * ChipCommon core driver 4 * 5 * Copyright 2005, Broadcom Corporation 6 * Copyright 2006, 2007, Michael Buesch <m@bues.ch> 7 * 8 * Licensed under the GNU/GPL. See COPYING for details. 9 */ 10 11 #include "bcma_private.h" 12 #include <linux/bcma/bcma.h> 13 14 static inline u32 bcma_cc_write32_masked(struct bcma_drv_cc *cc, u16 offset, 15 u32 mask, u32 value) 16 { 17 value &= mask; 18 value |= bcma_cc_read32(cc, offset) & ~mask; 19 bcma_cc_write32(cc, offset, value); 20 21 return value; 22 } 23 24 void bcma_core_chipcommon_init(struct bcma_drv_cc *cc) 25 { 26 u32 leddc_on = 10; 27 u32 leddc_off = 90; 28 29 if (cc->setup_done) 30 return; 31 32 if (cc->core->id.rev >= 11) 33 cc->status = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT); 34 cc->capabilities = bcma_cc_read32(cc, BCMA_CC_CAP); 35 if (cc->core->id.rev >= 35) 36 cc->capabilities_ext = bcma_cc_read32(cc, BCMA_CC_CAP_EXT); 37 38 if (cc->core->id.rev >= 20) { 39 bcma_cc_write32(cc, BCMA_CC_GPIOPULLUP, 0); 40 bcma_cc_write32(cc, BCMA_CC_GPIOPULLDOWN, 0); 41 } 42 43 if (cc->capabilities & BCMA_CC_CAP_PMU) 44 bcma_pmu_init(cc); 45 if (cc->capabilities & BCMA_CC_CAP_PCTL) 46 pr_err("Power control not implemented!\n"); 47 48 if (cc->core->id.rev >= 16) { 49 if (cc->core->bus->sprom.leddc_on_time && 50 cc->core->bus->sprom.leddc_off_time) { 51 leddc_on = cc->core->bus->sprom.leddc_on_time; 52 leddc_off = cc->core->bus->sprom.leddc_off_time; 53 } 54 bcma_cc_write32(cc, BCMA_CC_GPIOTIMER, 55 ((leddc_on << BCMA_CC_GPIOTIMER_ONTIME_SHIFT) | 56 (leddc_off << BCMA_CC_GPIOTIMER_OFFTIME_SHIFT))); 57 } 58 59 cc->setup_done = true; 60 } 61 62 /* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */ 63 void bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks) 64 { 65 /* instant NMI */ 66 bcma_cc_write32(cc, BCMA_CC_WATCHDOG, ticks); 67 } 68 69 void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value) 70 { 71 bcma_cc_write32_masked(cc, BCMA_CC_IRQMASK, mask, value); 72 } 73 74 u32 bcma_chipco_irq_status(struct bcma_drv_cc *cc, u32 mask) 75 { 76 return bcma_cc_read32(cc, BCMA_CC_IRQSTAT) & mask; 77 } 78 79 u32 bcma_chipco_gpio_in(struct bcma_drv_cc *cc, u32 mask) 80 { 81 return bcma_cc_read32(cc, BCMA_CC_GPIOIN) & mask; 82 } 83 84 u32 bcma_chipco_gpio_out(struct bcma_drv_cc *cc, u32 mask, u32 value) 85 { 86 return bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUT, mask, value); 87 } 88 89 u32 bcma_chipco_gpio_outen(struct bcma_drv_cc *cc, u32 mask, u32 value) 90 { 91 return bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUTEN, mask, value); 92 } 93 94 u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, u32 value) 95 { 96 return bcma_cc_write32_masked(cc, BCMA_CC_GPIOCTL, mask, value); 97 } 98 EXPORT_SYMBOL_GPL(bcma_chipco_gpio_control); 99 100 u32 bcma_chipco_gpio_intmask(struct bcma_drv_cc *cc, u32 mask, u32 value) 101 { 102 return bcma_cc_write32_masked(cc, BCMA_CC_GPIOIRQ, mask, value); 103 } 104 105 u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value) 106 { 107 return bcma_cc_write32_masked(cc, BCMA_CC_GPIOPOL, mask, value); 108 } 109 110 #ifdef CONFIG_BCMA_DRIVER_MIPS 111 void bcma_chipco_serial_init(struct bcma_drv_cc *cc) 112 { 113 unsigned int irq; 114 u32 baud_base; 115 u32 i; 116 unsigned int ccrev = cc->core->id.rev; 117 struct bcma_serial_port *ports = cc->serial_ports; 118 119 if (ccrev >= 11 && ccrev != 15) { 120 /* Fixed ALP clock */ 121 baud_base = bcma_pmu_alp_clock(cc); 122 if (ccrev >= 21) { 123 /* Turn off UART clock before switching clocksource. */ 124 bcma_cc_write32(cc, BCMA_CC_CORECTL, 125 bcma_cc_read32(cc, BCMA_CC_CORECTL) 126 & ~BCMA_CC_CORECTL_UARTCLKEN); 127 } 128 /* Set the override bit so we don't divide it */ 129 bcma_cc_write32(cc, BCMA_CC_CORECTL, 130 bcma_cc_read32(cc, BCMA_CC_CORECTL) 131 | BCMA_CC_CORECTL_UARTCLK0); 132 if (ccrev >= 21) { 133 /* Re-enable the UART clock. */ 134 bcma_cc_write32(cc, BCMA_CC_CORECTL, 135 bcma_cc_read32(cc, BCMA_CC_CORECTL) 136 | BCMA_CC_CORECTL_UARTCLKEN); 137 } 138 } else { 139 pr_err("serial not supported on this device ccrev: 0x%x\n", 140 ccrev); 141 return; 142 } 143 144 irq = bcma_core_mips_irq(cc->core); 145 146 /* Determine the registers of the UARTs */ 147 cc->nr_serial_ports = (cc->capabilities & BCMA_CC_CAP_NRUART); 148 for (i = 0; i < cc->nr_serial_ports; i++) { 149 ports[i].regs = cc->core->io_addr + BCMA_CC_UART0_DATA + 150 (i * 256); 151 ports[i].irq = irq; 152 ports[i].baud_base = baud_base; 153 ports[i].reg_shift = 0; 154 } 155 } 156 #endif /* CONFIG_BCMA_DRIVER_MIPS */ 157