xref: /openbmc/linux/drivers/base/regmap/regmap-irq.c (revision f01ee60fffa4dc6c77122121233a793f7f696e67)
1 /*
2  * regmap based irq_chip
3  *
4  * Copyright 2011 Wolfson Microelectronics plc
5  *
6  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License version 2 as
10  * published by the Free Software Foundation.
11  */
12 
13 #include <linux/export.h>
14 #include <linux/device.h>
15 #include <linux/regmap.h>
16 #include <linux/irq.h>
17 #include <linux/interrupt.h>
18 #include <linux/slab.h>
19 
20 #include "internal.h"
21 
22 struct regmap_irq_chip_data {
23 	struct mutex lock;
24 
25 	struct regmap *map;
26 	struct regmap_irq_chip *chip;
27 
28 	int irq_base;
29 
30 	void *status_reg_buf;
31 	unsigned int *status_buf;
32 	unsigned int *mask_buf;
33 	unsigned int *mask_buf_def;
34 };
35 
36 static inline const
37 struct regmap_irq *irq_to_regmap_irq(struct regmap_irq_chip_data *data,
38 				     int irq)
39 {
40 	return &data->chip->irqs[irq - data->irq_base];
41 }
42 
43 static void regmap_irq_lock(struct irq_data *data)
44 {
45 	struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
46 
47 	mutex_lock(&d->lock);
48 }
49 
50 static void regmap_irq_sync_unlock(struct irq_data *data)
51 {
52 	struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
53 	int i, ret;
54 
55 	/*
56 	 * If there's been a change in the mask write it back to the
57 	 * hardware.  We rely on the use of the regmap core cache to
58 	 * suppress pointless writes.
59 	 */
60 	for (i = 0; i < d->chip->num_regs; i++) {
61 		ret = regmap_update_bits(d->map, d->chip->mask_base +
62 						(i * map->map->reg_stride),
63 					 d->mask_buf_def[i], d->mask_buf[i]);
64 		if (ret != 0)
65 			dev_err(d->map->dev, "Failed to sync masks in %x\n",
66 				d->chip->mask_base + (i * map->reg_stride));
67 	}
68 
69 	mutex_unlock(&d->lock);
70 }
71 
72 static void regmap_irq_enable(struct irq_data *data)
73 {
74 	struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
75 	const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->irq);
76 
77 	d->mask_buf[irq_data->reg_offset / map->reg_stride] &= ~irq_data->mask;
78 }
79 
80 static void regmap_irq_disable(struct irq_data *data)
81 {
82 	struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
83 	const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->irq);
84 
85 	d->mask_buf[irq_data->reg_offset / map->reg_stride] |= irq_data->mask;
86 }
87 
88 static struct irq_chip regmap_irq_chip = {
89 	.name			= "regmap",
90 	.irq_bus_lock		= regmap_irq_lock,
91 	.irq_bus_sync_unlock	= regmap_irq_sync_unlock,
92 	.irq_disable		= regmap_irq_disable,
93 	.irq_enable		= regmap_irq_enable,
94 };
95 
96 static irqreturn_t regmap_irq_thread(int irq, void *d)
97 {
98 	struct regmap_irq_chip_data *data = d;
99 	struct regmap_irq_chip *chip = data->chip;
100 	struct regmap *map = data->map;
101 	int ret, i;
102 	u8 *buf8 = data->status_reg_buf;
103 	u16 *buf16 = data->status_reg_buf;
104 	u32 *buf32 = data->status_reg_buf;
105 	bool handled = false;
106 
107 	ret = regmap_bulk_read(map, chip->status_base, data->status_reg_buf,
108 			       chip->num_regs);
109 	if (ret != 0) {
110 		dev_err(map->dev, "Failed to read IRQ status: %d\n", ret);
111 		return IRQ_NONE;
112 	}
113 
114 	/*
115 	 * Ignore masked IRQs and ack if we need to; we ack early so
116 	 * there is no race between handling and acknowleding the
117 	 * interrupt.  We assume that typically few of the interrupts
118 	 * will fire simultaneously so don't worry about overhead from
119 	 * doing a write per register.
120 	 */
121 	for (i = 0; i < data->chip->num_regs; i++) {
122 		switch (map->format.val_bytes) {
123 		case 1:
124 			data->status_buf[i] = buf8[i];
125 			break;
126 		case 2:
127 			data->status_buf[i] = buf16[i];
128 			break;
129 		case 4:
130 			data->status_buf[i] = buf32[i];
131 			break;
132 		default:
133 			BUG();
134 			return IRQ_NONE;
135 		}
136 
137 		data->status_buf[i] &= ~data->mask_buf[i];
138 
139 		if (data->status_buf[i] && chip->ack_base) {
140 			ret = regmap_write(map, chip->ack_base +
141 						(i * map->reg_stride),
142 					   data->status_buf[i]);
143 			if (ret != 0)
144 				dev_err(map->dev, "Failed to ack 0x%x: %d\n",
145 					chip->ack_base + (i * map->reg_stride),
146 					ret);
147 		}
148 	}
149 
150 	for (i = 0; i < chip->num_irqs; i++) {
151 		if (data->status_buf[chip->irqs[i].reg_offset /
152 				     map->reg_stride] & chip->irqs[i].mask) {
153 			handle_nested_irq(data->irq_base + i);
154 			handled = true;
155 		}
156 	}
157 
158 	if (handled)
159 		return IRQ_HANDLED;
160 	else
161 		return IRQ_NONE;
162 }
163 
164 /**
165  * regmap_add_irq_chip(): Use standard regmap IRQ controller handling
166  *
167  * map:       The regmap for the device.
168  * irq:       The IRQ the device uses to signal interrupts
169  * irq_flags: The IRQF_ flags to use for the primary interrupt.
170  * chip:      Configuration for the interrupt controller.
171  * data:      Runtime data structure for the controller, allocated on success
172  *
173  * Returns 0 on success or an errno on failure.
174  *
175  * In order for this to be efficient the chip really should use a
176  * register cache.  The chip driver is responsible for restoring the
177  * register values used by the IRQ controller over suspend and resume.
178  */
179 int regmap_add_irq_chip(struct regmap *map, int irq, int irq_flags,
180 			int irq_base, struct regmap_irq_chip *chip,
181 			struct regmap_irq_chip_data **data)
182 {
183 	struct regmap_irq_chip_data *d;
184 	int cur_irq, i;
185 	int ret = -ENOMEM;
186 
187 	for (i = 0; i < chip->num_irqs; i++) {
188 		if (chip->irqs[i].reg_offset % map->reg_stride)
189 			return -EINVAL;
190 		if (chip->irqs[i].reg_offset / map->reg_stride >=
191 		    chip->num_regs)
192 			return -EINVAL;
193 	}
194 
195 	irq_base = irq_alloc_descs(irq_base, 0, chip->num_irqs, 0);
196 	if (irq_base < 0) {
197 		dev_warn(map->dev, "Failed to allocate IRQs: %d\n",
198 			 irq_base);
199 		return irq_base;
200 	}
201 
202 	d = kzalloc(sizeof(*d), GFP_KERNEL);
203 	if (!d)
204 		return -ENOMEM;
205 
206 	d->status_buf = kzalloc(sizeof(unsigned int) * chip->num_regs,
207 				GFP_KERNEL);
208 	if (!d->status_buf)
209 		goto err_alloc;
210 
211 	d->status_reg_buf = kzalloc(map->format.val_bytes * chip->num_regs,
212 				    GFP_KERNEL);
213 	if (!d->status_reg_buf)
214 		goto err_alloc;
215 
216 	d->mask_buf = kzalloc(sizeof(unsigned int) * chip->num_regs,
217 			      GFP_KERNEL);
218 	if (!d->mask_buf)
219 		goto err_alloc;
220 
221 	d->mask_buf_def = kzalloc(sizeof(unsigned int) * chip->num_regs,
222 				  GFP_KERNEL);
223 	if (!d->mask_buf_def)
224 		goto err_alloc;
225 
226 	d->map = map;
227 	d->chip = chip;
228 	d->irq_base = irq_base;
229 	mutex_init(&d->lock);
230 
231 	for (i = 0; i < chip->num_irqs; i++)
232 		d->mask_buf_def[chip->irqs[i].reg_offset / map->reg_stride]
233 			|= chip->irqs[i].mask;
234 
235 	/* Mask all the interrupts by default */
236 	for (i = 0; i < chip->num_regs; i++) {
237 		d->mask_buf[i] = d->mask_buf_def[i];
238 		ret = regmap_write(map, chip->mask_base + (i * map->reg_stride),
239 				   d->mask_buf[i]);
240 		if (ret != 0) {
241 			dev_err(map->dev, "Failed to set masks in 0x%x: %d\n",
242 				chip->mask_base + (i * map->reg_stride), ret);
243 			goto err_alloc;
244 		}
245 	}
246 
247 	/* Register them with genirq */
248 	for (cur_irq = irq_base;
249 	     cur_irq < chip->num_irqs + irq_base;
250 	     cur_irq++) {
251 		irq_set_chip_data(cur_irq, d);
252 		irq_set_chip_and_handler(cur_irq, &regmap_irq_chip,
253 					 handle_edge_irq);
254 		irq_set_nested_thread(cur_irq, 1);
255 
256 		/* ARM needs us to explicitly flag the IRQ as valid
257 		 * and will set them noprobe when we do so. */
258 #ifdef CONFIG_ARM
259 		set_irq_flags(cur_irq, IRQF_VALID);
260 #else
261 		irq_set_noprobe(cur_irq);
262 #endif
263 	}
264 
265 	ret = request_threaded_irq(irq, NULL, regmap_irq_thread, irq_flags,
266 				   chip->name, d);
267 	if (ret != 0) {
268 		dev_err(map->dev, "Failed to request IRQ %d: %d\n", irq, ret);
269 		goto err_alloc;
270 	}
271 
272 	return 0;
273 
274 err_alloc:
275 	kfree(d->mask_buf_def);
276 	kfree(d->mask_buf);
277 	kfree(d->status_reg_buf);
278 	kfree(d->status_buf);
279 	kfree(d);
280 	return ret;
281 }
282 EXPORT_SYMBOL_GPL(regmap_add_irq_chip);
283 
284 /**
285  * regmap_del_irq_chip(): Stop interrupt handling for a regmap IRQ chip
286  *
287  * @irq: Primary IRQ for the device
288  * @d:   regmap_irq_chip_data allocated by regmap_add_irq_chip()
289  */
290 void regmap_del_irq_chip(int irq, struct regmap_irq_chip_data *d)
291 {
292 	if (!d)
293 		return;
294 
295 	free_irq(irq, d);
296 	kfree(d->mask_buf_def);
297 	kfree(d->mask_buf);
298 	kfree(d->status_reg_buf);
299 	kfree(d->status_buf);
300 	kfree(d);
301 }
302 EXPORT_SYMBOL_GPL(regmap_del_irq_chip);
303 
304 /**
305  * regmap_irq_chip_get_base(): Retrieve interrupt base for a regmap IRQ chip
306  *
307  * Useful for drivers to request their own IRQs.
308  *
309  * @data: regmap_irq controller to operate on.
310  */
311 int regmap_irq_chip_get_base(struct regmap_irq_chip_data *data)
312 {
313 	return data->irq_base;
314 }
315 EXPORT_SYMBOL_GPL(regmap_irq_chip_get_base);
316