1 /* lanai.c -- Copyright 1999-2003 by Mitchell Blank Jr <mitch@sfgoth.com> 2 * 3 * This program is free software; you can redistribute it and/or 4 * modify it under the terms of the GNU General Public License 5 * as published by the Free Software Foundation; either version 6 * 2 of the License, or (at your option) any later version. 7 * 8 * This driver supports ATM cards based on the Efficient "Lanai" 9 * chipset such as the Speedstream 3010 and the ENI-25p. The 10 * Speedstream 3060 is currently not supported since we don't 11 * have the code to drive the on-board Alcatel DSL chipset (yet). 12 * 13 * Thanks to Efficient for supporting this project with hardware, 14 * documentation, and by answering my questions. 15 * 16 * Things not working yet: 17 * 18 * o We don't support the Speedstream 3060 yet - this card has 19 * an on-board DSL modem chip by Alcatel and the driver will 20 * need some extra code added to handle it 21 * 22 * o Note that due to limitations of the Lanai only one VCC can be 23 * in CBR at once 24 * 25 * o We don't currently parse the EEPROM at all. The code is all 26 * there as per the spec, but it doesn't actually work. I think 27 * there may be some issues with the docs. Anyway, do NOT 28 * enable it yet - bugs in that code may actually damage your 29 * hardware! Because of this you should hardware an ESI before 30 * trying to use this in a LANE or MPOA environment. 31 * 32 * o AAL0 is stubbed in but the actual rx/tx path isn't written yet: 33 * vcc_tx_aal0() needs to send or queue a SKB 34 * vcc_tx_unqueue_aal0() needs to attempt to send queued SKBs 35 * vcc_rx_aal0() needs to handle AAL0 interrupts 36 * This isn't too much work - I just wanted to get other things 37 * done first. 38 * 39 * o lanai_change_qos() isn't written yet 40 * 41 * o There aren't any ioctl's yet -- I'd like to eventually support 42 * setting loopback and LED modes that way. 43 * 44 * o If the segmentation engine or DMA gets shut down we should restart 45 * card as per section 17.0i. (see lanai_reset) 46 * 47 * o setsockopt(SO_CIRANGE) isn't done (although despite what the 48 * API says it isn't exactly commonly implemented) 49 */ 50 51 /* Version history: 52 * v.1.00 -- 26-JUL-2003 -- PCI/DMA updates 53 * v.0.02 -- 11-JAN-2000 -- Endian fixes 54 * v.0.01 -- 30-NOV-1999 -- Initial release 55 */ 56 57 #include <linux/module.h> 58 #include <linux/mm.h> 59 #include <linux/atmdev.h> 60 #include <asm/io.h> 61 #include <asm/byteorder.h> 62 #include <linux/spinlock.h> 63 #include <linux/pci.h> 64 #include <linux/dma-mapping.h> 65 #include <linux/init.h> 66 #include <linux/delay.h> 67 #include <linux/interrupt.h> 68 #include <linux/dma-mapping.h> 69 70 /* -------------------- TUNABLE PARAMATERS: */ 71 72 /* 73 * Maximum number of VCIs per card. Setting it lower could theoretically 74 * save some memory, but since we allocate our vcc list with get_free_pages, 75 * it's not really likely for most architectures 76 */ 77 #define NUM_VCI (1024) 78 79 /* 80 * Enable extra debugging 81 */ 82 #define DEBUG 83 /* 84 * Debug _all_ register operations with card, except the memory test. 85 * Also disables the timed poll to prevent extra chattiness. This 86 * isn't for normal use 87 */ 88 #undef DEBUG_RW 89 90 /* 91 * The programming guide specifies a full test of the on-board SRAM 92 * at initialization time. Undefine to remove this 93 */ 94 #define FULL_MEMORY_TEST 95 96 /* 97 * This is the number of (4 byte) service entries that we will 98 * try to allocate at startup. Note that we will end up with 99 * one PAGE_SIZE's worth regardless of what this is set to 100 */ 101 #define SERVICE_ENTRIES (1024) 102 /* TODO: make above a module load-time option */ 103 104 /* 105 * We normally read the onboard EEPROM in order to discover our MAC 106 * address. Undefine to _not_ do this 107 */ 108 /* #define READ_EEPROM */ /* ***DONT ENABLE YET*** */ 109 /* TODO: make above a module load-time option (also) */ 110 111 /* 112 * Depth of TX fifo (in 128 byte units; range 2-31) 113 * Smaller numbers are better for network latency 114 * Larger numbers are better for PCI latency 115 * I'm really sure where the best tradeoff is, but the BSD driver uses 116 * 7 and it seems to work ok. 117 */ 118 #define TX_FIFO_DEPTH (7) 119 /* TODO: make above a module load-time option */ 120 121 /* 122 * How often (in jiffies) we will try to unstick stuck connections - 123 * shouldn't need to happen much 124 */ 125 #define LANAI_POLL_PERIOD (10*HZ) 126 /* TODO: make above a module load-time option */ 127 128 /* 129 * When allocating an AAL5 receiving buffer, try to make it at least 130 * large enough to hold this many max_sdu sized PDUs 131 */ 132 #define AAL5_RX_MULTIPLIER (3) 133 /* TODO: make above a module load-time option */ 134 135 /* 136 * Same for transmitting buffer 137 */ 138 #define AAL5_TX_MULTIPLIER (3) 139 /* TODO: make above a module load-time option */ 140 141 /* 142 * When allocating an AAL0 transmiting buffer, how many cells should fit. 143 * Remember we'll end up with a PAGE_SIZE of them anyway, so this isn't 144 * really critical 145 */ 146 #define AAL0_TX_MULTIPLIER (40) 147 /* TODO: make above a module load-time option */ 148 149 /* 150 * How large should we make the AAL0 receiving buffer. Remember that this 151 * is shared between all AAL0 VC's 152 */ 153 #define AAL0_RX_BUFFER_SIZE (PAGE_SIZE) 154 /* TODO: make above a module load-time option */ 155 156 /* 157 * Should we use Lanai's "powerdown" feature when no vcc's are bound? 158 */ 159 /* #define USE_POWERDOWN */ 160 /* TODO: make above a module load-time option (also) */ 161 162 /* -------------------- DEBUGGING AIDS: */ 163 164 #define DEV_LABEL "lanai" 165 166 #ifdef DEBUG 167 168 #define DPRINTK(format, args...) \ 169 printk(KERN_DEBUG DEV_LABEL ": " format, ##args) 170 #define APRINTK(truth, format, args...) \ 171 do { \ 172 if (unlikely(!(truth))) \ 173 printk(KERN_ERR DEV_LABEL ": " format, ##args); \ 174 } while (0) 175 176 #else /* !DEBUG */ 177 178 #define DPRINTK(format, args...) 179 #define APRINTK(truth, format, args...) 180 181 #endif /* DEBUG */ 182 183 #ifdef DEBUG_RW 184 #define RWDEBUG(format, args...) \ 185 printk(KERN_DEBUG DEV_LABEL ": " format, ##args) 186 #else /* !DEBUG_RW */ 187 #define RWDEBUG(format, args...) 188 #endif 189 190 /* -------------------- DATA DEFINITIONS: */ 191 192 #define LANAI_MAPPING_SIZE (0x40000) 193 #define LANAI_EEPROM_SIZE (128) 194 195 typedef int vci_t; 196 typedef void __iomem *bus_addr_t; 197 198 /* DMA buffer in host memory for TX, RX, or service list. */ 199 struct lanai_buffer { 200 u32 *start; /* From get_free_pages */ 201 u32 *end; /* One past last byte */ 202 u32 *ptr; /* Pointer to current host location */ 203 dma_addr_t dmaaddr; 204 }; 205 206 struct lanai_vcc_stats { 207 unsigned rx_nomem; 208 union { 209 struct { 210 unsigned rx_badlen; 211 unsigned service_trash; 212 unsigned service_stream; 213 unsigned service_rxcrc; 214 } aal5; 215 struct { 216 } aal0; 217 } x; 218 }; 219 220 struct lanai_dev; /* Forward declaration */ 221 222 /* 223 * This is the card-specific per-vcc data. Note that unlike some other 224 * drivers there is NOT a 1-to-1 correspondance between these and 225 * atm_vcc's - each one of these represents an actual 2-way vcc, but 226 * an atm_vcc can be 1-way and share with a 1-way vcc in the other 227 * direction. To make it weirder, there can even be 0-way vccs 228 * bound to us, waiting to do a change_qos 229 */ 230 struct lanai_vcc { 231 bus_addr_t vbase; /* Base of VCC's registers */ 232 struct lanai_vcc_stats stats; 233 int nref; /* # of atm_vcc's who reference us */ 234 vci_t vci; 235 struct { 236 struct lanai_buffer buf; 237 struct atm_vcc *atmvcc; /* atm_vcc who is receiver */ 238 } rx; 239 struct { 240 struct lanai_buffer buf; 241 struct atm_vcc *atmvcc; /* atm_vcc who is transmitter */ 242 int endptr; /* last endptr from service entry */ 243 struct sk_buff_head backlog; 244 void (*unqueue)(struct lanai_dev *, struct lanai_vcc *, int); 245 } tx; 246 }; 247 248 enum lanai_type { 249 lanai2 = PCI_VENDOR_ID_EF_ATM_LANAI2, 250 lanaihb = PCI_VENDOR_ID_EF_ATM_LANAIHB 251 }; 252 253 struct lanai_dev_stats { 254 unsigned ovfl_trash; /* # of cells dropped - buffer overflow */ 255 unsigned vci_trash; /* # of cells dropped - closed vci */ 256 unsigned hec_err; /* # of cells dropped - bad HEC */ 257 unsigned atm_ovfl; /* # of cells dropped - rx fifo overflow */ 258 unsigned pcierr_parity_detect; 259 unsigned pcierr_serr_set; 260 unsigned pcierr_master_abort; 261 unsigned pcierr_m_target_abort; 262 unsigned pcierr_s_target_abort; 263 unsigned pcierr_master_parity; 264 unsigned service_notx; 265 unsigned service_norx; 266 unsigned service_rxnotaal5; 267 unsigned dma_reenable; 268 unsigned card_reset; 269 }; 270 271 struct lanai_dev { 272 bus_addr_t base; 273 struct lanai_dev_stats stats; 274 struct lanai_buffer service; 275 struct lanai_vcc **vccs; 276 #ifdef USE_POWERDOWN 277 int nbound; /* number of bound vccs */ 278 #endif 279 enum lanai_type type; 280 vci_t num_vci; /* Currently just NUM_VCI */ 281 u8 eeprom[LANAI_EEPROM_SIZE]; 282 u32 serialno, magicno; 283 struct pci_dev *pci; 284 DECLARE_BITMAP(backlog_vccs, NUM_VCI); /* VCCs with tx backlog */ 285 DECLARE_BITMAP(transmit_ready, NUM_VCI); /* VCCs with transmit space */ 286 struct timer_list timer; 287 int naal0; 288 struct lanai_buffer aal0buf; /* AAL0 RX buffers */ 289 u32 conf1, conf2; /* CONFIG[12] registers */ 290 u32 status; /* STATUS register */ 291 spinlock_t endtxlock; 292 spinlock_t servicelock; 293 struct atm_vcc *cbrvcc; 294 int number; 295 int board_rev; 296 u8 pci_revision; 297 /* TODO - look at race conditions with maintence of conf1/conf2 */ 298 /* TODO - transmit locking: should we use _irq not _irqsave? */ 299 /* TODO - organize above in some rational fashion (see <asm/cache.h>) */ 300 }; 301 302 /* 303 * Each device has two bitmaps for each VCC (baclog_vccs and transmit_ready) 304 * This function iterates one of these, calling a given function for each 305 * vci with their bit set 306 */ 307 static void vci_bitfield_iterate(struct lanai_dev *lanai, 308 const unsigned long *lp, 309 void (*func)(struct lanai_dev *,vci_t vci)) 310 { 311 vci_t vci = find_first_bit(lp, NUM_VCI); 312 while (vci < NUM_VCI) { 313 func(lanai, vci); 314 vci = find_next_bit(lp, NUM_VCI, vci + 1); 315 } 316 } 317 318 /* -------------------- BUFFER UTILITIES: */ 319 320 /* 321 * Lanai needs DMA buffers aligned to 256 bytes of at least 1024 bytes - 322 * usually any page allocation will do. Just to be safe in case 323 * PAGE_SIZE is insanely tiny, though... 324 */ 325 #define LANAI_PAGE_SIZE ((PAGE_SIZE >= 1024) ? PAGE_SIZE : 1024) 326 327 /* 328 * Allocate a buffer in host RAM for service list, RX, or TX 329 * Returns buf->start==NULL if no memory 330 * Note that the size will be rounded up 2^n bytes, and 331 * if we can't allocate that we'll settle for something smaller 332 * until minbytes 333 */ 334 static void lanai_buf_allocate(struct lanai_buffer *buf, 335 size_t bytes, size_t minbytes, struct pci_dev *pci) 336 { 337 int size; 338 339 if (bytes > (128 * 1024)) /* max lanai buffer size */ 340 bytes = 128 * 1024; 341 for (size = LANAI_PAGE_SIZE; size < bytes; size *= 2) 342 ; 343 if (minbytes < LANAI_PAGE_SIZE) 344 minbytes = LANAI_PAGE_SIZE; 345 do { 346 /* 347 * Technically we could use non-consistent mappings for 348 * everything, but the way the lanai uses DMA memory would 349 * make that a terrific pain. This is much simpler. 350 */ 351 buf->start = pci_alloc_consistent(pci, size, &buf->dmaaddr); 352 if (buf->start != NULL) { /* Success */ 353 /* Lanai requires 256-byte alignment of DMA bufs */ 354 APRINTK((buf->dmaaddr & ~0xFFFFFF00) == 0, 355 "bad dmaaddr: 0x%lx\n", 356 (unsigned long) buf->dmaaddr); 357 buf->ptr = buf->start; 358 buf->end = (u32 *) 359 (&((unsigned char *) buf->start)[size]); 360 memset(buf->start, 0, size); 361 break; 362 } 363 size /= 2; 364 } while (size >= minbytes); 365 } 366 367 /* size of buffer in bytes */ 368 static inline size_t lanai_buf_size(const struct lanai_buffer *buf) 369 { 370 return ((unsigned long) buf->end) - ((unsigned long) buf->start); 371 } 372 373 static void lanai_buf_deallocate(struct lanai_buffer *buf, 374 struct pci_dev *pci) 375 { 376 if (buf->start != NULL) { 377 pci_free_consistent(pci, lanai_buf_size(buf), 378 buf->start, buf->dmaaddr); 379 buf->start = buf->end = buf->ptr = NULL; 380 } 381 } 382 383 /* size of buffer as "card order" (0=1k .. 7=128k) */ 384 static int lanai_buf_size_cardorder(const struct lanai_buffer *buf) 385 { 386 int order = get_order(lanai_buf_size(buf)) + (PAGE_SHIFT - 10); 387 388 /* This can only happen if PAGE_SIZE is gigantic, but just in case */ 389 if (order > 7) 390 order = 7; 391 return order; 392 } 393 394 /* -------------------- PORT I/O UTILITIES: */ 395 396 /* Registers (and their bit-fields) */ 397 enum lanai_register { 398 Reset_Reg = 0x00, /* Reset; read for chip type; bits: */ 399 #define RESET_GET_BOARD_REV(x) (((x)>> 0)&0x03) /* Board revision */ 400 #define RESET_GET_BOARD_ID(x) (((x)>> 2)&0x03) /* Board ID */ 401 #define BOARD_ID_LANAI256 (0) /* 25.6M adapter card */ 402 Endian_Reg = 0x04, /* Endian setting */ 403 IntStatus_Reg = 0x08, /* Interrupt status */ 404 IntStatusMasked_Reg = 0x0C, /* Interrupt status (masked) */ 405 IntAck_Reg = 0x10, /* Interrupt acknowledge */ 406 IntAckMasked_Reg = 0x14, /* Interrupt acknowledge (masked) */ 407 IntStatusSet_Reg = 0x18, /* Get status + enable/disable */ 408 IntStatusSetMasked_Reg = 0x1C, /* Get status + en/di (masked) */ 409 IntControlEna_Reg = 0x20, /* Interrupt control enable */ 410 IntControlDis_Reg = 0x24, /* Interrupt control disable */ 411 Status_Reg = 0x28, /* Status */ 412 #define STATUS_PROMDATA (0x00000001) /* PROM_DATA pin */ 413 #define STATUS_WAITING (0x00000002) /* Interrupt being delayed */ 414 #define STATUS_SOOL (0x00000004) /* SOOL alarm */ 415 #define STATUS_LOCD (0x00000008) /* LOCD alarm */ 416 #define STATUS_LED (0x00000010) /* LED (HAPPI) output */ 417 #define STATUS_GPIN (0x00000020) /* GPIN pin */ 418 #define STATUS_BUTTBUSY (0x00000040) /* Butt register is pending */ 419 Config1_Reg = 0x2C, /* Config word 1; bits: */ 420 #define CONFIG1_PROMDATA (0x00000001) /* PROM_DATA pin */ 421 #define CONFIG1_PROMCLK (0x00000002) /* PROM_CLK pin */ 422 #define CONFIG1_SET_READMODE(x) ((x)*0x004) /* PCI BM reads; values: */ 423 #define READMODE_PLAIN (0) /* Plain memory read */ 424 #define READMODE_LINE (2) /* Memory read line */ 425 #define READMODE_MULTIPLE (3) /* Memory read multiple */ 426 #define CONFIG1_DMA_ENABLE (0x00000010) /* Turn on DMA */ 427 #define CONFIG1_POWERDOWN (0x00000020) /* Turn off clocks */ 428 #define CONFIG1_SET_LOOPMODE(x) ((x)*0x080) /* Clock&loop mode; values: */ 429 #define LOOPMODE_NORMAL (0) /* Normal - no loop */ 430 #define LOOPMODE_TIME (1) 431 #define LOOPMODE_DIAG (2) 432 #define LOOPMODE_LINE (3) 433 #define CONFIG1_MASK_LOOPMODE (0x00000180) 434 #define CONFIG1_SET_LEDMODE(x) ((x)*0x0200) /* Mode of LED; values: */ 435 #define LEDMODE_NOT_SOOL (0) /* !SOOL */ 436 #define LEDMODE_OFF (1) /* 0 */ 437 #define LEDMODE_ON (2) /* 1 */ 438 #define LEDMODE_NOT_LOCD (3) /* !LOCD */ 439 #define LEDMORE_GPIN (4) /* GPIN */ 440 #define LEDMODE_NOT_GPIN (7) /* !GPIN */ 441 #define CONFIG1_MASK_LEDMODE (0x00000E00) 442 #define CONFIG1_GPOUT1 (0x00001000) /* Toggle for reset */ 443 #define CONFIG1_GPOUT2 (0x00002000) /* Loopback PHY */ 444 #define CONFIG1_GPOUT3 (0x00004000) /* Loopback lanai */ 445 Config2_Reg = 0x30, /* Config word 2; bits: */ 446 #define CONFIG2_HOWMANY (0x00000001) /* >512 VCIs? */ 447 #define CONFIG2_PTI7_MODE (0x00000002) /* Make PTI=7 RM, not OAM */ 448 #define CONFIG2_VPI_CHK_DIS (0x00000004) /* Ignore RX VPI value */ 449 #define CONFIG2_HEC_DROP (0x00000008) /* Drop cells w/ HEC errors */ 450 #define CONFIG2_VCI0_NORMAL (0x00000010) /* Treat VCI=0 normally */ 451 #define CONFIG2_CBR_ENABLE (0x00000020) /* Deal with CBR traffic */ 452 #define CONFIG2_TRASH_ALL (0x00000040) /* Trashing incoming cells */ 453 #define CONFIG2_TX_DISABLE (0x00000080) /* Trashing outgoing cells */ 454 #define CONFIG2_SET_TRASH (0x00000100) /* Turn trashing on */ 455 Statistics_Reg = 0x34, /* Statistics; bits: */ 456 #define STATS_GET_FIFO_OVFL(x) (((x)>> 0)&0xFF) /* FIFO overflowed */ 457 #define STATS_GET_HEC_ERR(x) (((x)>> 8)&0xFF) /* HEC was bad */ 458 #define STATS_GET_BAD_VCI(x) (((x)>>16)&0xFF) /* VCI not open */ 459 #define STATS_GET_BUF_OVFL(x) (((x)>>24)&0xFF) /* VCC buffer full */ 460 ServiceStuff_Reg = 0x38, /* Service stuff; bits: */ 461 #define SSTUFF_SET_SIZE(x) ((x)*0x20000000) /* size of service buffer */ 462 #define SSTUFF_SET_ADDR(x) ((x)>>8) /* set address of buffer */ 463 ServWrite_Reg = 0x3C, /* ServWrite Pointer */ 464 ServRead_Reg = 0x40, /* ServRead Pointer */ 465 TxDepth_Reg = 0x44, /* FIFO Transmit Depth */ 466 Butt_Reg = 0x48, /* Butt register */ 467 CBR_ICG_Reg = 0x50, 468 CBR_PTR_Reg = 0x54, 469 PingCount_Reg = 0x58, /* Ping count */ 470 DMA_Addr_Reg = 0x5C /* DMA address */ 471 }; 472 473 static inline bus_addr_t reg_addr(const struct lanai_dev *lanai, 474 enum lanai_register reg) 475 { 476 return lanai->base + reg; 477 } 478 479 static inline u32 reg_read(const struct lanai_dev *lanai, 480 enum lanai_register reg) 481 { 482 u32 t; 483 t = readl(reg_addr(lanai, reg)); 484 RWDEBUG("R [0x%08X] 0x%02X = 0x%08X\n", (unsigned int) lanai->base, 485 (int) reg, t); 486 return t; 487 } 488 489 static inline void reg_write(const struct lanai_dev *lanai, u32 val, 490 enum lanai_register reg) 491 { 492 RWDEBUG("W [0x%08X] 0x%02X < 0x%08X\n", (unsigned int) lanai->base, 493 (int) reg, val); 494 writel(val, reg_addr(lanai, reg)); 495 } 496 497 static inline void conf1_write(const struct lanai_dev *lanai) 498 { 499 reg_write(lanai, lanai->conf1, Config1_Reg); 500 } 501 502 static inline void conf2_write(const struct lanai_dev *lanai) 503 { 504 reg_write(lanai, lanai->conf2, Config2_Reg); 505 } 506 507 /* Same as conf2_write(), but defers I/O if we're powered down */ 508 static inline void conf2_write_if_powerup(const struct lanai_dev *lanai) 509 { 510 #ifdef USE_POWERDOWN 511 if (unlikely((lanai->conf1 & CONFIG1_POWERDOWN) != 0)) 512 return; 513 #endif /* USE_POWERDOWN */ 514 conf2_write(lanai); 515 } 516 517 static inline void reset_board(const struct lanai_dev *lanai) 518 { 519 DPRINTK("about to reset board\n"); 520 reg_write(lanai, 0, Reset_Reg); 521 /* 522 * If we don't delay a little while here then we can end up 523 * leaving the card in a VERY weird state and lock up the 524 * PCI bus. This isn't documented anywhere but I've convinced 525 * myself after a lot of painful experimentation 526 */ 527 udelay(5); 528 } 529 530 /* -------------------- CARD SRAM UTILITIES: */ 531 532 /* The SRAM is mapped into normal PCI memory space - the only catch is 533 * that it is only 16-bits wide but must be accessed as 32-bit. The 534 * 16 high bits will be zero. We don't hide this, since they get 535 * programmed mostly like discrete registers anyway 536 */ 537 #define SRAM_START (0x20000) 538 #define SRAM_BYTES (0x20000) /* Again, half don't really exist */ 539 540 static inline bus_addr_t sram_addr(const struct lanai_dev *lanai, int offset) 541 { 542 return lanai->base + SRAM_START + offset; 543 } 544 545 static inline u32 sram_read(const struct lanai_dev *lanai, int offset) 546 { 547 return readl(sram_addr(lanai, offset)); 548 } 549 550 static inline void sram_write(const struct lanai_dev *lanai, 551 u32 val, int offset) 552 { 553 writel(val, sram_addr(lanai, offset)); 554 } 555 556 static int __init sram_test_word( 557 const struct lanai_dev *lanai, int offset, u32 pattern) 558 { 559 u32 readback; 560 sram_write(lanai, pattern, offset); 561 readback = sram_read(lanai, offset); 562 if (likely(readback == pattern)) 563 return 0; 564 printk(KERN_ERR DEV_LABEL 565 "(itf %d): SRAM word at %d bad: wrote 0x%X, read 0x%X\n", 566 lanai->number, offset, 567 (unsigned int) pattern, (unsigned int) readback); 568 return -EIO; 569 } 570 571 static int __devinit sram_test_pass(const struct lanai_dev *lanai, u32 pattern) 572 { 573 int offset, result = 0; 574 for (offset = 0; offset < SRAM_BYTES && result == 0; offset += 4) 575 result = sram_test_word(lanai, offset, pattern); 576 return result; 577 } 578 579 static int __devinit sram_test_and_clear(const struct lanai_dev *lanai) 580 { 581 #ifdef FULL_MEMORY_TEST 582 int result; 583 DPRINTK("testing SRAM\n"); 584 if ((result = sram_test_pass(lanai, 0x5555)) != 0) 585 return result; 586 if ((result = sram_test_pass(lanai, 0xAAAA)) != 0) 587 return result; 588 #endif 589 DPRINTK("clearing SRAM\n"); 590 return sram_test_pass(lanai, 0x0000); 591 } 592 593 /* -------------------- CARD-BASED VCC TABLE UTILITIES: */ 594 595 /* vcc table */ 596 enum lanai_vcc_offset { 597 vcc_rxaddr1 = 0x00, /* Location1, plus bits: */ 598 #define RXADDR1_SET_SIZE(x) ((x)*0x0000100) /* size of RX buffer */ 599 #define RXADDR1_SET_RMMODE(x) ((x)*0x00800) /* RM cell action; values: */ 600 #define RMMODE_TRASH (0) /* discard */ 601 #define RMMODE_PRESERVE (1) /* input as AAL0 */ 602 #define RMMODE_PIPE (2) /* pipe to coscheduler */ 603 #define RMMODE_PIPEALL (3) /* pipe non-RM too */ 604 #define RXADDR1_OAM_PRESERVE (0x00002000) /* Input OAM cells as AAL0 */ 605 #define RXADDR1_SET_MODE(x) ((x)*0x0004000) /* Reassembly mode */ 606 #define RXMODE_TRASH (0) /* discard */ 607 #define RXMODE_AAL0 (1) /* non-AAL5 mode */ 608 #define RXMODE_AAL5 (2) /* AAL5, intr. each PDU */ 609 #define RXMODE_AAL5_STREAM (3) /* AAL5 w/o per-PDU intr */ 610 vcc_rxaddr2 = 0x04, /* Location2 */ 611 vcc_rxcrc1 = 0x08, /* RX CRC claculation space */ 612 vcc_rxcrc2 = 0x0C, 613 vcc_rxwriteptr = 0x10, /* RX writeptr, plus bits: */ 614 #define RXWRITEPTR_LASTEFCI (0x00002000) /* Last PDU had EFCI bit */ 615 #define RXWRITEPTR_DROPPING (0x00004000) /* Had error, dropping */ 616 #define RXWRITEPTR_TRASHING (0x00008000) /* Trashing */ 617 vcc_rxbufstart = 0x14, /* RX bufstart, plus bits: */ 618 #define RXBUFSTART_CLP (0x00004000) 619 #define RXBUFSTART_CI (0x00008000) 620 vcc_rxreadptr = 0x18, /* RX readptr */ 621 vcc_txicg = 0x1C, /* TX ICG */ 622 vcc_txaddr1 = 0x20, /* Location1, plus bits: */ 623 #define TXADDR1_SET_SIZE(x) ((x)*0x0000100) /* size of TX buffer */ 624 #define TXADDR1_ABR (0x00008000) /* use ABR (doesn't work) */ 625 vcc_txaddr2 = 0x24, /* Location2 */ 626 vcc_txcrc1 = 0x28, /* TX CRC claculation space */ 627 vcc_txcrc2 = 0x2C, 628 vcc_txreadptr = 0x30, /* TX Readptr, plus bits: */ 629 #define TXREADPTR_GET_PTR(x) ((x)&0x01FFF) 630 #define TXREADPTR_MASK_DELTA (0x0000E000) /* ? */ 631 vcc_txendptr = 0x34, /* TX Endptr, plus bits: */ 632 #define TXENDPTR_CLP (0x00002000) 633 #define TXENDPTR_MASK_PDUMODE (0x0000C000) /* PDU mode; values: */ 634 #define PDUMODE_AAL0 (0*0x04000) 635 #define PDUMODE_AAL5 (2*0x04000) 636 #define PDUMODE_AAL5STREAM (3*0x04000) 637 vcc_txwriteptr = 0x38, /* TX Writeptr */ 638 #define TXWRITEPTR_GET_PTR(x) ((x)&0x1FFF) 639 vcc_txcbr_next = 0x3C /* # of next CBR VCI in ring */ 640 #define TXCBR_NEXT_BOZO (0x00008000) /* "bozo bit" */ 641 }; 642 643 #define CARDVCC_SIZE (0x40) 644 645 static inline bus_addr_t cardvcc_addr(const struct lanai_dev *lanai, 646 vci_t vci) 647 { 648 return sram_addr(lanai, vci * CARDVCC_SIZE); 649 } 650 651 static inline u32 cardvcc_read(const struct lanai_vcc *lvcc, 652 enum lanai_vcc_offset offset) 653 { 654 u32 val; 655 APRINTK(lvcc->vbase != NULL, "cardvcc_read: unbound vcc!\n"); 656 val= readl(lvcc->vbase + offset); 657 RWDEBUG("VR vci=%04d 0x%02X = 0x%08X\n", 658 lvcc->vci, (int) offset, val); 659 return val; 660 } 661 662 static inline void cardvcc_write(const struct lanai_vcc *lvcc, 663 u32 val, enum lanai_vcc_offset offset) 664 { 665 APRINTK(lvcc->vbase != NULL, "cardvcc_write: unbound vcc!\n"); 666 APRINTK((val & ~0xFFFF) == 0, 667 "cardvcc_write: bad val 0x%X (vci=%d, addr=0x%02X)\n", 668 (unsigned int) val, lvcc->vci, (unsigned int) offset); 669 RWDEBUG("VW vci=%04d 0x%02X > 0x%08X\n", 670 lvcc->vci, (unsigned int) offset, (unsigned int) val); 671 writel(val, lvcc->vbase + offset); 672 } 673 674 /* -------------------- COMPUTE SIZE OF AN AAL5 PDU: */ 675 676 /* How many bytes will an AAL5 PDU take to transmit - remember that: 677 * o we need to add 8 bytes for length, CPI, UU, and CRC 678 * o we need to round up to 48 bytes for cells 679 */ 680 static inline int aal5_size(int size) 681 { 682 int cells = (size + 8 + 47) / 48; 683 return cells * 48; 684 } 685 686 /* How many bytes can we send if we have "space" space, assuming we have 687 * to send full cells 688 */ 689 static inline int aal5_spacefor(int space) 690 { 691 int cells = space / 48; 692 return cells * 48; 693 } 694 695 /* -------------------- FREE AN ATM SKB: */ 696 697 static inline void lanai_free_skb(struct atm_vcc *atmvcc, struct sk_buff *skb) 698 { 699 if (atmvcc->pop != NULL) 700 atmvcc->pop(atmvcc, skb); 701 else 702 dev_kfree_skb_any(skb); 703 } 704 705 /* -------------------- TURN VCCS ON AND OFF: */ 706 707 static void host_vcc_start_rx(const struct lanai_vcc *lvcc) 708 { 709 u32 addr1; 710 if (lvcc->rx.atmvcc->qos.aal == ATM_AAL5) { 711 dma_addr_t dmaaddr = lvcc->rx.buf.dmaaddr; 712 cardvcc_write(lvcc, 0xFFFF, vcc_rxcrc1); 713 cardvcc_write(lvcc, 0xFFFF, vcc_rxcrc2); 714 cardvcc_write(lvcc, 0, vcc_rxwriteptr); 715 cardvcc_write(lvcc, 0, vcc_rxbufstart); 716 cardvcc_write(lvcc, 0, vcc_rxreadptr); 717 cardvcc_write(lvcc, (dmaaddr >> 16) & 0xFFFF, vcc_rxaddr2); 718 addr1 = ((dmaaddr >> 8) & 0xFF) | 719 RXADDR1_SET_SIZE(lanai_buf_size_cardorder(&lvcc->rx.buf))| 720 RXADDR1_SET_RMMODE(RMMODE_TRASH) | /* ??? */ 721 /* RXADDR1_OAM_PRESERVE | --- no OAM support yet */ 722 RXADDR1_SET_MODE(RXMODE_AAL5); 723 } else 724 addr1 = RXADDR1_SET_RMMODE(RMMODE_PRESERVE) | /* ??? */ 725 RXADDR1_OAM_PRESERVE | /* ??? */ 726 RXADDR1_SET_MODE(RXMODE_AAL0); 727 /* This one must be last! */ 728 cardvcc_write(lvcc, addr1, vcc_rxaddr1); 729 } 730 731 static void host_vcc_start_tx(const struct lanai_vcc *lvcc) 732 { 733 dma_addr_t dmaaddr = lvcc->tx.buf.dmaaddr; 734 cardvcc_write(lvcc, 0, vcc_txicg); 735 cardvcc_write(lvcc, 0xFFFF, vcc_txcrc1); 736 cardvcc_write(lvcc, 0xFFFF, vcc_txcrc2); 737 cardvcc_write(lvcc, 0, vcc_txreadptr); 738 cardvcc_write(lvcc, 0, vcc_txendptr); 739 cardvcc_write(lvcc, 0, vcc_txwriteptr); 740 cardvcc_write(lvcc, 741 (lvcc->tx.atmvcc->qos.txtp.traffic_class == ATM_CBR) ? 742 TXCBR_NEXT_BOZO | lvcc->vci : 0, vcc_txcbr_next); 743 cardvcc_write(lvcc, (dmaaddr >> 16) & 0xFFFF, vcc_txaddr2); 744 cardvcc_write(lvcc, 745 ((dmaaddr >> 8) & 0xFF) | 746 TXADDR1_SET_SIZE(lanai_buf_size_cardorder(&lvcc->tx.buf)), 747 vcc_txaddr1); 748 } 749 750 /* Shutdown receiving on card */ 751 static void lanai_shutdown_rx_vci(const struct lanai_vcc *lvcc) 752 { 753 if (lvcc->vbase == NULL) /* We were never bound to a VCI */ 754 return; 755 /* 15.1.1 - set to trashing, wait one cell time (15us) */ 756 cardvcc_write(lvcc, 757 RXADDR1_SET_RMMODE(RMMODE_TRASH) | 758 RXADDR1_SET_MODE(RXMODE_TRASH), vcc_rxaddr1); 759 udelay(15); 760 /* 15.1.2 - clear rest of entries */ 761 cardvcc_write(lvcc, 0, vcc_rxaddr2); 762 cardvcc_write(lvcc, 0, vcc_rxcrc1); 763 cardvcc_write(lvcc, 0, vcc_rxcrc2); 764 cardvcc_write(lvcc, 0, vcc_rxwriteptr); 765 cardvcc_write(lvcc, 0, vcc_rxbufstart); 766 cardvcc_write(lvcc, 0, vcc_rxreadptr); 767 } 768 769 /* Shutdown transmitting on card. 770 * Unfortunately the lanai needs us to wait until all the data 771 * drains out of the buffer before we can dealloc it, so this 772 * can take awhile -- up to 370ms for a full 128KB buffer 773 * assuming everone else is quiet. In theory the time is 774 * boundless if there's a CBR VCC holding things up. 775 */ 776 static void lanai_shutdown_tx_vci(struct lanai_dev *lanai, 777 struct lanai_vcc *lvcc) 778 { 779 struct sk_buff *skb; 780 unsigned long flags, timeout; 781 int read, write, lastread = -1; 782 APRINTK(!in_interrupt(), 783 "lanai_shutdown_tx_vci called w/o process context!\n"); 784 if (lvcc->vbase == NULL) /* We were never bound to a VCI */ 785 return; 786 /* 15.2.1 - wait for queue to drain */ 787 while ((skb = skb_dequeue(&lvcc->tx.backlog)) != NULL) 788 lanai_free_skb(lvcc->tx.atmvcc, skb); 789 read_lock_irqsave(&vcc_sklist_lock, flags); 790 __clear_bit(lvcc->vci, lanai->backlog_vccs); 791 read_unlock_irqrestore(&vcc_sklist_lock, flags); 792 /* 793 * We need to wait for the VCC to drain but don't wait forever. We 794 * give each 1K of buffer size 1/128th of a second to clear out. 795 * TODO: maybe disable CBR if we're about to timeout? 796 */ 797 timeout = jiffies + 798 (((lanai_buf_size(&lvcc->tx.buf) / 1024) * HZ) >> 7); 799 write = TXWRITEPTR_GET_PTR(cardvcc_read(lvcc, vcc_txwriteptr)); 800 for (;;) { 801 read = TXREADPTR_GET_PTR(cardvcc_read(lvcc, vcc_txreadptr)); 802 if (read == write && /* Is TX buffer empty? */ 803 (lvcc->tx.atmvcc->qos.txtp.traffic_class != ATM_CBR || 804 (cardvcc_read(lvcc, vcc_txcbr_next) & 805 TXCBR_NEXT_BOZO) == 0)) 806 break; 807 if (read != lastread) { /* Has there been any progress? */ 808 lastread = read; 809 timeout += HZ / 10; 810 } 811 if (unlikely(time_after(jiffies, timeout))) { 812 printk(KERN_ERR DEV_LABEL "(itf %d): Timed out on " 813 "backlog closing vci %d\n", 814 lvcc->tx.atmvcc->dev->number, lvcc->vci); 815 DPRINTK("read, write = %d, %d\n", read, write); 816 break; 817 } 818 msleep(40); 819 } 820 /* 15.2.2 - clear out all tx registers */ 821 cardvcc_write(lvcc, 0, vcc_txreadptr); 822 cardvcc_write(lvcc, 0, vcc_txwriteptr); 823 cardvcc_write(lvcc, 0, vcc_txendptr); 824 cardvcc_write(lvcc, 0, vcc_txcrc1); 825 cardvcc_write(lvcc, 0, vcc_txcrc2); 826 cardvcc_write(lvcc, 0, vcc_txaddr2); 827 cardvcc_write(lvcc, 0, vcc_txaddr1); 828 } 829 830 /* -------------------- MANAGING AAL0 RX BUFFER: */ 831 832 static inline int aal0_buffer_allocate(struct lanai_dev *lanai) 833 { 834 DPRINTK("aal0_buffer_allocate: allocating AAL0 RX buffer\n"); 835 lanai_buf_allocate(&lanai->aal0buf, AAL0_RX_BUFFER_SIZE, 80, 836 lanai->pci); 837 return (lanai->aal0buf.start == NULL) ? -ENOMEM : 0; 838 } 839 840 static inline void aal0_buffer_free(struct lanai_dev *lanai) 841 { 842 DPRINTK("aal0_buffer_allocate: freeing AAL0 RX buffer\n"); 843 lanai_buf_deallocate(&lanai->aal0buf, lanai->pci); 844 } 845 846 /* -------------------- EEPROM UTILITIES: */ 847 848 /* Offsets of data in the EEPROM */ 849 #define EEPROM_COPYRIGHT (0) 850 #define EEPROM_COPYRIGHT_LEN (44) 851 #define EEPROM_CHECKSUM (62) 852 #define EEPROM_CHECKSUM_REV (63) 853 #define EEPROM_MAC (64) 854 #define EEPROM_MAC_REV (70) 855 #define EEPROM_SERIAL (112) 856 #define EEPROM_SERIAL_REV (116) 857 #define EEPROM_MAGIC (120) 858 #define EEPROM_MAGIC_REV (124) 859 860 #define EEPROM_MAGIC_VALUE (0x5AB478D2) 861 862 #ifndef READ_EEPROM 863 864 /* Stub functions to use if EEPROM reading is disabled */ 865 static int __devinit eeprom_read(struct lanai_dev *lanai) 866 { 867 printk(KERN_INFO DEV_LABEL "(itf %d): *NOT* reading EEPROM\n", 868 lanai->number); 869 memset(&lanai->eeprom[EEPROM_MAC], 0, 6); 870 return 0; 871 } 872 873 static int __devinit eeprom_validate(struct lanai_dev *lanai) 874 { 875 lanai->serialno = 0; 876 lanai->magicno = EEPROM_MAGIC_VALUE; 877 return 0; 878 } 879 880 #else /* READ_EEPROM */ 881 882 static int __devinit eeprom_read(struct lanai_dev *lanai) 883 { 884 int i, address; 885 u8 data; 886 u32 tmp; 887 #define set_config1(x) do { lanai->conf1 = x; conf1_write(lanai); \ 888 } while (0) 889 #define clock_h() set_config1(lanai->conf1 | CONFIG1_PROMCLK) 890 #define clock_l() set_config1(lanai->conf1 &~ CONFIG1_PROMCLK) 891 #define data_h() set_config1(lanai->conf1 | CONFIG1_PROMDATA) 892 #define data_l() set_config1(lanai->conf1 &~ CONFIG1_PROMDATA) 893 #define pre_read() do { data_h(); clock_h(); udelay(5); } while (0) 894 #define read_pin() (reg_read(lanai, Status_Reg) & STATUS_PROMDATA) 895 #define send_stop() do { data_l(); udelay(5); clock_h(); udelay(5); \ 896 data_h(); udelay(5); } while (0) 897 /* start with both clock and data high */ 898 data_h(); clock_h(); udelay(5); 899 for (address = 0; address < LANAI_EEPROM_SIZE; address++) { 900 data = (address << 1) | 1; /* Command=read + address */ 901 /* send start bit */ 902 data_l(); udelay(5); 903 clock_l(); udelay(5); 904 for (i = 128; i != 0; i >>= 1) { /* write command out */ 905 tmp = (lanai->conf1 & ~CONFIG1_PROMDATA) | 906 (data & i) ? CONFIG1_PROMDATA : 0; 907 if (lanai->conf1 != tmp) { 908 set_config1(tmp); 909 udelay(5); /* Let new data settle */ 910 } 911 clock_h(); udelay(5); clock_l(); udelay(5); 912 } 913 /* look for ack */ 914 data_h(); clock_h(); udelay(5); 915 if (read_pin() != 0) 916 goto error; /* No ack seen */ 917 clock_l(); udelay(5); 918 /* read back result */ 919 for (data = 0, i = 7; i >= 0; i--) { 920 data_h(); clock_h(); udelay(5); 921 data = (data << 1) | !!read_pin(); 922 clock_l(); udelay(5); 923 } 924 /* look again for ack */ 925 data_h(); clock_h(); udelay(5); 926 if (read_pin() == 0) 927 goto error; /* Spurious ack */ 928 clock_l(); udelay(5); 929 send_stop(); 930 lanai->eeprom[address] = data; 931 DPRINTK("EEPROM 0x%04X %02X\n", 932 (unsigned int) address, (unsigned int) data); 933 } 934 return 0; 935 error: 936 clock_l(); udelay(5); /* finish read */ 937 send_stop(); 938 printk(KERN_ERR DEV_LABEL "(itf %d): error reading EEPROM byte %d\n", 939 lanai->number, address); 940 return -EIO; 941 #undef set_config1 942 #undef clock_h 943 #undef clock_l 944 #undef data_h 945 #undef data_l 946 #undef pre_read 947 #undef read_pin 948 #undef send_stop 949 } 950 951 /* read a big-endian 4-byte value out of eeprom */ 952 static inline u32 eeprom_be4(const struct lanai_dev *lanai, int address) 953 { 954 return be32_to_cpup((const u32 *) &lanai->eeprom[address]); 955 } 956 957 /* Checksum/validate EEPROM contents */ 958 static int __devinit eeprom_validate(struct lanai_dev *lanai) 959 { 960 int i, s; 961 u32 v; 962 const u8 *e = lanai->eeprom; 963 #ifdef DEBUG 964 /* First, see if we can get an ASCIIZ string out of the copyright */ 965 for (i = EEPROM_COPYRIGHT; 966 i < (EEPROM_COPYRIGHT + EEPROM_COPYRIGHT_LEN); i++) 967 if (e[i] < 0x20 || e[i] > 0x7E) 968 break; 969 if ( i != EEPROM_COPYRIGHT && 970 i != EEPROM_COPYRIGHT + EEPROM_COPYRIGHT_LEN && e[i] == '\0') 971 DPRINTK("eeprom: copyright = \"%s\"\n", 972 (char *) &e[EEPROM_COPYRIGHT]); 973 else 974 DPRINTK("eeprom: copyright not found\n"); 975 #endif 976 /* Validate checksum */ 977 for (i = s = 0; i < EEPROM_CHECKSUM; i++) 978 s += e[i]; 979 s &= 0xFF; 980 if (s != e[EEPROM_CHECKSUM]) { 981 printk(KERN_ERR DEV_LABEL "(itf %d): EEPROM checksum bad " 982 "(wanted 0x%02X, got 0x%02X)\n", lanai->number, 983 (unsigned int) s, (unsigned int) e[EEPROM_CHECKSUM]); 984 return -EIO; 985 } 986 s ^= 0xFF; 987 if (s != e[EEPROM_CHECKSUM_REV]) { 988 printk(KERN_ERR DEV_LABEL "(itf %d): EEPROM inverse checksum " 989 "bad (wanted 0x%02X, got 0x%02X)\n", lanai->number, 990 (unsigned int) s, (unsigned int) e[EEPROM_CHECKSUM_REV]); 991 return -EIO; 992 } 993 /* Verify MAC address */ 994 for (i = 0; i < 6; i++) 995 if ((e[EEPROM_MAC + i] ^ e[EEPROM_MAC_REV + i]) != 0xFF) { 996 printk(KERN_ERR DEV_LABEL 997 "(itf %d) : EEPROM MAC addresses don't match " 998 "(0x%02X, inverse 0x%02X)\n", lanai->number, 999 (unsigned int) e[EEPROM_MAC + i], 1000 (unsigned int) e[EEPROM_MAC_REV + i]); 1001 return -EIO; 1002 } 1003 DPRINTK("eeprom: MAC address = %02X:%02X:%02X:%02X:%02X:%02X\n", 1004 e[EEPROM_MAC + 0], e[EEPROM_MAC + 1], e[EEPROM_MAC + 2], 1005 e[EEPROM_MAC + 3], e[EEPROM_MAC + 4], e[EEPROM_MAC + 5]); 1006 /* Verify serial number */ 1007 lanai->serialno = eeprom_be4(lanai, EEPROM_SERIAL); 1008 v = eeprom_be4(lanai, EEPROM_SERIAL_REV); 1009 if ((lanai->serialno ^ v) != 0xFFFFFFFF) { 1010 printk(KERN_ERR DEV_LABEL "(itf %d): EEPROM serial numbers " 1011 "don't match (0x%08X, inverse 0x%08X)\n", lanai->number, 1012 (unsigned int) lanai->serialno, (unsigned int) v); 1013 return -EIO; 1014 } 1015 DPRINTK("eeprom: Serial number = %d\n", (unsigned int) lanai->serialno); 1016 /* Verify magic number */ 1017 lanai->magicno = eeprom_be4(lanai, EEPROM_MAGIC); 1018 v = eeprom_be4(lanai, EEPROM_MAGIC_REV); 1019 if ((lanai->magicno ^ v) != 0xFFFFFFFF) { 1020 printk(KERN_ERR DEV_LABEL "(itf %d): EEPROM magic numbers " 1021 "don't match (0x%08X, inverse 0x%08X)\n", lanai->number, 1022 lanai->magicno, v); 1023 return -EIO; 1024 } 1025 DPRINTK("eeprom: Magic number = 0x%08X\n", lanai->magicno); 1026 if (lanai->magicno != EEPROM_MAGIC_VALUE) 1027 printk(KERN_WARNING DEV_LABEL "(itf %d): warning - EEPROM " 1028 "magic not what expected (got 0x%08X, not 0x%08X)\n", 1029 lanai->number, (unsigned int) lanai->magicno, 1030 (unsigned int) EEPROM_MAGIC_VALUE); 1031 return 0; 1032 } 1033 1034 #endif /* READ_EEPROM */ 1035 1036 static inline const u8 *eeprom_mac(const struct lanai_dev *lanai) 1037 { 1038 return &lanai->eeprom[EEPROM_MAC]; 1039 } 1040 1041 /* -------------------- INTERRUPT HANDLING UTILITIES: */ 1042 1043 /* Interrupt types */ 1044 #define INT_STATS (0x00000002) /* Statistics counter overflow */ 1045 #define INT_SOOL (0x00000004) /* SOOL changed state */ 1046 #define INT_LOCD (0x00000008) /* LOCD changed state */ 1047 #define INT_LED (0x00000010) /* LED (HAPPI) changed state */ 1048 #define INT_GPIN (0x00000020) /* GPIN changed state */ 1049 #define INT_PING (0x00000040) /* PING_COUNT fulfilled */ 1050 #define INT_WAKE (0x00000080) /* Lanai wants bus */ 1051 #define INT_CBR0 (0x00000100) /* CBR sched hit VCI 0 */ 1052 #define INT_LOCK (0x00000200) /* Service list overflow */ 1053 #define INT_MISMATCH (0x00000400) /* TX magic list mismatch */ 1054 #define INT_AAL0_STR (0x00000800) /* Non-AAL5 buffer half filled */ 1055 #define INT_AAL0 (0x00001000) /* Non-AAL5 data available */ 1056 #define INT_SERVICE (0x00002000) /* Service list entries available */ 1057 #define INT_TABORTSENT (0x00004000) /* Target abort sent by lanai */ 1058 #define INT_TABORTBM (0x00008000) /* Abort rcv'd as bus master */ 1059 #define INT_TIMEOUTBM (0x00010000) /* No response to bus master */ 1060 #define INT_PCIPARITY (0x00020000) /* Parity error on PCI */ 1061 1062 /* Sets of the above */ 1063 #define INT_ALL (0x0003FFFE) /* All interrupts */ 1064 #define INT_STATUS (0x0000003C) /* Some status pin changed */ 1065 #define INT_DMASHUT (0x00038000) /* DMA engine got shut down */ 1066 #define INT_SEGSHUT (0x00000700) /* Segmentation got shut down */ 1067 1068 static inline u32 intr_pending(const struct lanai_dev *lanai) 1069 { 1070 return reg_read(lanai, IntStatusMasked_Reg); 1071 } 1072 1073 static inline void intr_enable(const struct lanai_dev *lanai, u32 i) 1074 { 1075 reg_write(lanai, i, IntControlEna_Reg); 1076 } 1077 1078 static inline void intr_disable(const struct lanai_dev *lanai, u32 i) 1079 { 1080 reg_write(lanai, i, IntControlDis_Reg); 1081 } 1082 1083 /* -------------------- CARD/PCI STATUS: */ 1084 1085 static void status_message(int itf, const char *name, int status) 1086 { 1087 static const char *onoff[2] = { "off to on", "on to off" }; 1088 printk(KERN_INFO DEV_LABEL "(itf %d): %s changed from %s\n", 1089 itf, name, onoff[!status]); 1090 } 1091 1092 static void lanai_check_status(struct lanai_dev *lanai) 1093 { 1094 u32 new = reg_read(lanai, Status_Reg); 1095 u32 changes = new ^ lanai->status; 1096 lanai->status = new; 1097 #define e(flag, name) \ 1098 if (changes & flag) \ 1099 status_message(lanai->number, name, new & flag) 1100 e(STATUS_SOOL, "SOOL"); 1101 e(STATUS_LOCD, "LOCD"); 1102 e(STATUS_LED, "LED"); 1103 e(STATUS_GPIN, "GPIN"); 1104 #undef e 1105 } 1106 1107 static void pcistatus_got(int itf, const char *name) 1108 { 1109 printk(KERN_INFO DEV_LABEL "(itf %d): PCI got %s error\n", itf, name); 1110 } 1111 1112 static void pcistatus_check(struct lanai_dev *lanai, int clearonly) 1113 { 1114 u16 s; 1115 int result; 1116 result = pci_read_config_word(lanai->pci, PCI_STATUS, &s); 1117 if (result != PCIBIOS_SUCCESSFUL) { 1118 printk(KERN_ERR DEV_LABEL "(itf %d): can't read PCI_STATUS: " 1119 "%d\n", lanai->number, result); 1120 return; 1121 } 1122 s &= PCI_STATUS_DETECTED_PARITY | PCI_STATUS_SIG_SYSTEM_ERROR | 1123 PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT | 1124 PCI_STATUS_SIG_TARGET_ABORT | PCI_STATUS_PARITY; 1125 if (s == 0) 1126 return; 1127 result = pci_write_config_word(lanai->pci, PCI_STATUS, s); 1128 if (result != PCIBIOS_SUCCESSFUL) 1129 printk(KERN_ERR DEV_LABEL "(itf %d): can't write PCI_STATUS: " 1130 "%d\n", lanai->number, result); 1131 if (clearonly) 1132 return; 1133 #define e(flag, name, stat) \ 1134 if (s & flag) { \ 1135 pcistatus_got(lanai->number, name); \ 1136 ++lanai->stats.pcierr_##stat; \ 1137 } 1138 e(PCI_STATUS_DETECTED_PARITY, "parity", parity_detect); 1139 e(PCI_STATUS_SIG_SYSTEM_ERROR, "signalled system", serr_set); 1140 e(PCI_STATUS_REC_MASTER_ABORT, "master", master_abort); 1141 e(PCI_STATUS_REC_TARGET_ABORT, "master target", m_target_abort); 1142 e(PCI_STATUS_SIG_TARGET_ABORT, "slave", s_target_abort); 1143 e(PCI_STATUS_PARITY, "master parity", master_parity); 1144 #undef e 1145 } 1146 1147 /* -------------------- VCC TX BUFFER UTILITIES: */ 1148 1149 /* space left in tx buffer in bytes */ 1150 static inline int vcc_tx_space(const struct lanai_vcc *lvcc, int endptr) 1151 { 1152 int r; 1153 r = endptr * 16; 1154 r -= ((unsigned long) lvcc->tx.buf.ptr) - 1155 ((unsigned long) lvcc->tx.buf.start); 1156 r -= 16; /* Leave "bubble" - if start==end it looks empty */ 1157 if (r < 0) 1158 r += lanai_buf_size(&lvcc->tx.buf); 1159 return r; 1160 } 1161 1162 /* test if VCC is currently backlogged */ 1163 static inline int vcc_is_backlogged(const struct lanai_vcc *lvcc) 1164 { 1165 return !skb_queue_empty(&lvcc->tx.backlog); 1166 } 1167 1168 /* Bit fields in the segmentation buffer descriptor */ 1169 #define DESCRIPTOR_MAGIC (0xD0000000) 1170 #define DESCRIPTOR_AAL5 (0x00008000) 1171 #define DESCRIPTOR_AAL5_STREAM (0x00004000) 1172 #define DESCRIPTOR_CLP (0x00002000) 1173 1174 /* Add 32-bit descriptor with its padding */ 1175 static inline void vcc_tx_add_aal5_descriptor(struct lanai_vcc *lvcc, 1176 u32 flags, int len) 1177 { 1178 int pos; 1179 APRINTK((((unsigned long) lvcc->tx.buf.ptr) & 15) == 0, 1180 "vcc_tx_add_aal5_descriptor: bad ptr=%p\n", lvcc->tx.buf.ptr); 1181 lvcc->tx.buf.ptr += 4; /* Hope the values REALLY don't matter */ 1182 pos = ((unsigned char *) lvcc->tx.buf.ptr) - 1183 (unsigned char *) lvcc->tx.buf.start; 1184 APRINTK((pos & ~0x0001FFF0) == 0, 1185 "vcc_tx_add_aal5_descriptor: bad pos (%d) before, vci=%d, " 1186 "start,ptr,end=%p,%p,%p\n", pos, lvcc->vci, 1187 lvcc->tx.buf.start, lvcc->tx.buf.ptr, lvcc->tx.buf.end); 1188 pos = (pos + len) & (lanai_buf_size(&lvcc->tx.buf) - 1); 1189 APRINTK((pos & ~0x0001FFF0) == 0, 1190 "vcc_tx_add_aal5_descriptor: bad pos (%d) after, vci=%d, " 1191 "start,ptr,end=%p,%p,%p\n", pos, lvcc->vci, 1192 lvcc->tx.buf.start, lvcc->tx.buf.ptr, lvcc->tx.buf.end); 1193 lvcc->tx.buf.ptr[-1] = 1194 cpu_to_le32(DESCRIPTOR_MAGIC | DESCRIPTOR_AAL5 | 1195 ((lvcc->tx.atmvcc->atm_options & ATM_ATMOPT_CLP) ? 1196 DESCRIPTOR_CLP : 0) | flags | pos >> 4); 1197 if (lvcc->tx.buf.ptr >= lvcc->tx.buf.end) 1198 lvcc->tx.buf.ptr = lvcc->tx.buf.start; 1199 } 1200 1201 /* Add 32-bit AAL5 trailer and leave room for its CRC */ 1202 static inline void vcc_tx_add_aal5_trailer(struct lanai_vcc *lvcc, 1203 int len, int cpi, int uu) 1204 { 1205 APRINTK((((unsigned long) lvcc->tx.buf.ptr) & 15) == 8, 1206 "vcc_tx_add_aal5_trailer: bad ptr=%p\n", lvcc->tx.buf.ptr); 1207 lvcc->tx.buf.ptr += 2; 1208 lvcc->tx.buf.ptr[-2] = cpu_to_be32((uu << 24) | (cpi << 16) | len); 1209 if (lvcc->tx.buf.ptr >= lvcc->tx.buf.end) 1210 lvcc->tx.buf.ptr = lvcc->tx.buf.start; 1211 } 1212 1213 static inline void vcc_tx_memcpy(struct lanai_vcc *lvcc, 1214 const unsigned char *src, int n) 1215 { 1216 unsigned char *e; 1217 int m; 1218 e = ((unsigned char *) lvcc->tx.buf.ptr) + n; 1219 m = e - (unsigned char *) lvcc->tx.buf.end; 1220 if (m < 0) 1221 m = 0; 1222 memcpy(lvcc->tx.buf.ptr, src, n - m); 1223 if (m != 0) { 1224 memcpy(lvcc->tx.buf.start, src + n - m, m); 1225 e = ((unsigned char *) lvcc->tx.buf.start) + m; 1226 } 1227 lvcc->tx.buf.ptr = (u32 *) e; 1228 } 1229 1230 static inline void vcc_tx_memzero(struct lanai_vcc *lvcc, int n) 1231 { 1232 unsigned char *e; 1233 int m; 1234 if (n == 0) 1235 return; 1236 e = ((unsigned char *) lvcc->tx.buf.ptr) + n; 1237 m = e - (unsigned char *) lvcc->tx.buf.end; 1238 if (m < 0) 1239 m = 0; 1240 memset(lvcc->tx.buf.ptr, 0, n - m); 1241 if (m != 0) { 1242 memset(lvcc->tx.buf.start, 0, m); 1243 e = ((unsigned char *) lvcc->tx.buf.start) + m; 1244 } 1245 lvcc->tx.buf.ptr = (u32 *) e; 1246 } 1247 1248 /* Update "butt" register to specify new WritePtr */ 1249 static inline void lanai_endtx(struct lanai_dev *lanai, 1250 const struct lanai_vcc *lvcc) 1251 { 1252 int i, ptr = ((unsigned char *) lvcc->tx.buf.ptr) - 1253 (unsigned char *) lvcc->tx.buf.start; 1254 APRINTK((ptr & ~0x0001FFF0) == 0, 1255 "lanai_endtx: bad ptr (%d), vci=%d, start,ptr,end=%p,%p,%p\n", 1256 ptr, lvcc->vci, lvcc->tx.buf.start, lvcc->tx.buf.ptr, 1257 lvcc->tx.buf.end); 1258 1259 /* 1260 * Since the "butt register" is a shared resounce on the card we 1261 * serialize all accesses to it through this spinlock. This is 1262 * mostly just paranoia sicne the register is rarely "busy" anyway 1263 * but is needed for correctness. 1264 */ 1265 spin_lock(&lanai->endtxlock); 1266 /* 1267 * We need to check if the "butt busy" bit is set before 1268 * updating the butt register. In theory this should 1269 * never happen because the ATM card is plenty fast at 1270 * updating the register. Still, we should make sure 1271 */ 1272 for (i = 0; reg_read(lanai, Status_Reg) & STATUS_BUTTBUSY; i++) { 1273 if (unlikely(i > 50)) { 1274 printk(KERN_ERR DEV_LABEL "(itf %d): butt register " 1275 "always busy!\n", lanai->number); 1276 break; 1277 } 1278 udelay(5); 1279 } 1280 /* 1281 * Before we tall the card to start work we need to be sure 100% of 1282 * the info in the service buffer has been written before we tell 1283 * the card about it 1284 */ 1285 wmb(); 1286 reg_write(lanai, (ptr << 12) | lvcc->vci, Butt_Reg); 1287 spin_unlock(&lanai->endtxlock); 1288 } 1289 1290 /* 1291 * Add one AAL5 PDU to lvcc's transmit buffer. Caller garauntees there's 1292 * space available. "pdusize" is the number of bytes the PDU will take 1293 */ 1294 static void lanai_send_one_aal5(struct lanai_dev *lanai, 1295 struct lanai_vcc *lvcc, struct sk_buff *skb, int pdusize) 1296 { 1297 int pad; 1298 APRINTK(pdusize == aal5_size(skb->len), 1299 "lanai_send_one_aal5: wrong size packet (%d != %d)\n", 1300 pdusize, aal5_size(skb->len)); 1301 vcc_tx_add_aal5_descriptor(lvcc, 0, pdusize); 1302 pad = pdusize - skb->len - 8; 1303 APRINTK(pad >= 0, "pad is negative (%d)\n", pad); 1304 APRINTK(pad < 48, "pad is too big (%d)\n", pad); 1305 vcc_tx_memcpy(lvcc, skb->data, skb->len); 1306 vcc_tx_memzero(lvcc, pad); 1307 vcc_tx_add_aal5_trailer(lvcc, skb->len, 0, 0); 1308 lanai_endtx(lanai, lvcc); 1309 lanai_free_skb(lvcc->tx.atmvcc, skb); 1310 atomic_inc(&lvcc->tx.atmvcc->stats->tx); 1311 } 1312 1313 /* Try to fill the buffer - don't call unless there is backlog */ 1314 static void vcc_tx_unqueue_aal5(struct lanai_dev *lanai, 1315 struct lanai_vcc *lvcc, int endptr) 1316 { 1317 int n; 1318 struct sk_buff *skb; 1319 int space = vcc_tx_space(lvcc, endptr); 1320 APRINTK(vcc_is_backlogged(lvcc), 1321 "vcc_tx_unqueue() called with empty backlog (vci=%d)\n", 1322 lvcc->vci); 1323 while (space >= 64) { 1324 skb = skb_dequeue(&lvcc->tx.backlog); 1325 if (skb == NULL) 1326 goto no_backlog; 1327 n = aal5_size(skb->len); 1328 if (n + 16 > space) { 1329 /* No room for this packet - put it back on queue */ 1330 skb_queue_head(&lvcc->tx.backlog, skb); 1331 return; 1332 } 1333 lanai_send_one_aal5(lanai, lvcc, skb, n); 1334 space -= n + 16; 1335 } 1336 if (!vcc_is_backlogged(lvcc)) { 1337 no_backlog: 1338 __clear_bit(lvcc->vci, lanai->backlog_vccs); 1339 } 1340 } 1341 1342 /* Given an skb that we want to transmit either send it now or queue */ 1343 static void vcc_tx_aal5(struct lanai_dev *lanai, struct lanai_vcc *lvcc, 1344 struct sk_buff *skb) 1345 { 1346 int space, n; 1347 if (vcc_is_backlogged(lvcc)) /* Already backlogged */ 1348 goto queue_it; 1349 space = vcc_tx_space(lvcc, 1350 TXREADPTR_GET_PTR(cardvcc_read(lvcc, vcc_txreadptr))); 1351 n = aal5_size(skb->len); 1352 APRINTK(n + 16 >= 64, "vcc_tx_aal5: n too small (%d)\n", n); 1353 if (space < n + 16) { /* No space for this PDU */ 1354 __set_bit(lvcc->vci, lanai->backlog_vccs); 1355 queue_it: 1356 skb_queue_tail(&lvcc->tx.backlog, skb); 1357 return; 1358 } 1359 lanai_send_one_aal5(lanai, lvcc, skb, n); 1360 } 1361 1362 static void vcc_tx_unqueue_aal0(struct lanai_dev *lanai, 1363 struct lanai_vcc *lvcc, int endptr) 1364 { 1365 printk(KERN_INFO DEV_LABEL 1366 ": vcc_tx_unqueue_aal0: not implemented\n"); 1367 } 1368 1369 static void vcc_tx_aal0(struct lanai_dev *lanai, struct lanai_vcc *lvcc, 1370 struct sk_buff *skb) 1371 { 1372 printk(KERN_INFO DEV_LABEL ": vcc_tx_aal0: not implemented\n"); 1373 /* Remember to increment lvcc->tx.atmvcc->stats->tx */ 1374 lanai_free_skb(lvcc->tx.atmvcc, skb); 1375 } 1376 1377 /* -------------------- VCC RX BUFFER UTILITIES: */ 1378 1379 /* unlike the _tx_ cousins, this doesn't update ptr */ 1380 static inline void vcc_rx_memcpy(unsigned char *dest, 1381 const struct lanai_vcc *lvcc, int n) 1382 { 1383 int m = ((const unsigned char *) lvcc->rx.buf.ptr) + n - 1384 ((const unsigned char *) (lvcc->rx.buf.end)); 1385 if (m < 0) 1386 m = 0; 1387 memcpy(dest, lvcc->rx.buf.ptr, n - m); 1388 memcpy(dest + n - m, lvcc->rx.buf.start, m); 1389 /* Make sure that these copies don't get reordered */ 1390 barrier(); 1391 } 1392 1393 /* Receive AAL5 data on a VCC with a particular endptr */ 1394 static void vcc_rx_aal5(struct lanai_vcc *lvcc, int endptr) 1395 { 1396 int size; 1397 struct sk_buff *skb; 1398 const u32 *x; 1399 u32 *end = &lvcc->rx.buf.start[endptr * 4]; 1400 int n = ((unsigned long) end) - ((unsigned long) lvcc->rx.buf.ptr); 1401 if (n < 0) 1402 n += lanai_buf_size(&lvcc->rx.buf); 1403 APRINTK(n >= 0 && n < lanai_buf_size(&lvcc->rx.buf) && !(n & 15), 1404 "vcc_rx_aal5: n out of range (%d/%Zu)\n", 1405 n, lanai_buf_size(&lvcc->rx.buf)); 1406 /* Recover the second-to-last word to get true pdu length */ 1407 if ((x = &end[-2]) < lvcc->rx.buf.start) 1408 x = &lvcc->rx.buf.end[-2]; 1409 /* 1410 * Before we actually read from the buffer, make sure the memory 1411 * changes have arrived 1412 */ 1413 rmb(); 1414 size = be32_to_cpup(x) & 0xffff; 1415 if (unlikely(n != aal5_size(size))) { 1416 /* Make sure size matches padding */ 1417 printk(KERN_INFO DEV_LABEL "(itf %d): Got bad AAL5 length " 1418 "on vci=%d - size=%d n=%d\n", 1419 lvcc->rx.atmvcc->dev->number, lvcc->vci, size, n); 1420 lvcc->stats.x.aal5.rx_badlen++; 1421 goto out; 1422 } 1423 skb = atm_alloc_charge(lvcc->rx.atmvcc, size, GFP_ATOMIC); 1424 if (unlikely(skb == NULL)) { 1425 lvcc->stats.rx_nomem++; 1426 goto out; 1427 } 1428 skb_put(skb, size); 1429 vcc_rx_memcpy(skb->data, lvcc, size); 1430 ATM_SKB(skb)->vcc = lvcc->rx.atmvcc; 1431 __net_timestamp(skb); 1432 lvcc->rx.atmvcc->push(lvcc->rx.atmvcc, skb); 1433 atomic_inc(&lvcc->rx.atmvcc->stats->rx); 1434 out: 1435 lvcc->rx.buf.ptr = end; 1436 cardvcc_write(lvcc, endptr, vcc_rxreadptr); 1437 } 1438 1439 static void vcc_rx_aal0(struct lanai_dev *lanai) 1440 { 1441 printk(KERN_INFO DEV_LABEL ": vcc_rx_aal0: not implemented\n"); 1442 /* Remember to get read_lock(&vcc_sklist_lock) while looking up VC */ 1443 /* Remember to increment lvcc->rx.atmvcc->stats->rx */ 1444 } 1445 1446 /* -------------------- MANAGING HOST-BASED VCC TABLE: */ 1447 1448 /* Decide whether to use vmalloc or get_zeroed_page for VCC table */ 1449 #if (NUM_VCI * BITS_PER_LONG) <= PAGE_SIZE 1450 #define VCCTABLE_GETFREEPAGE 1451 #else 1452 #include <linux/vmalloc.h> 1453 #endif 1454 1455 static int __devinit vcc_table_allocate(struct lanai_dev *lanai) 1456 { 1457 #ifdef VCCTABLE_GETFREEPAGE 1458 APRINTK((lanai->num_vci) * sizeof(struct lanai_vcc *) <= PAGE_SIZE, 1459 "vcc table > PAGE_SIZE!"); 1460 lanai->vccs = (struct lanai_vcc **) get_zeroed_page(GFP_KERNEL); 1461 return (lanai->vccs == NULL) ? -ENOMEM : 0; 1462 #else 1463 int bytes = (lanai->num_vci) * sizeof(struct lanai_vcc *); 1464 lanai->vccs = (struct lanai_vcc **) vmalloc(bytes); 1465 if (unlikely(lanai->vccs == NULL)) 1466 return -ENOMEM; 1467 memset(lanai->vccs, 0, bytes); 1468 return 0; 1469 #endif 1470 } 1471 1472 static inline void vcc_table_deallocate(const struct lanai_dev *lanai) 1473 { 1474 #ifdef VCCTABLE_GETFREEPAGE 1475 free_page((unsigned long) lanai->vccs); 1476 #else 1477 vfree(lanai->vccs); 1478 #endif 1479 } 1480 1481 /* Allocate a fresh lanai_vcc, with the appropriate things cleared */ 1482 static inline struct lanai_vcc *new_lanai_vcc(void) 1483 { 1484 struct lanai_vcc *lvcc; 1485 lvcc = kzalloc(sizeof(*lvcc), GFP_KERNEL); 1486 if (likely(lvcc != NULL)) { 1487 skb_queue_head_init(&lvcc->tx.backlog); 1488 #ifdef DEBUG 1489 lvcc->vci = -1; 1490 #endif 1491 } 1492 return lvcc; 1493 } 1494 1495 static int lanai_get_sized_buffer(struct lanai_dev *lanai, 1496 struct lanai_buffer *buf, int max_sdu, int multiplier, 1497 const char *name) 1498 { 1499 int size; 1500 if (unlikely(max_sdu < 1)) 1501 max_sdu = 1; 1502 max_sdu = aal5_size(max_sdu); 1503 size = (max_sdu + 16) * multiplier + 16; 1504 lanai_buf_allocate(buf, size, max_sdu + 32, lanai->pci); 1505 if (unlikely(buf->start == NULL)) 1506 return -ENOMEM; 1507 if (unlikely(lanai_buf_size(buf) < size)) 1508 printk(KERN_WARNING DEV_LABEL "(itf %d): wanted %d bytes " 1509 "for %s buffer, got only %Zu\n", lanai->number, size, 1510 name, lanai_buf_size(buf)); 1511 DPRINTK("Allocated %Zu byte %s buffer\n", lanai_buf_size(buf), name); 1512 return 0; 1513 } 1514 1515 /* Setup a RX buffer for a currently unbound AAL5 vci */ 1516 static inline int lanai_setup_rx_vci_aal5(struct lanai_dev *lanai, 1517 struct lanai_vcc *lvcc, const struct atm_qos *qos) 1518 { 1519 return lanai_get_sized_buffer(lanai, &lvcc->rx.buf, 1520 qos->rxtp.max_sdu, AAL5_RX_MULTIPLIER, "RX"); 1521 } 1522 1523 /* Setup a TX buffer for a currently unbound AAL5 vci */ 1524 static int lanai_setup_tx_vci(struct lanai_dev *lanai, struct lanai_vcc *lvcc, 1525 const struct atm_qos *qos) 1526 { 1527 int max_sdu, multiplier; 1528 if (qos->aal == ATM_AAL0) { 1529 lvcc->tx.unqueue = vcc_tx_unqueue_aal0; 1530 max_sdu = ATM_CELL_SIZE - 1; 1531 multiplier = AAL0_TX_MULTIPLIER; 1532 } else { 1533 lvcc->tx.unqueue = vcc_tx_unqueue_aal5; 1534 max_sdu = qos->txtp.max_sdu; 1535 multiplier = AAL5_TX_MULTIPLIER; 1536 } 1537 return lanai_get_sized_buffer(lanai, &lvcc->tx.buf, max_sdu, 1538 multiplier, "TX"); 1539 } 1540 1541 static inline void host_vcc_bind(struct lanai_dev *lanai, 1542 struct lanai_vcc *lvcc, vci_t vci) 1543 { 1544 if (lvcc->vbase != NULL) 1545 return; /* We already were bound in the other direction */ 1546 DPRINTK("Binding vci %d\n", vci); 1547 #ifdef USE_POWERDOWN 1548 if (lanai->nbound++ == 0) { 1549 DPRINTK("Coming out of powerdown\n"); 1550 lanai->conf1 &= ~CONFIG1_POWERDOWN; 1551 conf1_write(lanai); 1552 conf2_write(lanai); 1553 } 1554 #endif 1555 lvcc->vbase = cardvcc_addr(lanai, vci); 1556 lanai->vccs[lvcc->vci = vci] = lvcc; 1557 } 1558 1559 static inline void host_vcc_unbind(struct lanai_dev *lanai, 1560 struct lanai_vcc *lvcc) 1561 { 1562 if (lvcc->vbase == NULL) 1563 return; /* This vcc was never bound */ 1564 DPRINTK("Unbinding vci %d\n", lvcc->vci); 1565 lvcc->vbase = NULL; 1566 lanai->vccs[lvcc->vci] = NULL; 1567 #ifdef USE_POWERDOWN 1568 if (--lanai->nbound == 0) { 1569 DPRINTK("Going into powerdown\n"); 1570 lanai->conf1 |= CONFIG1_POWERDOWN; 1571 conf1_write(lanai); 1572 } 1573 #endif 1574 } 1575 1576 /* -------------------- RESET CARD: */ 1577 1578 static void lanai_reset(struct lanai_dev *lanai) 1579 { 1580 printk(KERN_CRIT DEV_LABEL "(itf %d): *NOT* reseting - not " 1581 "implemented\n", lanai->number); 1582 /* TODO */ 1583 /* The following is just a hack until we write the real 1584 * resetter - at least ack whatever interrupt sent us 1585 * here 1586 */ 1587 reg_write(lanai, INT_ALL, IntAck_Reg); 1588 lanai->stats.card_reset++; 1589 } 1590 1591 /* -------------------- SERVICE LIST UTILITIES: */ 1592 1593 /* 1594 * Allocate service buffer and tell card about it 1595 */ 1596 static int __devinit service_buffer_allocate(struct lanai_dev *lanai) 1597 { 1598 lanai_buf_allocate(&lanai->service, SERVICE_ENTRIES * 4, 8, 1599 lanai->pci); 1600 if (unlikely(lanai->service.start == NULL)) 1601 return -ENOMEM; 1602 DPRINTK("allocated service buffer at 0x%08lX, size %Zu(%d)\n", 1603 (unsigned long) lanai->service.start, 1604 lanai_buf_size(&lanai->service), 1605 lanai_buf_size_cardorder(&lanai->service)); 1606 /* Clear ServWrite register to be safe */ 1607 reg_write(lanai, 0, ServWrite_Reg); 1608 /* ServiceStuff register contains size and address of buffer */ 1609 reg_write(lanai, 1610 SSTUFF_SET_SIZE(lanai_buf_size_cardorder(&lanai->service)) | 1611 SSTUFF_SET_ADDR(lanai->service.dmaaddr), 1612 ServiceStuff_Reg); 1613 return 0; 1614 } 1615 1616 static inline void service_buffer_deallocate(struct lanai_dev *lanai) 1617 { 1618 lanai_buf_deallocate(&lanai->service, lanai->pci); 1619 } 1620 1621 /* Bitfields in service list */ 1622 #define SERVICE_TX (0x80000000) /* Was from transmission */ 1623 #define SERVICE_TRASH (0x40000000) /* RXed PDU was trashed */ 1624 #define SERVICE_CRCERR (0x20000000) /* RXed PDU had CRC error */ 1625 #define SERVICE_CI (0x10000000) /* RXed PDU had CI set */ 1626 #define SERVICE_CLP (0x08000000) /* RXed PDU had CLP set */ 1627 #define SERVICE_STREAM (0x04000000) /* RX Stream mode */ 1628 #define SERVICE_GET_VCI(x) (((x)>>16)&0x3FF) 1629 #define SERVICE_GET_END(x) ((x)&0x1FFF) 1630 1631 /* Handle one thing from the service list - returns true if it marked a 1632 * VCC ready for xmit 1633 */ 1634 static int handle_service(struct lanai_dev *lanai, u32 s) 1635 { 1636 vci_t vci = SERVICE_GET_VCI(s); 1637 struct lanai_vcc *lvcc; 1638 read_lock(&vcc_sklist_lock); 1639 lvcc = lanai->vccs[vci]; 1640 if (unlikely(lvcc == NULL)) { 1641 read_unlock(&vcc_sklist_lock); 1642 DPRINTK("(itf %d) got service entry 0x%X for nonexistent " 1643 "vcc %d\n", lanai->number, (unsigned int) s, vci); 1644 if (s & SERVICE_TX) 1645 lanai->stats.service_notx++; 1646 else 1647 lanai->stats.service_norx++; 1648 return 0; 1649 } 1650 if (s & SERVICE_TX) { /* segmentation interrupt */ 1651 if (unlikely(lvcc->tx.atmvcc == NULL)) { 1652 read_unlock(&vcc_sklist_lock); 1653 DPRINTK("(itf %d) got service entry 0x%X for non-TX " 1654 "vcc %d\n", lanai->number, (unsigned int) s, vci); 1655 lanai->stats.service_notx++; 1656 return 0; 1657 } 1658 __set_bit(vci, lanai->transmit_ready); 1659 lvcc->tx.endptr = SERVICE_GET_END(s); 1660 read_unlock(&vcc_sklist_lock); 1661 return 1; 1662 } 1663 if (unlikely(lvcc->rx.atmvcc == NULL)) { 1664 read_unlock(&vcc_sklist_lock); 1665 DPRINTK("(itf %d) got service entry 0x%X for non-RX " 1666 "vcc %d\n", lanai->number, (unsigned int) s, vci); 1667 lanai->stats.service_norx++; 1668 return 0; 1669 } 1670 if (unlikely(lvcc->rx.atmvcc->qos.aal != ATM_AAL5)) { 1671 read_unlock(&vcc_sklist_lock); 1672 DPRINTK("(itf %d) got RX service entry 0x%X for non-AAL5 " 1673 "vcc %d\n", lanai->number, (unsigned int) s, vci); 1674 lanai->stats.service_rxnotaal5++; 1675 atomic_inc(&lvcc->rx.atmvcc->stats->rx_err); 1676 return 0; 1677 } 1678 if (likely(!(s & (SERVICE_TRASH | SERVICE_STREAM | SERVICE_CRCERR)))) { 1679 vcc_rx_aal5(lvcc, SERVICE_GET_END(s)); 1680 read_unlock(&vcc_sklist_lock); 1681 return 0; 1682 } 1683 if (s & SERVICE_TRASH) { 1684 int bytes; 1685 read_unlock(&vcc_sklist_lock); 1686 DPRINTK("got trashed rx pdu on vci %d\n", vci); 1687 atomic_inc(&lvcc->rx.atmvcc->stats->rx_err); 1688 lvcc->stats.x.aal5.service_trash++; 1689 bytes = (SERVICE_GET_END(s) * 16) - 1690 (((unsigned long) lvcc->rx.buf.ptr) - 1691 ((unsigned long) lvcc->rx.buf.start)) + 47; 1692 if (bytes < 0) 1693 bytes += lanai_buf_size(&lvcc->rx.buf); 1694 lanai->stats.ovfl_trash += (bytes / 48); 1695 return 0; 1696 } 1697 if (s & SERVICE_STREAM) { 1698 read_unlock(&vcc_sklist_lock); 1699 atomic_inc(&lvcc->rx.atmvcc->stats->rx_err); 1700 lvcc->stats.x.aal5.service_stream++; 1701 printk(KERN_ERR DEV_LABEL "(itf %d): Got AAL5 stream " 1702 "PDU on VCI %d!\n", lanai->number, vci); 1703 lanai_reset(lanai); 1704 return 0; 1705 } 1706 DPRINTK("got rx crc error on vci %d\n", vci); 1707 atomic_inc(&lvcc->rx.atmvcc->stats->rx_err); 1708 lvcc->stats.x.aal5.service_rxcrc++; 1709 lvcc->rx.buf.ptr = &lvcc->rx.buf.start[SERVICE_GET_END(s) * 4]; 1710 cardvcc_write(lvcc, SERVICE_GET_END(s), vcc_rxreadptr); 1711 read_unlock(&vcc_sklist_lock); 1712 return 0; 1713 } 1714 1715 /* Try transmitting on all VCIs that we marked ready to serve */ 1716 static void iter_transmit(struct lanai_dev *lanai, vci_t vci) 1717 { 1718 struct lanai_vcc *lvcc = lanai->vccs[vci]; 1719 if (vcc_is_backlogged(lvcc)) 1720 lvcc->tx.unqueue(lanai, lvcc, lvcc->tx.endptr); 1721 } 1722 1723 /* Run service queue -- called from interrupt context or with 1724 * interrupts otherwise disabled and with the lanai->servicelock 1725 * lock held 1726 */ 1727 static void run_service(struct lanai_dev *lanai) 1728 { 1729 int ntx = 0; 1730 u32 wreg = reg_read(lanai, ServWrite_Reg); 1731 const u32 *end = lanai->service.start + wreg; 1732 while (lanai->service.ptr != end) { 1733 ntx += handle_service(lanai, 1734 le32_to_cpup(lanai->service.ptr++)); 1735 if (lanai->service.ptr >= lanai->service.end) 1736 lanai->service.ptr = lanai->service.start; 1737 } 1738 reg_write(lanai, wreg, ServRead_Reg); 1739 if (ntx != 0) { 1740 read_lock(&vcc_sklist_lock); 1741 vci_bitfield_iterate(lanai, lanai->transmit_ready, 1742 iter_transmit); 1743 bitmap_zero(lanai->transmit_ready, NUM_VCI); 1744 read_unlock(&vcc_sklist_lock); 1745 } 1746 } 1747 1748 /* -------------------- GATHER STATISTICS: */ 1749 1750 static void get_statistics(struct lanai_dev *lanai) 1751 { 1752 u32 statreg = reg_read(lanai, Statistics_Reg); 1753 lanai->stats.atm_ovfl += STATS_GET_FIFO_OVFL(statreg); 1754 lanai->stats.hec_err += STATS_GET_HEC_ERR(statreg); 1755 lanai->stats.vci_trash += STATS_GET_BAD_VCI(statreg); 1756 lanai->stats.ovfl_trash += STATS_GET_BUF_OVFL(statreg); 1757 } 1758 1759 /* -------------------- POLLING TIMER: */ 1760 1761 #ifndef DEBUG_RW 1762 /* Try to undequeue 1 backlogged vcc */ 1763 static void iter_dequeue(struct lanai_dev *lanai, vci_t vci) 1764 { 1765 struct lanai_vcc *lvcc = lanai->vccs[vci]; 1766 int endptr; 1767 if (lvcc == NULL || lvcc->tx.atmvcc == NULL || 1768 !vcc_is_backlogged(lvcc)) { 1769 __clear_bit(vci, lanai->backlog_vccs); 1770 return; 1771 } 1772 endptr = TXREADPTR_GET_PTR(cardvcc_read(lvcc, vcc_txreadptr)); 1773 lvcc->tx.unqueue(lanai, lvcc, endptr); 1774 } 1775 #endif /* !DEBUG_RW */ 1776 1777 static void lanai_timed_poll(unsigned long arg) 1778 { 1779 struct lanai_dev *lanai = (struct lanai_dev *) arg; 1780 #ifndef DEBUG_RW 1781 unsigned long flags; 1782 #ifdef USE_POWERDOWN 1783 if (lanai->conf1 & CONFIG1_POWERDOWN) 1784 return; 1785 #endif /* USE_POWERDOWN */ 1786 local_irq_save(flags); 1787 /* If we can grab the spinlock, check if any services need to be run */ 1788 if (spin_trylock(&lanai->servicelock)) { 1789 run_service(lanai); 1790 spin_unlock(&lanai->servicelock); 1791 } 1792 /* ...and see if any backlogged VCs can make progress */ 1793 /* unfortunately linux has no read_trylock() currently */ 1794 read_lock(&vcc_sklist_lock); 1795 vci_bitfield_iterate(lanai, lanai->backlog_vccs, iter_dequeue); 1796 read_unlock(&vcc_sklist_lock); 1797 local_irq_restore(flags); 1798 1799 get_statistics(lanai); 1800 #endif /* !DEBUG_RW */ 1801 mod_timer(&lanai->timer, jiffies + LANAI_POLL_PERIOD); 1802 } 1803 1804 static inline void lanai_timed_poll_start(struct lanai_dev *lanai) 1805 { 1806 init_timer(&lanai->timer); 1807 lanai->timer.expires = jiffies + LANAI_POLL_PERIOD; 1808 lanai->timer.data = (unsigned long) lanai; 1809 lanai->timer.function = lanai_timed_poll; 1810 add_timer(&lanai->timer); 1811 } 1812 1813 static inline void lanai_timed_poll_stop(struct lanai_dev *lanai) 1814 { 1815 del_timer_sync(&lanai->timer); 1816 } 1817 1818 /* -------------------- INTERRUPT SERVICE: */ 1819 1820 static inline void lanai_int_1(struct lanai_dev *lanai, u32 reason) 1821 { 1822 u32 ack = 0; 1823 if (reason & INT_SERVICE) { 1824 ack = INT_SERVICE; 1825 spin_lock(&lanai->servicelock); 1826 run_service(lanai); 1827 spin_unlock(&lanai->servicelock); 1828 } 1829 if (reason & (INT_AAL0_STR | INT_AAL0)) { 1830 ack |= reason & (INT_AAL0_STR | INT_AAL0); 1831 vcc_rx_aal0(lanai); 1832 } 1833 /* The rest of the interrupts are pretty rare */ 1834 if (ack == reason) 1835 goto done; 1836 if (reason & INT_STATS) { 1837 reason &= ~INT_STATS; /* No need to ack */ 1838 get_statistics(lanai); 1839 } 1840 if (reason & INT_STATUS) { 1841 ack |= reason & INT_STATUS; 1842 lanai_check_status(lanai); 1843 } 1844 if (unlikely(reason & INT_DMASHUT)) { 1845 printk(KERN_ERR DEV_LABEL "(itf %d): driver error - DMA " 1846 "shutdown, reason=0x%08X, address=0x%08X\n", 1847 lanai->number, (unsigned int) (reason & INT_DMASHUT), 1848 (unsigned int) reg_read(lanai, DMA_Addr_Reg)); 1849 if (reason & INT_TABORTBM) { 1850 lanai_reset(lanai); 1851 return; 1852 } 1853 ack |= (reason & INT_DMASHUT); 1854 printk(KERN_ERR DEV_LABEL "(itf %d): re-enabling DMA\n", 1855 lanai->number); 1856 conf1_write(lanai); 1857 lanai->stats.dma_reenable++; 1858 pcistatus_check(lanai, 0); 1859 } 1860 if (unlikely(reason & INT_TABORTSENT)) { 1861 ack |= (reason & INT_TABORTSENT); 1862 printk(KERN_ERR DEV_LABEL "(itf %d): sent PCI target abort\n", 1863 lanai->number); 1864 pcistatus_check(lanai, 0); 1865 } 1866 if (unlikely(reason & INT_SEGSHUT)) { 1867 printk(KERN_ERR DEV_LABEL "(itf %d): driver error - " 1868 "segmentation shutdown, reason=0x%08X\n", lanai->number, 1869 (unsigned int) (reason & INT_SEGSHUT)); 1870 lanai_reset(lanai); 1871 return; 1872 } 1873 if (unlikely(reason & (INT_PING | INT_WAKE))) { 1874 printk(KERN_ERR DEV_LABEL "(itf %d): driver error - " 1875 "unexpected interrupt 0x%08X, resetting\n", 1876 lanai->number, 1877 (unsigned int) (reason & (INT_PING | INT_WAKE))); 1878 lanai_reset(lanai); 1879 return; 1880 } 1881 #ifdef DEBUG 1882 if (unlikely(ack != reason)) { 1883 DPRINTK("unacked ints: 0x%08X\n", 1884 (unsigned int) (reason & ~ack)); 1885 ack = reason; 1886 } 1887 #endif 1888 done: 1889 if (ack != 0) 1890 reg_write(lanai, ack, IntAck_Reg); 1891 } 1892 1893 static irqreturn_t lanai_int(int irq, void *devid) 1894 { 1895 struct lanai_dev *lanai = devid; 1896 u32 reason; 1897 1898 #ifdef USE_POWERDOWN 1899 /* 1900 * If we're powered down we shouldn't be generating any interrupts - 1901 * so assume that this is a shared interrupt line and it's for someone 1902 * else 1903 */ 1904 if (unlikely(lanai->conf1 & CONFIG1_POWERDOWN)) 1905 return IRQ_NONE; 1906 #endif 1907 1908 reason = intr_pending(lanai); 1909 if (reason == 0) 1910 return IRQ_NONE; /* Must be for someone else */ 1911 1912 do { 1913 if (unlikely(reason == 0xFFFFFFFF)) 1914 break; /* Maybe we've been unplugged? */ 1915 lanai_int_1(lanai, reason); 1916 reason = intr_pending(lanai); 1917 } while (reason != 0); 1918 1919 return IRQ_HANDLED; 1920 } 1921 1922 /* TODO - it would be nice if we could use the "delayed interrupt" system 1923 * to some advantage 1924 */ 1925 1926 /* -------------------- CHECK BOARD ID/REV: */ 1927 1928 /* 1929 * The board id and revision are stored both in the reset register and 1930 * in the PCI configuration space - the documentation says to check 1931 * each of them. If revp!=NULL we store the revision there 1932 */ 1933 static int check_board_id_and_rev(const char *name, u32 val, int *revp) 1934 { 1935 DPRINTK("%s says board_id=%d, board_rev=%d\n", name, 1936 (int) RESET_GET_BOARD_ID(val), 1937 (int) RESET_GET_BOARD_REV(val)); 1938 if (RESET_GET_BOARD_ID(val) != BOARD_ID_LANAI256) { 1939 printk(KERN_ERR DEV_LABEL ": Found %s board-id %d -- not a " 1940 "Lanai 25.6\n", name, (int) RESET_GET_BOARD_ID(val)); 1941 return -ENODEV; 1942 } 1943 if (revp != NULL) 1944 *revp = RESET_GET_BOARD_REV(val); 1945 return 0; 1946 } 1947 1948 /* -------------------- PCI INITIALIZATION/SHUTDOWN: */ 1949 1950 static int __devinit lanai_pci_start(struct lanai_dev *lanai) 1951 { 1952 struct pci_dev *pci = lanai->pci; 1953 int result; 1954 u16 w; 1955 1956 if (pci_enable_device(pci) != 0) { 1957 printk(KERN_ERR DEV_LABEL "(itf %d): can't enable " 1958 "PCI device", lanai->number); 1959 return -ENXIO; 1960 } 1961 pci_set_master(pci); 1962 if (pci_set_dma_mask(pci, DMA_32BIT_MASK) != 0) { 1963 printk(KERN_WARNING DEV_LABEL 1964 "(itf %d): No suitable DMA available.\n", lanai->number); 1965 return -EBUSY; 1966 } 1967 if (pci_set_consistent_dma_mask(pci, DMA_32BIT_MASK) != 0) { 1968 printk(KERN_WARNING DEV_LABEL 1969 "(itf %d): No suitable DMA available.\n", lanai->number); 1970 return -EBUSY; 1971 } 1972 /* Get the pci revision byte */ 1973 result = pci_read_config_byte(pci, PCI_REVISION_ID, 1974 &lanai->pci_revision); 1975 if (result != PCIBIOS_SUCCESSFUL) { 1976 printk(KERN_ERR DEV_LABEL "(itf %d): can't read " 1977 "PCI_REVISION_ID: %d\n", lanai->number, result); 1978 return -EINVAL; 1979 } 1980 result = pci_read_config_word(pci, PCI_SUBSYSTEM_ID, &w); 1981 if (result != PCIBIOS_SUCCESSFUL) { 1982 printk(KERN_ERR DEV_LABEL "(itf %d): can't read " 1983 "PCI_SUBSYSTEM_ID: %d\n", lanai->number, result); 1984 return -EINVAL; 1985 } 1986 result = check_board_id_and_rev("PCI", w, NULL); 1987 if (result != 0) 1988 return result; 1989 /* Set latency timer to zero as per lanai docs */ 1990 result = pci_write_config_byte(pci, PCI_LATENCY_TIMER, 0); 1991 if (result != PCIBIOS_SUCCESSFUL) { 1992 printk(KERN_ERR DEV_LABEL "(itf %d): can't write " 1993 "PCI_LATENCY_TIMER: %d\n", lanai->number, result); 1994 return -EINVAL; 1995 } 1996 pcistatus_check(lanai, 1); 1997 pcistatus_check(lanai, 0); 1998 return 0; 1999 } 2000 2001 /* -------------------- VPI/VCI ALLOCATION: */ 2002 2003 /* 2004 * We _can_ use VCI==0 for normal traffic, but only for UBR (or we'll 2005 * get a CBRZERO interrupt), and we can use it only if noone is receiving 2006 * AAL0 traffic (since they will use the same queue) - according to the 2007 * docs we shouldn't even use it for AAL0 traffic 2008 */ 2009 static inline int vci0_is_ok(struct lanai_dev *lanai, 2010 const struct atm_qos *qos) 2011 { 2012 if (qos->txtp.traffic_class == ATM_CBR || qos->aal == ATM_AAL0) 2013 return 0; 2014 if (qos->rxtp.traffic_class != ATM_NONE) { 2015 if (lanai->naal0 != 0) 2016 return 0; 2017 lanai->conf2 |= CONFIG2_VCI0_NORMAL; 2018 conf2_write_if_powerup(lanai); 2019 } 2020 return 1; 2021 } 2022 2023 /* return true if vci is currently unused, or if requested qos is 2024 * compatible 2025 */ 2026 static int vci_is_ok(struct lanai_dev *lanai, vci_t vci, 2027 const struct atm_vcc *atmvcc) 2028 { 2029 const struct atm_qos *qos = &atmvcc->qos; 2030 const struct lanai_vcc *lvcc = lanai->vccs[vci]; 2031 if (vci == 0 && !vci0_is_ok(lanai, qos)) 2032 return 0; 2033 if (unlikely(lvcc != NULL)) { 2034 if (qos->rxtp.traffic_class != ATM_NONE && 2035 lvcc->rx.atmvcc != NULL && lvcc->rx.atmvcc != atmvcc) 2036 return 0; 2037 if (qos->txtp.traffic_class != ATM_NONE && 2038 lvcc->tx.atmvcc != NULL && lvcc->tx.atmvcc != atmvcc) 2039 return 0; 2040 if (qos->txtp.traffic_class == ATM_CBR && 2041 lanai->cbrvcc != NULL && lanai->cbrvcc != atmvcc) 2042 return 0; 2043 } 2044 if (qos->aal == ATM_AAL0 && lanai->naal0 == 0 && 2045 qos->rxtp.traffic_class != ATM_NONE) { 2046 const struct lanai_vcc *vci0 = lanai->vccs[0]; 2047 if (vci0 != NULL && vci0->rx.atmvcc != NULL) 2048 return 0; 2049 lanai->conf2 &= ~CONFIG2_VCI0_NORMAL; 2050 conf2_write_if_powerup(lanai); 2051 } 2052 return 1; 2053 } 2054 2055 static int lanai_normalize_ci(struct lanai_dev *lanai, 2056 const struct atm_vcc *atmvcc, short *vpip, vci_t *vcip) 2057 { 2058 switch (*vpip) { 2059 case ATM_VPI_ANY: 2060 *vpip = 0; 2061 /* FALLTHROUGH */ 2062 case 0: 2063 break; 2064 default: 2065 return -EADDRINUSE; 2066 } 2067 switch (*vcip) { 2068 case ATM_VCI_ANY: 2069 for (*vcip = ATM_NOT_RSV_VCI; *vcip < lanai->num_vci; 2070 (*vcip)++) 2071 if (vci_is_ok(lanai, *vcip, atmvcc)) 2072 return 0; 2073 return -EADDRINUSE; 2074 default: 2075 if (*vcip >= lanai->num_vci || *vcip < 0 || 2076 !vci_is_ok(lanai, *vcip, atmvcc)) 2077 return -EADDRINUSE; 2078 } 2079 return 0; 2080 } 2081 2082 /* -------------------- MANAGE CBR: */ 2083 2084 /* 2085 * CBR ICG is stored as a fixed-point number with 4 fractional bits. 2086 * Note that storing a number greater than 2046.0 will result in 2087 * incorrect shaping 2088 */ 2089 #define CBRICG_FRAC_BITS (4) 2090 #define CBRICG_MAX (2046 << CBRICG_FRAC_BITS) 2091 2092 /* 2093 * ICG is related to PCR with the formula PCR = MAXPCR / (ICG + 1) 2094 * where MAXPCR is (according to the docs) 25600000/(54*8), 2095 * which is equal to (3125<<9)/27. 2096 * 2097 * Solving for ICG, we get: 2098 * ICG = MAXPCR/PCR - 1 2099 * ICG = (3125<<9)/(27*PCR) - 1 2100 * ICG = ((3125<<9) - (27*PCR)) / (27*PCR) 2101 * 2102 * The end result is supposed to be a fixed-point number with FRAC_BITS 2103 * bits of a fractional part, so we keep everything in the numerator 2104 * shifted by that much as we compute 2105 * 2106 */ 2107 static int pcr_to_cbricg(const struct atm_qos *qos) 2108 { 2109 int rounddown = 0; /* 1 = Round PCR down, i.e. round ICG _up_ */ 2110 int x, icg, pcr = atm_pcr_goal(&qos->txtp); 2111 if (pcr == 0) /* Use maximum bandwidth */ 2112 return 0; 2113 if (pcr < 0) { 2114 rounddown = 1; 2115 pcr = -pcr; 2116 } 2117 x = pcr * 27; 2118 icg = (3125 << (9 + CBRICG_FRAC_BITS)) - (x << CBRICG_FRAC_BITS); 2119 if (rounddown) 2120 icg += x - 1; 2121 icg /= x; 2122 if (icg > CBRICG_MAX) 2123 icg = CBRICG_MAX; 2124 DPRINTK("pcr_to_cbricg: pcr=%d rounddown=%c icg=%d\n", 2125 pcr, rounddown ? 'Y' : 'N', icg); 2126 return icg; 2127 } 2128 2129 static inline void lanai_cbr_setup(struct lanai_dev *lanai) 2130 { 2131 reg_write(lanai, pcr_to_cbricg(&lanai->cbrvcc->qos), CBR_ICG_Reg); 2132 reg_write(lanai, lanai->cbrvcc->vci, CBR_PTR_Reg); 2133 lanai->conf2 |= CONFIG2_CBR_ENABLE; 2134 conf2_write(lanai); 2135 } 2136 2137 static inline void lanai_cbr_shutdown(struct lanai_dev *lanai) 2138 { 2139 lanai->conf2 &= ~CONFIG2_CBR_ENABLE; 2140 conf2_write(lanai); 2141 } 2142 2143 /* -------------------- OPERATIONS: */ 2144 2145 /* setup a newly detected device */ 2146 static int __devinit lanai_dev_open(struct atm_dev *atmdev) 2147 { 2148 struct lanai_dev *lanai = (struct lanai_dev *) atmdev->dev_data; 2149 unsigned long raw_base; 2150 int result; 2151 2152 DPRINTK("In lanai_dev_open()\n"); 2153 /* Basic device fields */ 2154 lanai->number = atmdev->number; 2155 lanai->num_vci = NUM_VCI; 2156 bitmap_zero(lanai->backlog_vccs, NUM_VCI); 2157 bitmap_zero(lanai->transmit_ready, NUM_VCI); 2158 lanai->naal0 = 0; 2159 #ifdef USE_POWERDOWN 2160 lanai->nbound = 0; 2161 #endif 2162 lanai->cbrvcc = NULL; 2163 memset(&lanai->stats, 0, sizeof lanai->stats); 2164 spin_lock_init(&lanai->endtxlock); 2165 spin_lock_init(&lanai->servicelock); 2166 atmdev->ci_range.vpi_bits = 0; 2167 atmdev->ci_range.vci_bits = 0; 2168 while (1 << atmdev->ci_range.vci_bits < lanai->num_vci) 2169 atmdev->ci_range.vci_bits++; 2170 atmdev->link_rate = ATM_25_PCR; 2171 2172 /* 3.2: PCI initialization */ 2173 if ((result = lanai_pci_start(lanai)) != 0) 2174 goto error; 2175 raw_base = lanai->pci->resource[0].start; 2176 lanai->base = (bus_addr_t) ioremap(raw_base, LANAI_MAPPING_SIZE); 2177 if (lanai->base == NULL) { 2178 printk(KERN_ERR DEV_LABEL ": couldn't remap I/O space\n"); 2179 goto error_pci; 2180 } 2181 /* 3.3: Reset lanai and PHY */ 2182 reset_board(lanai); 2183 lanai->conf1 = reg_read(lanai, Config1_Reg); 2184 lanai->conf1 &= ~(CONFIG1_GPOUT1 | CONFIG1_POWERDOWN | 2185 CONFIG1_MASK_LEDMODE); 2186 lanai->conf1 |= CONFIG1_SET_LEDMODE(LEDMODE_NOT_SOOL); 2187 reg_write(lanai, lanai->conf1 | CONFIG1_GPOUT1, Config1_Reg); 2188 udelay(1000); 2189 conf1_write(lanai); 2190 2191 /* 2192 * 3.4: Turn on endian mode for big-endian hardware 2193 * We don't actually want to do this - the actual bit fields 2194 * in the endian register are not documented anywhere. 2195 * Instead we do the bit-flipping ourselves on big-endian 2196 * hardware. 2197 * 2198 * 3.5: get the board ID/rev by reading the reset register 2199 */ 2200 result = check_board_id_and_rev("register", 2201 reg_read(lanai, Reset_Reg), &lanai->board_rev); 2202 if (result != 0) 2203 goto error_unmap; 2204 2205 /* 3.6: read EEPROM */ 2206 if ((result = eeprom_read(lanai)) != 0) 2207 goto error_unmap; 2208 if ((result = eeprom_validate(lanai)) != 0) 2209 goto error_unmap; 2210 2211 /* 3.7: re-reset PHY, do loopback tests, setup PHY */ 2212 reg_write(lanai, lanai->conf1 | CONFIG1_GPOUT1, Config1_Reg); 2213 udelay(1000); 2214 conf1_write(lanai); 2215 /* TODO - loopback tests */ 2216 lanai->conf1 |= (CONFIG1_GPOUT2 | CONFIG1_GPOUT3 | CONFIG1_DMA_ENABLE); 2217 conf1_write(lanai); 2218 2219 /* 3.8/3.9: test and initialize card SRAM */ 2220 if ((result = sram_test_and_clear(lanai)) != 0) 2221 goto error_unmap; 2222 2223 /* 3.10: initialize lanai registers */ 2224 lanai->conf1 |= CONFIG1_DMA_ENABLE; 2225 conf1_write(lanai); 2226 if ((result = service_buffer_allocate(lanai)) != 0) 2227 goto error_unmap; 2228 if ((result = vcc_table_allocate(lanai)) != 0) 2229 goto error_service; 2230 lanai->conf2 = (lanai->num_vci >= 512 ? CONFIG2_HOWMANY : 0) | 2231 CONFIG2_HEC_DROP | /* ??? */ CONFIG2_PTI7_MODE; 2232 conf2_write(lanai); 2233 reg_write(lanai, TX_FIFO_DEPTH, TxDepth_Reg); 2234 reg_write(lanai, 0, CBR_ICG_Reg); /* CBR defaults to no limit */ 2235 if ((result = request_irq(lanai->pci->irq, lanai_int, IRQF_SHARED, 2236 DEV_LABEL, lanai)) != 0) { 2237 printk(KERN_ERR DEV_LABEL ": can't allocate interrupt\n"); 2238 goto error_vcctable; 2239 } 2240 mb(); /* Make sure that all that made it */ 2241 intr_enable(lanai, INT_ALL & ~(INT_PING | INT_WAKE)); 2242 /* 3.11: initialize loop mode (i.e. turn looping off) */ 2243 lanai->conf1 = (lanai->conf1 & ~CONFIG1_MASK_LOOPMODE) | 2244 CONFIG1_SET_LOOPMODE(LOOPMODE_NORMAL) | 2245 CONFIG1_GPOUT2 | CONFIG1_GPOUT3; 2246 conf1_write(lanai); 2247 lanai->status = reg_read(lanai, Status_Reg); 2248 /* We're now done initializing this card */ 2249 #ifdef USE_POWERDOWN 2250 lanai->conf1 |= CONFIG1_POWERDOWN; 2251 conf1_write(lanai); 2252 #endif 2253 memcpy(atmdev->esi, eeprom_mac(lanai), ESI_LEN); 2254 lanai_timed_poll_start(lanai); 2255 printk(KERN_NOTICE DEV_LABEL "(itf %d): rev.%d, base=0x%lx, irq=%u " 2256 "(%02X-%02X-%02X-%02X-%02X-%02X)\n", lanai->number, 2257 (int) lanai->pci_revision, (unsigned long) lanai->base, 2258 lanai->pci->irq, 2259 atmdev->esi[0], atmdev->esi[1], atmdev->esi[2], 2260 atmdev->esi[3], atmdev->esi[4], atmdev->esi[5]); 2261 printk(KERN_NOTICE DEV_LABEL "(itf %d): LANAI%s, serialno=%u(0x%X), " 2262 "board_rev=%d\n", lanai->number, 2263 lanai->type==lanai2 ? "2" : "HB", (unsigned int) lanai->serialno, 2264 (unsigned int) lanai->serialno, lanai->board_rev); 2265 return 0; 2266 2267 error_vcctable: 2268 vcc_table_deallocate(lanai); 2269 error_service: 2270 service_buffer_deallocate(lanai); 2271 error_unmap: 2272 reset_board(lanai); 2273 #ifdef USE_POWERDOWN 2274 lanai->conf1 = reg_read(lanai, Config1_Reg) | CONFIG1_POWERDOWN; 2275 conf1_write(lanai); 2276 #endif 2277 iounmap(lanai->base); 2278 error_pci: 2279 pci_disable_device(lanai->pci); 2280 error: 2281 return result; 2282 } 2283 2284 /* called when device is being shutdown, and all vcc's are gone - higher 2285 * levels will deallocate the atm device for us 2286 */ 2287 static void lanai_dev_close(struct atm_dev *atmdev) 2288 { 2289 struct lanai_dev *lanai = (struct lanai_dev *) atmdev->dev_data; 2290 printk(KERN_INFO DEV_LABEL "(itf %d): shutting down interface\n", 2291 lanai->number); 2292 lanai_timed_poll_stop(lanai); 2293 #ifdef USE_POWERDOWN 2294 lanai->conf1 = reg_read(lanai, Config1_Reg) & ~CONFIG1_POWERDOWN; 2295 conf1_write(lanai); 2296 #endif 2297 intr_disable(lanai, INT_ALL); 2298 free_irq(lanai->pci->irq, lanai); 2299 reset_board(lanai); 2300 #ifdef USE_POWERDOWN 2301 lanai->conf1 |= CONFIG1_POWERDOWN; 2302 conf1_write(lanai); 2303 #endif 2304 pci_disable_device(lanai->pci); 2305 vcc_table_deallocate(lanai); 2306 service_buffer_deallocate(lanai); 2307 iounmap(lanai->base); 2308 kfree(lanai); 2309 } 2310 2311 /* close a vcc */ 2312 static void lanai_close(struct atm_vcc *atmvcc) 2313 { 2314 struct lanai_vcc *lvcc = (struct lanai_vcc *) atmvcc->dev_data; 2315 struct lanai_dev *lanai = (struct lanai_dev *) atmvcc->dev->dev_data; 2316 if (lvcc == NULL) 2317 return; 2318 clear_bit(ATM_VF_READY, &atmvcc->flags); 2319 clear_bit(ATM_VF_PARTIAL, &atmvcc->flags); 2320 if (lvcc->rx.atmvcc == atmvcc) { 2321 lanai_shutdown_rx_vci(lvcc); 2322 if (atmvcc->qos.aal == ATM_AAL0) { 2323 if (--lanai->naal0 <= 0) 2324 aal0_buffer_free(lanai); 2325 } else 2326 lanai_buf_deallocate(&lvcc->rx.buf, lanai->pci); 2327 lvcc->rx.atmvcc = NULL; 2328 } 2329 if (lvcc->tx.atmvcc == atmvcc) { 2330 if (atmvcc == lanai->cbrvcc) { 2331 if (lvcc->vbase != NULL) 2332 lanai_cbr_shutdown(lanai); 2333 lanai->cbrvcc = NULL; 2334 } 2335 lanai_shutdown_tx_vci(lanai, lvcc); 2336 lanai_buf_deallocate(&lvcc->tx.buf, lanai->pci); 2337 lvcc->tx.atmvcc = NULL; 2338 } 2339 if (--lvcc->nref == 0) { 2340 host_vcc_unbind(lanai, lvcc); 2341 kfree(lvcc); 2342 } 2343 atmvcc->dev_data = NULL; 2344 clear_bit(ATM_VF_ADDR, &atmvcc->flags); 2345 } 2346 2347 /* open a vcc on the card to vpi/vci */ 2348 static int lanai_open(struct atm_vcc *atmvcc) 2349 { 2350 struct lanai_dev *lanai; 2351 struct lanai_vcc *lvcc; 2352 int result = 0; 2353 int vci = atmvcc->vci; 2354 short vpi = atmvcc->vpi; 2355 /* we don't support partial open - it's not really useful anyway */ 2356 if ((test_bit(ATM_VF_PARTIAL, &atmvcc->flags)) || 2357 (vpi == ATM_VPI_UNSPEC) || (vci == ATM_VCI_UNSPEC)) 2358 return -EINVAL; 2359 lanai = (struct lanai_dev *) atmvcc->dev->dev_data; 2360 result = lanai_normalize_ci(lanai, atmvcc, &vpi, &vci); 2361 if (unlikely(result != 0)) 2362 goto out; 2363 set_bit(ATM_VF_ADDR, &atmvcc->flags); 2364 if (atmvcc->qos.aal != ATM_AAL0 && atmvcc->qos.aal != ATM_AAL5) 2365 return -EINVAL; 2366 DPRINTK(DEV_LABEL "(itf %d): open %d.%d\n", lanai->number, 2367 (int) vpi, vci); 2368 lvcc = lanai->vccs[vci]; 2369 if (lvcc == NULL) { 2370 lvcc = new_lanai_vcc(); 2371 if (unlikely(lvcc == NULL)) 2372 return -ENOMEM; 2373 atmvcc->dev_data = lvcc; 2374 } 2375 lvcc->nref++; 2376 if (atmvcc->qos.rxtp.traffic_class != ATM_NONE) { 2377 APRINTK(lvcc->rx.atmvcc == NULL, "rx.atmvcc!=NULL, vci=%d\n", 2378 vci); 2379 if (atmvcc->qos.aal == ATM_AAL0) { 2380 if (lanai->naal0 == 0) 2381 result = aal0_buffer_allocate(lanai); 2382 } else 2383 result = lanai_setup_rx_vci_aal5( 2384 lanai, lvcc, &atmvcc->qos); 2385 if (unlikely(result != 0)) 2386 goto out_free; 2387 lvcc->rx.atmvcc = atmvcc; 2388 lvcc->stats.rx_nomem = 0; 2389 lvcc->stats.x.aal5.rx_badlen = 0; 2390 lvcc->stats.x.aal5.service_trash = 0; 2391 lvcc->stats.x.aal5.service_stream = 0; 2392 lvcc->stats.x.aal5.service_rxcrc = 0; 2393 if (atmvcc->qos.aal == ATM_AAL0) 2394 lanai->naal0++; 2395 } 2396 if (atmvcc->qos.txtp.traffic_class != ATM_NONE) { 2397 APRINTK(lvcc->tx.atmvcc == NULL, "tx.atmvcc!=NULL, vci=%d\n", 2398 vci); 2399 result = lanai_setup_tx_vci(lanai, lvcc, &atmvcc->qos); 2400 if (unlikely(result != 0)) 2401 goto out_free; 2402 lvcc->tx.atmvcc = atmvcc; 2403 if (atmvcc->qos.txtp.traffic_class == ATM_CBR) { 2404 APRINTK(lanai->cbrvcc == NULL, 2405 "cbrvcc!=NULL, vci=%d\n", vci); 2406 lanai->cbrvcc = atmvcc; 2407 } 2408 } 2409 host_vcc_bind(lanai, lvcc, vci); 2410 /* 2411 * Make sure everything made it to RAM before we tell the card about 2412 * the VCC 2413 */ 2414 wmb(); 2415 if (atmvcc == lvcc->rx.atmvcc) 2416 host_vcc_start_rx(lvcc); 2417 if (atmvcc == lvcc->tx.atmvcc) { 2418 host_vcc_start_tx(lvcc); 2419 if (lanai->cbrvcc == atmvcc) 2420 lanai_cbr_setup(lanai); 2421 } 2422 set_bit(ATM_VF_READY, &atmvcc->flags); 2423 return 0; 2424 out_free: 2425 lanai_close(atmvcc); 2426 out: 2427 return result; 2428 } 2429 2430 static int lanai_send(struct atm_vcc *atmvcc, struct sk_buff *skb) 2431 { 2432 struct lanai_vcc *lvcc = (struct lanai_vcc *) atmvcc->dev_data; 2433 struct lanai_dev *lanai = (struct lanai_dev *) atmvcc->dev->dev_data; 2434 unsigned long flags; 2435 if (unlikely(lvcc == NULL || lvcc->vbase == NULL || 2436 lvcc->tx.atmvcc != atmvcc)) 2437 goto einval; 2438 #ifdef DEBUG 2439 if (unlikely(skb == NULL)) { 2440 DPRINTK("lanai_send: skb==NULL for vci=%d\n", atmvcc->vci); 2441 goto einval; 2442 } 2443 if (unlikely(lanai == NULL)) { 2444 DPRINTK("lanai_send: lanai==NULL for vci=%d\n", atmvcc->vci); 2445 goto einval; 2446 } 2447 #endif 2448 ATM_SKB(skb)->vcc = atmvcc; 2449 switch (atmvcc->qos.aal) { 2450 case ATM_AAL5: 2451 read_lock_irqsave(&vcc_sklist_lock, flags); 2452 vcc_tx_aal5(lanai, lvcc, skb); 2453 read_unlock_irqrestore(&vcc_sklist_lock, flags); 2454 return 0; 2455 case ATM_AAL0: 2456 if (unlikely(skb->len != ATM_CELL_SIZE-1)) 2457 goto einval; 2458 /* NOTE - this next line is technically invalid - we haven't unshared skb */ 2459 cpu_to_be32s((u32 *) skb->data); 2460 read_lock_irqsave(&vcc_sklist_lock, flags); 2461 vcc_tx_aal0(lanai, lvcc, skb); 2462 read_unlock_irqrestore(&vcc_sklist_lock, flags); 2463 return 0; 2464 } 2465 DPRINTK("lanai_send: bad aal=%d on vci=%d\n", (int) atmvcc->qos.aal, 2466 atmvcc->vci); 2467 einval: 2468 lanai_free_skb(atmvcc, skb); 2469 return -EINVAL; 2470 } 2471 2472 static int lanai_change_qos(struct atm_vcc *atmvcc, 2473 /*const*/ struct atm_qos *qos, int flags) 2474 { 2475 return -EBUSY; /* TODO: need to write this */ 2476 } 2477 2478 #ifndef CONFIG_PROC_FS 2479 #define lanai_proc_read NULL 2480 #else 2481 static int lanai_proc_read(struct atm_dev *atmdev, loff_t *pos, char *page) 2482 { 2483 struct lanai_dev *lanai = (struct lanai_dev *) atmdev->dev_data; 2484 loff_t left = *pos; 2485 struct lanai_vcc *lvcc; 2486 if (left-- == 0) 2487 return sprintf(page, DEV_LABEL "(itf %d): chip=LANAI%s, " 2488 "serial=%u, magic=0x%08X, num_vci=%d\n", 2489 atmdev->number, lanai->type==lanai2 ? "2" : "HB", 2490 (unsigned int) lanai->serialno, 2491 (unsigned int) lanai->magicno, lanai->num_vci); 2492 if (left-- == 0) 2493 return sprintf(page, "revision: board=%d, pci_if=%d\n", 2494 lanai->board_rev, (int) lanai->pci_revision); 2495 if (left-- == 0) 2496 return sprintf(page, "EEPROM ESI: " 2497 "%02X:%02X:%02X:%02X:%02X:%02X\n", 2498 lanai->eeprom[EEPROM_MAC + 0], 2499 lanai->eeprom[EEPROM_MAC + 1], 2500 lanai->eeprom[EEPROM_MAC + 2], 2501 lanai->eeprom[EEPROM_MAC + 3], 2502 lanai->eeprom[EEPROM_MAC + 4], 2503 lanai->eeprom[EEPROM_MAC + 5]); 2504 if (left-- == 0) 2505 return sprintf(page, "status: SOOL=%d, LOCD=%d, LED=%d, " 2506 "GPIN=%d\n", (lanai->status & STATUS_SOOL) ? 1 : 0, 2507 (lanai->status & STATUS_LOCD) ? 1 : 0, 2508 (lanai->status & STATUS_LED) ? 1 : 0, 2509 (lanai->status & STATUS_GPIN) ? 1 : 0); 2510 if (left-- == 0) 2511 return sprintf(page, "global buffer sizes: service=%Zu, " 2512 "aal0_rx=%Zu\n", lanai_buf_size(&lanai->service), 2513 lanai->naal0 ? lanai_buf_size(&lanai->aal0buf) : 0); 2514 if (left-- == 0) { 2515 get_statistics(lanai); 2516 return sprintf(page, "cells in error: overflow=%u, " 2517 "closed_vci=%u, bad_HEC=%u, rx_fifo=%u\n", 2518 lanai->stats.ovfl_trash, lanai->stats.vci_trash, 2519 lanai->stats.hec_err, lanai->stats.atm_ovfl); 2520 } 2521 if (left-- == 0) 2522 return sprintf(page, "PCI errors: parity_detect=%u, " 2523 "master_abort=%u, master_target_abort=%u,\n", 2524 lanai->stats.pcierr_parity_detect, 2525 lanai->stats.pcierr_serr_set, 2526 lanai->stats.pcierr_m_target_abort); 2527 if (left-- == 0) 2528 return sprintf(page, " slave_target_abort=%u, " 2529 "master_parity=%u\n", lanai->stats.pcierr_s_target_abort, 2530 lanai->stats.pcierr_master_parity); 2531 if (left-- == 0) 2532 return sprintf(page, " no_tx=%u, " 2533 "no_rx=%u, bad_rx_aal=%u\n", lanai->stats.service_norx, 2534 lanai->stats.service_notx, 2535 lanai->stats.service_rxnotaal5); 2536 if (left-- == 0) 2537 return sprintf(page, "resets: dma=%u, card=%u\n", 2538 lanai->stats.dma_reenable, lanai->stats.card_reset); 2539 /* At this point, "left" should be the VCI we're looking for */ 2540 read_lock(&vcc_sklist_lock); 2541 for (; ; left++) { 2542 if (left >= NUM_VCI) { 2543 left = 0; 2544 goto out; 2545 } 2546 if ((lvcc = lanai->vccs[left]) != NULL) 2547 break; 2548 (*pos)++; 2549 } 2550 /* Note that we re-use "left" here since we're done with it */ 2551 left = sprintf(page, "VCI %4d: nref=%d, rx_nomem=%u", (vci_t) left, 2552 lvcc->nref, lvcc->stats.rx_nomem); 2553 if (lvcc->rx.atmvcc != NULL) { 2554 left += sprintf(&page[left], ",\n rx_AAL=%d", 2555 lvcc->rx.atmvcc->qos.aal == ATM_AAL5 ? 5 : 0); 2556 if (lvcc->rx.atmvcc->qos.aal == ATM_AAL5) 2557 left += sprintf(&page[left], ", rx_buf_size=%Zu, " 2558 "rx_bad_len=%u,\n rx_service_trash=%u, " 2559 "rx_service_stream=%u, rx_bad_crc=%u", 2560 lanai_buf_size(&lvcc->rx.buf), 2561 lvcc->stats.x.aal5.rx_badlen, 2562 lvcc->stats.x.aal5.service_trash, 2563 lvcc->stats.x.aal5.service_stream, 2564 lvcc->stats.x.aal5.service_rxcrc); 2565 } 2566 if (lvcc->tx.atmvcc != NULL) 2567 left += sprintf(&page[left], ",\n tx_AAL=%d, " 2568 "tx_buf_size=%Zu, tx_qos=%cBR, tx_backlogged=%c", 2569 lvcc->tx.atmvcc->qos.aal == ATM_AAL5 ? 5 : 0, 2570 lanai_buf_size(&lvcc->tx.buf), 2571 lvcc->tx.atmvcc == lanai->cbrvcc ? 'C' : 'U', 2572 vcc_is_backlogged(lvcc) ? 'Y' : 'N'); 2573 page[left++] = '\n'; 2574 page[left] = '\0'; 2575 out: 2576 read_unlock(&vcc_sklist_lock); 2577 return left; 2578 } 2579 #endif /* CONFIG_PROC_FS */ 2580 2581 /* -------------------- HOOKS: */ 2582 2583 static const struct atmdev_ops ops = { 2584 .dev_close = lanai_dev_close, 2585 .open = lanai_open, 2586 .close = lanai_close, 2587 .getsockopt = NULL, 2588 .setsockopt = NULL, 2589 .send = lanai_send, 2590 .phy_put = NULL, 2591 .phy_get = NULL, 2592 .change_qos = lanai_change_qos, 2593 .proc_read = lanai_proc_read, 2594 .owner = THIS_MODULE 2595 }; 2596 2597 /* initialize one probed card */ 2598 static int __devinit lanai_init_one(struct pci_dev *pci, 2599 const struct pci_device_id *ident) 2600 { 2601 struct lanai_dev *lanai; 2602 struct atm_dev *atmdev; 2603 int result; 2604 2605 lanai = kmalloc(sizeof(*lanai), GFP_KERNEL); 2606 if (lanai == NULL) { 2607 printk(KERN_ERR DEV_LABEL 2608 ": couldn't allocate dev_data structure!\n"); 2609 return -ENOMEM; 2610 } 2611 2612 atmdev = atm_dev_register(DEV_LABEL, &ops, -1, NULL); 2613 if (atmdev == NULL) { 2614 printk(KERN_ERR DEV_LABEL 2615 ": couldn't register atm device!\n"); 2616 kfree(lanai); 2617 return -EBUSY; 2618 } 2619 2620 atmdev->dev_data = lanai; 2621 lanai->pci = pci; 2622 lanai->type = (enum lanai_type) ident->device; 2623 2624 result = lanai_dev_open(atmdev); 2625 if (result != 0) { 2626 DPRINTK("lanai_start() failed, err=%d\n", -result); 2627 atm_dev_deregister(atmdev); 2628 kfree(lanai); 2629 } 2630 return result; 2631 } 2632 2633 static struct pci_device_id lanai_pci_tbl[] = { 2634 { 2635 PCI_VENDOR_ID_EF, PCI_VENDOR_ID_EF_ATM_LANAI2, 2636 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 2637 }, 2638 { 2639 PCI_VENDOR_ID_EF, PCI_VENDOR_ID_EF_ATM_LANAIHB, 2640 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 2641 }, 2642 { 0, } /* terminal entry */ 2643 }; 2644 MODULE_DEVICE_TABLE(pci, lanai_pci_tbl); 2645 2646 static struct pci_driver lanai_driver = { 2647 .name = DEV_LABEL, 2648 .id_table = lanai_pci_tbl, 2649 .probe = lanai_init_one, 2650 }; 2651 2652 static int __init lanai_module_init(void) 2653 { 2654 int x; 2655 2656 x = pci_register_driver(&lanai_driver); 2657 if (x != 0) 2658 printk(KERN_ERR DEV_LABEL ": no adapter found\n"); 2659 return x; 2660 } 2661 2662 static void __exit lanai_module_exit(void) 2663 { 2664 /* We'll only get called when all the interfaces are already 2665 * gone, so there isn't much to do 2666 */ 2667 DPRINTK("cleanup_module()\n"); 2668 pci_unregister_driver(&lanai_driver); 2669 } 2670 2671 module_init(lanai_module_init); 2672 module_exit(lanai_module_exit); 2673 2674 MODULE_AUTHOR("Mitchell Blank Jr <mitch@sfgoth.com>"); 2675 MODULE_DESCRIPTION("Efficient Networks Speedstream 3010 driver"); 2676 MODULE_LICENSE("GPL"); 2677