xref: /openbmc/linux/drivers/ata/sata_sil.c (revision e868d61272caa648214046a096e5a6bfc068dc8c)
1 /*
2  *  sata_sil.c - Silicon Image SATA
3  *
4  *  Maintained by:  Jeff Garzik <jgarzik@pobox.com>
5  *  		    Please ALWAYS copy linux-ide@vger.kernel.org
6  *		    on emails.
7  *
8  *  Copyright 2003-2005 Red Hat, Inc.
9  *  Copyright 2003 Benjamin Herrenschmidt
10  *
11  *
12  *  This program is free software; you can redistribute it and/or modify
13  *  it under the terms of the GNU General Public License as published by
14  *  the Free Software Foundation; either version 2, or (at your option)
15  *  any later version.
16  *
17  *  This program is distributed in the hope that it will be useful,
18  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
19  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
20  *  GNU General Public License for more details.
21  *
22  *  You should have received a copy of the GNU General Public License
23  *  along with this program; see the file COPYING.  If not, write to
24  *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
25  *
26  *
27  *  libata documentation is available via 'make {ps|pdf}docs',
28  *  as Documentation/DocBook/libata.*
29  *
30  *  Documentation for SiI 3112:
31  *  http://gkernel.sourceforge.net/specs/sii/3112A_SiI-DS-0095-B2.pdf.bz2
32  *
33  *  Other errata and documentation available under NDA.
34  *
35  */
36 
37 #include <linux/kernel.h>
38 #include <linux/module.h>
39 #include <linux/pci.h>
40 #include <linux/init.h>
41 #include <linux/blkdev.h>
42 #include <linux/delay.h>
43 #include <linux/interrupt.h>
44 #include <linux/device.h>
45 #include <scsi/scsi_host.h>
46 #include <linux/libata.h>
47 
48 #define DRV_NAME	"sata_sil"
49 #define DRV_VERSION	"2.2"
50 
51 enum {
52 	SIL_MMIO_BAR		= 5,
53 
54 	/*
55 	 * host flags
56 	 */
57 	SIL_FLAG_NO_SATA_IRQ	= (1 << 28),
58 	SIL_FLAG_RERR_ON_DMA_ACT = (1 << 29),
59 	SIL_FLAG_MOD15WRITE	= (1 << 30),
60 
61 	SIL_DFL_PORT_FLAGS	= ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
62 				  ATA_FLAG_MMIO | ATA_FLAG_HRST_TO_RESUME,
63 
64 	/*
65 	 * Controller IDs
66 	 */
67 	sil_3112		= 0,
68 	sil_3112_no_sata_irq	= 1,
69 	sil_3512		= 2,
70 	sil_3114		= 3,
71 
72 	/*
73 	 * Register offsets
74 	 */
75 	SIL_SYSCFG		= 0x48,
76 
77 	/*
78 	 * Register bits
79 	 */
80 	/* SYSCFG */
81 	SIL_MASK_IDE0_INT	= (1 << 22),
82 	SIL_MASK_IDE1_INT	= (1 << 23),
83 	SIL_MASK_IDE2_INT	= (1 << 24),
84 	SIL_MASK_IDE3_INT	= (1 << 25),
85 	SIL_MASK_2PORT		= SIL_MASK_IDE0_INT | SIL_MASK_IDE1_INT,
86 	SIL_MASK_4PORT		= SIL_MASK_2PORT |
87 				  SIL_MASK_IDE2_INT | SIL_MASK_IDE3_INT,
88 
89 	/* BMDMA/BMDMA2 */
90 	SIL_INTR_STEERING	= (1 << 1),
91 
92 	SIL_DMA_ENABLE		= (1 << 0),  /* DMA run switch */
93 	SIL_DMA_RDWR		= (1 << 3),  /* DMA Rd-Wr */
94 	SIL_DMA_SATA_IRQ	= (1 << 4),  /* OR of all SATA IRQs */
95 	SIL_DMA_ACTIVE		= (1 << 16), /* DMA running */
96 	SIL_DMA_ERROR		= (1 << 17), /* PCI bus error */
97 	SIL_DMA_COMPLETE	= (1 << 18), /* cmd complete / IRQ pending */
98 	SIL_DMA_N_SATA_IRQ	= (1 << 6),  /* SATA_IRQ for the next channel */
99 	SIL_DMA_N_ACTIVE	= (1 << 24), /* ACTIVE for the next channel */
100 	SIL_DMA_N_ERROR		= (1 << 25), /* ERROR for the next channel */
101 	SIL_DMA_N_COMPLETE	= (1 << 26), /* COMPLETE for the next channel */
102 
103 	/* SIEN */
104 	SIL_SIEN_N		= (1 << 16), /* triggered by SError.N */
105 
106 	/*
107 	 * Others
108 	 */
109 	SIL_QUIRK_MOD15WRITE	= (1 << 0),
110 	SIL_QUIRK_UDMA5MAX	= (1 << 1),
111 };
112 
113 static int sil_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
114 #ifdef CONFIG_PM
115 static int sil_pci_device_resume(struct pci_dev *pdev);
116 #endif
117 static void sil_dev_config(struct ata_device *dev);
118 static u32 sil_scr_read (struct ata_port *ap, unsigned int sc_reg);
119 static void sil_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
120 static int sil_set_mode (struct ata_port *ap, struct ata_device **r_failed);
121 static void sil_freeze(struct ata_port *ap);
122 static void sil_thaw(struct ata_port *ap);
123 
124 
125 static const struct pci_device_id sil_pci_tbl[] = {
126 	{ PCI_VDEVICE(CMD, 0x3112), sil_3112 },
127 	{ PCI_VDEVICE(CMD, 0x0240), sil_3112 },
128 	{ PCI_VDEVICE(CMD, 0x3512), sil_3512 },
129 	{ PCI_VDEVICE(CMD, 0x3114), sil_3114 },
130 	{ PCI_VDEVICE(ATI, 0x436e), sil_3112 },
131 	{ PCI_VDEVICE(ATI, 0x4379), sil_3112_no_sata_irq },
132 	{ PCI_VDEVICE(ATI, 0x437a), sil_3112_no_sata_irq },
133 
134 	{ }	/* terminate list */
135 };
136 
137 
138 /* TODO firmware versions should be added - eric */
139 static const struct sil_drivelist {
140 	const char * product;
141 	unsigned int quirk;
142 } sil_blacklist [] = {
143 	{ "ST320012AS",		SIL_QUIRK_MOD15WRITE },
144 	{ "ST330013AS",		SIL_QUIRK_MOD15WRITE },
145 	{ "ST340017AS",		SIL_QUIRK_MOD15WRITE },
146 	{ "ST360015AS",		SIL_QUIRK_MOD15WRITE },
147 	{ "ST380023AS",		SIL_QUIRK_MOD15WRITE },
148 	{ "ST3120023AS",	SIL_QUIRK_MOD15WRITE },
149 	{ "ST340014ASL",	SIL_QUIRK_MOD15WRITE },
150 	{ "ST360014ASL",	SIL_QUIRK_MOD15WRITE },
151 	{ "ST380011ASL",	SIL_QUIRK_MOD15WRITE },
152 	{ "ST3120022ASL",	SIL_QUIRK_MOD15WRITE },
153 	{ "ST3160021ASL",	SIL_QUIRK_MOD15WRITE },
154 	{ "Maxtor 4D060H3",	SIL_QUIRK_UDMA5MAX },
155 	{ }
156 };
157 
158 static struct pci_driver sil_pci_driver = {
159 	.name			= DRV_NAME,
160 	.id_table		= sil_pci_tbl,
161 	.probe			= sil_init_one,
162 	.remove			= ata_pci_remove_one,
163 #ifdef CONFIG_PM
164 	.suspend		= ata_pci_device_suspend,
165 	.resume			= sil_pci_device_resume,
166 #endif
167 };
168 
169 static struct scsi_host_template sil_sht = {
170 	.module			= THIS_MODULE,
171 	.name			= DRV_NAME,
172 	.ioctl			= ata_scsi_ioctl,
173 	.queuecommand		= ata_scsi_queuecmd,
174 	.can_queue		= ATA_DEF_QUEUE,
175 	.this_id		= ATA_SHT_THIS_ID,
176 	.sg_tablesize		= LIBATA_MAX_PRD,
177 	.cmd_per_lun		= ATA_SHT_CMD_PER_LUN,
178 	.emulated		= ATA_SHT_EMULATED,
179 	.use_clustering		= ATA_SHT_USE_CLUSTERING,
180 	.proc_name		= DRV_NAME,
181 	.dma_boundary		= ATA_DMA_BOUNDARY,
182 	.slave_configure	= ata_scsi_slave_config,
183 	.slave_destroy		= ata_scsi_slave_destroy,
184 	.bios_param		= ata_std_bios_param,
185 };
186 
187 static const struct ata_port_operations sil_ops = {
188 	.port_disable		= ata_port_disable,
189 	.dev_config		= sil_dev_config,
190 	.tf_load		= ata_tf_load,
191 	.tf_read		= ata_tf_read,
192 	.check_status		= ata_check_status,
193 	.exec_command		= ata_exec_command,
194 	.dev_select		= ata_std_dev_select,
195 	.set_mode		= sil_set_mode,
196 	.bmdma_setup            = ata_bmdma_setup,
197 	.bmdma_start            = ata_bmdma_start,
198 	.bmdma_stop		= ata_bmdma_stop,
199 	.bmdma_status		= ata_bmdma_status,
200 	.qc_prep		= ata_qc_prep,
201 	.qc_issue		= ata_qc_issue_prot,
202 	.data_xfer		= ata_data_xfer,
203 	.freeze			= sil_freeze,
204 	.thaw			= sil_thaw,
205 	.error_handler		= ata_bmdma_error_handler,
206 	.post_internal_cmd	= ata_bmdma_post_internal_cmd,
207 	.irq_clear		= ata_bmdma_irq_clear,
208 	.irq_on			= ata_irq_on,
209 	.irq_ack		= ata_irq_ack,
210 	.scr_read		= sil_scr_read,
211 	.scr_write		= sil_scr_write,
212 	.port_start		= ata_port_start,
213 };
214 
215 static const struct ata_port_info sil_port_info[] = {
216 	/* sil_3112 */
217 	{
218 		.flags		= SIL_DFL_PORT_FLAGS | SIL_FLAG_MOD15WRITE,
219 		.pio_mask	= 0x1f,			/* pio0-4 */
220 		.mwdma_mask	= 0x07,			/* mwdma0-2 */
221 		.udma_mask	= 0x3f,			/* udma0-5 */
222 		.port_ops	= &sil_ops,
223 	},
224 	/* sil_3112_no_sata_irq */
225 	{
226 		.flags		= SIL_DFL_PORT_FLAGS | SIL_FLAG_MOD15WRITE |
227 				  SIL_FLAG_NO_SATA_IRQ,
228 		.pio_mask	= 0x1f,			/* pio0-4 */
229 		.mwdma_mask	= 0x07,			/* mwdma0-2 */
230 		.udma_mask	= 0x3f,			/* udma0-5 */
231 		.port_ops	= &sil_ops,
232 	},
233 	/* sil_3512 */
234 	{
235 		.flags		= SIL_DFL_PORT_FLAGS | SIL_FLAG_RERR_ON_DMA_ACT,
236 		.pio_mask	= 0x1f,			/* pio0-4 */
237 		.mwdma_mask	= 0x07,			/* mwdma0-2 */
238 		.udma_mask	= 0x3f,			/* udma0-5 */
239 		.port_ops	= &sil_ops,
240 	},
241 	/* sil_3114 */
242 	{
243 		.flags		= SIL_DFL_PORT_FLAGS | SIL_FLAG_RERR_ON_DMA_ACT,
244 		.pio_mask	= 0x1f,			/* pio0-4 */
245 		.mwdma_mask	= 0x07,			/* mwdma0-2 */
246 		.udma_mask	= 0x3f,			/* udma0-5 */
247 		.port_ops	= &sil_ops,
248 	},
249 };
250 
251 /* per-port register offsets */
252 /* TODO: we can probably calculate rather than use a table */
253 static const struct {
254 	unsigned long tf;	/* ATA taskfile register block */
255 	unsigned long ctl;	/* ATA control/altstatus register block */
256 	unsigned long bmdma;	/* DMA register block */
257 	unsigned long bmdma2;	/* DMA register block #2 */
258 	unsigned long fifo_cfg;	/* FIFO Valid Byte Count and Control */
259 	unsigned long scr;	/* SATA control register block */
260 	unsigned long sien;	/* SATA Interrupt Enable register */
261 	unsigned long xfer_mode;/* data transfer mode register */
262 	unsigned long sfis_cfg;	/* SATA FIS reception config register */
263 } sil_port[] = {
264 	/* port 0 ... */
265 	{ 0x80, 0x8A, 0x00, 0x10, 0x40, 0x100, 0x148, 0xb4, 0x14c },
266 	{ 0xC0, 0xCA, 0x08, 0x18, 0x44, 0x180, 0x1c8, 0xf4, 0x1cc },
267 	{ 0x280, 0x28A, 0x200, 0x210, 0x240, 0x300, 0x348, 0x2b4, 0x34c },
268 	{ 0x2C0, 0x2CA, 0x208, 0x218, 0x244, 0x380, 0x3c8, 0x2f4, 0x3cc },
269 	/* ... port 3 */
270 };
271 
272 MODULE_AUTHOR("Jeff Garzik");
273 MODULE_DESCRIPTION("low-level driver for Silicon Image SATA controller");
274 MODULE_LICENSE("GPL");
275 MODULE_DEVICE_TABLE(pci, sil_pci_tbl);
276 MODULE_VERSION(DRV_VERSION);
277 
278 static int slow_down = 0;
279 module_param(slow_down, int, 0444);
280 MODULE_PARM_DESC(slow_down, "Sledgehammer used to work around random problems, by limiting commands to 15 sectors (0=off, 1=on)");
281 
282 
283 static unsigned char sil_get_device_cache_line(struct pci_dev *pdev)
284 {
285 	u8 cache_line = 0;
286 	pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache_line);
287 	return cache_line;
288 }
289 
290 /**
291  *	sil_set_mode		-	wrap set_mode functions
292  *	@ap: port to set up
293  *	@r_failed: returned device when we fail
294  *
295  *	Wrap the libata method for device setup as after the setup we need
296  *	to inspect the results and do some configuration work
297  */
298 
299 static int sil_set_mode (struct ata_port *ap, struct ata_device **r_failed)
300 {
301 	struct ata_host *host = ap->host;
302 	struct ata_device *dev;
303 	void __iomem *mmio_base = host->iomap[SIL_MMIO_BAR];
304 	void __iomem *addr = mmio_base + sil_port[ap->port_no].xfer_mode;
305 	u32 tmp, dev_mode[2];
306 	unsigned int i;
307 	int rc;
308 
309 	rc = ata_do_set_mode(ap, r_failed);
310 	if (rc)
311 		return rc;
312 
313 	for (i = 0; i < 2; i++) {
314 		dev = &ap->device[i];
315 		if (!ata_dev_enabled(dev))
316 			dev_mode[i] = 0;	/* PIO0/1/2 */
317 		else if (dev->flags & ATA_DFLAG_PIO)
318 			dev_mode[i] = 1;	/* PIO3/4 */
319 		else
320 			dev_mode[i] = 3;	/* UDMA */
321 		/* value 2 indicates MDMA */
322 	}
323 
324 	tmp = readl(addr);
325 	tmp &= ~((1<<5) | (1<<4) | (1<<1) | (1<<0));
326 	tmp |= dev_mode[0];
327 	tmp |= (dev_mode[1] << 4);
328 	writel(tmp, addr);
329 	readl(addr);	/* flush */
330 	return 0;
331 }
332 
333 static inline void __iomem *sil_scr_addr(struct ata_port *ap, unsigned int sc_reg)
334 {
335 	void __iomem *offset = ap->ioaddr.scr_addr;
336 
337 	switch (sc_reg) {
338 	case SCR_STATUS:
339 		return offset + 4;
340 	case SCR_ERROR:
341 		return offset + 8;
342 	case SCR_CONTROL:
343 		return offset;
344 	default:
345 		/* do nothing */
346 		break;
347 	}
348 
349 	return NULL;
350 }
351 
352 static u32 sil_scr_read (struct ata_port *ap, unsigned int sc_reg)
353 {
354 	void __iomem *mmio = sil_scr_addr(ap, sc_reg);
355 	if (mmio)
356 		return readl(mmio);
357 	return 0xffffffffU;
358 }
359 
360 static void sil_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
361 {
362 	void __iomem *mmio = sil_scr_addr(ap, sc_reg);
363 	if (mmio)
364 		writel(val, mmio);
365 }
366 
367 static void sil_host_intr(struct ata_port *ap, u32 bmdma2)
368 {
369 	struct ata_eh_info *ehi = &ap->eh_info;
370 	struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->active_tag);
371 	u8 status;
372 
373 	if (unlikely(bmdma2 & SIL_DMA_SATA_IRQ)) {
374 		u32 serror;
375 
376 		/* SIEN doesn't mask SATA IRQs on some 3112s.  Those
377 		 * controllers continue to assert IRQ as long as
378 		 * SError bits are pending.  Clear SError immediately.
379 		 */
380 		serror = sil_scr_read(ap, SCR_ERROR);
381 		sil_scr_write(ap, SCR_ERROR, serror);
382 
383 		/* Trigger hotplug and accumulate SError only if the
384 		 * port isn't already frozen.  Otherwise, PHY events
385 		 * during hardreset makes controllers with broken SIEN
386 		 * repeat probing needlessly.
387 		 */
388 		if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
389 			ata_ehi_hotplugged(&ap->eh_info);
390 			ap->eh_info.serror |= serror;
391 		}
392 
393 		goto freeze;
394 	}
395 
396 	if (unlikely(!qc))
397 		goto freeze;
398 
399 	if (unlikely(qc->tf.flags & ATA_TFLAG_POLLING)) {
400 		/* this sometimes happens, just clear IRQ */
401 		ata_chk_status(ap);
402 		return;
403 	}
404 
405 	/* Check whether we are expecting interrupt in this state */
406 	switch (ap->hsm_task_state) {
407 	case HSM_ST_FIRST:
408 		/* Some pre-ATAPI-4 devices assert INTRQ
409 		 * at this state when ready to receive CDB.
410 		 */
411 
412 		/* Check the ATA_DFLAG_CDB_INTR flag is enough here.
413 		 * The flag was turned on only for atapi devices.
414 		 * No need to check is_atapi_taskfile(&qc->tf) again.
415 		 */
416 		if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR))
417 			goto err_hsm;
418 		break;
419 	case HSM_ST_LAST:
420 		if (qc->tf.protocol == ATA_PROT_DMA ||
421 		    qc->tf.protocol == ATA_PROT_ATAPI_DMA) {
422 			/* clear DMA-Start bit */
423 			ap->ops->bmdma_stop(qc);
424 
425 			if (bmdma2 & SIL_DMA_ERROR) {
426 				qc->err_mask |= AC_ERR_HOST_BUS;
427 				ap->hsm_task_state = HSM_ST_ERR;
428 			}
429 		}
430 		break;
431 	case HSM_ST:
432 		break;
433 	default:
434 		goto err_hsm;
435 	}
436 
437 	/* check main status, clearing INTRQ */
438 	status = ata_chk_status(ap);
439 	if (unlikely(status & ATA_BUSY))
440 		goto err_hsm;
441 
442 	/* ack bmdma irq events */
443 	ata_bmdma_irq_clear(ap);
444 
445 	/* kick HSM in the ass */
446 	ata_hsm_move(ap, qc, status, 0);
447 
448 	if (unlikely(qc->err_mask) && (qc->tf.protocol == ATA_PROT_DMA ||
449 				       qc->tf.protocol == ATA_PROT_ATAPI_DMA))
450 		ata_ehi_push_desc(ehi, "BMDMA2 stat 0x%x", bmdma2);
451 
452 	return;
453 
454  err_hsm:
455 	qc->err_mask |= AC_ERR_HSM;
456  freeze:
457 	ata_port_freeze(ap);
458 }
459 
460 static irqreturn_t sil_interrupt(int irq, void *dev_instance)
461 {
462 	struct ata_host *host = dev_instance;
463 	void __iomem *mmio_base = host->iomap[SIL_MMIO_BAR];
464 	int handled = 0;
465 	int i;
466 
467 	spin_lock(&host->lock);
468 
469 	for (i = 0; i < host->n_ports; i++) {
470 		struct ata_port *ap = host->ports[i];
471 		u32 bmdma2 = readl(mmio_base + sil_port[ap->port_no].bmdma2);
472 
473 		if (unlikely(!ap || ap->flags & ATA_FLAG_DISABLED))
474 			continue;
475 
476 		/* turn off SATA_IRQ if not supported */
477 		if (ap->flags & SIL_FLAG_NO_SATA_IRQ)
478 			bmdma2 &= ~SIL_DMA_SATA_IRQ;
479 
480 		if (bmdma2 == 0xffffffff ||
481 		    !(bmdma2 & (SIL_DMA_COMPLETE | SIL_DMA_SATA_IRQ)))
482 			continue;
483 
484 		sil_host_intr(ap, bmdma2);
485 		handled = 1;
486 	}
487 
488 	spin_unlock(&host->lock);
489 
490 	return IRQ_RETVAL(handled);
491 }
492 
493 static void sil_freeze(struct ata_port *ap)
494 {
495 	void __iomem *mmio_base = ap->host->iomap[SIL_MMIO_BAR];
496 	u32 tmp;
497 
498 	/* global IRQ mask doesn't block SATA IRQ, turn off explicitly */
499 	writel(0, mmio_base + sil_port[ap->port_no].sien);
500 
501 	/* plug IRQ */
502 	tmp = readl(mmio_base + SIL_SYSCFG);
503 	tmp |= SIL_MASK_IDE0_INT << ap->port_no;
504 	writel(tmp, mmio_base + SIL_SYSCFG);
505 	readl(mmio_base + SIL_SYSCFG);	/* flush */
506 }
507 
508 static void sil_thaw(struct ata_port *ap)
509 {
510 	void __iomem *mmio_base = ap->host->iomap[SIL_MMIO_BAR];
511 	u32 tmp;
512 
513 	/* clear IRQ */
514 	ata_chk_status(ap);
515 	ata_bmdma_irq_clear(ap);
516 
517 	/* turn on SATA IRQ if supported */
518 	if (!(ap->flags & SIL_FLAG_NO_SATA_IRQ))
519 		writel(SIL_SIEN_N, mmio_base + sil_port[ap->port_no].sien);
520 
521 	/* turn on IRQ */
522 	tmp = readl(mmio_base + SIL_SYSCFG);
523 	tmp &= ~(SIL_MASK_IDE0_INT << ap->port_no);
524 	writel(tmp, mmio_base + SIL_SYSCFG);
525 }
526 
527 /**
528  *	sil_dev_config - Apply device/host-specific errata fixups
529  *	@dev: Device to be examined
530  *
531  *	After the IDENTIFY [PACKET] DEVICE step is complete, and a
532  *	device is known to be present, this function is called.
533  *	We apply two errata fixups which are specific to Silicon Image,
534  *	a Seagate and a Maxtor fixup.
535  *
536  *	For certain Seagate devices, we must limit the maximum sectors
537  *	to under 8K.
538  *
539  *	For certain Maxtor devices, we must not program the drive
540  *	beyond udma5.
541  *
542  *	Both fixups are unfairly pessimistic.  As soon as I get more
543  *	information on these errata, I will create a more exhaustive
544  *	list, and apply the fixups to only the specific
545  *	devices/hosts/firmwares that need it.
546  *
547  *	20040111 - Seagate drives affected by the Mod15Write bug are blacklisted
548  *	The Maxtor quirk is in the blacklist, but I'm keeping the original
549  *	pessimistic fix for the following reasons...
550  *	- There seems to be less info on it, only one device gleaned off the
551  *	Windows	driver, maybe only one is affected.  More info would be greatly
552  *	appreciated.
553  *	- But then again UDMA5 is hardly anything to complain about
554  */
555 static void sil_dev_config(struct ata_device *dev)
556 {
557 	struct ata_port *ap = dev->ap;
558 	int print_info = ap->eh_context.i.flags & ATA_EHI_PRINTINFO;
559 	unsigned int n, quirks = 0;
560 	unsigned char model_num[ATA_ID_PROD_LEN + 1];
561 
562 	ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num));
563 
564 	for (n = 0; sil_blacklist[n].product; n++)
565 		if (!strcmp(sil_blacklist[n].product, model_num)) {
566 			quirks = sil_blacklist[n].quirk;
567 			break;
568 		}
569 
570 	/* limit requests to 15 sectors */
571 	if (slow_down ||
572 	    ((ap->flags & SIL_FLAG_MOD15WRITE) &&
573 	     (quirks & SIL_QUIRK_MOD15WRITE))) {
574 		if (print_info)
575 			ata_dev_printk(dev, KERN_INFO, "applying Seagate "
576 				       "errata fix (mod15write workaround)\n");
577 		dev->max_sectors = 15;
578 		return;
579 	}
580 
581 	/* limit to udma5 */
582 	if (quirks & SIL_QUIRK_UDMA5MAX) {
583 		if (print_info)
584 			ata_dev_printk(dev, KERN_INFO, "applying Maxtor "
585 				       "errata fix %s\n", model_num);
586 		dev->udma_mask &= ATA_UDMA5;
587 		return;
588 	}
589 }
590 
591 static void sil_init_controller(struct ata_host *host)
592 {
593 	struct pci_dev *pdev = to_pci_dev(host->dev);
594 	void __iomem *mmio_base = host->iomap[SIL_MMIO_BAR];
595 	u8 cls;
596 	u32 tmp;
597 	int i;
598 
599 	/* Initialize FIFO PCI bus arbitration */
600 	cls = sil_get_device_cache_line(pdev);
601 	if (cls) {
602 		cls >>= 3;
603 		cls++;  /* cls = (line_size/8)+1 */
604 		for (i = 0; i < host->n_ports; i++)
605 			writew(cls << 8 | cls,
606 			       mmio_base + sil_port[i].fifo_cfg);
607 	} else
608 		dev_printk(KERN_WARNING, &pdev->dev,
609 			   "cache line size not set.  Driver may not function\n");
610 
611 	/* Apply R_ERR on DMA activate FIS errata workaround */
612 	if (host->ports[0]->flags & SIL_FLAG_RERR_ON_DMA_ACT) {
613 		int cnt;
614 
615 		for (i = 0, cnt = 0; i < host->n_ports; i++) {
616 			tmp = readl(mmio_base + sil_port[i].sfis_cfg);
617 			if ((tmp & 0x3) != 0x01)
618 				continue;
619 			if (!cnt)
620 				dev_printk(KERN_INFO, &pdev->dev,
621 					   "Applying R_ERR on DMA activate "
622 					   "FIS errata fix\n");
623 			writel(tmp & ~0x3, mmio_base + sil_port[i].sfis_cfg);
624 			cnt++;
625 		}
626 	}
627 
628 	if (host->n_ports == 4) {
629 		/* flip the magic "make 4 ports work" bit */
630 		tmp = readl(mmio_base + sil_port[2].bmdma);
631 		if ((tmp & SIL_INTR_STEERING) == 0)
632 			writel(tmp | SIL_INTR_STEERING,
633 			       mmio_base + sil_port[2].bmdma);
634 	}
635 }
636 
637 static int sil_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
638 {
639 	static int printed_version;
640 	int board_id = ent->driver_data;
641 	const struct ata_port_info *ppi[] = { &sil_port_info[board_id], NULL };
642 	struct ata_host *host;
643 	void __iomem *mmio_base;
644 	int n_ports, rc;
645 	unsigned int i;
646 
647 	if (!printed_version++)
648 		dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
649 
650 	/* allocate host */
651 	n_ports = 2;
652 	if (board_id == sil_3114)
653 		n_ports = 4;
654 
655 	host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
656 	if (!host)
657 		return -ENOMEM;
658 
659 	/* acquire resources and fill host */
660 	rc = pcim_enable_device(pdev);
661 	if (rc)
662 		return rc;
663 
664 	rc = pcim_iomap_regions(pdev, 1 << SIL_MMIO_BAR, DRV_NAME);
665 	if (rc == -EBUSY)
666 		pcim_pin_device(pdev);
667 	if (rc)
668 		return rc;
669 	host->iomap = pcim_iomap_table(pdev);
670 
671 	rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
672 	if (rc)
673 		return rc;
674 	rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
675 	if (rc)
676 		return rc;
677 
678 	mmio_base = host->iomap[SIL_MMIO_BAR];
679 
680 	for (i = 0; i < host->n_ports; i++) {
681 		struct ata_ioports *ioaddr = &host->ports[i]->ioaddr;
682 
683 		ioaddr->cmd_addr = mmio_base + sil_port[i].tf;
684 		ioaddr->altstatus_addr =
685 		ioaddr->ctl_addr = mmio_base + sil_port[i].ctl;
686 		ioaddr->bmdma_addr = mmio_base + sil_port[i].bmdma;
687 		ioaddr->scr_addr = mmio_base + sil_port[i].scr;
688 		ata_std_ports(ioaddr);
689 	}
690 
691 	/* initialize and activate */
692 	sil_init_controller(host);
693 
694 	pci_set_master(pdev);
695 	return ata_host_activate(host, pdev->irq, sil_interrupt, IRQF_SHARED,
696 				 &sil_sht);
697 }
698 
699 #ifdef CONFIG_PM
700 static int sil_pci_device_resume(struct pci_dev *pdev)
701 {
702 	struct ata_host *host = dev_get_drvdata(&pdev->dev);
703 	int rc;
704 
705 	rc = ata_pci_device_do_resume(pdev);
706 	if (rc)
707 		return rc;
708 
709 	sil_init_controller(host);
710 	ata_host_resume(host);
711 
712 	return 0;
713 }
714 #endif
715 
716 static int __init sil_init(void)
717 {
718 	return pci_register_driver(&sil_pci_driver);
719 }
720 
721 static void __exit sil_exit(void)
722 {
723 	pci_unregister_driver(&sil_pci_driver);
724 }
725 
726 
727 module_init(sil_init);
728 module_exit(sil_exit);
729