1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Renesas R-Car SATA driver 4 * 5 * Author: Vladimir Barinov <source@cogentembedded.com> 6 * Copyright (C) 2013-2015 Cogent Embedded, Inc. 7 * Copyright (C) 2013-2015 Renesas Solutions Corp. 8 */ 9 10 #include <linux/kernel.h> 11 #include <linux/module.h> 12 #include <linux/ata.h> 13 #include <linux/libata.h> 14 #include <linux/of_device.h> 15 #include <linux/platform_device.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/err.h> 18 19 #define DRV_NAME "sata_rcar" 20 21 /* SH-Navi2G/ATAPI-ATA compatible task registers */ 22 #define DATA_REG 0x100 23 #define SDEVCON_REG 0x138 24 25 /* SH-Navi2G/ATAPI module compatible control registers */ 26 #define ATAPI_CONTROL1_REG 0x180 27 #define ATAPI_STATUS_REG 0x184 28 #define ATAPI_INT_ENABLE_REG 0x188 29 #define ATAPI_DTB_ADR_REG 0x198 30 #define ATAPI_DMA_START_ADR_REG 0x19C 31 #define ATAPI_DMA_TRANS_CNT_REG 0x1A0 32 #define ATAPI_CONTROL2_REG 0x1A4 33 #define ATAPI_SIG_ST_REG 0x1B0 34 #define ATAPI_BYTE_SWAP_REG 0x1BC 35 36 /* ATAPI control 1 register (ATAPI_CONTROL1) bits */ 37 #define ATAPI_CONTROL1_ISM BIT(16) 38 #define ATAPI_CONTROL1_DTA32M BIT(11) 39 #define ATAPI_CONTROL1_RESET BIT(7) 40 #define ATAPI_CONTROL1_DESE BIT(3) 41 #define ATAPI_CONTROL1_RW BIT(2) 42 #define ATAPI_CONTROL1_STOP BIT(1) 43 #define ATAPI_CONTROL1_START BIT(0) 44 45 /* ATAPI status register (ATAPI_STATUS) bits */ 46 #define ATAPI_STATUS_SATAINT BIT(11) 47 #define ATAPI_STATUS_DNEND BIT(6) 48 #define ATAPI_STATUS_DEVTRM BIT(5) 49 #define ATAPI_STATUS_DEVINT BIT(4) 50 #define ATAPI_STATUS_ERR BIT(2) 51 #define ATAPI_STATUS_NEND BIT(1) 52 #define ATAPI_STATUS_ACT BIT(0) 53 54 /* Interrupt enable register (ATAPI_INT_ENABLE) bits */ 55 #define ATAPI_INT_ENABLE_SATAINT BIT(11) 56 #define ATAPI_INT_ENABLE_DNEND BIT(6) 57 #define ATAPI_INT_ENABLE_DEVTRM BIT(5) 58 #define ATAPI_INT_ENABLE_DEVINT BIT(4) 59 #define ATAPI_INT_ENABLE_ERR BIT(2) 60 #define ATAPI_INT_ENABLE_NEND BIT(1) 61 #define ATAPI_INT_ENABLE_ACT BIT(0) 62 63 /* Access control registers for physical layer control register */ 64 #define SATAPHYADDR_REG 0x200 65 #define SATAPHYWDATA_REG 0x204 66 #define SATAPHYACCEN_REG 0x208 67 #define SATAPHYRESET_REG 0x20C 68 #define SATAPHYRDATA_REG 0x210 69 #define SATAPHYACK_REG 0x214 70 71 /* Physical layer control address command register (SATAPHYADDR) bits */ 72 #define SATAPHYADDR_PHYRATEMODE BIT(10) 73 #define SATAPHYADDR_PHYCMD_READ BIT(9) 74 #define SATAPHYADDR_PHYCMD_WRITE BIT(8) 75 76 /* Physical layer control enable register (SATAPHYACCEN) bits */ 77 #define SATAPHYACCEN_PHYLANE BIT(0) 78 79 /* Physical layer control reset register (SATAPHYRESET) bits */ 80 #define SATAPHYRESET_PHYRST BIT(1) 81 #define SATAPHYRESET_PHYSRES BIT(0) 82 83 /* Physical layer control acknowledge register (SATAPHYACK) bits */ 84 #define SATAPHYACK_PHYACK BIT(0) 85 86 /* Serial-ATA HOST control registers */ 87 #define BISTCONF_REG 0x102C 88 #define SDATA_REG 0x1100 89 #define SSDEVCON_REG 0x1204 90 91 #define SCRSSTS_REG 0x1400 92 #define SCRSERR_REG 0x1404 93 #define SCRSCON_REG 0x1408 94 #define SCRSACT_REG 0x140C 95 96 #define SATAINTSTAT_REG 0x1508 97 #define SATAINTMASK_REG 0x150C 98 99 /* SATA INT status register (SATAINTSTAT) bits */ 100 #define SATAINTSTAT_SERR BIT(3) 101 #define SATAINTSTAT_ATA BIT(0) 102 103 /* SATA INT mask register (SATAINTSTAT) bits */ 104 #define SATAINTMASK_SERRMSK BIT(3) 105 #define SATAINTMASK_ERRMSK BIT(2) 106 #define SATAINTMASK_ERRCRTMSK BIT(1) 107 #define SATAINTMASK_ATAMSK BIT(0) 108 #define SATAINTMASK_ALL_GEN1 0x7ff 109 #define SATAINTMASK_ALL_GEN2 0xfff 110 111 #define SATA_RCAR_INT_MASK (SATAINTMASK_SERRMSK | \ 112 SATAINTMASK_ATAMSK) 113 114 /* Physical Layer Control Registers */ 115 #define SATAPCTLR1_REG 0x43 116 #define SATAPCTLR2_REG 0x52 117 #define SATAPCTLR3_REG 0x5A 118 #define SATAPCTLR4_REG 0x60 119 120 /* Descriptor table word 0 bit (when DTA32M = 1) */ 121 #define SATA_RCAR_DTEND BIT(0) 122 123 #define SATA_RCAR_DMA_BOUNDARY 0x1FFFFFFFUL 124 125 /* Gen2 Physical Layer Control Registers */ 126 #define RCAR_GEN2_PHY_CTL1_REG 0x1704 127 #define RCAR_GEN2_PHY_CTL1 0x34180002 128 #define RCAR_GEN2_PHY_CTL1_SS 0xC180 /* Spread Spectrum */ 129 130 #define RCAR_GEN2_PHY_CTL2_REG 0x170C 131 #define RCAR_GEN2_PHY_CTL2 0x00002303 132 133 #define RCAR_GEN2_PHY_CTL3_REG 0x171C 134 #define RCAR_GEN2_PHY_CTL3 0x000B0194 135 136 #define RCAR_GEN2_PHY_CTL4_REG 0x1724 137 #define RCAR_GEN2_PHY_CTL4 0x00030994 138 139 #define RCAR_GEN2_PHY_CTL5_REG 0x1740 140 #define RCAR_GEN2_PHY_CTL5 0x03004001 141 #define RCAR_GEN2_PHY_CTL5_DC BIT(1) /* DC connection */ 142 #define RCAR_GEN2_PHY_CTL5_TR BIT(2) /* Termination Resistor */ 143 144 enum sata_rcar_type { 145 RCAR_GEN1_SATA, 146 RCAR_GEN2_SATA, 147 RCAR_GEN3_SATA, 148 RCAR_R8A7790_ES1_SATA, 149 }; 150 151 struct sata_rcar_priv { 152 void __iomem *base; 153 u32 sataint_mask; 154 enum sata_rcar_type type; 155 }; 156 157 static void sata_rcar_gen1_phy_preinit(struct sata_rcar_priv *priv) 158 { 159 void __iomem *base = priv->base; 160 161 /* idle state */ 162 iowrite32(0, base + SATAPHYADDR_REG); 163 /* reset */ 164 iowrite32(SATAPHYRESET_PHYRST, base + SATAPHYRESET_REG); 165 udelay(10); 166 /* deassert reset */ 167 iowrite32(0, base + SATAPHYRESET_REG); 168 } 169 170 static void sata_rcar_gen1_phy_write(struct sata_rcar_priv *priv, u16 reg, 171 u32 val, int group) 172 { 173 void __iomem *base = priv->base; 174 int timeout; 175 176 /* deassert reset */ 177 iowrite32(0, base + SATAPHYRESET_REG); 178 /* lane 1 */ 179 iowrite32(SATAPHYACCEN_PHYLANE, base + SATAPHYACCEN_REG); 180 /* write phy register value */ 181 iowrite32(val, base + SATAPHYWDATA_REG); 182 /* set register group */ 183 if (group) 184 reg |= SATAPHYADDR_PHYRATEMODE; 185 /* write command */ 186 iowrite32(SATAPHYADDR_PHYCMD_WRITE | reg, base + SATAPHYADDR_REG); 187 /* wait for ack */ 188 for (timeout = 0; timeout < 100; timeout++) { 189 val = ioread32(base + SATAPHYACK_REG); 190 if (val & SATAPHYACK_PHYACK) 191 break; 192 } 193 if (timeout >= 100) 194 pr_err("%s timeout\n", __func__); 195 /* idle state */ 196 iowrite32(0, base + SATAPHYADDR_REG); 197 } 198 199 static void sata_rcar_gen1_phy_init(struct sata_rcar_priv *priv) 200 { 201 sata_rcar_gen1_phy_preinit(priv); 202 sata_rcar_gen1_phy_write(priv, SATAPCTLR1_REG, 0x00200188, 0); 203 sata_rcar_gen1_phy_write(priv, SATAPCTLR1_REG, 0x00200188, 1); 204 sata_rcar_gen1_phy_write(priv, SATAPCTLR3_REG, 0x0000A061, 0); 205 sata_rcar_gen1_phy_write(priv, SATAPCTLR2_REG, 0x20000000, 0); 206 sata_rcar_gen1_phy_write(priv, SATAPCTLR2_REG, 0x20000000, 1); 207 sata_rcar_gen1_phy_write(priv, SATAPCTLR4_REG, 0x28E80000, 0); 208 } 209 210 static void sata_rcar_gen2_phy_init(struct sata_rcar_priv *priv) 211 { 212 void __iomem *base = priv->base; 213 214 iowrite32(RCAR_GEN2_PHY_CTL1, base + RCAR_GEN2_PHY_CTL1_REG); 215 iowrite32(RCAR_GEN2_PHY_CTL2, base + RCAR_GEN2_PHY_CTL2_REG); 216 iowrite32(RCAR_GEN2_PHY_CTL3, base + RCAR_GEN2_PHY_CTL3_REG); 217 iowrite32(RCAR_GEN2_PHY_CTL4, base + RCAR_GEN2_PHY_CTL4_REG); 218 iowrite32(RCAR_GEN2_PHY_CTL5 | RCAR_GEN2_PHY_CTL5_DC | 219 RCAR_GEN2_PHY_CTL5_TR, base + RCAR_GEN2_PHY_CTL5_REG); 220 } 221 222 static void sata_rcar_freeze(struct ata_port *ap) 223 { 224 struct sata_rcar_priv *priv = ap->host->private_data; 225 226 /* mask */ 227 iowrite32(priv->sataint_mask, priv->base + SATAINTMASK_REG); 228 229 ata_sff_freeze(ap); 230 } 231 232 static void sata_rcar_thaw(struct ata_port *ap) 233 { 234 struct sata_rcar_priv *priv = ap->host->private_data; 235 void __iomem *base = priv->base; 236 237 /* ack */ 238 iowrite32(~(u32)SATA_RCAR_INT_MASK, base + SATAINTSTAT_REG); 239 240 ata_sff_thaw(ap); 241 242 /* unmask */ 243 iowrite32(priv->sataint_mask & ~SATA_RCAR_INT_MASK, base + SATAINTMASK_REG); 244 } 245 246 static void sata_rcar_ioread16_rep(void __iomem *reg, void *buffer, int count) 247 { 248 u16 *ptr = buffer; 249 250 while (count--) { 251 u16 data = ioread32(reg); 252 253 *ptr++ = data; 254 } 255 } 256 257 static void sata_rcar_iowrite16_rep(void __iomem *reg, void *buffer, int count) 258 { 259 const u16 *ptr = buffer; 260 261 while (count--) 262 iowrite32(*ptr++, reg); 263 } 264 265 static u8 sata_rcar_check_status(struct ata_port *ap) 266 { 267 return ioread32(ap->ioaddr.status_addr); 268 } 269 270 static u8 sata_rcar_check_altstatus(struct ata_port *ap) 271 { 272 return ioread32(ap->ioaddr.altstatus_addr); 273 } 274 275 static void sata_rcar_set_devctl(struct ata_port *ap, u8 ctl) 276 { 277 iowrite32(ctl, ap->ioaddr.ctl_addr); 278 } 279 280 static void sata_rcar_dev_select(struct ata_port *ap, unsigned int device) 281 { 282 iowrite32(ATA_DEVICE_OBS, ap->ioaddr.device_addr); 283 ata_sff_pause(ap); /* needed; also flushes, for mmio */ 284 } 285 286 static unsigned int sata_rcar_ata_devchk(struct ata_port *ap, 287 unsigned int device) 288 { 289 struct ata_ioports *ioaddr = &ap->ioaddr; 290 u8 nsect, lbal; 291 292 sata_rcar_dev_select(ap, device); 293 294 iowrite32(0x55, ioaddr->nsect_addr); 295 iowrite32(0xaa, ioaddr->lbal_addr); 296 297 iowrite32(0xaa, ioaddr->nsect_addr); 298 iowrite32(0x55, ioaddr->lbal_addr); 299 300 iowrite32(0x55, ioaddr->nsect_addr); 301 iowrite32(0xaa, ioaddr->lbal_addr); 302 303 nsect = ioread32(ioaddr->nsect_addr); 304 lbal = ioread32(ioaddr->lbal_addr); 305 306 if (nsect == 0x55 && lbal == 0xaa) 307 return 1; /* found a device */ 308 309 return 0; /* nothing found */ 310 } 311 312 static int sata_rcar_wait_after_reset(struct ata_link *link, 313 unsigned long deadline) 314 { 315 struct ata_port *ap = link->ap; 316 317 ata_msleep(ap, ATA_WAIT_AFTER_RESET); 318 319 return ata_sff_wait_ready(link, deadline); 320 } 321 322 static int sata_rcar_bus_softreset(struct ata_port *ap, unsigned long deadline) 323 { 324 struct ata_ioports *ioaddr = &ap->ioaddr; 325 326 /* software reset. causes dev0 to be selected */ 327 iowrite32(ap->ctl, ioaddr->ctl_addr); 328 udelay(20); 329 iowrite32(ap->ctl | ATA_SRST, ioaddr->ctl_addr); 330 udelay(20); 331 iowrite32(ap->ctl, ioaddr->ctl_addr); 332 ap->last_ctl = ap->ctl; 333 334 /* wait the port to become ready */ 335 return sata_rcar_wait_after_reset(&ap->link, deadline); 336 } 337 338 static int sata_rcar_softreset(struct ata_link *link, unsigned int *classes, 339 unsigned long deadline) 340 { 341 struct ata_port *ap = link->ap; 342 unsigned int devmask = 0; 343 int rc; 344 u8 err; 345 346 /* determine if device 0 is present */ 347 if (sata_rcar_ata_devchk(ap, 0)) 348 devmask |= 1 << 0; 349 350 /* issue bus reset */ 351 rc = sata_rcar_bus_softreset(ap, deadline); 352 /* if link is occupied, -ENODEV too is an error */ 353 if (rc && (rc != -ENODEV || sata_scr_valid(link))) { 354 ata_link_err(link, "SRST failed (errno=%d)\n", rc); 355 return rc; 356 } 357 358 /* determine by signature whether we have ATA or ATAPI devices */ 359 classes[0] = ata_sff_dev_classify(&link->device[0], devmask, &err); 360 361 return 0; 362 } 363 364 static void sata_rcar_tf_load(struct ata_port *ap, 365 const struct ata_taskfile *tf) 366 { 367 struct ata_ioports *ioaddr = &ap->ioaddr; 368 unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR; 369 370 if (tf->ctl != ap->last_ctl) { 371 iowrite32(tf->ctl, ioaddr->ctl_addr); 372 ap->last_ctl = tf->ctl; 373 ata_wait_idle(ap); 374 } 375 376 if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) { 377 iowrite32(tf->hob_feature, ioaddr->feature_addr); 378 iowrite32(tf->hob_nsect, ioaddr->nsect_addr); 379 iowrite32(tf->hob_lbal, ioaddr->lbal_addr); 380 iowrite32(tf->hob_lbam, ioaddr->lbam_addr); 381 iowrite32(tf->hob_lbah, ioaddr->lbah_addr); 382 VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n", 383 tf->hob_feature, 384 tf->hob_nsect, 385 tf->hob_lbal, 386 tf->hob_lbam, 387 tf->hob_lbah); 388 } 389 390 if (is_addr) { 391 iowrite32(tf->feature, ioaddr->feature_addr); 392 iowrite32(tf->nsect, ioaddr->nsect_addr); 393 iowrite32(tf->lbal, ioaddr->lbal_addr); 394 iowrite32(tf->lbam, ioaddr->lbam_addr); 395 iowrite32(tf->lbah, ioaddr->lbah_addr); 396 VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n", 397 tf->feature, 398 tf->nsect, 399 tf->lbal, 400 tf->lbam, 401 tf->lbah); 402 } 403 404 if (tf->flags & ATA_TFLAG_DEVICE) { 405 iowrite32(tf->device, ioaddr->device_addr); 406 VPRINTK("device 0x%X\n", tf->device); 407 } 408 409 ata_wait_idle(ap); 410 } 411 412 static void sata_rcar_tf_read(struct ata_port *ap, struct ata_taskfile *tf) 413 { 414 struct ata_ioports *ioaddr = &ap->ioaddr; 415 416 tf->command = sata_rcar_check_status(ap); 417 tf->feature = ioread32(ioaddr->error_addr); 418 tf->nsect = ioread32(ioaddr->nsect_addr); 419 tf->lbal = ioread32(ioaddr->lbal_addr); 420 tf->lbam = ioread32(ioaddr->lbam_addr); 421 tf->lbah = ioread32(ioaddr->lbah_addr); 422 tf->device = ioread32(ioaddr->device_addr); 423 424 if (tf->flags & ATA_TFLAG_LBA48) { 425 iowrite32(tf->ctl | ATA_HOB, ioaddr->ctl_addr); 426 tf->hob_feature = ioread32(ioaddr->error_addr); 427 tf->hob_nsect = ioread32(ioaddr->nsect_addr); 428 tf->hob_lbal = ioread32(ioaddr->lbal_addr); 429 tf->hob_lbam = ioread32(ioaddr->lbam_addr); 430 tf->hob_lbah = ioread32(ioaddr->lbah_addr); 431 iowrite32(tf->ctl, ioaddr->ctl_addr); 432 ap->last_ctl = tf->ctl; 433 } 434 } 435 436 static void sata_rcar_exec_command(struct ata_port *ap, 437 const struct ata_taskfile *tf) 438 { 439 iowrite32(tf->command, ap->ioaddr.command_addr); 440 ata_sff_pause(ap); 441 } 442 443 static unsigned int sata_rcar_data_xfer(struct ata_queued_cmd *qc, 444 unsigned char *buf, 445 unsigned int buflen, int rw) 446 { 447 struct ata_port *ap = qc->dev->link->ap; 448 void __iomem *data_addr = ap->ioaddr.data_addr; 449 unsigned int words = buflen >> 1; 450 451 /* Transfer multiple of 2 bytes */ 452 if (rw == READ) 453 sata_rcar_ioread16_rep(data_addr, buf, words); 454 else 455 sata_rcar_iowrite16_rep(data_addr, buf, words); 456 457 /* Transfer trailing byte, if any. */ 458 if (unlikely(buflen & 0x01)) { 459 unsigned char pad[2] = { }; 460 461 /* Point buf to the tail of buffer */ 462 buf += buflen - 1; 463 464 /* 465 * Use io*16_rep() accessors here as well to avoid pointlessly 466 * swapping bytes to and from on the big endian machines... 467 */ 468 if (rw == READ) { 469 sata_rcar_ioread16_rep(data_addr, pad, 1); 470 *buf = pad[0]; 471 } else { 472 pad[0] = *buf; 473 sata_rcar_iowrite16_rep(data_addr, pad, 1); 474 } 475 words++; 476 } 477 478 return words << 1; 479 } 480 481 static void sata_rcar_drain_fifo(struct ata_queued_cmd *qc) 482 { 483 int count; 484 struct ata_port *ap; 485 486 /* We only need to flush incoming data when a command was running */ 487 if (qc == NULL || qc->dma_dir == DMA_TO_DEVICE) 488 return; 489 490 ap = qc->ap; 491 /* Drain up to 64K of data before we give up this recovery method */ 492 for (count = 0; (ap->ops->sff_check_status(ap) & ATA_DRQ) && 493 count < 65536; count += 2) 494 ioread32(ap->ioaddr.data_addr); 495 496 /* Can become DEBUG later */ 497 if (count) 498 ata_port_dbg(ap, "drained %d bytes to clear DRQ\n", count); 499 } 500 501 static int sata_rcar_scr_read(struct ata_link *link, unsigned int sc_reg, 502 u32 *val) 503 { 504 if (sc_reg > SCR_ACTIVE) 505 return -EINVAL; 506 507 *val = ioread32(link->ap->ioaddr.scr_addr + (sc_reg << 2)); 508 return 0; 509 } 510 511 static int sata_rcar_scr_write(struct ata_link *link, unsigned int sc_reg, 512 u32 val) 513 { 514 if (sc_reg > SCR_ACTIVE) 515 return -EINVAL; 516 517 iowrite32(val, link->ap->ioaddr.scr_addr + (sc_reg << 2)); 518 return 0; 519 } 520 521 static void sata_rcar_bmdma_fill_sg(struct ata_queued_cmd *qc) 522 { 523 struct ata_port *ap = qc->ap; 524 struct ata_bmdma_prd *prd = ap->bmdma_prd; 525 struct scatterlist *sg; 526 unsigned int si; 527 528 for_each_sg(qc->sg, sg, qc->n_elem, si) { 529 u32 addr, sg_len; 530 531 /* 532 * Note: h/w doesn't support 64-bit, so we unconditionally 533 * truncate dma_addr_t to u32. 534 */ 535 addr = (u32)sg_dma_address(sg); 536 sg_len = sg_dma_len(sg); 537 538 prd[si].addr = cpu_to_le32(addr); 539 prd[si].flags_len = cpu_to_le32(sg_len); 540 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", si, addr, sg_len); 541 } 542 543 /* end-of-table flag */ 544 prd[si - 1].addr |= cpu_to_le32(SATA_RCAR_DTEND); 545 } 546 547 static enum ata_completion_errors sata_rcar_qc_prep(struct ata_queued_cmd *qc) 548 { 549 if (!(qc->flags & ATA_QCFLAG_DMAMAP)) 550 return AC_ERR_OK; 551 552 sata_rcar_bmdma_fill_sg(qc); 553 554 return AC_ERR_OK; 555 } 556 557 static void sata_rcar_bmdma_setup(struct ata_queued_cmd *qc) 558 { 559 struct ata_port *ap = qc->ap; 560 unsigned int rw = qc->tf.flags & ATA_TFLAG_WRITE; 561 struct sata_rcar_priv *priv = ap->host->private_data; 562 void __iomem *base = priv->base; 563 u32 dmactl; 564 565 /* load PRD table addr. */ 566 mb(); /* make sure PRD table writes are visible to controller */ 567 iowrite32(ap->bmdma_prd_dma, base + ATAPI_DTB_ADR_REG); 568 569 /* specify data direction, triple-check start bit is clear */ 570 dmactl = ioread32(base + ATAPI_CONTROL1_REG); 571 dmactl &= ~(ATAPI_CONTROL1_RW | ATAPI_CONTROL1_STOP); 572 if (dmactl & ATAPI_CONTROL1_START) { 573 dmactl &= ~ATAPI_CONTROL1_START; 574 dmactl |= ATAPI_CONTROL1_STOP; 575 } 576 if (!rw) 577 dmactl |= ATAPI_CONTROL1_RW; 578 iowrite32(dmactl, base + ATAPI_CONTROL1_REG); 579 580 /* issue r/w command */ 581 ap->ops->sff_exec_command(ap, &qc->tf); 582 } 583 584 static void sata_rcar_bmdma_start(struct ata_queued_cmd *qc) 585 { 586 struct ata_port *ap = qc->ap; 587 struct sata_rcar_priv *priv = ap->host->private_data; 588 void __iomem *base = priv->base; 589 u32 dmactl; 590 591 /* start host DMA transaction */ 592 dmactl = ioread32(base + ATAPI_CONTROL1_REG); 593 dmactl &= ~ATAPI_CONTROL1_STOP; 594 dmactl |= ATAPI_CONTROL1_START; 595 iowrite32(dmactl, base + ATAPI_CONTROL1_REG); 596 } 597 598 static void sata_rcar_bmdma_stop(struct ata_queued_cmd *qc) 599 { 600 struct ata_port *ap = qc->ap; 601 struct sata_rcar_priv *priv = ap->host->private_data; 602 void __iomem *base = priv->base; 603 u32 dmactl; 604 605 /* force termination of DMA transfer if active */ 606 dmactl = ioread32(base + ATAPI_CONTROL1_REG); 607 if (dmactl & ATAPI_CONTROL1_START) { 608 dmactl &= ~ATAPI_CONTROL1_START; 609 dmactl |= ATAPI_CONTROL1_STOP; 610 iowrite32(dmactl, base + ATAPI_CONTROL1_REG); 611 } 612 613 /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */ 614 ata_sff_dma_pause(ap); 615 } 616 617 static u8 sata_rcar_bmdma_status(struct ata_port *ap) 618 { 619 struct sata_rcar_priv *priv = ap->host->private_data; 620 u8 host_stat = 0; 621 u32 status; 622 623 status = ioread32(priv->base + ATAPI_STATUS_REG); 624 if (status & ATAPI_STATUS_DEVINT) 625 host_stat |= ATA_DMA_INTR; 626 if (status & ATAPI_STATUS_ACT) 627 host_stat |= ATA_DMA_ACTIVE; 628 629 return host_stat; 630 } 631 632 static struct scsi_host_template sata_rcar_sht = { 633 ATA_BASE_SHT(DRV_NAME), 634 /* 635 * This controller allows transfer chunks up to 512MB which cross 64KB 636 * boundaries, therefore the DMA limits are more relaxed than standard 637 * ATA SFF. 638 */ 639 .sg_tablesize = ATA_MAX_PRD, 640 .dma_boundary = SATA_RCAR_DMA_BOUNDARY, 641 }; 642 643 static struct ata_port_operations sata_rcar_port_ops = { 644 .inherits = &ata_bmdma_port_ops, 645 646 .freeze = sata_rcar_freeze, 647 .thaw = sata_rcar_thaw, 648 .softreset = sata_rcar_softreset, 649 650 .scr_read = sata_rcar_scr_read, 651 .scr_write = sata_rcar_scr_write, 652 653 .sff_dev_select = sata_rcar_dev_select, 654 .sff_set_devctl = sata_rcar_set_devctl, 655 .sff_check_status = sata_rcar_check_status, 656 .sff_check_altstatus = sata_rcar_check_altstatus, 657 .sff_tf_load = sata_rcar_tf_load, 658 .sff_tf_read = sata_rcar_tf_read, 659 .sff_exec_command = sata_rcar_exec_command, 660 .sff_data_xfer = sata_rcar_data_xfer, 661 .sff_drain_fifo = sata_rcar_drain_fifo, 662 663 .qc_prep = sata_rcar_qc_prep, 664 665 .bmdma_setup = sata_rcar_bmdma_setup, 666 .bmdma_start = sata_rcar_bmdma_start, 667 .bmdma_stop = sata_rcar_bmdma_stop, 668 .bmdma_status = sata_rcar_bmdma_status, 669 }; 670 671 static void sata_rcar_serr_interrupt(struct ata_port *ap) 672 { 673 struct sata_rcar_priv *priv = ap->host->private_data; 674 struct ata_eh_info *ehi = &ap->link.eh_info; 675 int freeze = 0; 676 u32 serror; 677 678 serror = ioread32(priv->base + SCRSERR_REG); 679 if (!serror) 680 return; 681 682 ata_port_dbg(ap, "SError @host_intr: 0x%x\n", serror); 683 684 /* first, analyze and record host port events */ 685 ata_ehi_clear_desc(ehi); 686 687 if (serror & (SERR_DEV_XCHG | SERR_PHYRDY_CHG)) { 688 /* Setup a soft-reset EH action */ 689 ata_ehi_hotplugged(ehi); 690 ata_ehi_push_desc(ehi, "%s", "hotplug"); 691 692 freeze = serror & SERR_COMM_WAKE ? 0 : 1; 693 } 694 695 /* freeze or abort */ 696 if (freeze) 697 ata_port_freeze(ap); 698 else 699 ata_port_abort(ap); 700 } 701 702 static void sata_rcar_ata_interrupt(struct ata_port *ap) 703 { 704 struct ata_queued_cmd *qc; 705 int handled = 0; 706 707 qc = ata_qc_from_tag(ap, ap->link.active_tag); 708 if (qc) 709 handled |= ata_bmdma_port_intr(ap, qc); 710 711 /* be sure to clear ATA interrupt */ 712 if (!handled) 713 sata_rcar_check_status(ap); 714 } 715 716 static irqreturn_t sata_rcar_interrupt(int irq, void *dev_instance) 717 { 718 struct ata_host *host = dev_instance; 719 struct sata_rcar_priv *priv = host->private_data; 720 void __iomem *base = priv->base; 721 unsigned int handled = 0; 722 struct ata_port *ap; 723 u32 sataintstat; 724 unsigned long flags; 725 726 spin_lock_irqsave(&host->lock, flags); 727 728 sataintstat = ioread32(base + SATAINTSTAT_REG); 729 sataintstat &= SATA_RCAR_INT_MASK; 730 if (!sataintstat) 731 goto done; 732 /* ack */ 733 iowrite32(~sataintstat & priv->sataint_mask, base + SATAINTSTAT_REG); 734 735 ap = host->ports[0]; 736 737 if (sataintstat & SATAINTSTAT_ATA) 738 sata_rcar_ata_interrupt(ap); 739 740 if (sataintstat & SATAINTSTAT_SERR) 741 sata_rcar_serr_interrupt(ap); 742 743 handled = 1; 744 done: 745 spin_unlock_irqrestore(&host->lock, flags); 746 747 return IRQ_RETVAL(handled); 748 } 749 750 static void sata_rcar_setup_port(struct ata_host *host) 751 { 752 struct ata_port *ap = host->ports[0]; 753 struct ata_ioports *ioaddr = &ap->ioaddr; 754 struct sata_rcar_priv *priv = host->private_data; 755 void __iomem *base = priv->base; 756 757 ap->ops = &sata_rcar_port_ops; 758 ap->pio_mask = ATA_PIO4; 759 ap->udma_mask = ATA_UDMA6; 760 ap->flags |= ATA_FLAG_SATA; 761 762 if (priv->type == RCAR_R8A7790_ES1_SATA) 763 ap->flags |= ATA_FLAG_NO_DIPM; 764 765 ioaddr->cmd_addr = base + SDATA_REG; 766 ioaddr->ctl_addr = base + SSDEVCON_REG; 767 ioaddr->scr_addr = base + SCRSSTS_REG; 768 ioaddr->altstatus_addr = ioaddr->ctl_addr; 769 770 ioaddr->data_addr = ioaddr->cmd_addr + (ATA_REG_DATA << 2); 771 ioaddr->error_addr = ioaddr->cmd_addr + (ATA_REG_ERR << 2); 772 ioaddr->feature_addr = ioaddr->cmd_addr + (ATA_REG_FEATURE << 2); 773 ioaddr->nsect_addr = ioaddr->cmd_addr + (ATA_REG_NSECT << 2); 774 ioaddr->lbal_addr = ioaddr->cmd_addr + (ATA_REG_LBAL << 2); 775 ioaddr->lbam_addr = ioaddr->cmd_addr + (ATA_REG_LBAM << 2); 776 ioaddr->lbah_addr = ioaddr->cmd_addr + (ATA_REG_LBAH << 2); 777 ioaddr->device_addr = ioaddr->cmd_addr + (ATA_REG_DEVICE << 2); 778 ioaddr->status_addr = ioaddr->cmd_addr + (ATA_REG_STATUS << 2); 779 ioaddr->command_addr = ioaddr->cmd_addr + (ATA_REG_CMD << 2); 780 } 781 782 static void sata_rcar_init_module(struct sata_rcar_priv *priv) 783 { 784 void __iomem *base = priv->base; 785 u32 val; 786 787 /* SATA-IP reset state */ 788 val = ioread32(base + ATAPI_CONTROL1_REG); 789 val |= ATAPI_CONTROL1_RESET; 790 iowrite32(val, base + ATAPI_CONTROL1_REG); 791 792 /* ISM mode, PRD mode, DTEND flag at bit 0 */ 793 val = ioread32(base + ATAPI_CONTROL1_REG); 794 val |= ATAPI_CONTROL1_ISM; 795 val |= ATAPI_CONTROL1_DESE; 796 val |= ATAPI_CONTROL1_DTA32M; 797 iowrite32(val, base + ATAPI_CONTROL1_REG); 798 799 /* Release the SATA-IP from the reset state */ 800 val = ioread32(base + ATAPI_CONTROL1_REG); 801 val &= ~ATAPI_CONTROL1_RESET; 802 iowrite32(val, base + ATAPI_CONTROL1_REG); 803 804 /* ack and mask */ 805 iowrite32(0, base + SATAINTSTAT_REG); 806 iowrite32(priv->sataint_mask, base + SATAINTMASK_REG); 807 808 /* enable interrupts */ 809 iowrite32(ATAPI_INT_ENABLE_SATAINT, base + ATAPI_INT_ENABLE_REG); 810 } 811 812 static void sata_rcar_init_controller(struct ata_host *host) 813 { 814 struct sata_rcar_priv *priv = host->private_data; 815 816 priv->sataint_mask = SATAINTMASK_ALL_GEN2; 817 818 /* reset and setup phy */ 819 switch (priv->type) { 820 case RCAR_GEN1_SATA: 821 priv->sataint_mask = SATAINTMASK_ALL_GEN1; 822 sata_rcar_gen1_phy_init(priv); 823 break; 824 case RCAR_GEN2_SATA: 825 case RCAR_R8A7790_ES1_SATA: 826 sata_rcar_gen2_phy_init(priv); 827 break; 828 case RCAR_GEN3_SATA: 829 break; 830 default: 831 dev_warn(host->dev, "SATA phy is not initialized\n"); 832 break; 833 } 834 835 sata_rcar_init_module(priv); 836 } 837 838 static const struct of_device_id sata_rcar_match[] = { 839 { 840 /* Deprecated by "renesas,sata-r8a7779" */ 841 .compatible = "renesas,rcar-sata", 842 .data = (void *)RCAR_GEN1_SATA, 843 }, 844 { 845 .compatible = "renesas,sata-r8a7779", 846 .data = (void *)RCAR_GEN1_SATA, 847 }, 848 { 849 .compatible = "renesas,sata-r8a7790", 850 .data = (void *)RCAR_GEN2_SATA 851 }, 852 { 853 .compatible = "renesas,sata-r8a7790-es1", 854 .data = (void *)RCAR_R8A7790_ES1_SATA 855 }, 856 { 857 .compatible = "renesas,sata-r8a7791", 858 .data = (void *)RCAR_GEN2_SATA 859 }, 860 { 861 .compatible = "renesas,sata-r8a7793", 862 .data = (void *)RCAR_GEN2_SATA 863 }, 864 { 865 .compatible = "renesas,sata-r8a7795", 866 .data = (void *)RCAR_GEN3_SATA 867 }, 868 { 869 .compatible = "renesas,rcar-gen2-sata", 870 .data = (void *)RCAR_GEN2_SATA 871 }, 872 { 873 .compatible = "renesas,rcar-gen3-sata", 874 .data = (void *)RCAR_GEN3_SATA 875 }, 876 { }, 877 }; 878 MODULE_DEVICE_TABLE(of, sata_rcar_match); 879 880 static int sata_rcar_probe(struct platform_device *pdev) 881 { 882 struct device *dev = &pdev->dev; 883 struct ata_host *host; 884 struct sata_rcar_priv *priv; 885 struct resource *mem; 886 int irq; 887 int ret = 0; 888 889 irq = platform_get_irq(pdev, 0); 890 if (irq < 0) 891 return irq; 892 if (!irq) 893 return -EINVAL; 894 895 priv = devm_kzalloc(dev, sizeof(struct sata_rcar_priv), GFP_KERNEL); 896 if (!priv) 897 return -ENOMEM; 898 899 priv->type = (enum sata_rcar_type)of_device_get_match_data(dev); 900 901 pm_runtime_enable(dev); 902 ret = pm_runtime_get_sync(dev); 903 if (ret < 0) 904 goto err_pm_put; 905 906 host = ata_host_alloc(dev, 1); 907 if (!host) { 908 ret = -ENOMEM; 909 goto err_pm_put; 910 } 911 912 host->private_data = priv; 913 914 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 915 priv->base = devm_ioremap_resource(dev, mem); 916 if (IS_ERR(priv->base)) { 917 ret = PTR_ERR(priv->base); 918 goto err_pm_put; 919 } 920 921 /* setup port */ 922 sata_rcar_setup_port(host); 923 924 /* initialize host controller */ 925 sata_rcar_init_controller(host); 926 927 ret = ata_host_activate(host, irq, sata_rcar_interrupt, 0, 928 &sata_rcar_sht); 929 if (!ret) 930 return 0; 931 932 err_pm_put: 933 pm_runtime_put(dev); 934 pm_runtime_disable(dev); 935 return ret; 936 } 937 938 static int sata_rcar_remove(struct platform_device *pdev) 939 { 940 struct ata_host *host = platform_get_drvdata(pdev); 941 struct sata_rcar_priv *priv = host->private_data; 942 void __iomem *base = priv->base; 943 944 ata_host_detach(host); 945 946 /* disable interrupts */ 947 iowrite32(0, base + ATAPI_INT_ENABLE_REG); 948 /* ack and mask */ 949 iowrite32(0, base + SATAINTSTAT_REG); 950 iowrite32(priv->sataint_mask, base + SATAINTMASK_REG); 951 952 pm_runtime_put(&pdev->dev); 953 pm_runtime_disable(&pdev->dev); 954 955 return 0; 956 } 957 958 #ifdef CONFIG_PM_SLEEP 959 static int sata_rcar_suspend(struct device *dev) 960 { 961 struct ata_host *host = dev_get_drvdata(dev); 962 struct sata_rcar_priv *priv = host->private_data; 963 void __iomem *base = priv->base; 964 int ret; 965 966 ret = ata_host_suspend(host, PMSG_SUSPEND); 967 if (!ret) { 968 /* disable interrupts */ 969 iowrite32(0, base + ATAPI_INT_ENABLE_REG); 970 /* mask */ 971 iowrite32(priv->sataint_mask, base + SATAINTMASK_REG); 972 973 pm_runtime_put(dev); 974 } 975 976 return ret; 977 } 978 979 static int sata_rcar_resume(struct device *dev) 980 { 981 struct ata_host *host = dev_get_drvdata(dev); 982 struct sata_rcar_priv *priv = host->private_data; 983 void __iomem *base = priv->base; 984 int ret; 985 986 ret = pm_runtime_get_sync(dev); 987 if (ret < 0) { 988 pm_runtime_put(dev); 989 return ret; 990 } 991 992 if (priv->type == RCAR_GEN3_SATA) { 993 sata_rcar_init_module(priv); 994 } else { 995 /* ack and mask */ 996 iowrite32(0, base + SATAINTSTAT_REG); 997 iowrite32(priv->sataint_mask, base + SATAINTMASK_REG); 998 999 /* enable interrupts */ 1000 iowrite32(ATAPI_INT_ENABLE_SATAINT, 1001 base + ATAPI_INT_ENABLE_REG); 1002 } 1003 1004 ata_host_resume(host); 1005 1006 return 0; 1007 } 1008 1009 static int sata_rcar_restore(struct device *dev) 1010 { 1011 struct ata_host *host = dev_get_drvdata(dev); 1012 int ret; 1013 1014 ret = pm_runtime_get_sync(dev); 1015 if (ret < 0) { 1016 pm_runtime_put(dev); 1017 return ret; 1018 } 1019 1020 sata_rcar_setup_port(host); 1021 1022 /* initialize host controller */ 1023 sata_rcar_init_controller(host); 1024 1025 ata_host_resume(host); 1026 1027 return 0; 1028 } 1029 1030 static const struct dev_pm_ops sata_rcar_pm_ops = { 1031 .suspend = sata_rcar_suspend, 1032 .resume = sata_rcar_resume, 1033 .freeze = sata_rcar_suspend, 1034 .thaw = sata_rcar_resume, 1035 .poweroff = sata_rcar_suspend, 1036 .restore = sata_rcar_restore, 1037 }; 1038 #endif 1039 1040 static struct platform_driver sata_rcar_driver = { 1041 .probe = sata_rcar_probe, 1042 .remove = sata_rcar_remove, 1043 .driver = { 1044 .name = DRV_NAME, 1045 .of_match_table = sata_rcar_match, 1046 #ifdef CONFIG_PM_SLEEP 1047 .pm = &sata_rcar_pm_ops, 1048 #endif 1049 }, 1050 }; 1051 1052 module_platform_driver(sata_rcar_driver); 1053 1054 MODULE_LICENSE("GPL"); 1055 MODULE_AUTHOR("Vladimir Barinov"); 1056 MODULE_DESCRIPTION("Renesas R-Car SATA controller low level driver"); 1057