1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Renesas R-Car SATA driver 4 * 5 * Author: Vladimir Barinov <source@cogentembedded.com> 6 * Copyright (C) 2013-2015 Cogent Embedded, Inc. 7 * Copyright (C) 2013-2015 Renesas Solutions Corp. 8 */ 9 10 #include <linux/kernel.h> 11 #include <linux/module.h> 12 #include <linux/ata.h> 13 #include <linux/libata.h> 14 #include <linux/of_device.h> 15 #include <linux/platform_device.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/err.h> 18 19 #define DRV_NAME "sata_rcar" 20 21 /* SH-Navi2G/ATAPI-ATA compatible task registers */ 22 #define DATA_REG 0x100 23 #define SDEVCON_REG 0x138 24 25 /* SH-Navi2G/ATAPI module compatible control registers */ 26 #define ATAPI_CONTROL1_REG 0x180 27 #define ATAPI_STATUS_REG 0x184 28 #define ATAPI_INT_ENABLE_REG 0x188 29 #define ATAPI_DTB_ADR_REG 0x198 30 #define ATAPI_DMA_START_ADR_REG 0x19C 31 #define ATAPI_DMA_TRANS_CNT_REG 0x1A0 32 #define ATAPI_CONTROL2_REG 0x1A4 33 #define ATAPI_SIG_ST_REG 0x1B0 34 #define ATAPI_BYTE_SWAP_REG 0x1BC 35 36 /* ATAPI control 1 register (ATAPI_CONTROL1) bits */ 37 #define ATAPI_CONTROL1_ISM BIT(16) 38 #define ATAPI_CONTROL1_DTA32M BIT(11) 39 #define ATAPI_CONTROL1_RESET BIT(7) 40 #define ATAPI_CONTROL1_DESE BIT(3) 41 #define ATAPI_CONTROL1_RW BIT(2) 42 #define ATAPI_CONTROL1_STOP BIT(1) 43 #define ATAPI_CONTROL1_START BIT(0) 44 45 /* ATAPI status register (ATAPI_STATUS) bits */ 46 #define ATAPI_STATUS_SATAINT BIT(11) 47 #define ATAPI_STATUS_DNEND BIT(6) 48 #define ATAPI_STATUS_DEVTRM BIT(5) 49 #define ATAPI_STATUS_DEVINT BIT(4) 50 #define ATAPI_STATUS_ERR BIT(2) 51 #define ATAPI_STATUS_NEND BIT(1) 52 #define ATAPI_STATUS_ACT BIT(0) 53 54 /* Interrupt enable register (ATAPI_INT_ENABLE) bits */ 55 #define ATAPI_INT_ENABLE_SATAINT BIT(11) 56 #define ATAPI_INT_ENABLE_DNEND BIT(6) 57 #define ATAPI_INT_ENABLE_DEVTRM BIT(5) 58 #define ATAPI_INT_ENABLE_DEVINT BIT(4) 59 #define ATAPI_INT_ENABLE_ERR BIT(2) 60 #define ATAPI_INT_ENABLE_NEND BIT(1) 61 #define ATAPI_INT_ENABLE_ACT BIT(0) 62 63 /* Access control registers for physical layer control register */ 64 #define SATAPHYADDR_REG 0x200 65 #define SATAPHYWDATA_REG 0x204 66 #define SATAPHYACCEN_REG 0x208 67 #define SATAPHYRESET_REG 0x20C 68 #define SATAPHYRDATA_REG 0x210 69 #define SATAPHYACK_REG 0x214 70 71 /* Physical layer control address command register (SATAPHYADDR) bits */ 72 #define SATAPHYADDR_PHYRATEMODE BIT(10) 73 #define SATAPHYADDR_PHYCMD_READ BIT(9) 74 #define SATAPHYADDR_PHYCMD_WRITE BIT(8) 75 76 /* Physical layer control enable register (SATAPHYACCEN) bits */ 77 #define SATAPHYACCEN_PHYLANE BIT(0) 78 79 /* Physical layer control reset register (SATAPHYRESET) bits */ 80 #define SATAPHYRESET_PHYRST BIT(1) 81 #define SATAPHYRESET_PHYSRES BIT(0) 82 83 /* Physical layer control acknowledge register (SATAPHYACK) bits */ 84 #define SATAPHYACK_PHYACK BIT(0) 85 86 /* Serial-ATA HOST control registers */ 87 #define BISTCONF_REG 0x102C 88 #define SDATA_REG 0x1100 89 #define SSDEVCON_REG 0x1204 90 91 #define SCRSSTS_REG 0x1400 92 #define SCRSERR_REG 0x1404 93 #define SCRSCON_REG 0x1408 94 #define SCRSACT_REG 0x140C 95 96 #define SATAINTSTAT_REG 0x1508 97 #define SATAINTMASK_REG 0x150C 98 99 /* SATA INT status register (SATAINTSTAT) bits */ 100 #define SATAINTSTAT_SERR BIT(3) 101 #define SATAINTSTAT_ATA BIT(0) 102 103 /* SATA INT mask register (SATAINTSTAT) bits */ 104 #define SATAINTMASK_SERRMSK BIT(3) 105 #define SATAINTMASK_ERRMSK BIT(2) 106 #define SATAINTMASK_ERRCRTMSK BIT(1) 107 #define SATAINTMASK_ATAMSK BIT(0) 108 #define SATAINTMASK_ALL_GEN1 0x7ff 109 #define SATAINTMASK_ALL_GEN2 0xfff 110 111 #define SATA_RCAR_INT_MASK (SATAINTMASK_SERRMSK | \ 112 SATAINTMASK_ATAMSK) 113 114 /* Physical Layer Control Registers */ 115 #define SATAPCTLR1_REG 0x43 116 #define SATAPCTLR2_REG 0x52 117 #define SATAPCTLR3_REG 0x5A 118 #define SATAPCTLR4_REG 0x60 119 120 /* Descriptor table word 0 bit (when DTA32M = 1) */ 121 #define SATA_RCAR_DTEND BIT(0) 122 123 #define SATA_RCAR_DMA_BOUNDARY 0x1FFFFFFFUL 124 125 /* Gen2 Physical Layer Control Registers */ 126 #define RCAR_GEN2_PHY_CTL1_REG 0x1704 127 #define RCAR_GEN2_PHY_CTL1 0x34180002 128 #define RCAR_GEN2_PHY_CTL1_SS 0xC180 /* Spread Spectrum */ 129 130 #define RCAR_GEN2_PHY_CTL2_REG 0x170C 131 #define RCAR_GEN2_PHY_CTL2 0x00002303 132 133 #define RCAR_GEN2_PHY_CTL3_REG 0x171C 134 #define RCAR_GEN2_PHY_CTL3 0x000B0194 135 136 #define RCAR_GEN2_PHY_CTL4_REG 0x1724 137 #define RCAR_GEN2_PHY_CTL4 0x00030994 138 139 #define RCAR_GEN2_PHY_CTL5_REG 0x1740 140 #define RCAR_GEN2_PHY_CTL5 0x03004001 141 #define RCAR_GEN2_PHY_CTL5_DC BIT(1) /* DC connection */ 142 #define RCAR_GEN2_PHY_CTL5_TR BIT(2) /* Termination Resistor */ 143 144 enum sata_rcar_type { 145 RCAR_GEN1_SATA, 146 RCAR_GEN2_SATA, 147 RCAR_GEN3_SATA, 148 RCAR_R8A7790_ES1_SATA, 149 }; 150 151 struct sata_rcar_priv { 152 void __iomem *base; 153 u32 sataint_mask; 154 enum sata_rcar_type type; 155 }; 156 157 static void sata_rcar_gen1_phy_preinit(struct sata_rcar_priv *priv) 158 { 159 void __iomem *base = priv->base; 160 161 /* idle state */ 162 iowrite32(0, base + SATAPHYADDR_REG); 163 /* reset */ 164 iowrite32(SATAPHYRESET_PHYRST, base + SATAPHYRESET_REG); 165 udelay(10); 166 /* deassert reset */ 167 iowrite32(0, base + SATAPHYRESET_REG); 168 } 169 170 static void sata_rcar_gen1_phy_write(struct sata_rcar_priv *priv, u16 reg, 171 u32 val, int group) 172 { 173 void __iomem *base = priv->base; 174 int timeout; 175 176 /* deassert reset */ 177 iowrite32(0, base + SATAPHYRESET_REG); 178 /* lane 1 */ 179 iowrite32(SATAPHYACCEN_PHYLANE, base + SATAPHYACCEN_REG); 180 /* write phy register value */ 181 iowrite32(val, base + SATAPHYWDATA_REG); 182 /* set register group */ 183 if (group) 184 reg |= SATAPHYADDR_PHYRATEMODE; 185 /* write command */ 186 iowrite32(SATAPHYADDR_PHYCMD_WRITE | reg, base + SATAPHYADDR_REG); 187 /* wait for ack */ 188 for (timeout = 0; timeout < 100; timeout++) { 189 val = ioread32(base + SATAPHYACK_REG); 190 if (val & SATAPHYACK_PHYACK) 191 break; 192 } 193 if (timeout >= 100) 194 pr_err("%s timeout\n", __func__); 195 /* idle state */ 196 iowrite32(0, base + SATAPHYADDR_REG); 197 } 198 199 static void sata_rcar_gen1_phy_init(struct sata_rcar_priv *priv) 200 { 201 sata_rcar_gen1_phy_preinit(priv); 202 sata_rcar_gen1_phy_write(priv, SATAPCTLR1_REG, 0x00200188, 0); 203 sata_rcar_gen1_phy_write(priv, SATAPCTLR1_REG, 0x00200188, 1); 204 sata_rcar_gen1_phy_write(priv, SATAPCTLR3_REG, 0x0000A061, 0); 205 sata_rcar_gen1_phy_write(priv, SATAPCTLR2_REG, 0x20000000, 0); 206 sata_rcar_gen1_phy_write(priv, SATAPCTLR2_REG, 0x20000000, 1); 207 sata_rcar_gen1_phy_write(priv, SATAPCTLR4_REG, 0x28E80000, 0); 208 } 209 210 static void sata_rcar_gen2_phy_init(struct sata_rcar_priv *priv) 211 { 212 void __iomem *base = priv->base; 213 214 iowrite32(RCAR_GEN2_PHY_CTL1, base + RCAR_GEN2_PHY_CTL1_REG); 215 iowrite32(RCAR_GEN2_PHY_CTL2, base + RCAR_GEN2_PHY_CTL2_REG); 216 iowrite32(RCAR_GEN2_PHY_CTL3, base + RCAR_GEN2_PHY_CTL3_REG); 217 iowrite32(RCAR_GEN2_PHY_CTL4, base + RCAR_GEN2_PHY_CTL4_REG); 218 iowrite32(RCAR_GEN2_PHY_CTL5 | RCAR_GEN2_PHY_CTL5_DC | 219 RCAR_GEN2_PHY_CTL5_TR, base + RCAR_GEN2_PHY_CTL5_REG); 220 } 221 222 static void sata_rcar_freeze(struct ata_port *ap) 223 { 224 struct sata_rcar_priv *priv = ap->host->private_data; 225 226 /* mask */ 227 iowrite32(priv->sataint_mask, priv->base + SATAINTMASK_REG); 228 229 ata_sff_freeze(ap); 230 } 231 232 static void sata_rcar_thaw(struct ata_port *ap) 233 { 234 struct sata_rcar_priv *priv = ap->host->private_data; 235 void __iomem *base = priv->base; 236 237 /* ack */ 238 iowrite32(~(u32)SATA_RCAR_INT_MASK, base + SATAINTSTAT_REG); 239 240 ata_sff_thaw(ap); 241 242 /* unmask */ 243 iowrite32(priv->sataint_mask & ~SATA_RCAR_INT_MASK, base + SATAINTMASK_REG); 244 } 245 246 static void sata_rcar_ioread16_rep(void __iomem *reg, void *buffer, int count) 247 { 248 u16 *ptr = buffer; 249 250 while (count--) { 251 u16 data = ioread32(reg); 252 253 *ptr++ = data; 254 } 255 } 256 257 static void sata_rcar_iowrite16_rep(void __iomem *reg, void *buffer, int count) 258 { 259 const u16 *ptr = buffer; 260 261 while (count--) 262 iowrite32(*ptr++, reg); 263 } 264 265 static u8 sata_rcar_check_status(struct ata_port *ap) 266 { 267 return ioread32(ap->ioaddr.status_addr); 268 } 269 270 static u8 sata_rcar_check_altstatus(struct ata_port *ap) 271 { 272 return ioread32(ap->ioaddr.altstatus_addr); 273 } 274 275 static void sata_rcar_set_devctl(struct ata_port *ap, u8 ctl) 276 { 277 iowrite32(ctl, ap->ioaddr.ctl_addr); 278 } 279 280 static void sata_rcar_dev_select(struct ata_port *ap, unsigned int device) 281 { 282 iowrite32(ATA_DEVICE_OBS, ap->ioaddr.device_addr); 283 ata_sff_pause(ap); /* needed; also flushes, for mmio */ 284 } 285 286 static bool sata_rcar_ata_devchk(struct ata_port *ap, unsigned int device) 287 { 288 struct ata_ioports *ioaddr = &ap->ioaddr; 289 u8 nsect, lbal; 290 291 sata_rcar_dev_select(ap, device); 292 293 iowrite32(0x55, ioaddr->nsect_addr); 294 iowrite32(0xaa, ioaddr->lbal_addr); 295 296 iowrite32(0xaa, ioaddr->nsect_addr); 297 iowrite32(0x55, ioaddr->lbal_addr); 298 299 iowrite32(0x55, ioaddr->nsect_addr); 300 iowrite32(0xaa, ioaddr->lbal_addr); 301 302 nsect = ioread32(ioaddr->nsect_addr); 303 lbal = ioread32(ioaddr->lbal_addr); 304 305 if (nsect == 0x55 && lbal == 0xaa) 306 return true; /* found a device */ 307 308 return false; /* nothing found */ 309 } 310 311 static int sata_rcar_wait_after_reset(struct ata_link *link, 312 unsigned long deadline) 313 { 314 struct ata_port *ap = link->ap; 315 316 ata_msleep(ap, ATA_WAIT_AFTER_RESET); 317 318 return ata_sff_wait_ready(link, deadline); 319 } 320 321 static int sata_rcar_bus_softreset(struct ata_port *ap, unsigned long deadline) 322 { 323 struct ata_ioports *ioaddr = &ap->ioaddr; 324 325 /* software reset. causes dev0 to be selected */ 326 iowrite32(ap->ctl, ioaddr->ctl_addr); 327 udelay(20); 328 iowrite32(ap->ctl | ATA_SRST, ioaddr->ctl_addr); 329 udelay(20); 330 iowrite32(ap->ctl, ioaddr->ctl_addr); 331 ap->last_ctl = ap->ctl; 332 333 /* wait the port to become ready */ 334 return sata_rcar_wait_after_reset(&ap->link, deadline); 335 } 336 337 static int sata_rcar_softreset(struct ata_link *link, unsigned int *classes, 338 unsigned long deadline) 339 { 340 struct ata_port *ap = link->ap; 341 unsigned int devmask = 0; 342 int rc; 343 u8 err; 344 345 /* determine if device 0 is present */ 346 if (sata_rcar_ata_devchk(ap, 0)) 347 devmask |= 1 << 0; 348 349 /* issue bus reset */ 350 rc = sata_rcar_bus_softreset(ap, deadline); 351 /* if link is occupied, -ENODEV too is an error */ 352 if (rc && (rc != -ENODEV || sata_scr_valid(link))) { 353 ata_link_err(link, "SRST failed (errno=%d)\n", rc); 354 return rc; 355 } 356 357 /* determine by signature whether we have ATA or ATAPI devices */ 358 classes[0] = ata_sff_dev_classify(&link->device[0], devmask, &err); 359 360 return 0; 361 } 362 363 static void sata_rcar_tf_load(struct ata_port *ap, 364 const struct ata_taskfile *tf) 365 { 366 struct ata_ioports *ioaddr = &ap->ioaddr; 367 unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR; 368 369 if (tf->ctl != ap->last_ctl) { 370 iowrite32(tf->ctl, ioaddr->ctl_addr); 371 ap->last_ctl = tf->ctl; 372 ata_wait_idle(ap); 373 } 374 375 if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) { 376 iowrite32(tf->hob_feature, ioaddr->feature_addr); 377 iowrite32(tf->hob_nsect, ioaddr->nsect_addr); 378 iowrite32(tf->hob_lbal, ioaddr->lbal_addr); 379 iowrite32(tf->hob_lbam, ioaddr->lbam_addr); 380 iowrite32(tf->hob_lbah, ioaddr->lbah_addr); 381 } 382 383 if (is_addr) { 384 iowrite32(tf->feature, ioaddr->feature_addr); 385 iowrite32(tf->nsect, ioaddr->nsect_addr); 386 iowrite32(tf->lbal, ioaddr->lbal_addr); 387 iowrite32(tf->lbam, ioaddr->lbam_addr); 388 iowrite32(tf->lbah, ioaddr->lbah_addr); 389 } 390 391 if (tf->flags & ATA_TFLAG_DEVICE) 392 iowrite32(tf->device, ioaddr->device_addr); 393 394 ata_wait_idle(ap); 395 } 396 397 static void sata_rcar_tf_read(struct ata_port *ap, struct ata_taskfile *tf) 398 { 399 struct ata_ioports *ioaddr = &ap->ioaddr; 400 401 tf->command = sata_rcar_check_status(ap); 402 tf->feature = ioread32(ioaddr->error_addr); 403 tf->nsect = ioread32(ioaddr->nsect_addr); 404 tf->lbal = ioread32(ioaddr->lbal_addr); 405 tf->lbam = ioread32(ioaddr->lbam_addr); 406 tf->lbah = ioread32(ioaddr->lbah_addr); 407 tf->device = ioread32(ioaddr->device_addr); 408 409 if (tf->flags & ATA_TFLAG_LBA48) { 410 iowrite32(tf->ctl | ATA_HOB, ioaddr->ctl_addr); 411 tf->hob_feature = ioread32(ioaddr->error_addr); 412 tf->hob_nsect = ioread32(ioaddr->nsect_addr); 413 tf->hob_lbal = ioread32(ioaddr->lbal_addr); 414 tf->hob_lbam = ioread32(ioaddr->lbam_addr); 415 tf->hob_lbah = ioread32(ioaddr->lbah_addr); 416 iowrite32(tf->ctl, ioaddr->ctl_addr); 417 ap->last_ctl = tf->ctl; 418 } 419 } 420 421 static void sata_rcar_exec_command(struct ata_port *ap, 422 const struct ata_taskfile *tf) 423 { 424 iowrite32(tf->command, ap->ioaddr.command_addr); 425 ata_sff_pause(ap); 426 } 427 428 static unsigned int sata_rcar_data_xfer(struct ata_queued_cmd *qc, 429 unsigned char *buf, 430 unsigned int buflen, int rw) 431 { 432 struct ata_port *ap = qc->dev->link->ap; 433 void __iomem *data_addr = ap->ioaddr.data_addr; 434 unsigned int words = buflen >> 1; 435 436 /* Transfer multiple of 2 bytes */ 437 if (rw == READ) 438 sata_rcar_ioread16_rep(data_addr, buf, words); 439 else 440 sata_rcar_iowrite16_rep(data_addr, buf, words); 441 442 /* Transfer trailing byte, if any. */ 443 if (unlikely(buflen & 0x01)) { 444 unsigned char pad[2] = { }; 445 446 /* Point buf to the tail of buffer */ 447 buf += buflen - 1; 448 449 /* 450 * Use io*16_rep() accessors here as well to avoid pointlessly 451 * swapping bytes to and from on the big endian machines... 452 */ 453 if (rw == READ) { 454 sata_rcar_ioread16_rep(data_addr, pad, 1); 455 *buf = pad[0]; 456 } else { 457 pad[0] = *buf; 458 sata_rcar_iowrite16_rep(data_addr, pad, 1); 459 } 460 words++; 461 } 462 463 return words << 1; 464 } 465 466 static void sata_rcar_drain_fifo(struct ata_queued_cmd *qc) 467 { 468 int count; 469 struct ata_port *ap; 470 471 /* We only need to flush incoming data when a command was running */ 472 if (qc == NULL || qc->dma_dir == DMA_TO_DEVICE) 473 return; 474 475 ap = qc->ap; 476 /* Drain up to 64K of data before we give up this recovery method */ 477 for (count = 0; (ap->ops->sff_check_status(ap) & ATA_DRQ) && 478 count < 65536; count += 2) 479 ioread32(ap->ioaddr.data_addr); 480 481 if (count) 482 ata_port_dbg(ap, "drained %d bytes to clear DRQ\n", count); 483 } 484 485 static int sata_rcar_scr_read(struct ata_link *link, unsigned int sc_reg, 486 u32 *val) 487 { 488 if (sc_reg > SCR_ACTIVE) 489 return -EINVAL; 490 491 *val = ioread32(link->ap->ioaddr.scr_addr + (sc_reg << 2)); 492 return 0; 493 } 494 495 static int sata_rcar_scr_write(struct ata_link *link, unsigned int sc_reg, 496 u32 val) 497 { 498 if (sc_reg > SCR_ACTIVE) 499 return -EINVAL; 500 501 iowrite32(val, link->ap->ioaddr.scr_addr + (sc_reg << 2)); 502 return 0; 503 } 504 505 static void sata_rcar_bmdma_fill_sg(struct ata_queued_cmd *qc) 506 { 507 struct ata_port *ap = qc->ap; 508 struct ata_bmdma_prd *prd = ap->bmdma_prd; 509 struct scatterlist *sg; 510 unsigned int si; 511 512 for_each_sg(qc->sg, sg, qc->n_elem, si) { 513 u32 addr, sg_len; 514 515 /* 516 * Note: h/w doesn't support 64-bit, so we unconditionally 517 * truncate dma_addr_t to u32. 518 */ 519 addr = (u32)sg_dma_address(sg); 520 sg_len = sg_dma_len(sg); 521 522 prd[si].addr = cpu_to_le32(addr); 523 prd[si].flags_len = cpu_to_le32(sg_len); 524 } 525 526 /* end-of-table flag */ 527 prd[si - 1].addr |= cpu_to_le32(SATA_RCAR_DTEND); 528 } 529 530 static enum ata_completion_errors sata_rcar_qc_prep(struct ata_queued_cmd *qc) 531 { 532 if (!(qc->flags & ATA_QCFLAG_DMAMAP)) 533 return AC_ERR_OK; 534 535 sata_rcar_bmdma_fill_sg(qc); 536 537 return AC_ERR_OK; 538 } 539 540 static void sata_rcar_bmdma_setup(struct ata_queued_cmd *qc) 541 { 542 struct ata_port *ap = qc->ap; 543 unsigned int rw = qc->tf.flags & ATA_TFLAG_WRITE; 544 struct sata_rcar_priv *priv = ap->host->private_data; 545 void __iomem *base = priv->base; 546 u32 dmactl; 547 548 /* load PRD table addr. */ 549 mb(); /* make sure PRD table writes are visible to controller */ 550 iowrite32(ap->bmdma_prd_dma, base + ATAPI_DTB_ADR_REG); 551 552 /* specify data direction, triple-check start bit is clear */ 553 dmactl = ioread32(base + ATAPI_CONTROL1_REG); 554 dmactl &= ~(ATAPI_CONTROL1_RW | ATAPI_CONTROL1_STOP); 555 if (dmactl & ATAPI_CONTROL1_START) { 556 dmactl &= ~ATAPI_CONTROL1_START; 557 dmactl |= ATAPI_CONTROL1_STOP; 558 } 559 if (!rw) 560 dmactl |= ATAPI_CONTROL1_RW; 561 iowrite32(dmactl, base + ATAPI_CONTROL1_REG); 562 563 /* issue r/w command */ 564 ap->ops->sff_exec_command(ap, &qc->tf); 565 } 566 567 static void sata_rcar_bmdma_start(struct ata_queued_cmd *qc) 568 { 569 struct ata_port *ap = qc->ap; 570 struct sata_rcar_priv *priv = ap->host->private_data; 571 void __iomem *base = priv->base; 572 u32 dmactl; 573 574 /* start host DMA transaction */ 575 dmactl = ioread32(base + ATAPI_CONTROL1_REG); 576 dmactl &= ~ATAPI_CONTROL1_STOP; 577 dmactl |= ATAPI_CONTROL1_START; 578 iowrite32(dmactl, base + ATAPI_CONTROL1_REG); 579 } 580 581 static void sata_rcar_bmdma_stop(struct ata_queued_cmd *qc) 582 { 583 struct ata_port *ap = qc->ap; 584 struct sata_rcar_priv *priv = ap->host->private_data; 585 void __iomem *base = priv->base; 586 u32 dmactl; 587 588 /* force termination of DMA transfer if active */ 589 dmactl = ioread32(base + ATAPI_CONTROL1_REG); 590 if (dmactl & ATAPI_CONTROL1_START) { 591 dmactl &= ~ATAPI_CONTROL1_START; 592 dmactl |= ATAPI_CONTROL1_STOP; 593 iowrite32(dmactl, base + ATAPI_CONTROL1_REG); 594 } 595 596 /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */ 597 ata_sff_dma_pause(ap); 598 } 599 600 static u8 sata_rcar_bmdma_status(struct ata_port *ap) 601 { 602 struct sata_rcar_priv *priv = ap->host->private_data; 603 u8 host_stat = 0; 604 u32 status; 605 606 status = ioread32(priv->base + ATAPI_STATUS_REG); 607 if (status & ATAPI_STATUS_DEVINT) 608 host_stat |= ATA_DMA_INTR; 609 if (status & ATAPI_STATUS_ACT) 610 host_stat |= ATA_DMA_ACTIVE; 611 612 return host_stat; 613 } 614 615 static struct scsi_host_template sata_rcar_sht = { 616 ATA_BASE_SHT(DRV_NAME), 617 /* 618 * This controller allows transfer chunks up to 512MB which cross 64KB 619 * boundaries, therefore the DMA limits are more relaxed than standard 620 * ATA SFF. 621 */ 622 .sg_tablesize = ATA_MAX_PRD, 623 .dma_boundary = SATA_RCAR_DMA_BOUNDARY, 624 }; 625 626 static struct ata_port_operations sata_rcar_port_ops = { 627 .inherits = &ata_bmdma_port_ops, 628 629 .freeze = sata_rcar_freeze, 630 .thaw = sata_rcar_thaw, 631 .softreset = sata_rcar_softreset, 632 633 .scr_read = sata_rcar_scr_read, 634 .scr_write = sata_rcar_scr_write, 635 636 .sff_dev_select = sata_rcar_dev_select, 637 .sff_set_devctl = sata_rcar_set_devctl, 638 .sff_check_status = sata_rcar_check_status, 639 .sff_check_altstatus = sata_rcar_check_altstatus, 640 .sff_tf_load = sata_rcar_tf_load, 641 .sff_tf_read = sata_rcar_tf_read, 642 .sff_exec_command = sata_rcar_exec_command, 643 .sff_data_xfer = sata_rcar_data_xfer, 644 .sff_drain_fifo = sata_rcar_drain_fifo, 645 646 .qc_prep = sata_rcar_qc_prep, 647 648 .bmdma_setup = sata_rcar_bmdma_setup, 649 .bmdma_start = sata_rcar_bmdma_start, 650 .bmdma_stop = sata_rcar_bmdma_stop, 651 .bmdma_status = sata_rcar_bmdma_status, 652 }; 653 654 static void sata_rcar_serr_interrupt(struct ata_port *ap) 655 { 656 struct sata_rcar_priv *priv = ap->host->private_data; 657 struct ata_eh_info *ehi = &ap->link.eh_info; 658 int freeze = 0; 659 u32 serror; 660 661 serror = ioread32(priv->base + SCRSERR_REG); 662 if (!serror) 663 return; 664 665 ata_port_dbg(ap, "SError @host_intr: 0x%x\n", serror); 666 667 /* first, analyze and record host port events */ 668 ata_ehi_clear_desc(ehi); 669 670 if (serror & (SERR_DEV_XCHG | SERR_PHYRDY_CHG)) { 671 /* Setup a soft-reset EH action */ 672 ata_ehi_hotplugged(ehi); 673 ata_ehi_push_desc(ehi, "%s", "hotplug"); 674 675 freeze = serror & SERR_COMM_WAKE ? 0 : 1; 676 } 677 678 /* freeze or abort */ 679 if (freeze) 680 ata_port_freeze(ap); 681 else 682 ata_port_abort(ap); 683 } 684 685 static void sata_rcar_ata_interrupt(struct ata_port *ap) 686 { 687 struct ata_queued_cmd *qc; 688 int handled = 0; 689 690 qc = ata_qc_from_tag(ap, ap->link.active_tag); 691 if (qc) 692 handled |= ata_bmdma_port_intr(ap, qc); 693 694 /* be sure to clear ATA interrupt */ 695 if (!handled) 696 sata_rcar_check_status(ap); 697 } 698 699 static irqreturn_t sata_rcar_interrupt(int irq, void *dev_instance) 700 { 701 struct ata_host *host = dev_instance; 702 struct sata_rcar_priv *priv = host->private_data; 703 void __iomem *base = priv->base; 704 unsigned int handled = 0; 705 struct ata_port *ap; 706 u32 sataintstat; 707 unsigned long flags; 708 709 spin_lock_irqsave(&host->lock, flags); 710 711 sataintstat = ioread32(base + SATAINTSTAT_REG); 712 sataintstat &= SATA_RCAR_INT_MASK; 713 if (!sataintstat) 714 goto done; 715 /* ack */ 716 iowrite32(~sataintstat & priv->sataint_mask, base + SATAINTSTAT_REG); 717 718 ap = host->ports[0]; 719 720 if (sataintstat & SATAINTSTAT_ATA) 721 sata_rcar_ata_interrupt(ap); 722 723 if (sataintstat & SATAINTSTAT_SERR) 724 sata_rcar_serr_interrupt(ap); 725 726 handled = 1; 727 done: 728 spin_unlock_irqrestore(&host->lock, flags); 729 730 return IRQ_RETVAL(handled); 731 } 732 733 static void sata_rcar_setup_port(struct ata_host *host) 734 { 735 struct ata_port *ap = host->ports[0]; 736 struct ata_ioports *ioaddr = &ap->ioaddr; 737 struct sata_rcar_priv *priv = host->private_data; 738 void __iomem *base = priv->base; 739 740 ap->ops = &sata_rcar_port_ops; 741 ap->pio_mask = ATA_PIO4; 742 ap->udma_mask = ATA_UDMA6; 743 ap->flags |= ATA_FLAG_SATA; 744 745 if (priv->type == RCAR_R8A7790_ES1_SATA) 746 ap->flags |= ATA_FLAG_NO_DIPM; 747 748 ioaddr->cmd_addr = base + SDATA_REG; 749 ioaddr->ctl_addr = base + SSDEVCON_REG; 750 ioaddr->scr_addr = base + SCRSSTS_REG; 751 ioaddr->altstatus_addr = ioaddr->ctl_addr; 752 753 ioaddr->data_addr = ioaddr->cmd_addr + (ATA_REG_DATA << 2); 754 ioaddr->error_addr = ioaddr->cmd_addr + (ATA_REG_ERR << 2); 755 ioaddr->feature_addr = ioaddr->cmd_addr + (ATA_REG_FEATURE << 2); 756 ioaddr->nsect_addr = ioaddr->cmd_addr + (ATA_REG_NSECT << 2); 757 ioaddr->lbal_addr = ioaddr->cmd_addr + (ATA_REG_LBAL << 2); 758 ioaddr->lbam_addr = ioaddr->cmd_addr + (ATA_REG_LBAM << 2); 759 ioaddr->lbah_addr = ioaddr->cmd_addr + (ATA_REG_LBAH << 2); 760 ioaddr->device_addr = ioaddr->cmd_addr + (ATA_REG_DEVICE << 2); 761 ioaddr->status_addr = ioaddr->cmd_addr + (ATA_REG_STATUS << 2); 762 ioaddr->command_addr = ioaddr->cmd_addr + (ATA_REG_CMD << 2); 763 } 764 765 static void sata_rcar_init_module(struct sata_rcar_priv *priv) 766 { 767 void __iomem *base = priv->base; 768 u32 val; 769 770 /* SATA-IP reset state */ 771 val = ioread32(base + ATAPI_CONTROL1_REG); 772 val |= ATAPI_CONTROL1_RESET; 773 iowrite32(val, base + ATAPI_CONTROL1_REG); 774 775 /* ISM mode, PRD mode, DTEND flag at bit 0 */ 776 val = ioread32(base + ATAPI_CONTROL1_REG); 777 val |= ATAPI_CONTROL1_ISM; 778 val |= ATAPI_CONTROL1_DESE; 779 val |= ATAPI_CONTROL1_DTA32M; 780 iowrite32(val, base + ATAPI_CONTROL1_REG); 781 782 /* Release the SATA-IP from the reset state */ 783 val = ioread32(base + ATAPI_CONTROL1_REG); 784 val &= ~ATAPI_CONTROL1_RESET; 785 iowrite32(val, base + ATAPI_CONTROL1_REG); 786 787 /* ack and mask */ 788 iowrite32(0, base + SATAINTSTAT_REG); 789 iowrite32(priv->sataint_mask, base + SATAINTMASK_REG); 790 791 /* enable interrupts */ 792 iowrite32(ATAPI_INT_ENABLE_SATAINT, base + ATAPI_INT_ENABLE_REG); 793 } 794 795 static void sata_rcar_init_controller(struct ata_host *host) 796 { 797 struct sata_rcar_priv *priv = host->private_data; 798 799 priv->sataint_mask = SATAINTMASK_ALL_GEN2; 800 801 /* reset and setup phy */ 802 switch (priv->type) { 803 case RCAR_GEN1_SATA: 804 priv->sataint_mask = SATAINTMASK_ALL_GEN1; 805 sata_rcar_gen1_phy_init(priv); 806 break; 807 case RCAR_GEN2_SATA: 808 case RCAR_R8A7790_ES1_SATA: 809 sata_rcar_gen2_phy_init(priv); 810 break; 811 case RCAR_GEN3_SATA: 812 break; 813 default: 814 dev_warn(host->dev, "SATA phy is not initialized\n"); 815 break; 816 } 817 818 sata_rcar_init_module(priv); 819 } 820 821 static const struct of_device_id sata_rcar_match[] = { 822 { 823 /* Deprecated by "renesas,sata-r8a7779" */ 824 .compatible = "renesas,rcar-sata", 825 .data = (void *)RCAR_GEN1_SATA, 826 }, 827 { 828 .compatible = "renesas,sata-r8a7779", 829 .data = (void *)RCAR_GEN1_SATA, 830 }, 831 { 832 .compatible = "renesas,sata-r8a7790", 833 .data = (void *)RCAR_GEN2_SATA 834 }, 835 { 836 .compatible = "renesas,sata-r8a7790-es1", 837 .data = (void *)RCAR_R8A7790_ES1_SATA 838 }, 839 { 840 .compatible = "renesas,sata-r8a7791", 841 .data = (void *)RCAR_GEN2_SATA 842 }, 843 { 844 .compatible = "renesas,sata-r8a7793", 845 .data = (void *)RCAR_GEN2_SATA 846 }, 847 { 848 .compatible = "renesas,sata-r8a7795", 849 .data = (void *)RCAR_GEN3_SATA 850 }, 851 { 852 .compatible = "renesas,rcar-gen2-sata", 853 .data = (void *)RCAR_GEN2_SATA 854 }, 855 { 856 .compatible = "renesas,rcar-gen3-sata", 857 .data = (void *)RCAR_GEN3_SATA 858 }, 859 { }, 860 }; 861 MODULE_DEVICE_TABLE(of, sata_rcar_match); 862 863 static int sata_rcar_probe(struct platform_device *pdev) 864 { 865 struct device *dev = &pdev->dev; 866 struct ata_host *host; 867 struct sata_rcar_priv *priv; 868 struct resource *mem; 869 int irq; 870 int ret = 0; 871 872 irq = platform_get_irq(pdev, 0); 873 if (irq < 0) 874 return irq; 875 if (!irq) 876 return -EINVAL; 877 878 priv = devm_kzalloc(dev, sizeof(struct sata_rcar_priv), GFP_KERNEL); 879 if (!priv) 880 return -ENOMEM; 881 882 priv->type = (enum sata_rcar_type)of_device_get_match_data(dev); 883 884 pm_runtime_enable(dev); 885 ret = pm_runtime_get_sync(dev); 886 if (ret < 0) 887 goto err_pm_put; 888 889 host = ata_host_alloc(dev, 1); 890 if (!host) { 891 ret = -ENOMEM; 892 goto err_pm_put; 893 } 894 895 host->private_data = priv; 896 897 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 898 priv->base = devm_ioremap_resource(dev, mem); 899 if (IS_ERR(priv->base)) { 900 ret = PTR_ERR(priv->base); 901 goto err_pm_put; 902 } 903 904 /* setup port */ 905 sata_rcar_setup_port(host); 906 907 /* initialize host controller */ 908 sata_rcar_init_controller(host); 909 910 ret = ata_host_activate(host, irq, sata_rcar_interrupt, 0, 911 &sata_rcar_sht); 912 if (!ret) 913 return 0; 914 915 err_pm_put: 916 pm_runtime_put(dev); 917 pm_runtime_disable(dev); 918 return ret; 919 } 920 921 static int sata_rcar_remove(struct platform_device *pdev) 922 { 923 struct ata_host *host = platform_get_drvdata(pdev); 924 struct sata_rcar_priv *priv = host->private_data; 925 void __iomem *base = priv->base; 926 927 ata_host_detach(host); 928 929 /* disable interrupts */ 930 iowrite32(0, base + ATAPI_INT_ENABLE_REG); 931 /* ack and mask */ 932 iowrite32(0, base + SATAINTSTAT_REG); 933 iowrite32(priv->sataint_mask, base + SATAINTMASK_REG); 934 935 pm_runtime_put(&pdev->dev); 936 pm_runtime_disable(&pdev->dev); 937 938 return 0; 939 } 940 941 #ifdef CONFIG_PM_SLEEP 942 static int sata_rcar_suspend(struct device *dev) 943 { 944 struct ata_host *host = dev_get_drvdata(dev); 945 struct sata_rcar_priv *priv = host->private_data; 946 void __iomem *base = priv->base; 947 948 ata_host_suspend(host, PMSG_SUSPEND); 949 950 /* disable interrupts */ 951 iowrite32(0, base + ATAPI_INT_ENABLE_REG); 952 /* mask */ 953 iowrite32(priv->sataint_mask, base + SATAINTMASK_REG); 954 955 pm_runtime_put(dev); 956 957 return 0; 958 } 959 960 static int sata_rcar_resume(struct device *dev) 961 { 962 struct ata_host *host = dev_get_drvdata(dev); 963 struct sata_rcar_priv *priv = host->private_data; 964 void __iomem *base = priv->base; 965 int ret; 966 967 ret = pm_runtime_get_sync(dev); 968 if (ret < 0) { 969 pm_runtime_put(dev); 970 return ret; 971 } 972 973 if (priv->type == RCAR_GEN3_SATA) { 974 sata_rcar_init_module(priv); 975 } else { 976 /* ack and mask */ 977 iowrite32(0, base + SATAINTSTAT_REG); 978 iowrite32(priv->sataint_mask, base + SATAINTMASK_REG); 979 980 /* enable interrupts */ 981 iowrite32(ATAPI_INT_ENABLE_SATAINT, 982 base + ATAPI_INT_ENABLE_REG); 983 } 984 985 ata_host_resume(host); 986 987 return 0; 988 } 989 990 static int sata_rcar_restore(struct device *dev) 991 { 992 struct ata_host *host = dev_get_drvdata(dev); 993 int ret; 994 995 ret = pm_runtime_get_sync(dev); 996 if (ret < 0) { 997 pm_runtime_put(dev); 998 return ret; 999 } 1000 1001 sata_rcar_setup_port(host); 1002 1003 /* initialize host controller */ 1004 sata_rcar_init_controller(host); 1005 1006 ata_host_resume(host); 1007 1008 return 0; 1009 } 1010 1011 static const struct dev_pm_ops sata_rcar_pm_ops = { 1012 .suspend = sata_rcar_suspend, 1013 .resume = sata_rcar_resume, 1014 .freeze = sata_rcar_suspend, 1015 .thaw = sata_rcar_resume, 1016 .poweroff = sata_rcar_suspend, 1017 .restore = sata_rcar_restore, 1018 }; 1019 #endif 1020 1021 static struct platform_driver sata_rcar_driver = { 1022 .probe = sata_rcar_probe, 1023 .remove = sata_rcar_remove, 1024 .driver = { 1025 .name = DRV_NAME, 1026 .of_match_table = sata_rcar_match, 1027 #ifdef CONFIG_PM_SLEEP 1028 .pm = &sata_rcar_pm_ops, 1029 #endif 1030 }, 1031 }; 1032 1033 module_platform_driver(sata_rcar_driver); 1034 1035 MODULE_LICENSE("GPL"); 1036 MODULE_AUTHOR("Vladimir Barinov"); 1037 MODULE_DESCRIPTION("Renesas R-Car SATA controller low level driver"); 1038