1 /* 2 * sata_promise.c - Promise SATA 3 * 4 * Maintained by: Jeff Garzik <jgarzik@pobox.com> 5 * Please ALWAYS copy linux-ide@vger.kernel.org 6 * on emails. 7 * 8 * Copyright 2003-2004 Red Hat, Inc. 9 * 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2, or (at your option) 14 * any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; see the file COPYING. If not, write to 23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. 24 * 25 * 26 * libata documentation is available via 'make {ps|pdf}docs', 27 * as Documentation/DocBook/libata.* 28 * 29 * Hardware information only available under NDA. 30 * 31 */ 32 33 #include <linux/kernel.h> 34 #include <linux/module.h> 35 #include <linux/pci.h> 36 #include <linux/init.h> 37 #include <linux/blkdev.h> 38 #include <linux/delay.h> 39 #include <linux/interrupt.h> 40 #include <linux/device.h> 41 #include <scsi/scsi.h> 42 #include <scsi/scsi_host.h> 43 #include <scsi/scsi_cmnd.h> 44 #include <linux/libata.h> 45 #include "sata_promise.h" 46 47 #define DRV_NAME "sata_promise" 48 #define DRV_VERSION "2.10" 49 50 enum { 51 PDC_MAX_PORTS = 4, 52 PDC_MMIO_BAR = 3, 53 54 /* register offsets */ 55 PDC_FEATURE = 0x04, /* Feature/Error reg (per port) */ 56 PDC_SECTOR_COUNT = 0x08, /* Sector count reg (per port) */ 57 PDC_SECTOR_NUMBER = 0x0C, /* Sector number reg (per port) */ 58 PDC_CYLINDER_LOW = 0x10, /* Cylinder low reg (per port) */ 59 PDC_CYLINDER_HIGH = 0x14, /* Cylinder high reg (per port) */ 60 PDC_DEVICE = 0x18, /* Device/Head reg (per port) */ 61 PDC_COMMAND = 0x1C, /* Command/status reg (per port) */ 62 PDC_ALTSTATUS = 0x38, /* Alternate-status/device-control reg (per port) */ 63 PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */ 64 PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */ 65 PDC_FLASH_CTL = 0x44, /* Flash control register */ 66 PDC_GLOBAL_CTL = 0x48, /* Global control/status (per port) */ 67 PDC_CTLSTAT = 0x60, /* IDE control and status (per port) */ 68 PDC_SATA_PLUG_CSR = 0x6C, /* SATA Plug control/status reg */ 69 PDC2_SATA_PLUG_CSR = 0x60, /* SATAII Plug control/status reg */ 70 PDC_TBG_MODE = 0x41C, /* TBG mode (not SATAII) */ 71 PDC_SLEW_CTL = 0x470, /* slew rate control reg (not SATAII) */ 72 73 /* PDC_GLOBAL_CTL bit definitions */ 74 PDC_PH_ERR = (1 << 8), /* PCI error while loading packet */ 75 PDC_SH_ERR = (1 << 9), /* PCI error while loading S/G table */ 76 PDC_DH_ERR = (1 << 10), /* PCI error while loading data */ 77 PDC2_HTO_ERR = (1 << 12), /* host bus timeout */ 78 PDC2_ATA_HBA_ERR = (1 << 13), /* error during SATA DATA FIS transmission */ 79 PDC2_ATA_DMA_CNT_ERR = (1 << 14), /* DMA DATA FIS size differs from S/G count */ 80 PDC_OVERRUN_ERR = (1 << 19), /* S/G byte count larger than HD requires */ 81 PDC_UNDERRUN_ERR = (1 << 20), /* S/G byte count less than HD requires */ 82 PDC_DRIVE_ERR = (1 << 21), /* drive error */ 83 PDC_PCI_SYS_ERR = (1 << 22), /* PCI system error */ 84 PDC1_PCI_PARITY_ERR = (1 << 23), /* PCI parity error (from SATA150 driver) */ 85 PDC1_ERR_MASK = PDC1_PCI_PARITY_ERR, 86 PDC2_ERR_MASK = PDC2_HTO_ERR | PDC2_ATA_HBA_ERR | PDC2_ATA_DMA_CNT_ERR, 87 PDC_ERR_MASK = (PDC_PH_ERR | PDC_SH_ERR | PDC_DH_ERR | PDC_OVERRUN_ERR 88 | PDC_UNDERRUN_ERR | PDC_DRIVE_ERR | PDC_PCI_SYS_ERR 89 | PDC1_ERR_MASK | PDC2_ERR_MASK), 90 91 board_2037x = 0, /* FastTrak S150 TX2plus */ 92 board_2037x_pata = 1, /* FastTrak S150 TX2plus PATA port */ 93 board_20319 = 2, /* FastTrak S150 TX4 */ 94 board_20619 = 3, /* FastTrak TX4000 */ 95 board_2057x = 4, /* SATAII150 Tx2plus */ 96 board_2057x_pata = 5, /* SATAII150 Tx2plus PATA port */ 97 board_40518 = 6, /* SATAII150 Tx4 */ 98 99 PDC_HAS_PATA = (1 << 1), /* PDC20375/20575 has PATA */ 100 101 /* Sequence counter control registers bit definitions */ 102 PDC_SEQCNTRL_INT_MASK = (1 << 5), /* Sequence Interrupt Mask */ 103 104 /* Feature register values */ 105 PDC_FEATURE_ATAPI_PIO = 0x00, /* ATAPI data xfer by PIO */ 106 PDC_FEATURE_ATAPI_DMA = 0x01, /* ATAPI data xfer by DMA */ 107 108 /* Device/Head register values */ 109 PDC_DEVICE_SATA = 0xE0, /* Device/Head value for SATA devices */ 110 111 /* PDC_CTLSTAT bit definitions */ 112 PDC_DMA_ENABLE = (1 << 7), 113 PDC_IRQ_DISABLE = (1 << 10), 114 PDC_RESET = (1 << 11), /* HDMA reset */ 115 116 PDC_COMMON_FLAGS = ATA_FLAG_NO_LEGACY | 117 ATA_FLAG_MMIO | 118 ATA_FLAG_PIO_POLLING, 119 120 /* ap->flags bits */ 121 PDC_FLAG_GEN_II = (1 << 24), 122 PDC_FLAG_SATA_PATA = (1 << 25), /* supports SATA + PATA */ 123 PDC_FLAG_4_PORTS = (1 << 26), /* 4 ports */ 124 }; 125 126 struct pdc_port_priv { 127 u8 *pkt; 128 dma_addr_t pkt_dma; 129 }; 130 131 static int pdc_sata_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val); 132 static int pdc_sata_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val); 133 static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent); 134 static int pdc_common_port_start(struct ata_port *ap); 135 static int pdc_sata_port_start(struct ata_port *ap); 136 static void pdc_qc_prep(struct ata_queued_cmd *qc); 137 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf); 138 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf); 139 static int pdc_check_atapi_dma(struct ata_queued_cmd *qc); 140 static int pdc_old_sata_check_atapi_dma(struct ata_queued_cmd *qc); 141 static void pdc_irq_clear(struct ata_port *ap); 142 static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc); 143 static void pdc_freeze(struct ata_port *ap); 144 static void pdc_thaw(struct ata_port *ap); 145 static void pdc_pata_error_handler(struct ata_port *ap); 146 static void pdc_sata_error_handler(struct ata_port *ap); 147 static void pdc_post_internal_cmd(struct ata_queued_cmd *qc); 148 static int pdc_pata_cable_detect(struct ata_port *ap); 149 static int pdc_sata_cable_detect(struct ata_port *ap); 150 151 static struct scsi_host_template pdc_ata_sht = { 152 .module = THIS_MODULE, 153 .name = DRV_NAME, 154 .ioctl = ata_scsi_ioctl, 155 .queuecommand = ata_scsi_queuecmd, 156 .can_queue = ATA_DEF_QUEUE, 157 .this_id = ATA_SHT_THIS_ID, 158 .sg_tablesize = LIBATA_MAX_PRD, 159 .cmd_per_lun = ATA_SHT_CMD_PER_LUN, 160 .emulated = ATA_SHT_EMULATED, 161 .use_clustering = ATA_SHT_USE_CLUSTERING, 162 .proc_name = DRV_NAME, 163 .dma_boundary = ATA_DMA_BOUNDARY, 164 .slave_configure = ata_scsi_slave_config, 165 .slave_destroy = ata_scsi_slave_destroy, 166 .bios_param = ata_std_bios_param, 167 }; 168 169 static const struct ata_port_operations pdc_sata_ops = { 170 .tf_load = pdc_tf_load_mmio, 171 .tf_read = ata_tf_read, 172 .check_status = ata_check_status, 173 .exec_command = pdc_exec_command_mmio, 174 .dev_select = ata_std_dev_select, 175 .check_atapi_dma = pdc_check_atapi_dma, 176 177 .qc_prep = pdc_qc_prep, 178 .qc_issue = pdc_qc_issue_prot, 179 .freeze = pdc_freeze, 180 .thaw = pdc_thaw, 181 .error_handler = pdc_sata_error_handler, 182 .post_internal_cmd = pdc_post_internal_cmd, 183 .cable_detect = pdc_sata_cable_detect, 184 .data_xfer = ata_data_xfer, 185 .irq_clear = pdc_irq_clear, 186 .irq_on = ata_irq_on, 187 188 .scr_read = pdc_sata_scr_read, 189 .scr_write = pdc_sata_scr_write, 190 .port_start = pdc_sata_port_start, 191 }; 192 193 /* First-generation chips need a more restrictive ->check_atapi_dma op */ 194 static const struct ata_port_operations pdc_old_sata_ops = { 195 .tf_load = pdc_tf_load_mmio, 196 .tf_read = ata_tf_read, 197 .check_status = ata_check_status, 198 .exec_command = pdc_exec_command_mmio, 199 .dev_select = ata_std_dev_select, 200 .check_atapi_dma = pdc_old_sata_check_atapi_dma, 201 202 .qc_prep = pdc_qc_prep, 203 .qc_issue = pdc_qc_issue_prot, 204 .freeze = pdc_freeze, 205 .thaw = pdc_thaw, 206 .error_handler = pdc_sata_error_handler, 207 .post_internal_cmd = pdc_post_internal_cmd, 208 .cable_detect = pdc_sata_cable_detect, 209 .data_xfer = ata_data_xfer, 210 .irq_clear = pdc_irq_clear, 211 .irq_on = ata_irq_on, 212 213 .scr_read = pdc_sata_scr_read, 214 .scr_write = pdc_sata_scr_write, 215 .port_start = pdc_sata_port_start, 216 }; 217 218 static const struct ata_port_operations pdc_pata_ops = { 219 .tf_load = pdc_tf_load_mmio, 220 .tf_read = ata_tf_read, 221 .check_status = ata_check_status, 222 .exec_command = pdc_exec_command_mmio, 223 .dev_select = ata_std_dev_select, 224 .check_atapi_dma = pdc_check_atapi_dma, 225 226 .qc_prep = pdc_qc_prep, 227 .qc_issue = pdc_qc_issue_prot, 228 .freeze = pdc_freeze, 229 .thaw = pdc_thaw, 230 .error_handler = pdc_pata_error_handler, 231 .post_internal_cmd = pdc_post_internal_cmd, 232 .cable_detect = pdc_pata_cable_detect, 233 .data_xfer = ata_data_xfer, 234 .irq_clear = pdc_irq_clear, 235 .irq_on = ata_irq_on, 236 237 .port_start = pdc_common_port_start, 238 }; 239 240 static const struct ata_port_info pdc_port_info[] = { 241 /* board_2037x */ 242 { 243 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA | 244 PDC_FLAG_SATA_PATA, 245 .pio_mask = 0x1f, /* pio0-4 */ 246 .mwdma_mask = 0x07, /* mwdma0-2 */ 247 .udma_mask = ATA_UDMA6, 248 .port_ops = &pdc_old_sata_ops, 249 }, 250 251 /* board_2037x_pata */ 252 { 253 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS, 254 .pio_mask = 0x1f, /* pio0-4 */ 255 .mwdma_mask = 0x07, /* mwdma0-2 */ 256 .udma_mask = ATA_UDMA6, 257 .port_ops = &pdc_pata_ops, 258 }, 259 260 /* board_20319 */ 261 { 262 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA | 263 PDC_FLAG_4_PORTS, 264 .pio_mask = 0x1f, /* pio0-4 */ 265 .mwdma_mask = 0x07, /* mwdma0-2 */ 266 .udma_mask = ATA_UDMA6, 267 .port_ops = &pdc_old_sata_ops, 268 }, 269 270 /* board_20619 */ 271 { 272 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS | 273 PDC_FLAG_4_PORTS, 274 .pio_mask = 0x1f, /* pio0-4 */ 275 .mwdma_mask = 0x07, /* mwdma0-2 */ 276 .udma_mask = ATA_UDMA6, 277 .port_ops = &pdc_pata_ops, 278 }, 279 280 /* board_2057x */ 281 { 282 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA | 283 PDC_FLAG_GEN_II | PDC_FLAG_SATA_PATA, 284 .pio_mask = 0x1f, /* pio0-4 */ 285 .mwdma_mask = 0x07, /* mwdma0-2 */ 286 .udma_mask = ATA_UDMA6, 287 .port_ops = &pdc_sata_ops, 288 }, 289 290 /* board_2057x_pata */ 291 { 292 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS | 293 PDC_FLAG_GEN_II, 294 .pio_mask = 0x1f, /* pio0-4 */ 295 .mwdma_mask = 0x07, /* mwdma0-2 */ 296 .udma_mask = ATA_UDMA6, 297 .port_ops = &pdc_pata_ops, 298 }, 299 300 /* board_40518 */ 301 { 302 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA | 303 PDC_FLAG_GEN_II | PDC_FLAG_4_PORTS, 304 .pio_mask = 0x1f, /* pio0-4 */ 305 .mwdma_mask = 0x07, /* mwdma0-2 */ 306 .udma_mask = ATA_UDMA6, 307 .port_ops = &pdc_sata_ops, 308 }, 309 }; 310 311 static const struct pci_device_id pdc_ata_pci_tbl[] = { 312 { PCI_VDEVICE(PROMISE, 0x3371), board_2037x }, 313 { PCI_VDEVICE(PROMISE, 0x3373), board_2037x }, 314 { PCI_VDEVICE(PROMISE, 0x3375), board_2037x }, 315 { PCI_VDEVICE(PROMISE, 0x3376), board_2037x }, 316 { PCI_VDEVICE(PROMISE, 0x3570), board_2057x }, 317 { PCI_VDEVICE(PROMISE, 0x3571), board_2057x }, 318 { PCI_VDEVICE(PROMISE, 0x3574), board_2057x }, 319 { PCI_VDEVICE(PROMISE, 0x3577), board_2057x }, 320 { PCI_VDEVICE(PROMISE, 0x3d73), board_2057x }, 321 { PCI_VDEVICE(PROMISE, 0x3d75), board_2057x }, 322 323 { PCI_VDEVICE(PROMISE, 0x3318), board_20319 }, 324 { PCI_VDEVICE(PROMISE, 0x3319), board_20319 }, 325 { PCI_VDEVICE(PROMISE, 0x3515), board_40518 }, 326 { PCI_VDEVICE(PROMISE, 0x3519), board_40518 }, 327 { PCI_VDEVICE(PROMISE, 0x3d17), board_40518 }, 328 { PCI_VDEVICE(PROMISE, 0x3d18), board_40518 }, 329 330 { PCI_VDEVICE(PROMISE, 0x6629), board_20619 }, 331 332 { } /* terminate list */ 333 }; 334 335 static struct pci_driver pdc_ata_pci_driver = { 336 .name = DRV_NAME, 337 .id_table = pdc_ata_pci_tbl, 338 .probe = pdc_ata_init_one, 339 .remove = ata_pci_remove_one, 340 }; 341 342 static int pdc_common_port_start(struct ata_port *ap) 343 { 344 struct device *dev = ap->host->dev; 345 struct pdc_port_priv *pp; 346 int rc; 347 348 rc = ata_port_start(ap); 349 if (rc) 350 return rc; 351 352 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); 353 if (!pp) 354 return -ENOMEM; 355 356 pp->pkt = dmam_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL); 357 if (!pp->pkt) 358 return -ENOMEM; 359 360 ap->private_data = pp; 361 362 return 0; 363 } 364 365 static int pdc_sata_port_start(struct ata_port *ap) 366 { 367 int rc; 368 369 rc = pdc_common_port_start(ap); 370 if (rc) 371 return rc; 372 373 /* fix up PHYMODE4 align timing */ 374 if (ap->flags & PDC_FLAG_GEN_II) { 375 void __iomem *mmio = ap->ioaddr.scr_addr; 376 unsigned int tmp; 377 378 tmp = readl(mmio + 0x014); 379 tmp = (tmp & ~3) | 1; /* set bits 1:0 = 0:1 */ 380 writel(tmp, mmio + 0x014); 381 } 382 383 return 0; 384 } 385 386 static void pdc_reset_port(struct ata_port *ap) 387 { 388 void __iomem *mmio = ap->ioaddr.cmd_addr + PDC_CTLSTAT; 389 unsigned int i; 390 u32 tmp; 391 392 for (i = 11; i > 0; i--) { 393 tmp = readl(mmio); 394 if (tmp & PDC_RESET) 395 break; 396 397 udelay(100); 398 399 tmp |= PDC_RESET; 400 writel(tmp, mmio); 401 } 402 403 tmp &= ~PDC_RESET; 404 writel(tmp, mmio); 405 readl(mmio); /* flush */ 406 } 407 408 static int pdc_pata_cable_detect(struct ata_port *ap) 409 { 410 u8 tmp; 411 void __iomem *mmio = ap->ioaddr.cmd_addr + PDC_CTLSTAT + 0x03; 412 413 tmp = readb(mmio); 414 if (tmp & 0x01) 415 return ATA_CBL_PATA40; 416 return ATA_CBL_PATA80; 417 } 418 419 static int pdc_sata_cable_detect(struct ata_port *ap) 420 { 421 return ATA_CBL_SATA; 422 } 423 424 static int pdc_sata_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val) 425 { 426 if (sc_reg > SCR_CONTROL) 427 return -EINVAL; 428 *val = readl(ap->ioaddr.scr_addr + (sc_reg * 4)); 429 return 0; 430 } 431 432 static int pdc_sata_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val) 433 { 434 if (sc_reg > SCR_CONTROL) 435 return -EINVAL; 436 writel(val, ap->ioaddr.scr_addr + (sc_reg * 4)); 437 return 0; 438 } 439 440 static void pdc_atapi_pkt(struct ata_queued_cmd *qc) 441 { 442 struct ata_port *ap = qc->ap; 443 dma_addr_t sg_table = ap->prd_dma; 444 unsigned int cdb_len = qc->dev->cdb_len; 445 u8 *cdb = qc->cdb; 446 struct pdc_port_priv *pp = ap->private_data; 447 u8 *buf = pp->pkt; 448 u32 *buf32 = (u32 *) buf; 449 unsigned int dev_sel, feature, nbytes; 450 451 /* set control bits (byte 0), zero delay seq id (byte 3), 452 * and seq id (byte 2) 453 */ 454 switch (qc->tf.protocol) { 455 case ATA_PROT_ATAPI_DMA: 456 if (!(qc->tf.flags & ATA_TFLAG_WRITE)) 457 buf32[0] = cpu_to_le32(PDC_PKT_READ); 458 else 459 buf32[0] = 0; 460 break; 461 case ATA_PROT_ATAPI_NODATA: 462 buf32[0] = cpu_to_le32(PDC_PKT_NODATA); 463 break; 464 default: 465 BUG(); 466 break; 467 } 468 buf32[1] = cpu_to_le32(sg_table); /* S/G table addr */ 469 buf32[2] = 0; /* no next-packet */ 470 471 /* select drive */ 472 if (sata_scr_valid(&ap->link)) { 473 dev_sel = PDC_DEVICE_SATA; 474 } else { 475 dev_sel = ATA_DEVICE_OBS; 476 if (qc->dev->devno != 0) 477 dev_sel |= ATA_DEV1; 478 } 479 buf[12] = (1 << 5) | ATA_REG_DEVICE; 480 buf[13] = dev_sel; 481 buf[14] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_CLEAR_BSY; 482 buf[15] = dev_sel; /* once more, waiting for BSY to clear */ 483 484 buf[16] = (1 << 5) | ATA_REG_NSECT; 485 buf[17] = 0x00; 486 buf[18] = (1 << 5) | ATA_REG_LBAL; 487 buf[19] = 0x00; 488 489 /* set feature and byte counter registers */ 490 if (qc->tf.protocol != ATA_PROT_ATAPI_DMA) { 491 feature = PDC_FEATURE_ATAPI_PIO; 492 /* set byte counter register to real transfer byte count */ 493 nbytes = qc->nbytes; 494 if (nbytes > 0xffff) 495 nbytes = 0xffff; 496 } else { 497 feature = PDC_FEATURE_ATAPI_DMA; 498 /* set byte counter register to 0 */ 499 nbytes = 0; 500 } 501 buf[20] = (1 << 5) | ATA_REG_FEATURE; 502 buf[21] = feature; 503 buf[22] = (1 << 5) | ATA_REG_BYTEL; 504 buf[23] = nbytes & 0xFF; 505 buf[24] = (1 << 5) | ATA_REG_BYTEH; 506 buf[25] = (nbytes >> 8) & 0xFF; 507 508 /* send ATAPI packet command 0xA0 */ 509 buf[26] = (1 << 5) | ATA_REG_CMD; 510 buf[27] = ATA_CMD_PACKET; 511 512 /* select drive and check DRQ */ 513 buf[28] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_WAIT_DRDY; 514 buf[29] = dev_sel; 515 516 /* we can represent cdb lengths 2/4/6/8/10/12/14/16 */ 517 BUG_ON(cdb_len & ~0x1E); 518 519 /* append the CDB as the final part */ 520 buf[30] = (((cdb_len >> 1) & 7) << 5) | ATA_REG_DATA | PDC_LAST_REG; 521 memcpy(buf+31, cdb, cdb_len); 522 } 523 524 static void pdc_qc_prep(struct ata_queued_cmd *qc) 525 { 526 struct pdc_port_priv *pp = qc->ap->private_data; 527 unsigned int i; 528 529 VPRINTK("ENTER\n"); 530 531 switch (qc->tf.protocol) { 532 case ATA_PROT_DMA: 533 ata_qc_prep(qc); 534 /* fall through */ 535 536 case ATA_PROT_NODATA: 537 i = pdc_pkt_header(&qc->tf, qc->ap->prd_dma, 538 qc->dev->devno, pp->pkt); 539 540 if (qc->tf.flags & ATA_TFLAG_LBA48) 541 i = pdc_prep_lba48(&qc->tf, pp->pkt, i); 542 else 543 i = pdc_prep_lba28(&qc->tf, pp->pkt, i); 544 545 pdc_pkt_footer(&qc->tf, pp->pkt, i); 546 break; 547 548 case ATA_PROT_ATAPI: 549 ata_qc_prep(qc); 550 break; 551 552 case ATA_PROT_ATAPI_DMA: 553 ata_qc_prep(qc); 554 /*FALLTHROUGH*/ 555 case ATA_PROT_ATAPI_NODATA: 556 pdc_atapi_pkt(qc); 557 break; 558 559 default: 560 break; 561 } 562 } 563 564 static void pdc_freeze(struct ata_port *ap) 565 { 566 void __iomem *mmio = ap->ioaddr.cmd_addr; 567 u32 tmp; 568 569 tmp = readl(mmio + PDC_CTLSTAT); 570 tmp |= PDC_IRQ_DISABLE; 571 tmp &= ~PDC_DMA_ENABLE; 572 writel(tmp, mmio + PDC_CTLSTAT); 573 readl(mmio + PDC_CTLSTAT); /* flush */ 574 } 575 576 static void pdc_thaw(struct ata_port *ap) 577 { 578 void __iomem *mmio = ap->ioaddr.cmd_addr; 579 u32 tmp; 580 581 /* clear IRQ */ 582 readl(mmio + PDC_INT_SEQMASK); 583 584 /* turn IRQ back on */ 585 tmp = readl(mmio + PDC_CTLSTAT); 586 tmp &= ~PDC_IRQ_DISABLE; 587 writel(tmp, mmio + PDC_CTLSTAT); 588 readl(mmio + PDC_CTLSTAT); /* flush */ 589 } 590 591 static void pdc_common_error_handler(struct ata_port *ap, ata_reset_fn_t hardreset) 592 { 593 if (!(ap->pflags & ATA_PFLAG_FROZEN)) 594 pdc_reset_port(ap); 595 596 /* perform recovery */ 597 ata_do_eh(ap, ata_std_prereset, ata_std_softreset, hardreset, 598 ata_std_postreset); 599 } 600 601 static void pdc_pata_error_handler(struct ata_port *ap) 602 { 603 pdc_common_error_handler(ap, NULL); 604 } 605 606 static void pdc_sata_error_handler(struct ata_port *ap) 607 { 608 pdc_common_error_handler(ap, sata_std_hardreset); 609 } 610 611 static void pdc_post_internal_cmd(struct ata_queued_cmd *qc) 612 { 613 struct ata_port *ap = qc->ap; 614 615 /* make DMA engine forget about the failed command */ 616 if (qc->flags & ATA_QCFLAG_FAILED) 617 pdc_reset_port(ap); 618 } 619 620 static void pdc_error_intr(struct ata_port *ap, struct ata_queued_cmd *qc, 621 u32 port_status, u32 err_mask) 622 { 623 struct ata_eh_info *ehi = &ap->link.eh_info; 624 unsigned int ac_err_mask = 0; 625 626 ata_ehi_clear_desc(ehi); 627 ata_ehi_push_desc(ehi, "port_status 0x%08x", port_status); 628 port_status &= err_mask; 629 630 if (port_status & PDC_DRIVE_ERR) 631 ac_err_mask |= AC_ERR_DEV; 632 if (port_status & (PDC_OVERRUN_ERR | PDC_UNDERRUN_ERR)) 633 ac_err_mask |= AC_ERR_HSM; 634 if (port_status & (PDC2_ATA_HBA_ERR | PDC2_ATA_DMA_CNT_ERR)) 635 ac_err_mask |= AC_ERR_ATA_BUS; 636 if (port_status & (PDC_PH_ERR | PDC_SH_ERR | PDC_DH_ERR | PDC2_HTO_ERR 637 | PDC_PCI_SYS_ERR | PDC1_PCI_PARITY_ERR)) 638 ac_err_mask |= AC_ERR_HOST_BUS; 639 640 if (sata_scr_valid(&ap->link)) { 641 u32 serror; 642 643 pdc_sata_scr_read(ap, SCR_ERROR, &serror); 644 ehi->serror |= serror; 645 } 646 647 qc->err_mask |= ac_err_mask; 648 649 pdc_reset_port(ap); 650 651 ata_port_abort(ap); 652 } 653 654 static inline unsigned int pdc_host_intr(struct ata_port *ap, 655 struct ata_queued_cmd *qc) 656 { 657 unsigned int handled = 0; 658 void __iomem *port_mmio = ap->ioaddr.cmd_addr; 659 u32 port_status, err_mask; 660 661 err_mask = PDC_ERR_MASK; 662 if (ap->flags & PDC_FLAG_GEN_II) 663 err_mask &= ~PDC1_ERR_MASK; 664 else 665 err_mask &= ~PDC2_ERR_MASK; 666 port_status = readl(port_mmio + PDC_GLOBAL_CTL); 667 if (unlikely(port_status & err_mask)) { 668 pdc_error_intr(ap, qc, port_status, err_mask); 669 return 1; 670 } 671 672 switch (qc->tf.protocol) { 673 case ATA_PROT_DMA: 674 case ATA_PROT_NODATA: 675 case ATA_PROT_ATAPI_DMA: 676 case ATA_PROT_ATAPI_NODATA: 677 qc->err_mask |= ac_err_mask(ata_wait_idle(ap)); 678 ata_qc_complete(qc); 679 handled = 1; 680 break; 681 682 default: 683 ap->stats.idle_irq++; 684 break; 685 } 686 687 return handled; 688 } 689 690 static void pdc_irq_clear(struct ata_port *ap) 691 { 692 struct ata_host *host = ap->host; 693 void __iomem *mmio = host->iomap[PDC_MMIO_BAR]; 694 695 readl(mmio + PDC_INT_SEQMASK); 696 } 697 698 static inline int pdc_is_sataii_tx4(unsigned long flags) 699 { 700 const unsigned long mask = PDC_FLAG_GEN_II | PDC_FLAG_4_PORTS; 701 return (flags & mask) == mask; 702 } 703 704 static inline unsigned int pdc_port_no_to_ata_no(unsigned int port_no, int is_sataii_tx4) 705 { 706 static const unsigned char sataii_tx4_port_remap[4] = { 3, 1, 0, 2}; 707 return is_sataii_tx4 ? sataii_tx4_port_remap[port_no] : port_no; 708 } 709 710 static irqreturn_t pdc_interrupt (int irq, void *dev_instance) 711 { 712 struct ata_host *host = dev_instance; 713 struct ata_port *ap; 714 u32 mask = 0; 715 unsigned int i, tmp; 716 unsigned int handled = 0; 717 void __iomem *mmio_base; 718 unsigned int hotplug_offset, ata_no; 719 u32 hotplug_status; 720 int is_sataii_tx4; 721 722 VPRINTK("ENTER\n"); 723 724 if (!host || !host->iomap[PDC_MMIO_BAR]) { 725 VPRINTK("QUICK EXIT\n"); 726 return IRQ_NONE; 727 } 728 729 mmio_base = host->iomap[PDC_MMIO_BAR]; 730 731 /* read and clear hotplug flags for all ports */ 732 if (host->ports[0]->flags & PDC_FLAG_GEN_II) 733 hotplug_offset = PDC2_SATA_PLUG_CSR; 734 else 735 hotplug_offset = PDC_SATA_PLUG_CSR; 736 hotplug_status = readl(mmio_base + hotplug_offset); 737 if (hotplug_status & 0xff) 738 writel(hotplug_status | 0xff, mmio_base + hotplug_offset); 739 hotplug_status &= 0xff; /* clear uninteresting bits */ 740 741 /* reading should also clear interrupts */ 742 mask = readl(mmio_base + PDC_INT_SEQMASK); 743 744 if (mask == 0xffffffff && hotplug_status == 0) { 745 VPRINTK("QUICK EXIT 2\n"); 746 return IRQ_NONE; 747 } 748 749 spin_lock(&host->lock); 750 751 mask &= 0xffff; /* only 16 tags possible */ 752 if (mask == 0 && hotplug_status == 0) { 753 VPRINTK("QUICK EXIT 3\n"); 754 goto done_irq; 755 } 756 757 writel(mask, mmio_base + PDC_INT_SEQMASK); 758 759 is_sataii_tx4 = pdc_is_sataii_tx4(host->ports[0]->flags); 760 761 for (i = 0; i < host->n_ports; i++) { 762 VPRINTK("port %u\n", i); 763 ap = host->ports[i]; 764 765 /* check for a plug or unplug event */ 766 ata_no = pdc_port_no_to_ata_no(i, is_sataii_tx4); 767 tmp = hotplug_status & (0x11 << ata_no); 768 if (tmp && ap && 769 !(ap->flags & ATA_FLAG_DISABLED)) { 770 struct ata_eh_info *ehi = &ap->link.eh_info; 771 ata_ehi_clear_desc(ehi); 772 ata_ehi_hotplugged(ehi); 773 ata_ehi_push_desc(ehi, "hotplug_status %#x", tmp); 774 ata_port_freeze(ap); 775 ++handled; 776 continue; 777 } 778 779 /* check for a packet interrupt */ 780 tmp = mask & (1 << (i + 1)); 781 if (tmp && ap && 782 !(ap->flags & ATA_FLAG_DISABLED)) { 783 struct ata_queued_cmd *qc; 784 785 qc = ata_qc_from_tag(ap, ap->link.active_tag); 786 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) 787 handled += pdc_host_intr(ap, qc); 788 } 789 } 790 791 VPRINTK("EXIT\n"); 792 793 done_irq: 794 spin_unlock(&host->lock); 795 return IRQ_RETVAL(handled); 796 } 797 798 static inline void pdc_packet_start(struct ata_queued_cmd *qc) 799 { 800 struct ata_port *ap = qc->ap; 801 struct pdc_port_priv *pp = ap->private_data; 802 void __iomem *mmio = ap->host->iomap[PDC_MMIO_BAR]; 803 unsigned int port_no = ap->port_no; 804 u8 seq = (u8) (port_no + 1); 805 806 VPRINTK("ENTER, ap %p\n", ap); 807 808 writel(0x00000001, mmio + (seq * 4)); 809 readl(mmio + (seq * 4)); /* flush */ 810 811 pp->pkt[2] = seq; 812 wmb(); /* flush PRD, pkt writes */ 813 writel(pp->pkt_dma, ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); 814 readl(ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); /* flush */ 815 } 816 817 static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc) 818 { 819 switch (qc->tf.protocol) { 820 case ATA_PROT_ATAPI_NODATA: 821 if (qc->dev->flags & ATA_DFLAG_CDB_INTR) 822 break; 823 /*FALLTHROUGH*/ 824 case ATA_PROT_NODATA: 825 if (qc->tf.flags & ATA_TFLAG_POLLING) 826 break; 827 /*FALLTHROUGH*/ 828 case ATA_PROT_ATAPI_DMA: 829 case ATA_PROT_DMA: 830 pdc_packet_start(qc); 831 return 0; 832 833 default: 834 break; 835 } 836 837 return ata_qc_issue_prot(qc); 838 } 839 840 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf) 841 { 842 WARN_ON (tf->protocol == ATA_PROT_DMA || 843 tf->protocol == ATA_PROT_ATAPI_DMA); 844 ata_tf_load(ap, tf); 845 } 846 847 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf) 848 { 849 WARN_ON (tf->protocol == ATA_PROT_DMA || 850 tf->protocol == ATA_PROT_ATAPI_DMA); 851 ata_exec_command(ap, tf); 852 } 853 854 static int pdc_check_atapi_dma(struct ata_queued_cmd *qc) 855 { 856 u8 *scsicmd = qc->scsicmd->cmnd; 857 int pio = 1; /* atapi dma off by default */ 858 859 /* Whitelist commands that may use DMA. */ 860 switch (scsicmd[0]) { 861 case WRITE_12: 862 case WRITE_10: 863 case WRITE_6: 864 case READ_12: 865 case READ_10: 866 case READ_6: 867 case 0xad: /* READ_DVD_STRUCTURE */ 868 case 0xbe: /* READ_CD */ 869 pio = 0; 870 } 871 /* -45150 (FFFF4FA2) to -1 (FFFFFFFF) shall use PIO mode */ 872 if (scsicmd[0] == WRITE_10) { 873 unsigned int lba; 874 lba = (scsicmd[2] << 24) | (scsicmd[3] << 16) | (scsicmd[4] << 8) | scsicmd[5]; 875 if (lba >= 0xFFFF4FA2) 876 pio = 1; 877 } 878 return pio; 879 } 880 881 static int pdc_old_sata_check_atapi_dma(struct ata_queued_cmd *qc) 882 { 883 /* First generation chips cannot use ATAPI DMA on SATA ports */ 884 return 1; 885 } 886 887 static void pdc_ata_setup_port(struct ata_port *ap, 888 void __iomem *base, void __iomem *scr_addr) 889 { 890 ap->ioaddr.cmd_addr = base; 891 ap->ioaddr.data_addr = base; 892 ap->ioaddr.feature_addr = 893 ap->ioaddr.error_addr = base + 0x4; 894 ap->ioaddr.nsect_addr = base + 0x8; 895 ap->ioaddr.lbal_addr = base + 0xc; 896 ap->ioaddr.lbam_addr = base + 0x10; 897 ap->ioaddr.lbah_addr = base + 0x14; 898 ap->ioaddr.device_addr = base + 0x18; 899 ap->ioaddr.command_addr = 900 ap->ioaddr.status_addr = base + 0x1c; 901 ap->ioaddr.altstatus_addr = 902 ap->ioaddr.ctl_addr = base + 0x38; 903 ap->ioaddr.scr_addr = scr_addr; 904 } 905 906 static void pdc_host_init(struct ata_host *host) 907 { 908 void __iomem *mmio = host->iomap[PDC_MMIO_BAR]; 909 int is_gen2 = host->ports[0]->flags & PDC_FLAG_GEN_II; 910 int hotplug_offset; 911 u32 tmp; 912 913 if (is_gen2) 914 hotplug_offset = PDC2_SATA_PLUG_CSR; 915 else 916 hotplug_offset = PDC_SATA_PLUG_CSR; 917 918 /* 919 * Except for the hotplug stuff, this is voodoo from the 920 * Promise driver. Label this entire section 921 * "TODO: figure out why we do this" 922 */ 923 924 /* enable BMR_BURST, maybe change FIFO_SHD to 8 dwords */ 925 tmp = readl(mmio + PDC_FLASH_CTL); 926 tmp |= 0x02000; /* bit 13 (enable bmr burst) */ 927 if (!is_gen2) 928 tmp |= 0x10000; /* bit 16 (fifo threshold at 8 dw) */ 929 writel(tmp, mmio + PDC_FLASH_CTL); 930 931 /* clear plug/unplug flags for all ports */ 932 tmp = readl(mmio + hotplug_offset); 933 writel(tmp | 0xff, mmio + hotplug_offset); 934 935 /* unmask plug/unplug ints */ 936 tmp = readl(mmio + hotplug_offset); 937 writel(tmp & ~0xff0000, mmio + hotplug_offset); 938 939 /* don't initialise TBG or SLEW on 2nd generation chips */ 940 if (is_gen2) 941 return; 942 943 /* reduce TBG clock to 133 Mhz. */ 944 tmp = readl(mmio + PDC_TBG_MODE); 945 tmp &= ~0x30000; /* clear bit 17, 16*/ 946 tmp |= 0x10000; /* set bit 17:16 = 0:1 */ 947 writel(tmp, mmio + PDC_TBG_MODE); 948 949 readl(mmio + PDC_TBG_MODE); /* flush */ 950 msleep(10); 951 952 /* adjust slew rate control register. */ 953 tmp = readl(mmio + PDC_SLEW_CTL); 954 tmp &= 0xFFFFF03F; /* clear bit 11 ~ 6 */ 955 tmp |= 0x00000900; /* set bit 11-9 = 100b , bit 8-6 = 100 */ 956 writel(tmp, mmio + PDC_SLEW_CTL); 957 } 958 959 static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) 960 { 961 static int printed_version; 962 const struct ata_port_info *pi = &pdc_port_info[ent->driver_data]; 963 const struct ata_port_info *ppi[PDC_MAX_PORTS]; 964 struct ata_host *host; 965 void __iomem *base; 966 int n_ports, i, rc; 967 int is_sataii_tx4; 968 969 if (!printed_version++) 970 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); 971 972 /* enable and acquire resources */ 973 rc = pcim_enable_device(pdev); 974 if (rc) 975 return rc; 976 977 rc = pcim_iomap_regions(pdev, 1 << PDC_MMIO_BAR, DRV_NAME); 978 if (rc == -EBUSY) 979 pcim_pin_device(pdev); 980 if (rc) 981 return rc; 982 base = pcim_iomap_table(pdev)[PDC_MMIO_BAR]; 983 984 /* determine port configuration and setup host */ 985 n_ports = 2; 986 if (pi->flags & PDC_FLAG_4_PORTS) 987 n_ports = 4; 988 for (i = 0; i < n_ports; i++) 989 ppi[i] = pi; 990 991 if (pi->flags & PDC_FLAG_SATA_PATA) { 992 u8 tmp = readb(base + PDC_FLASH_CTL+1); 993 if (!(tmp & 0x80)) 994 ppi[n_ports++] = pi + 1; 995 } 996 997 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); 998 if (!host) { 999 dev_printk(KERN_ERR, &pdev->dev, "failed to allocate host\n"); 1000 return -ENOMEM; 1001 } 1002 host->iomap = pcim_iomap_table(pdev); 1003 1004 is_sataii_tx4 = pdc_is_sataii_tx4(pi->flags); 1005 for (i = 0; i < host->n_ports; i++) { 1006 struct ata_port *ap = host->ports[i]; 1007 unsigned int ata_no = pdc_port_no_to_ata_no(i, is_sataii_tx4); 1008 unsigned int port_offset = 0x200 + ata_no * 0x80; 1009 unsigned int scr_offset = 0x400 + ata_no * 0x100; 1010 1011 pdc_ata_setup_port(ap, base + port_offset, base + scr_offset); 1012 1013 ata_port_pbar_desc(ap, PDC_MMIO_BAR, -1, "mmio"); 1014 ata_port_pbar_desc(ap, PDC_MMIO_BAR, port_offset, "port"); 1015 } 1016 1017 /* initialize adapter */ 1018 pdc_host_init(host); 1019 1020 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK); 1021 if (rc) 1022 return rc; 1023 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK); 1024 if (rc) 1025 return rc; 1026 1027 /* start host, request IRQ and attach */ 1028 pci_set_master(pdev); 1029 return ata_host_activate(host, pdev->irq, pdc_interrupt, IRQF_SHARED, 1030 &pdc_ata_sht); 1031 } 1032 1033 static int __init pdc_ata_init(void) 1034 { 1035 return pci_register_driver(&pdc_ata_pci_driver); 1036 } 1037 1038 static void __exit pdc_ata_exit(void) 1039 { 1040 pci_unregister_driver(&pdc_ata_pci_driver); 1041 } 1042 1043 MODULE_AUTHOR("Jeff Garzik"); 1044 MODULE_DESCRIPTION("Promise ATA TX2/TX4/TX4000 low-level driver"); 1045 MODULE_LICENSE("GPL"); 1046 MODULE_DEVICE_TABLE(pci, pdc_ata_pci_tbl); 1047 MODULE_VERSION(DRV_VERSION); 1048 1049 module_init(pdc_ata_init); 1050 module_exit(pdc_ata_exit); 1051