1 /* 2 * pata_sis.c - SiS ATA driver 3 * 4 * (C) 2005 Red Hat <alan@redhat.com> 5 * (C) 2007 Bartlomiej Zolnierkiewicz 6 * 7 * Based upon linux/drivers/ide/pci/sis5513.c 8 * Copyright (C) 1999-2000 Andre Hedrick <andre@linux-ide.org> 9 * Copyright (C) 2002 Lionel Bouton <Lionel.Bouton@inet6.fr>, Maintainer 10 * Copyright (C) 2003 Vojtech Pavlik <vojtech@suse.cz> 11 * SiS Taiwan : for direct support and hardware. 12 * Daniela Engert : for initial ATA100 advices and numerous others. 13 * John Fremlin, Manfred Spraul, Dave Morgan, Peter Kjellerstedt : 14 * for checking code correctness, providing patches. 15 * Original tests and design on the SiS620 chipset. 16 * ATA100 tests and design on the SiS735 chipset. 17 * ATA16/33 support from specs 18 * ATA133 support for SiS961/962 by L.C. Chang <lcchang@sis.com.tw> 19 * 20 * 21 * TODO 22 * Check MWDMA on drives that don't support MWDMA speed pio cycles ? 23 * More Testing 24 */ 25 26 #include <linux/kernel.h> 27 #include <linux/module.h> 28 #include <linux/pci.h> 29 #include <linux/init.h> 30 #include <linux/blkdev.h> 31 #include <linux/delay.h> 32 #include <linux/device.h> 33 #include <scsi/scsi_host.h> 34 #include <linux/libata.h> 35 #include <linux/ata.h> 36 #include "sis.h" 37 38 #define DRV_NAME "pata_sis" 39 #define DRV_VERSION "0.5.2" 40 41 struct sis_chipset { 42 u16 device; /* PCI host ID */ 43 const struct ata_port_info *info; /* Info block */ 44 /* Probably add family, cable detect type etc here to clean 45 up code later */ 46 }; 47 48 struct sis_laptop { 49 u16 device; 50 u16 subvendor; 51 u16 subdevice; 52 }; 53 54 static const struct sis_laptop sis_laptop[] = { 55 /* devid, subvendor, subdev */ 56 { 0x5513, 0x1043, 0x1107 }, /* ASUS A6K */ 57 { 0x5513, 0x1734, 0x105F }, /* FSC Amilo A1630 */ 58 /* end marker */ 59 { 0, } 60 }; 61 62 static int sis_short_ata40(struct pci_dev *dev) 63 { 64 const struct sis_laptop *lap = &sis_laptop[0]; 65 66 while (lap->device) { 67 if (lap->device == dev->device && 68 lap->subvendor == dev->subsystem_vendor && 69 lap->subdevice == dev->subsystem_device) 70 return 1; 71 lap++; 72 } 73 74 return 0; 75 } 76 77 /** 78 * sis_old_port_base - return PCI configuration base for dev 79 * @adev: device 80 * 81 * Returns the base of the PCI configuration registers for this port 82 * number. 83 */ 84 85 static int sis_old_port_base(struct ata_device *adev) 86 { 87 return 0x40 + (4 * adev->link->ap->port_no) + (2 * adev->devno); 88 } 89 90 /** 91 * sis_133_cable_detect - check for 40/80 pin 92 * @ap: Port 93 * @deadline: deadline jiffies for the operation 94 * 95 * Perform cable detection for the later UDMA133 capable 96 * SiS chipset. 97 */ 98 99 static int sis_133_cable_detect(struct ata_port *ap) 100 { 101 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 102 u16 tmp; 103 104 /* The top bit of this register is the cable detect bit */ 105 pci_read_config_word(pdev, 0x50 + 2 * ap->port_no, &tmp); 106 if ((tmp & 0x8000) && !sis_short_ata40(pdev)) 107 return ATA_CBL_PATA40; 108 return ATA_CBL_PATA80; 109 } 110 111 /** 112 * sis_66_cable_detect - check for 40/80 pin 113 * @ap: Port 114 * @deadline: deadline jiffies for the operation 115 * 116 * Perform cable detection on the UDMA66, UDMA100 and early UDMA133 117 * SiS IDE controllers. 118 */ 119 120 static int sis_66_cable_detect(struct ata_port *ap) 121 { 122 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 123 u8 tmp; 124 125 /* Older chips keep cable detect in bits 4/5 of reg 0x48 */ 126 pci_read_config_byte(pdev, 0x48, &tmp); 127 tmp >>= ap->port_no; 128 if ((tmp & 0x10) && !sis_short_ata40(pdev)) 129 return ATA_CBL_PATA40; 130 return ATA_CBL_PATA80; 131 } 132 133 134 /** 135 * sis_pre_reset - probe begin 136 * @link: ATA link 137 * @deadline: deadline jiffies for the operation 138 * 139 * Set up cable type and use generic probe init 140 */ 141 142 static int sis_pre_reset(struct ata_link *link, unsigned long deadline) 143 { 144 static const struct pci_bits sis_enable_bits[] = { 145 { 0x4aU, 1U, 0x02UL, 0x02UL }, /* port 0 */ 146 { 0x4aU, 1U, 0x04UL, 0x04UL }, /* port 1 */ 147 }; 148 149 struct ata_port *ap = link->ap; 150 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 151 152 if (!pci_test_config_bits(pdev, &sis_enable_bits[ap->port_no])) 153 return -ENOENT; 154 155 /* Clear the FIFO settings. We can't enable the FIFO until 156 we know we are poking at a disk */ 157 pci_write_config_byte(pdev, 0x4B, 0); 158 return ata_std_prereset(link, deadline); 159 } 160 161 162 /** 163 * sis_error_handler - Probe specified port on PATA host controller 164 * @ap: Port to probe 165 * 166 * LOCKING: 167 * None (inherited from caller). 168 */ 169 170 static void sis_error_handler(struct ata_port *ap) 171 { 172 ata_bmdma_drive_eh(ap, sis_pre_reset, ata_std_softreset, NULL, ata_std_postreset); 173 } 174 175 /** 176 * sis_set_fifo - Set RWP fifo bits for this device 177 * @ap: Port 178 * @adev: Device 179 * 180 * SIS chipsets implement prefetch/postwrite bits for each device 181 * on both channels. This functionality is not ATAPI compatible and 182 * must be configured according to the class of device present 183 */ 184 185 static void sis_set_fifo(struct ata_port *ap, struct ata_device *adev) 186 { 187 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 188 u8 fifoctrl; 189 u8 mask = 0x11; 190 191 mask <<= (2 * ap->port_no); 192 mask <<= adev->devno; 193 194 /* This holds various bits including the FIFO control */ 195 pci_read_config_byte(pdev, 0x4B, &fifoctrl); 196 fifoctrl &= ~mask; 197 198 /* Enable for ATA (disk) only */ 199 if (adev->class == ATA_DEV_ATA) 200 fifoctrl |= mask; 201 pci_write_config_byte(pdev, 0x4B, fifoctrl); 202 } 203 204 /** 205 * sis_old_set_piomode - Initialize host controller PATA PIO timings 206 * @ap: Port whose timings we are configuring 207 * @adev: Device we are configuring for. 208 * 209 * Set PIO mode for device, in host controller PCI config space. This 210 * function handles PIO set up for all chips that are pre ATA100 and 211 * also early ATA100 devices. 212 * 213 * LOCKING: 214 * None (inherited from caller). 215 */ 216 217 static void sis_old_set_piomode (struct ata_port *ap, struct ata_device *adev) 218 { 219 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 220 int port = sis_old_port_base(adev); 221 u8 t1, t2; 222 int speed = adev->pio_mode - XFER_PIO_0; 223 224 const u8 active[] = { 0x00, 0x07, 0x04, 0x03, 0x01 }; 225 const u8 recovery[] = { 0x00, 0x06, 0x04, 0x03, 0x03 }; 226 227 sis_set_fifo(ap, adev); 228 229 pci_read_config_byte(pdev, port, &t1); 230 pci_read_config_byte(pdev, port + 1, &t2); 231 232 t1 &= ~0x0F; /* Clear active/recovery timings */ 233 t2 &= ~0x07; 234 235 t1 |= active[speed]; 236 t2 |= recovery[speed]; 237 238 pci_write_config_byte(pdev, port, t1); 239 pci_write_config_byte(pdev, port + 1, t2); 240 } 241 242 /** 243 * sis_100_set_piomode - Initialize host controller PATA PIO timings 244 * @ap: Port whose timings we are configuring 245 * @adev: Device we are configuring for. 246 * 247 * Set PIO mode for device, in host controller PCI config space. This 248 * function handles PIO set up for ATA100 devices and early ATA133. 249 * 250 * LOCKING: 251 * None (inherited from caller). 252 */ 253 254 static void sis_100_set_piomode (struct ata_port *ap, struct ata_device *adev) 255 { 256 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 257 int port = sis_old_port_base(adev); 258 int speed = adev->pio_mode - XFER_PIO_0; 259 260 const u8 actrec[] = { 0x00, 0x67, 0x44, 0x33, 0x31 }; 261 262 sis_set_fifo(ap, adev); 263 264 pci_write_config_byte(pdev, port, actrec[speed]); 265 } 266 267 /** 268 * sis_133_set_piomode - Initialize host controller PATA PIO timings 269 * @ap: Port whose timings we are configuring 270 * @adev: Device we are configuring for. 271 * 272 * Set PIO mode for device, in host controller PCI config space. This 273 * function handles PIO set up for the later ATA133 devices. 274 * 275 * LOCKING: 276 * None (inherited from caller). 277 */ 278 279 static void sis_133_set_piomode (struct ata_port *ap, struct ata_device *adev) 280 { 281 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 282 int port = 0x40; 283 u32 t1; 284 u32 reg54; 285 int speed = adev->pio_mode - XFER_PIO_0; 286 287 const u32 timing133[] = { 288 0x28269000, /* Recovery << 24 | Act << 16 | Ini << 12 */ 289 0x0C266000, 290 0x04263000, 291 0x0C0A3000, 292 0x05093000 293 }; 294 const u32 timing100[] = { 295 0x1E1C6000, /* Recovery << 24 | Act << 16 | Ini << 12 */ 296 0x091C4000, 297 0x031C2000, 298 0x09072000, 299 0x04062000 300 }; 301 302 sis_set_fifo(ap, adev); 303 304 /* If bit 14 is set then the registers are mapped at 0x70 not 0x40 */ 305 pci_read_config_dword(pdev, 0x54, ®54); 306 if (reg54 & 0x40000000) 307 port = 0x70; 308 port += 8 * ap->port_no + 4 * adev->devno; 309 310 pci_read_config_dword(pdev, port, &t1); 311 t1 &= 0xC0C00FFF; /* Mask out timing */ 312 313 if (t1 & 0x08) /* 100 or 133 ? */ 314 t1 |= timing133[speed]; 315 else 316 t1 |= timing100[speed]; 317 pci_write_config_byte(pdev, port, t1); 318 } 319 320 /** 321 * sis_old_set_dmamode - Initialize host controller PATA DMA timings 322 * @ap: Port whose timings we are configuring 323 * @adev: Device to program 324 * 325 * Set UDMA/MWDMA mode for device, in host controller PCI config space. 326 * Handles pre UDMA and UDMA33 devices. Supports MWDMA as well unlike 327 * the old ide/pci driver. 328 * 329 * LOCKING: 330 * None (inherited from caller). 331 */ 332 333 static void sis_old_set_dmamode (struct ata_port *ap, struct ata_device *adev) 334 { 335 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 336 int speed = adev->dma_mode - XFER_MW_DMA_0; 337 int drive_pci = sis_old_port_base(adev); 338 u16 timing; 339 340 const u16 mwdma_bits[] = { 0x008, 0x302, 0x301 }; 341 const u16 udma_bits[] = { 0xE000, 0xC000, 0xA000 }; 342 343 pci_read_config_word(pdev, drive_pci, &timing); 344 345 if (adev->dma_mode < XFER_UDMA_0) { 346 /* bits 3-0 hold recovery timing bits 8-10 active timing and 347 the higer bits are dependant on the device */ 348 timing &= ~0x870F; 349 timing |= mwdma_bits[speed]; 350 } else { 351 /* Bit 15 is UDMA on/off, bit 13-14 are cycle time */ 352 speed = adev->dma_mode - XFER_UDMA_0; 353 timing &= ~0x6000; 354 timing |= udma_bits[speed]; 355 } 356 pci_write_config_word(pdev, drive_pci, timing); 357 } 358 359 /** 360 * sis_66_set_dmamode - Initialize host controller PATA DMA timings 361 * @ap: Port whose timings we are configuring 362 * @adev: Device to program 363 * 364 * Set UDMA/MWDMA mode for device, in host controller PCI config space. 365 * Handles UDMA66 and early UDMA100 devices. Supports MWDMA as well unlike 366 * the old ide/pci driver. 367 * 368 * LOCKING: 369 * None (inherited from caller). 370 */ 371 372 static void sis_66_set_dmamode (struct ata_port *ap, struct ata_device *adev) 373 { 374 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 375 int speed = adev->dma_mode - XFER_MW_DMA_0; 376 int drive_pci = sis_old_port_base(adev); 377 u16 timing; 378 379 /* MWDMA 0-2 and UDMA 0-5 */ 380 const u16 mwdma_bits[] = { 0x008, 0x302, 0x301 }; 381 const u16 udma_bits[] = { 0xF000, 0xD000, 0xB000, 0xA000, 0x9000, 0x8000 }; 382 383 pci_read_config_word(pdev, drive_pci, &timing); 384 385 if (adev->dma_mode < XFER_UDMA_0) { 386 /* bits 3-0 hold recovery timing bits 8-10 active timing and 387 the higer bits are dependant on the device, bit 15 udma */ 388 timing &= ~0x870F; 389 timing |= mwdma_bits[speed]; 390 } else { 391 /* Bit 15 is UDMA on/off, bit 12-14 are cycle time */ 392 speed = adev->dma_mode - XFER_UDMA_0; 393 timing &= ~0xF000; 394 timing |= udma_bits[speed]; 395 } 396 pci_write_config_word(pdev, drive_pci, timing); 397 } 398 399 /** 400 * sis_100_set_dmamode - Initialize host controller PATA DMA timings 401 * @ap: Port whose timings we are configuring 402 * @adev: Device to program 403 * 404 * Set UDMA/MWDMA mode for device, in host controller PCI config space. 405 * Handles UDMA66 and early UDMA100 devices. 406 * 407 * LOCKING: 408 * None (inherited from caller). 409 */ 410 411 static void sis_100_set_dmamode (struct ata_port *ap, struct ata_device *adev) 412 { 413 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 414 int speed = adev->dma_mode - XFER_MW_DMA_0; 415 int drive_pci = sis_old_port_base(adev); 416 u8 timing; 417 418 const u8 udma_bits[] = { 0x8B, 0x87, 0x85, 0x83, 0x82, 0x81}; 419 420 pci_read_config_byte(pdev, drive_pci + 1, &timing); 421 422 if (adev->dma_mode < XFER_UDMA_0) { 423 /* NOT SUPPORTED YET: NEED DATA SHEET. DITTO IN OLD DRIVER */ 424 } else { 425 /* Bit 7 is UDMA on/off, bit 0-3 are cycle time */ 426 speed = adev->dma_mode - XFER_UDMA_0; 427 timing &= ~0x8F; 428 timing |= udma_bits[speed]; 429 } 430 pci_write_config_byte(pdev, drive_pci + 1, timing); 431 } 432 433 /** 434 * sis_133_early_set_dmamode - Initialize host controller PATA DMA timings 435 * @ap: Port whose timings we are configuring 436 * @adev: Device to program 437 * 438 * Set UDMA/MWDMA mode for device, in host controller PCI config space. 439 * Handles early SiS 961 bridges. 440 * 441 * LOCKING: 442 * None (inherited from caller). 443 */ 444 445 static void sis_133_early_set_dmamode (struct ata_port *ap, struct ata_device *adev) 446 { 447 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 448 int speed = adev->dma_mode - XFER_MW_DMA_0; 449 int drive_pci = sis_old_port_base(adev); 450 u8 timing; 451 /* Low 4 bits are timing */ 452 static const u8 udma_bits[] = { 0x8F, 0x8A, 0x87, 0x85, 0x83, 0x82, 0x81}; 453 454 pci_read_config_byte(pdev, drive_pci + 1, &timing); 455 456 if (adev->dma_mode < XFER_UDMA_0) { 457 /* NOT SUPPORTED YET: NEED DATA SHEET. DITTO IN OLD DRIVER */ 458 } else { 459 /* Bit 7 is UDMA on/off, bit 0-3 are cycle time */ 460 speed = adev->dma_mode - XFER_UDMA_0; 461 timing &= ~0x8F; 462 timing |= udma_bits[speed]; 463 } 464 pci_write_config_byte(pdev, drive_pci + 1, timing); 465 } 466 467 /** 468 * sis_133_set_dmamode - Initialize host controller PATA DMA timings 469 * @ap: Port whose timings we are configuring 470 * @adev: Device to program 471 * 472 * Set UDMA/MWDMA mode for device, in host controller PCI config space. 473 * 474 * LOCKING: 475 * None (inherited from caller). 476 */ 477 478 static void sis_133_set_dmamode (struct ata_port *ap, struct ata_device *adev) 479 { 480 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 481 int speed = adev->dma_mode - XFER_MW_DMA_0; 482 int port = 0x40; 483 u32 t1; 484 u32 reg54; 485 486 /* bits 4- cycle time 8 - cvs time */ 487 static const u32 timing_u100[] = { 0x6B0, 0x470, 0x350, 0x140, 0x120, 0x110, 0x000 }; 488 static const u32 timing_u133[] = { 0x9F0, 0x6A0, 0x470, 0x250, 0x230, 0x220, 0x210 }; 489 490 /* If bit 14 is set then the registers are mapped at 0x70 not 0x40 */ 491 pci_read_config_dword(pdev, 0x54, ®54); 492 if (reg54 & 0x40000000) 493 port = 0x70; 494 port += (8 * ap->port_no) + (4 * adev->devno); 495 496 pci_read_config_dword(pdev, port, &t1); 497 498 if (adev->dma_mode < XFER_UDMA_0) { 499 t1 &= ~0x00000004; 500 /* FIXME: need data sheet to add MWDMA here. Also lacking on 501 ide/pci driver */ 502 } else { 503 speed = adev->dma_mode - XFER_UDMA_0; 504 /* if & 8 no UDMA133 - need info for ... */ 505 t1 &= ~0x00000FF0; 506 t1 |= 0x00000004; 507 if (t1 & 0x08) 508 t1 |= timing_u133[speed]; 509 else 510 t1 |= timing_u100[speed]; 511 } 512 pci_write_config_dword(pdev, port, t1); 513 } 514 515 static struct scsi_host_template sis_sht = { 516 .module = THIS_MODULE, 517 .name = DRV_NAME, 518 .ioctl = ata_scsi_ioctl, 519 .queuecommand = ata_scsi_queuecmd, 520 .can_queue = ATA_DEF_QUEUE, 521 .this_id = ATA_SHT_THIS_ID, 522 .sg_tablesize = LIBATA_MAX_PRD, 523 .cmd_per_lun = ATA_SHT_CMD_PER_LUN, 524 .emulated = ATA_SHT_EMULATED, 525 .use_clustering = ATA_SHT_USE_CLUSTERING, 526 .proc_name = DRV_NAME, 527 .dma_boundary = ATA_DMA_BOUNDARY, 528 .slave_configure = ata_scsi_slave_config, 529 .slave_destroy = ata_scsi_slave_destroy, 530 .bios_param = ata_std_bios_param, 531 }; 532 533 static const struct ata_port_operations sis_133_ops = { 534 .set_piomode = sis_133_set_piomode, 535 .set_dmamode = sis_133_set_dmamode, 536 .mode_filter = ata_pci_default_filter, 537 538 .tf_load = ata_tf_load, 539 .tf_read = ata_tf_read, 540 .check_status = ata_check_status, 541 .exec_command = ata_exec_command, 542 .dev_select = ata_std_dev_select, 543 544 .freeze = ata_bmdma_freeze, 545 .thaw = ata_bmdma_thaw, 546 .error_handler = sis_error_handler, 547 .post_internal_cmd = ata_bmdma_post_internal_cmd, 548 .cable_detect = sis_133_cable_detect, 549 550 .bmdma_setup = ata_bmdma_setup, 551 .bmdma_start = ata_bmdma_start, 552 .bmdma_stop = ata_bmdma_stop, 553 .bmdma_status = ata_bmdma_status, 554 .qc_prep = ata_qc_prep, 555 .qc_issue = ata_qc_issue_prot, 556 .data_xfer = ata_data_xfer, 557 558 .irq_handler = ata_interrupt, 559 .irq_clear = ata_bmdma_irq_clear, 560 .irq_on = ata_irq_on, 561 562 .port_start = ata_sff_port_start, 563 }; 564 565 static const struct ata_port_operations sis_133_for_sata_ops = { 566 .set_piomode = sis_133_set_piomode, 567 .set_dmamode = sis_133_set_dmamode, 568 .mode_filter = ata_pci_default_filter, 569 570 .tf_load = ata_tf_load, 571 .tf_read = ata_tf_read, 572 .check_status = ata_check_status, 573 .exec_command = ata_exec_command, 574 .dev_select = ata_std_dev_select, 575 576 .freeze = ata_bmdma_freeze, 577 .thaw = ata_bmdma_thaw, 578 .error_handler = ata_bmdma_error_handler, 579 .post_internal_cmd = ata_bmdma_post_internal_cmd, 580 .cable_detect = sis_133_cable_detect, 581 582 .bmdma_setup = ata_bmdma_setup, 583 .bmdma_start = ata_bmdma_start, 584 .bmdma_stop = ata_bmdma_stop, 585 .bmdma_status = ata_bmdma_status, 586 .qc_prep = ata_qc_prep, 587 .qc_issue = ata_qc_issue_prot, 588 .data_xfer = ata_data_xfer, 589 590 .irq_handler = ata_interrupt, 591 .irq_clear = ata_bmdma_irq_clear, 592 .irq_on = ata_irq_on, 593 594 .port_start = ata_sff_port_start, 595 }; 596 597 static const struct ata_port_operations sis_133_early_ops = { 598 .set_piomode = sis_100_set_piomode, 599 .set_dmamode = sis_133_early_set_dmamode, 600 .mode_filter = ata_pci_default_filter, 601 602 .tf_load = ata_tf_load, 603 .tf_read = ata_tf_read, 604 .check_status = ata_check_status, 605 .exec_command = ata_exec_command, 606 .dev_select = ata_std_dev_select, 607 608 .freeze = ata_bmdma_freeze, 609 .thaw = ata_bmdma_thaw, 610 .error_handler = sis_error_handler, 611 .post_internal_cmd = ata_bmdma_post_internal_cmd, 612 .cable_detect = sis_66_cable_detect, 613 614 .bmdma_setup = ata_bmdma_setup, 615 .bmdma_start = ata_bmdma_start, 616 .bmdma_stop = ata_bmdma_stop, 617 .bmdma_status = ata_bmdma_status, 618 .qc_prep = ata_qc_prep, 619 .qc_issue = ata_qc_issue_prot, 620 .data_xfer = ata_data_xfer, 621 622 .irq_handler = ata_interrupt, 623 .irq_clear = ata_bmdma_irq_clear, 624 .irq_on = ata_irq_on, 625 626 .port_start = ata_sff_port_start, 627 }; 628 629 static const struct ata_port_operations sis_100_ops = { 630 .set_piomode = sis_100_set_piomode, 631 .set_dmamode = sis_100_set_dmamode, 632 .mode_filter = ata_pci_default_filter, 633 634 .tf_load = ata_tf_load, 635 .tf_read = ata_tf_read, 636 .check_status = ata_check_status, 637 .exec_command = ata_exec_command, 638 .dev_select = ata_std_dev_select, 639 640 .freeze = ata_bmdma_freeze, 641 .thaw = ata_bmdma_thaw, 642 .error_handler = sis_error_handler, 643 .post_internal_cmd = ata_bmdma_post_internal_cmd, 644 .cable_detect = sis_66_cable_detect, 645 646 .bmdma_setup = ata_bmdma_setup, 647 .bmdma_start = ata_bmdma_start, 648 .bmdma_stop = ata_bmdma_stop, 649 .bmdma_status = ata_bmdma_status, 650 .qc_prep = ata_qc_prep, 651 .qc_issue = ata_qc_issue_prot, 652 .data_xfer = ata_data_xfer, 653 654 .irq_handler = ata_interrupt, 655 .irq_clear = ata_bmdma_irq_clear, 656 .irq_on = ata_irq_on, 657 658 .port_start = ata_sff_port_start, 659 }; 660 661 static const struct ata_port_operations sis_66_ops = { 662 .set_piomode = sis_old_set_piomode, 663 .set_dmamode = sis_66_set_dmamode, 664 .mode_filter = ata_pci_default_filter, 665 666 .tf_load = ata_tf_load, 667 .tf_read = ata_tf_read, 668 .check_status = ata_check_status, 669 .exec_command = ata_exec_command, 670 .dev_select = ata_std_dev_select, 671 .cable_detect = sis_66_cable_detect, 672 673 .freeze = ata_bmdma_freeze, 674 .thaw = ata_bmdma_thaw, 675 .error_handler = sis_error_handler, 676 .post_internal_cmd = ata_bmdma_post_internal_cmd, 677 678 .bmdma_setup = ata_bmdma_setup, 679 .bmdma_start = ata_bmdma_start, 680 .bmdma_stop = ata_bmdma_stop, 681 .bmdma_status = ata_bmdma_status, 682 .qc_prep = ata_qc_prep, 683 .qc_issue = ata_qc_issue_prot, 684 .data_xfer = ata_data_xfer, 685 686 .irq_handler = ata_interrupt, 687 .irq_clear = ata_bmdma_irq_clear, 688 .irq_on = ata_irq_on, 689 690 .port_start = ata_sff_port_start, 691 }; 692 693 static const struct ata_port_operations sis_old_ops = { 694 .set_piomode = sis_old_set_piomode, 695 .set_dmamode = sis_old_set_dmamode, 696 .mode_filter = ata_pci_default_filter, 697 698 .tf_load = ata_tf_load, 699 .tf_read = ata_tf_read, 700 .check_status = ata_check_status, 701 .exec_command = ata_exec_command, 702 .dev_select = ata_std_dev_select, 703 704 .freeze = ata_bmdma_freeze, 705 .thaw = ata_bmdma_thaw, 706 .error_handler = sis_error_handler, 707 .post_internal_cmd = ata_bmdma_post_internal_cmd, 708 .cable_detect = ata_cable_40wire, 709 710 .bmdma_setup = ata_bmdma_setup, 711 .bmdma_start = ata_bmdma_start, 712 .bmdma_stop = ata_bmdma_stop, 713 .bmdma_status = ata_bmdma_status, 714 .qc_prep = ata_qc_prep, 715 .qc_issue = ata_qc_issue_prot, 716 .data_xfer = ata_data_xfer, 717 718 .irq_handler = ata_interrupt, 719 .irq_clear = ata_bmdma_irq_clear, 720 .irq_on = ata_irq_on, 721 722 .port_start = ata_sff_port_start, 723 }; 724 725 static const struct ata_port_info sis_info = { 726 .sht = &sis_sht, 727 .flags = ATA_FLAG_SLAVE_POSS, 728 .pio_mask = 0x1f, /* pio0-4 */ 729 .mwdma_mask = 0x07, 730 .udma_mask = 0, 731 .port_ops = &sis_old_ops, 732 }; 733 static const struct ata_port_info sis_info33 = { 734 .sht = &sis_sht, 735 .flags = ATA_FLAG_SLAVE_POSS, 736 .pio_mask = 0x1f, /* pio0-4 */ 737 .mwdma_mask = 0x07, 738 .udma_mask = ATA_UDMA2, /* UDMA 33 */ 739 .port_ops = &sis_old_ops, 740 }; 741 static const struct ata_port_info sis_info66 = { 742 .sht = &sis_sht, 743 .flags = ATA_FLAG_SLAVE_POSS, 744 .pio_mask = 0x1f, /* pio0-4 */ 745 .udma_mask = ATA_UDMA4, /* UDMA 66 */ 746 .port_ops = &sis_66_ops, 747 }; 748 static const struct ata_port_info sis_info100 = { 749 .sht = &sis_sht, 750 .flags = ATA_FLAG_SLAVE_POSS, 751 .pio_mask = 0x1f, /* pio0-4 */ 752 .udma_mask = ATA_UDMA5, 753 .port_ops = &sis_100_ops, 754 }; 755 static const struct ata_port_info sis_info100_early = { 756 .sht = &sis_sht, 757 .flags = ATA_FLAG_SLAVE_POSS, 758 .udma_mask = ATA_UDMA5, 759 .pio_mask = 0x1f, /* pio0-4 */ 760 .port_ops = &sis_66_ops, 761 }; 762 static const struct ata_port_info sis_info133 = { 763 .sht = &sis_sht, 764 .flags = ATA_FLAG_SLAVE_POSS, 765 .pio_mask = 0x1f, /* pio0-4 */ 766 .udma_mask = ATA_UDMA6, 767 .port_ops = &sis_133_ops, 768 }; 769 const struct ata_port_info sis_info133_for_sata = { 770 .sht = &sis_sht, 771 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST, 772 .pio_mask = 0x1f, /* pio0-4 */ 773 .udma_mask = ATA_UDMA6, 774 .port_ops = &sis_133_for_sata_ops, 775 }; 776 static const struct ata_port_info sis_info133_early = { 777 .sht = &sis_sht, 778 .flags = ATA_FLAG_SLAVE_POSS, 779 .pio_mask = 0x1f, /* pio0-4 */ 780 .udma_mask = ATA_UDMA6, 781 .port_ops = &sis_133_early_ops, 782 }; 783 784 /* Privately shared with the SiS180 SATA driver, not for use elsewhere */ 785 EXPORT_SYMBOL_GPL(sis_info133_for_sata); 786 787 static void sis_fixup(struct pci_dev *pdev, struct sis_chipset *sis) 788 { 789 u16 regw; 790 u8 reg; 791 792 if (sis->info == &sis_info133) { 793 pci_read_config_word(pdev, 0x50, ®w); 794 if (regw & 0x08) 795 pci_write_config_word(pdev, 0x50, regw & ~0x08); 796 pci_read_config_word(pdev, 0x52, ®w); 797 if (regw & 0x08) 798 pci_write_config_word(pdev, 0x52, regw & ~0x08); 799 return; 800 } 801 802 if (sis->info == &sis_info133_early || sis->info == &sis_info100) { 803 /* Fix up latency */ 804 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80); 805 /* Set compatibility bit */ 806 pci_read_config_byte(pdev, 0x49, ®); 807 if (!(reg & 0x01)) 808 pci_write_config_byte(pdev, 0x49, reg | 0x01); 809 return; 810 } 811 812 if (sis->info == &sis_info66 || sis->info == &sis_info100_early) { 813 /* Fix up latency */ 814 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80); 815 /* Set compatibility bit */ 816 pci_read_config_byte(pdev, 0x52, ®); 817 if (!(reg & 0x04)) 818 pci_write_config_byte(pdev, 0x52, reg | 0x04); 819 return; 820 } 821 822 if (sis->info == &sis_info33) { 823 pci_read_config_byte(pdev, PCI_CLASS_PROG, ®); 824 if (( reg & 0x0F ) != 0x00) 825 pci_write_config_byte(pdev, PCI_CLASS_PROG, reg & 0xF0); 826 /* Fall through to ATA16 fixup below */ 827 } 828 829 if (sis->info == &sis_info || sis->info == &sis_info33) { 830 /* force per drive recovery and active timings 831 needed on ATA_33 and below chips */ 832 pci_read_config_byte(pdev, 0x52, ®); 833 if (!(reg & 0x08)) 834 pci_write_config_byte(pdev, 0x52, reg|0x08); 835 return; 836 } 837 838 BUG(); 839 } 840 841 /** 842 * sis_init_one - Register SiS ATA PCI device with kernel services 843 * @pdev: PCI device to register 844 * @ent: Entry in sis_pci_tbl matching with @pdev 845 * 846 * Called from kernel PCI layer. We probe for combined mode (sigh), 847 * and then hand over control to libata, for it to do the rest. 848 * 849 * LOCKING: 850 * Inherited from PCI layer (may sleep). 851 * 852 * RETURNS: 853 * Zero on success, or -ERRNO value. 854 */ 855 856 static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) 857 { 858 static int printed_version; 859 struct ata_port_info port; 860 const struct ata_port_info *ppi[] = { &port, NULL }; 861 struct pci_dev *host = NULL; 862 struct sis_chipset *chipset = NULL; 863 struct sis_chipset *sets; 864 865 static struct sis_chipset sis_chipsets[] = { 866 867 { 0x0968, &sis_info133 }, 868 { 0x0966, &sis_info133 }, 869 { 0x0965, &sis_info133 }, 870 { 0x0745, &sis_info100 }, 871 { 0x0735, &sis_info100 }, 872 { 0x0733, &sis_info100 }, 873 { 0x0635, &sis_info100 }, 874 { 0x0633, &sis_info100 }, 875 876 { 0x0730, &sis_info100_early }, /* 100 with ATA 66 layout */ 877 { 0x0550, &sis_info100_early }, /* 100 with ATA 66 layout */ 878 879 { 0x0640, &sis_info66 }, 880 { 0x0630, &sis_info66 }, 881 { 0x0620, &sis_info66 }, 882 { 0x0540, &sis_info66 }, 883 { 0x0530, &sis_info66 }, 884 885 { 0x5600, &sis_info33 }, 886 { 0x5598, &sis_info33 }, 887 { 0x5597, &sis_info33 }, 888 { 0x5591, &sis_info33 }, 889 { 0x5582, &sis_info33 }, 890 { 0x5581, &sis_info33 }, 891 892 { 0x5596, &sis_info }, 893 { 0x5571, &sis_info }, 894 { 0x5517, &sis_info }, 895 { 0x5511, &sis_info }, 896 897 {0} 898 }; 899 static struct sis_chipset sis133_early = { 900 0x0, &sis_info133_early 901 }; 902 static struct sis_chipset sis133 = { 903 0x0, &sis_info133 904 }; 905 static struct sis_chipset sis100_early = { 906 0x0, &sis_info100_early 907 }; 908 static struct sis_chipset sis100 = { 909 0x0, &sis_info100 910 }; 911 912 if (!printed_version++) 913 dev_printk(KERN_DEBUG, &pdev->dev, 914 "version " DRV_VERSION "\n"); 915 916 /* We have to find the bridge first */ 917 918 for (sets = &sis_chipsets[0]; sets->device; sets++) { 919 host = pci_get_device(PCI_VENDOR_ID_SI, sets->device, NULL); 920 if (host != NULL) { 921 chipset = sets; /* Match found */ 922 if (sets->device == 0x630) { /* SIS630 */ 923 if (host->revision >= 0x30) /* 630 ET */ 924 chipset = &sis100_early; 925 } 926 break; 927 } 928 } 929 930 /* Look for concealed bridges */ 931 if (chipset == NULL) { 932 /* Second check */ 933 u32 idemisc; 934 u16 trueid; 935 936 /* Disable ID masking and register remapping then 937 see what the real ID is */ 938 939 pci_read_config_dword(pdev, 0x54, &idemisc); 940 pci_write_config_dword(pdev, 0x54, idemisc & 0x7fffffff); 941 pci_read_config_word(pdev, PCI_DEVICE_ID, &trueid); 942 pci_write_config_dword(pdev, 0x54, idemisc); 943 944 switch(trueid) { 945 case 0x5518: /* SIS 962/963 */ 946 chipset = &sis133; 947 if ((idemisc & 0x40000000) == 0) { 948 pci_write_config_dword(pdev, 0x54, idemisc | 0x40000000); 949 printk(KERN_INFO "SIS5513: Switching to 5513 register mapping\n"); 950 } 951 break; 952 case 0x0180: /* SIS 965/965L */ 953 chipset = &sis133; 954 break; 955 case 0x1180: /* SIS 966/966L */ 956 chipset = &sis133; 957 break; 958 } 959 } 960 961 /* Further check */ 962 if (chipset == NULL) { 963 struct pci_dev *lpc_bridge; 964 u16 trueid; 965 u8 prefctl; 966 u8 idecfg; 967 968 /* Try the second unmasking technique */ 969 pci_read_config_byte(pdev, 0x4a, &idecfg); 970 pci_write_config_byte(pdev, 0x4a, idecfg | 0x10); 971 pci_read_config_word(pdev, PCI_DEVICE_ID, &trueid); 972 pci_write_config_byte(pdev, 0x4a, idecfg); 973 974 switch(trueid) { 975 case 0x5517: 976 lpc_bridge = pci_get_slot(pdev->bus, 0x10); /* Bus 0 Dev 2 Fn 0 */ 977 if (lpc_bridge == NULL) 978 break; 979 pci_read_config_byte(pdev, 0x49, &prefctl); 980 pci_dev_put(lpc_bridge); 981 982 if (lpc_bridge->revision == 0x10 && (prefctl & 0x80)) { 983 chipset = &sis133_early; 984 break; 985 } 986 chipset = &sis100; 987 break; 988 } 989 } 990 pci_dev_put(host); 991 992 /* No chipset info, no support */ 993 if (chipset == NULL) 994 return -ENODEV; 995 996 port = *chipset->info; 997 port.private_data = chipset; 998 999 sis_fixup(pdev, chipset); 1000 1001 return ata_pci_init_one(pdev, ppi); 1002 } 1003 1004 static const struct pci_device_id sis_pci_tbl[] = { 1005 { PCI_VDEVICE(SI, 0x5513), }, /* SiS 5513 */ 1006 { PCI_VDEVICE(SI, 0x5518), }, /* SiS 5518 */ 1007 { PCI_VDEVICE(SI, 0x1180), }, /* SiS 1180 */ 1008 1009 { } 1010 }; 1011 1012 static struct pci_driver sis_pci_driver = { 1013 .name = DRV_NAME, 1014 .id_table = sis_pci_tbl, 1015 .probe = sis_init_one, 1016 .remove = ata_pci_remove_one, 1017 #ifdef CONFIG_PM 1018 .suspend = ata_pci_device_suspend, 1019 .resume = ata_pci_device_resume, 1020 #endif 1021 }; 1022 1023 static int __init sis_init(void) 1024 { 1025 return pci_register_driver(&sis_pci_driver); 1026 } 1027 1028 static void __exit sis_exit(void) 1029 { 1030 pci_unregister_driver(&sis_pci_driver); 1031 } 1032 1033 module_init(sis_init); 1034 module_exit(sis_exit); 1035 1036 MODULE_AUTHOR("Alan Cox"); 1037 MODULE_DESCRIPTION("SCSI low-level driver for SiS ATA"); 1038 MODULE_LICENSE("GPL"); 1039 MODULE_DEVICE_TABLE(pci, sis_pci_tbl); 1040 MODULE_VERSION(DRV_VERSION); 1041 1042