1432d4130SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only
207ab85deSAlek Du /*
307ab85deSAlek Du * pata_sch.c - Intel SCH PATA controllers
407ab85deSAlek Du *
507ab85deSAlek Du * Copyright (c) 2008 Alek Du <alek.du@intel.com>
607ab85deSAlek Du */
707ab85deSAlek Du
807ab85deSAlek Du /*
907ab85deSAlek Du * Supports:
1007ab85deSAlek Du * Intel SCH (AF82US15W, AF82US15L, AF82UL11L) chipsets -- see spec at:
1107ab85deSAlek Du * http://download.intel.com/design/chipsets/embedded/datashts/319537.pdf
1207ab85deSAlek Du */
1307ab85deSAlek Du
1407ab85deSAlek Du #include <linux/kernel.h>
1507ab85deSAlek Du #include <linux/module.h>
1607ab85deSAlek Du #include <linux/pci.h>
1707ab85deSAlek Du #include <linux/blkdev.h>
1807ab85deSAlek Du #include <linux/delay.h>
1907ab85deSAlek Du #include <linux/device.h>
2007ab85deSAlek Du #include <scsi/scsi_host.h>
2107ab85deSAlek Du #include <linux/libata.h>
2207ab85deSAlek Du #include <linux/dmi.h>
2307ab85deSAlek Du
2407ab85deSAlek Du #define DRV_NAME "pata_sch"
2507ab85deSAlek Du #define DRV_VERSION "0.2"
2607ab85deSAlek Du
2707ab85deSAlek Du /* see SCH datasheet page 351 */
2807ab85deSAlek Du enum {
2907ab85deSAlek Du D0TIM = 0x80, /* Device 0 Timing Register */
3007ab85deSAlek Du D1TIM = 0x84, /* Device 1 Timing Register */
3107ab85deSAlek Du PM = 0x07, /* PIO Mode Bit Mask */
3207ab85deSAlek Du MDM = (0x03 << 8), /* Multi-word DMA Mode Bit Mask */
3307ab85deSAlek Du UDM = (0x07 << 16), /* Ultra DMA Mode Bit Mask */
3407ab85deSAlek Du PPE = (1 << 30), /* Prefetch/Post Enable */
3507ab85deSAlek Du USD = (1 << 31), /* Use Synchronous DMA */
3607ab85deSAlek Du };
3707ab85deSAlek Du
3807ab85deSAlek Du static int sch_init_one(struct pci_dev *pdev,
3907ab85deSAlek Du const struct pci_device_id *ent);
4007ab85deSAlek Du static void sch_set_piomode(struct ata_port *ap, struct ata_device *adev);
4107ab85deSAlek Du static void sch_set_dmamode(struct ata_port *ap, struct ata_device *adev);
4207ab85deSAlek Du
4307ab85deSAlek Du static const struct pci_device_id sch_pci_tbl[] = {
4407ab85deSAlek Du /* Intel SCH PATA Controller */
4507ab85deSAlek Du { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_SCH_IDE), 0 },
4607ab85deSAlek Du { } /* terminate list */
4707ab85deSAlek Du };
4807ab85deSAlek Du
4907ab85deSAlek Du static struct pci_driver sch_pci_driver = {
5007ab85deSAlek Du .name = DRV_NAME,
5107ab85deSAlek Du .id_table = sch_pci_tbl,
5207ab85deSAlek Du .probe = sch_init_one,
5307ab85deSAlek Du .remove = ata_pci_remove_one,
5458eb8cd5SBartlomiej Zolnierkiewicz #ifdef CONFIG_PM_SLEEP
5507ab85deSAlek Du .suspend = ata_pci_device_suspend,
5607ab85deSAlek Du .resume = ata_pci_device_resume,
5707ab85deSAlek Du #endif
5807ab85deSAlek Du };
5907ab85deSAlek Du
60*25df73d9SBart Van Assche static const struct scsi_host_template sch_sht = {
6107ab85deSAlek Du ATA_BMDMA_SHT(DRV_NAME),
6207ab85deSAlek Du };
6307ab85deSAlek Du
6407ab85deSAlek Du static struct ata_port_operations sch_pata_ops = {
6507ab85deSAlek Du .inherits = &ata_bmdma_port_ops,
6607ab85deSAlek Du .cable_detect = ata_cable_unknown,
6707ab85deSAlek Du .set_piomode = sch_set_piomode,
6807ab85deSAlek Du .set_dmamode = sch_set_dmamode,
6907ab85deSAlek Du };
7007ab85deSAlek Du
71f356b082SBhumika Goyal static const struct ata_port_info sch_port_info = {
72bc170e65SMark Salter .flags = ATA_FLAG_SLAVE_POSS,
7314bdef98SErik Inge Bolsø .pio_mask = ATA_PIO4,
7414bdef98SErik Inge Bolsø .mwdma_mask = ATA_MWDMA2,
7514bdef98SErik Inge Bolsø .udma_mask = ATA_UDMA5,
7607ab85deSAlek Du .port_ops = &sch_pata_ops,
7707ab85deSAlek Du };
7807ab85deSAlek Du
7907ab85deSAlek Du MODULE_AUTHOR("Alek Du <alek.du@intel.com>");
8007ab85deSAlek Du MODULE_DESCRIPTION("SCSI low-level driver for Intel SCH PATA controllers");
8107ab85deSAlek Du MODULE_LICENSE("GPL");
8207ab85deSAlek Du MODULE_DEVICE_TABLE(pci, sch_pci_tbl);
8307ab85deSAlek Du MODULE_VERSION(DRV_VERSION);
8407ab85deSAlek Du
8507ab85deSAlek Du /**
8607ab85deSAlek Du * sch_set_piomode - Initialize host controller PATA PIO timings
8707ab85deSAlek Du * @ap: Port whose timings we are configuring
8807ab85deSAlek Du * @adev: ATA device
8907ab85deSAlek Du *
9007ab85deSAlek Du * Set PIO mode for device, in host controller PCI config space.
9107ab85deSAlek Du *
9207ab85deSAlek Du * LOCKING:
9307ab85deSAlek Du * None (inherited from caller).
9407ab85deSAlek Du */
9507ab85deSAlek Du
sch_set_piomode(struct ata_port * ap,struct ata_device * adev)9607ab85deSAlek Du static void sch_set_piomode(struct ata_port *ap, struct ata_device *adev)
9707ab85deSAlek Du {
9807ab85deSAlek Du unsigned int pio = adev->pio_mode - XFER_PIO_0;
9907ab85deSAlek Du struct pci_dev *dev = to_pci_dev(ap->host->dev);
10007ab85deSAlek Du unsigned int port = adev->devno ? D1TIM : D0TIM;
10107ab85deSAlek Du unsigned int data;
10207ab85deSAlek Du
10307ab85deSAlek Du pci_read_config_dword(dev, port, &data);
10407ab85deSAlek Du /* see SCH datasheet page 351 */
10507ab85deSAlek Du /* set PIO mode */
10607ab85deSAlek Du data &= ~(PM | PPE);
10707ab85deSAlek Du data |= pio;
10807ab85deSAlek Du /* enable PPE for block device */
10907ab85deSAlek Du if (adev->class == ATA_DEV_ATA)
11007ab85deSAlek Du data |= PPE;
11107ab85deSAlek Du pci_write_config_dword(dev, port, data);
11207ab85deSAlek Du }
11307ab85deSAlek Du
11407ab85deSAlek Du /**
11507ab85deSAlek Du * sch_set_dmamode - Initialize host controller PATA DMA timings
11607ab85deSAlek Du * @ap: Port whose timings we are configuring
11707ab85deSAlek Du * @adev: ATA device
11807ab85deSAlek Du *
11907ab85deSAlek Du * Set MW/UDMA mode for device, in host controller PCI config space.
12007ab85deSAlek Du *
12107ab85deSAlek Du * LOCKING:
12207ab85deSAlek Du * None (inherited from caller).
12307ab85deSAlek Du */
12407ab85deSAlek Du
sch_set_dmamode(struct ata_port * ap,struct ata_device * adev)12507ab85deSAlek Du static void sch_set_dmamode(struct ata_port *ap, struct ata_device *adev)
12607ab85deSAlek Du {
12707ab85deSAlek Du unsigned int dma_mode = adev->dma_mode;
12807ab85deSAlek Du struct pci_dev *dev = to_pci_dev(ap->host->dev);
12907ab85deSAlek Du unsigned int port = adev->devno ? D1TIM : D0TIM;
13007ab85deSAlek Du unsigned int data;
13107ab85deSAlek Du
13207ab85deSAlek Du pci_read_config_dword(dev, port, &data);
13307ab85deSAlek Du /* see SCH datasheet page 351 */
13407ab85deSAlek Du if (dma_mode >= XFER_UDMA_0) {
13507ab85deSAlek Du /* enable Synchronous DMA mode */
13607ab85deSAlek Du data |= USD;
13707ab85deSAlek Du data &= ~UDM;
13807ab85deSAlek Du data |= (dma_mode - XFER_UDMA_0) << 16;
13907ab85deSAlek Du } else { /* must be MWDMA mode, since we masked SWDMA already */
14007ab85deSAlek Du data &= ~(USD | MDM);
14107ab85deSAlek Du data |= (dma_mode - XFER_MW_DMA_0) << 8;
14207ab85deSAlek Du }
14307ab85deSAlek Du pci_write_config_dword(dev, port, data);
14407ab85deSAlek Du }
14507ab85deSAlek Du
14607ab85deSAlek Du /**
14707ab85deSAlek Du * sch_init_one - Register SCH ATA PCI device with kernel services
14807ab85deSAlek Du * @pdev: PCI device to register
14907ab85deSAlek Du * @ent: Entry in sch_pci_tbl matching with @pdev
15007ab85deSAlek Du *
15107ab85deSAlek Du * LOCKING:
15207ab85deSAlek Du * Inherited from PCI layer (may sleep).
15307ab85deSAlek Du *
15407ab85deSAlek Du * RETURNS:
15507ab85deSAlek Du * Zero on success, or -ERRNO value.
15607ab85deSAlek Du */
15707ab85deSAlek Du
sch_init_one(struct pci_dev * pdev,const struct pci_device_id * ent)1580ec24914SGreg Kroah-Hartman static int sch_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
15907ab85deSAlek Du {
16007ab85deSAlek Du const struct ata_port_info *ppi[] = { &sch_port_info, NULL };
16107ab85deSAlek Du
16206296a1eSJoe Perches ata_print_version_once(&pdev->dev, DRV_VERSION);
16307ab85deSAlek Du
1641c5afdf7STejun Heo return ata_pci_bmdma_init_one(pdev, ppi, &sch_sht, NULL, 0);
16507ab85deSAlek Du }
16607ab85deSAlek Du
1672fc75da0SAxel Lin module_pci_driver(sch_pci_driver);
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