xref: /openbmc/linux/drivers/ata/pata_ali.c (revision 96de0e252cedffad61b3cb5e05662c591898e69a)
1 /*
2  * pata_ali.c 	- ALI 15x3 PATA for new ATA layer
3  *			  (C) 2005 Red Hat Inc
4  *			  Alan Cox <alan@redhat.com>
5  *
6  * based in part upon
7  * linux/drivers/ide/pci/alim15x3.c		Version 0.17	2003/01/02
8  *
9  *  Copyright (C) 1998-2000 Michel Aubry, Maintainer
10  *  Copyright (C) 1998-2000 Andrzej Krzysztofowicz, Maintainer
11  *  Copyright (C) 1999-2000 CJ, cjtsai@ali.com.tw, Maintainer
12  *
13  *  Copyright (C) 1998-2000 Andre Hedrick (andre@linux-ide.org)
14  *  May be copied or modified under the terms of the GNU General Public License
15  *  Copyright (C) 2002 Alan Cox <alan@redhat.com>
16  *  ALi (now ULi M5228) support by Clear Zhang <Clear.Zhang@ali.com.tw>
17  *
18  *  Documentation
19  *	Chipset documentation available under NDA only
20  *
21  *  TODO/CHECK
22  *	Cannot have ATAPI on both master & slave for rev < c2 (???) but
23  *	otherwise should do atapi DMA.
24  */
25 
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/pci.h>
29 #include <linux/init.h>
30 #include <linux/blkdev.h>
31 #include <linux/delay.h>
32 #include <scsi/scsi_host.h>
33 #include <linux/libata.h>
34 #include <linux/dmi.h>
35 
36 #define DRV_NAME "pata_ali"
37 #define DRV_VERSION "0.7.5"
38 
39 /*
40  *	Cable special cases
41  */
42 
43 static const struct dmi_system_id cable_dmi_table[] = {
44 	{
45 		.ident = "HP Pavilion N5430",
46 		.matches = {
47 			DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
48 			DMI_MATCH(DMI_BOARD_VERSION, "OmniBook N32N-736"),
49 		},
50 	},
51 	{
52 		.ident = "Toshiba Satelite S1800-814",
53 		.matches = {
54 			DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
55 			DMI_MATCH(DMI_PRODUCT_NAME, "S1800-814"),
56 		},
57 	},
58 	{ }
59 };
60 
61 static int ali_cable_override(struct pci_dev *pdev)
62 {
63 	/* Fujitsu P2000 */
64 	if (pdev->subsystem_vendor == 0x10CF && pdev->subsystem_device == 0x10AF)
65 	   	return 1;
66 	/* Systems by DMI */
67 	if (dmi_check_system(cable_dmi_table))
68 		return 1;
69 	return 0;
70 }
71 
72 /**
73  *	ali_c2_cable_detect	-	cable detection
74  *	@ap: ATA port
75  *
76  *	Perform cable detection for C2 and later revisions
77  */
78 
79 static int ali_c2_cable_detect(struct ata_port *ap)
80 {
81 	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
82 	u8 ata66;
83 
84 	/* Certain laptops use short but suitable cables and don't
85 	   implement the detect logic */
86 
87 	if (ali_cable_override(pdev))
88 		return ATA_CBL_PATA40_SHORT;
89 
90 	/* Host view cable detect 0x4A bit 0 primary bit 1 secondary
91 	   Bit set for 40 pin */
92 	pci_read_config_byte(pdev, 0x4A, &ata66);
93 	if (ata66 & (1 << ap->port_no))
94 		return ATA_CBL_PATA40;
95 	else
96 		return ATA_CBL_PATA80;
97 }
98 
99 /**
100  *	ali_20_filter		-	filter for earlier ALI DMA
101  *	@ap: ALi ATA port
102  *	@adev: attached device
103  *
104  *	Ensure that we do not do DMA on CD devices. We may be able to
105  *	fix that later on. Also ensure we do not do UDMA on WDC drives
106  */
107 
108 static unsigned long ali_20_filter(struct ata_device *adev, unsigned long mask)
109 {
110 	char model_num[ATA_ID_PROD_LEN + 1];
111 	/* No DMA on anything but a disk for now */
112 	if (adev->class != ATA_DEV_ATA)
113 		mask &= ~(ATA_MASK_MWDMA | ATA_MASK_UDMA);
114 	ata_id_c_string(adev->id, model_num, ATA_ID_PROD, sizeof(model_num));
115 	if (strstr(model_num, "WDC"))
116 		return mask &= ~ATA_MASK_UDMA;
117 	return ata_pci_default_filter(adev, mask);
118 }
119 
120 /**
121  *	ali_fifo_control	-	FIFO manager
122  *	@ap: ALi channel to control
123  *	@adev: device for FIFO control
124  *	@on: 0 for off 1 for on
125  *
126  *	Enable or disable the FIFO on a given device. Because of the way the
127  *	ALi FIFO works it provides a boost on ATA disk but can be confused by
128  *	ATAPI and we must therefore manage it.
129  */
130 
131 static void ali_fifo_control(struct ata_port *ap, struct ata_device *adev, int on)
132 {
133 	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
134 	int pio_fifo = 0x54 + ap->port_no;
135 	u8 fifo;
136 	int shift = 4 * adev->devno;
137 
138 	/* ATA - FIFO on set nibble to 0x05, ATAPI - FIFO off, set nibble to
139 	   0x00. Not all the docs agree but the behaviour we now use is the
140 	   one stated in the BIOS Programming Guide */
141 
142 	pci_read_config_byte(pdev, pio_fifo, &fifo);
143 	fifo &= ~(0x0F << shift);
144 	if (on)
145 		fifo |= (on << shift);
146 	pci_write_config_byte(pdev, pio_fifo, fifo);
147 }
148 
149 /**
150  *	ali_program_modes	-	load mode registers
151  *	@ap: ALi channel to load
152  *	@adev: Device the timing is for
153  *	@cmd: Command timing
154  *	@data: Data timing
155  *	@ultra: UDMA timing or zero for off
156  *
157  *	Loads the timing registers for cmd/data and disable UDMA if
158  *	ultra is zero. If ultra is set then load and enable the UDMA
159  *	timing but do not touch the command/data timing.
160  */
161 
162 static void ali_program_modes(struct ata_port *ap, struct ata_device *adev, struct ata_timing *t, u8 ultra)
163 {
164 	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
165 	int cas = 0x58 + 4 * ap->port_no;	/* Command timing */
166 	int cbt = 0x59 + 4 * ap->port_no;	/* Command timing */
167 	int drwt = 0x5A + 4 * ap->port_no + adev->devno; /* R/W timing */
168 	int udmat = 0x56 + ap->port_no;	/* UDMA timing */
169 	int shift = 4 * adev->devno;
170 	u8 udma;
171 
172 	if (t != NULL) {
173 		t->setup = FIT(t->setup, 1, 8) & 7;
174 		t->act8b = FIT(t->act8b, 1, 8) & 7;
175 		t->rec8b = FIT(t->rec8b, 1, 16) & 15;
176 		t->active = FIT(t->active, 1, 8) & 7;
177 		t->recover = FIT(t->recover, 1, 16) & 15;
178 
179 		pci_write_config_byte(pdev, cas, t->setup);
180 		pci_write_config_byte(pdev, cbt, (t->act8b << 4) | t->rec8b);
181 		pci_write_config_byte(pdev, drwt, (t->active << 4) | t->recover);
182 	}
183 
184 	/* Set up the UDMA enable */
185 	pci_read_config_byte(pdev, udmat, &udma);
186 	udma &= ~(0x0F << shift);
187 	udma |= ultra << shift;
188 	pci_write_config_byte(pdev, udmat, udma);
189 }
190 
191 /**
192  *	ali_set_piomode	-	set initial PIO mode data
193  *	@ap: ATA interface
194  *	@adev: ATA device
195  *
196  *	Program the ALi registers for PIO mode. FIXME: add timings for
197  *	PIO5.
198  */
199 
200 static void ali_set_piomode(struct ata_port *ap, struct ata_device *adev)
201 {
202 	struct ata_device *pair = ata_dev_pair(adev);
203 	struct ata_timing t;
204 	unsigned long T =  1000000000 / 33333;	/* PCI clock based */
205 
206 	ata_timing_compute(adev, adev->pio_mode, &t, T, 1);
207 	if (pair) {
208 		struct ata_timing p;
209 		ata_timing_compute(pair, pair->pio_mode, &p, T, 1);
210 		ata_timing_merge(&p, &t, &t, ATA_TIMING_SETUP|ATA_TIMING_8BIT);
211 		if (pair->dma_mode) {
212 			ata_timing_compute(pair, pair->dma_mode, &p, T, 1);
213 			ata_timing_merge(&p, &t, &t, ATA_TIMING_SETUP|ATA_TIMING_8BIT);
214 		}
215 	}
216 
217 	/* PIO FIFO is only permitted on ATA disk */
218 	if (adev->class != ATA_DEV_ATA)
219 		ali_fifo_control(ap, adev, 0x00);
220 	ali_program_modes(ap, adev, &t, 0);
221 	if (adev->class == ATA_DEV_ATA)
222 		ali_fifo_control(ap, adev, 0x05);
223 
224 }
225 
226 /**
227  *	ali_set_dmamode	-	set initial DMA mode data
228  *	@ap: ATA interface
229  *	@adev: ATA device
230  *
231  *	FIXME: MWDMA timings
232  */
233 
234 static void ali_set_dmamode(struct ata_port *ap, struct ata_device *adev)
235 {
236 	static u8 udma_timing[7] = { 0xC, 0xB, 0xA, 0x9, 0x8, 0xF, 0xD };
237 	struct ata_device *pair = ata_dev_pair(adev);
238 	struct ata_timing t;
239 	unsigned long T =  1000000000 / 33333;	/* PCI clock based */
240 	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
241 
242 
243 	if (adev->class == ATA_DEV_ATA)
244 		ali_fifo_control(ap, adev, 0x08);
245 
246 	if (adev->dma_mode >= XFER_UDMA_0) {
247 		ali_program_modes(ap, adev, NULL, udma_timing[adev->dma_mode - XFER_UDMA_0]);
248 		if (adev->dma_mode >= XFER_UDMA_3) {
249 			u8 reg4b;
250 			pci_read_config_byte(pdev, 0x4B, &reg4b);
251 			reg4b |= 1;
252 			pci_write_config_byte(pdev, 0x4B, reg4b);
253 		}
254 	} else {
255 		ata_timing_compute(adev, adev->dma_mode, &t, T, 1);
256 		if (pair) {
257 			struct ata_timing p;
258 			ata_timing_compute(pair, pair->pio_mode, &p, T, 1);
259 			ata_timing_merge(&p, &t, &t, ATA_TIMING_SETUP|ATA_TIMING_8BIT);
260 			if (pair->dma_mode) {
261 				ata_timing_compute(pair, pair->dma_mode, &p, T, 1);
262 				ata_timing_merge(&p, &t, &t, ATA_TIMING_SETUP|ATA_TIMING_8BIT);
263 			}
264 		}
265 		ali_program_modes(ap, adev, &t, 0);
266 	}
267 }
268 
269 /**
270  *	ali_lock_sectors	-	Keep older devices to 255 sector mode
271  *	@adev: Device
272  *
273  *	Called during the bus probe for each device that is found. We use
274  *	this call to lock the sector count of the device to 255 or less on
275  *	older ALi controllers. If we didn't do this then large I/O's would
276  *	require LBA48 commands which the older ALi requires are issued by
277  *	slower PIO methods
278  */
279 
280 static void ali_lock_sectors(struct ata_device *adev)
281 {
282 	adev->max_sectors = 255;
283 }
284 
285 static struct scsi_host_template ali_sht = {
286 	.module			= THIS_MODULE,
287 	.name			= DRV_NAME,
288 	.ioctl			= ata_scsi_ioctl,
289 	.queuecommand		= ata_scsi_queuecmd,
290 	.can_queue		= ATA_DEF_QUEUE,
291 	.this_id		= ATA_SHT_THIS_ID,
292 	.sg_tablesize		= LIBATA_MAX_PRD,
293 	.cmd_per_lun		= ATA_SHT_CMD_PER_LUN,
294 	.emulated		= ATA_SHT_EMULATED,
295 	.use_clustering		= ATA_SHT_USE_CLUSTERING,
296 	.proc_name		= DRV_NAME,
297 	.dma_boundary		= ATA_DMA_BOUNDARY,
298 	.slave_configure	= ata_scsi_slave_config,
299 	.slave_destroy		= ata_scsi_slave_destroy,
300 	.bios_param		= ata_std_bios_param,
301 };
302 
303 /*
304  *	Port operations for PIO only ALi
305  */
306 
307 static struct ata_port_operations ali_early_port_ops = {
308 	.set_piomode	= ali_set_piomode,
309 	.tf_load	= ata_tf_load,
310 	.tf_read	= ata_tf_read,
311 	.check_status 	= ata_check_status,
312 	.exec_command	= ata_exec_command,
313 	.dev_select 	= ata_std_dev_select,
314 
315 	.freeze		= ata_bmdma_freeze,
316 	.thaw		= ata_bmdma_thaw,
317 	.error_handler	= ata_bmdma_error_handler,
318 	.post_internal_cmd = ata_bmdma_post_internal_cmd,
319 	.cable_detect	= ata_cable_40wire,
320 
321 	.qc_prep 	= ata_qc_prep,
322 	.qc_issue	= ata_qc_issue_prot,
323 
324 	.data_xfer	= ata_data_xfer,
325 
326 	.irq_handler	= ata_interrupt,
327 	.irq_clear	= ata_bmdma_irq_clear,
328 	.irq_on		= ata_irq_on,
329 
330 	.port_start	= ata_sff_port_start,
331 };
332 
333 /*
334  *	Port operations for DMA capable ALi without cable
335  *	detect
336  */
337 static struct ata_port_operations ali_20_port_ops = {
338 	.set_piomode	= ali_set_piomode,
339 	.set_dmamode	= ali_set_dmamode,
340 	.mode_filter	= ali_20_filter,
341 
342 	.tf_load	= ata_tf_load,
343 	.tf_read	= ata_tf_read,
344 	.check_status 	= ata_check_status,
345 	.exec_command	= ata_exec_command,
346 	.dev_select 	= ata_std_dev_select,
347 	.dev_config	= ali_lock_sectors,
348 
349 	.freeze		= ata_bmdma_freeze,
350 	.thaw		= ata_bmdma_thaw,
351 	.error_handler	= ata_bmdma_error_handler,
352 	.post_internal_cmd = ata_bmdma_post_internal_cmd,
353 	.cable_detect	= ata_cable_40wire,
354 
355 	.bmdma_setup 	= ata_bmdma_setup,
356 	.bmdma_start 	= ata_bmdma_start,
357 	.bmdma_stop	= ata_bmdma_stop,
358 	.bmdma_status 	= ata_bmdma_status,
359 
360 	.qc_prep 	= ata_qc_prep,
361 	.qc_issue	= ata_qc_issue_prot,
362 
363 	.data_xfer	= ata_data_xfer,
364 
365 	.irq_handler	= ata_interrupt,
366 	.irq_clear	= ata_bmdma_irq_clear,
367 	.irq_on		= ata_irq_on,
368 
369 	.port_start	= ata_sff_port_start,
370 };
371 
372 /*
373  *	Port operations for DMA capable ALi with cable detect
374  */
375 static struct ata_port_operations ali_c2_port_ops = {
376 	.set_piomode	= ali_set_piomode,
377 	.set_dmamode	= ali_set_dmamode,
378 	.mode_filter	= ata_pci_default_filter,
379 	.tf_load	= ata_tf_load,
380 	.tf_read	= ata_tf_read,
381 	.check_status 	= ata_check_status,
382 	.exec_command	= ata_exec_command,
383 	.dev_select 	= ata_std_dev_select,
384 	.dev_config	= ali_lock_sectors,
385 
386 	.freeze		= ata_bmdma_freeze,
387 	.thaw		= ata_bmdma_thaw,
388 	.error_handler	= ata_bmdma_error_handler,
389 	.post_internal_cmd = ata_bmdma_post_internal_cmd,
390 	.cable_detect	= ali_c2_cable_detect,
391 
392 	.bmdma_setup 	= ata_bmdma_setup,
393 	.bmdma_start 	= ata_bmdma_start,
394 	.bmdma_stop	= ata_bmdma_stop,
395 	.bmdma_status 	= ata_bmdma_status,
396 
397 	.qc_prep 	= ata_qc_prep,
398 	.qc_issue	= ata_qc_issue_prot,
399 
400 	.data_xfer	= ata_data_xfer,
401 
402 	.irq_handler	= ata_interrupt,
403 	.irq_clear	= ata_bmdma_irq_clear,
404 	.irq_on		= ata_irq_on,
405 
406 	.port_start	= ata_sff_port_start,
407 };
408 
409 /*
410  *	Port operations for DMA capable ALi with cable detect and LBA48
411  */
412 static struct ata_port_operations ali_c5_port_ops = {
413 	.set_piomode	= ali_set_piomode,
414 	.set_dmamode	= ali_set_dmamode,
415 	.mode_filter	= ata_pci_default_filter,
416 	.tf_load	= ata_tf_load,
417 	.tf_read	= ata_tf_read,
418 	.check_status 	= ata_check_status,
419 	.exec_command	= ata_exec_command,
420 	.dev_select 	= ata_std_dev_select,
421 
422 	.freeze		= ata_bmdma_freeze,
423 	.thaw		= ata_bmdma_thaw,
424 	.error_handler	= ata_bmdma_error_handler,
425 	.post_internal_cmd = ata_bmdma_post_internal_cmd,
426 	.cable_detect	= ali_c2_cable_detect,
427 
428 	.bmdma_setup 	= ata_bmdma_setup,
429 	.bmdma_start 	= ata_bmdma_start,
430 	.bmdma_stop	= ata_bmdma_stop,
431 	.bmdma_status 	= ata_bmdma_status,
432 
433 	.qc_prep 	= ata_qc_prep,
434 	.qc_issue	= ata_qc_issue_prot,
435 
436 	.data_xfer	= ata_data_xfer,
437 
438 	.irq_handler	= ata_interrupt,
439 	.irq_clear	= ata_bmdma_irq_clear,
440 	.irq_on		= ata_irq_on,
441 
442 	.port_start	= ata_sff_port_start,
443 };
444 
445 
446 /**
447  *	ali_init_chipset	-	chip setup function
448  *	@pdev: PCI device of ATA controller
449  *
450  *	Perform the setup on the device that must be done both at boot
451  *	and at resume time.
452  */
453 
454 static void ali_init_chipset(struct pci_dev *pdev)
455 {
456 	u8 tmp;
457 	struct pci_dev *north, *isa_bridge;
458 
459 	/*
460 	 * The chipset revision selects the driver operations and
461 	 * mode data.
462 	 */
463 
464 	if (pdev->revision >= 0x20 && pdev->revision < 0xC2) {
465 		/* 1543-E/F, 1543C-C, 1543C-D, 1543C-E */
466 		pci_read_config_byte(pdev, 0x4B, &tmp);
467 		/* Clear CD-ROM DMA write bit */
468 		tmp &= 0x7F;
469 		pci_write_config_byte(pdev, 0x4B, tmp);
470 	} else if (pdev->revision >= 0xC2) {
471 		/* Enable cable detection logic */
472 		pci_read_config_byte(pdev, 0x4B, &tmp);
473 		pci_write_config_byte(pdev, 0x4B, tmp | 0x08);
474 	}
475 	north = pci_get_bus_and_slot(0, PCI_DEVFN(0,0));
476 	isa_bridge = pci_get_device(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, NULL);
477 
478 	if (north && north->vendor == PCI_VENDOR_ID_AL && isa_bridge) {
479 		/* Configure the ALi bridge logic. For non ALi rely on BIOS.
480 		   Set the south bridge enable bit */
481 		pci_read_config_byte(isa_bridge, 0x79, &tmp);
482 		if (pdev->revision == 0xC2)
483 			pci_write_config_byte(isa_bridge, 0x79, tmp | 0x04);
484 		else if (pdev->revision > 0xC2 && pdev->revision < 0xC5)
485 			pci_write_config_byte(isa_bridge, 0x79, tmp | 0x02);
486 	}
487 	if (pdev->revision >= 0x20) {
488 		/*
489 		 * CD_ROM DMA on (0x53 bit 0). Enable this even if we want
490 		 * to use PIO. 0x53 bit 1 (rev 20 only) - enable FIFO control
491 		 * via 0x54/55.
492 		 */
493 		pci_read_config_byte(pdev, 0x53, &tmp);
494 		if (pdev->revision <= 0x20)
495 			tmp &= ~0x02;
496 		if (pdev->revision >= 0xc7)
497 			tmp |= 0x03;
498 		else
499 			tmp |= 0x01;	/* CD_ROM enable for DMA */
500 		pci_write_config_byte(pdev, 0x53, tmp);
501 	}
502 	pci_dev_put(isa_bridge);
503 	pci_dev_put(north);
504 	ata_pci_clear_simplex(pdev);
505 }
506 /**
507  *	ali_init_one		-	discovery callback
508  *	@pdev: PCI device ID
509  *	@id: PCI table info
510  *
511  *	An ALi IDE interface has been discovered. Figure out what revision
512  *	and perform configuration work before handing it to the ATA layer
513  */
514 
515 static int ali_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
516 {
517 	static const struct ata_port_info info_early = {
518 		.sht = &ali_sht,
519 		.flags = ATA_FLAG_SLAVE_POSS,
520 		.pio_mask = 0x1f,
521 		.port_ops = &ali_early_port_ops
522 	};
523 	/* Revision 0x20 added DMA */
524 	static const struct ata_port_info info_20 = {
525 		.sht = &ali_sht,
526 		.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_PIO_LBA48,
527 		.pio_mask = 0x1f,
528 		.mwdma_mask = 0x07,
529 		.port_ops = &ali_20_port_ops
530 	};
531 	/* Revision 0x20 with support logic added UDMA */
532 	static const struct ata_port_info info_20_udma = {
533 		.sht = &ali_sht,
534 		.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_PIO_LBA48,
535 		.pio_mask = 0x1f,
536 		.mwdma_mask = 0x07,
537 		.udma_mask = 0x07,	/* UDMA33 */
538 		.port_ops = &ali_20_port_ops
539 	};
540 	/* Revision 0xC2 adds UDMA66 */
541 	static const struct ata_port_info info_c2 = {
542 		.sht = &ali_sht,
543 		.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_PIO_LBA48,
544 		.pio_mask = 0x1f,
545 		.mwdma_mask = 0x07,
546 		.udma_mask = ATA_UDMA4,
547 		.port_ops = &ali_c2_port_ops
548 	};
549 	/* Revision 0xC3 is UDMA66 for now */
550 	static const struct ata_port_info info_c3 = {
551 		.sht = &ali_sht,
552 		.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_PIO_LBA48,
553 		.pio_mask = 0x1f,
554 		.mwdma_mask = 0x07,
555 		.udma_mask = ATA_UDMA4,
556 		.port_ops = &ali_c2_port_ops
557 	};
558 	/* Revision 0xC4 is UDMA100 */
559 	static const struct ata_port_info info_c4 = {
560 		.sht = &ali_sht,
561 		.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_PIO_LBA48,
562 		.pio_mask = 0x1f,
563 		.mwdma_mask = 0x07,
564 		.udma_mask = ATA_UDMA5,
565 		.port_ops = &ali_c2_port_ops
566 	};
567 	/* Revision 0xC5 is UDMA133 with LBA48 DMA */
568 	static const struct ata_port_info info_c5 = {
569 		.sht = &ali_sht,
570 		.flags = ATA_FLAG_SLAVE_POSS,
571 		.pio_mask = 0x1f,
572 		.mwdma_mask = 0x07,
573 		.udma_mask = ATA_UDMA6,
574 		.port_ops = &ali_c5_port_ops
575 	};
576 
577 	const struct ata_port_info *ppi[] = { NULL, NULL };
578 	u8 tmp;
579 	struct pci_dev *isa_bridge;
580 
581 	/*
582 	 * The chipset revision selects the driver operations and
583 	 * mode data.
584 	 */
585 
586 	if (pdev->revision < 0x20) {
587 		ppi[0] = &info_early;
588 	} else if (pdev->revision < 0xC2) {
589         	ppi[0] = &info_20;
590 	} else if (pdev->revision == 0xC2) {
591         	ppi[0] = &info_c2;
592 	} else if (pdev->revision == 0xC3) {
593         	ppi[0] = &info_c3;
594 	} else if (pdev->revision == 0xC4) {
595         	ppi[0] = &info_c4;
596 	} else
597         	ppi[0] = &info_c5;
598 
599 	ali_init_chipset(pdev);
600 
601 	isa_bridge = pci_get_device(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, NULL);
602 	if (isa_bridge && pdev->revision >= 0x20 && pdev->revision < 0xC2) {
603 		/* Are we paired with a UDMA capable chip */
604 		pci_read_config_byte(isa_bridge, 0x5E, &tmp);
605 		if ((tmp & 0x1E) == 0x12)
606 	        	ppi[0] = &info_20_udma;
607 		pci_dev_put(isa_bridge);
608 	}
609 	return ata_pci_init_one(pdev, ppi);
610 }
611 
612 #ifdef CONFIG_PM
613 static int ali_reinit_one(struct pci_dev *pdev)
614 {
615 	ali_init_chipset(pdev);
616 	return ata_pci_device_resume(pdev);
617 }
618 #endif
619 
620 static const struct pci_device_id ali[] = {
621 	{ PCI_VDEVICE(AL, PCI_DEVICE_ID_AL_M5228), },
622 	{ PCI_VDEVICE(AL, PCI_DEVICE_ID_AL_M5229), },
623 
624 	{ },
625 };
626 
627 static struct pci_driver ali_pci_driver = {
628 	.name 		= DRV_NAME,
629 	.id_table	= ali,
630 	.probe 		= ali_init_one,
631 	.remove		= ata_pci_remove_one,
632 #ifdef CONFIG_PM
633 	.suspend	= ata_pci_device_suspend,
634 	.resume		= ali_reinit_one,
635 #endif
636 };
637 
638 static int __init ali_init(void)
639 {
640 	return pci_register_driver(&ali_pci_driver);
641 }
642 
643 
644 static void __exit ali_exit(void)
645 {
646 	pci_unregister_driver(&ali_pci_driver);
647 }
648 
649 
650 MODULE_AUTHOR("Alan Cox");
651 MODULE_DESCRIPTION("low-level driver for ALi PATA");
652 MODULE_LICENSE("GPL");
653 MODULE_DEVICE_TABLE(pci, ali);
654 MODULE_VERSION(DRV_VERSION);
655 
656 module_init(ali_init);
657 module_exit(ali_exit);
658