xref: /openbmc/linux/drivers/acpi/nfit/intel.h (revision 4b4193256c8d3bc3a5397b5cd9494c2ad386317d)
10ead1118SDan Williams // SPDX-License-Identifier: GPL-2.0
20ead1118SDan Williams /*
30ead1118SDan Williams  * Copyright(c) 2018 Intel Corporation. All rights reserved.
40ead1118SDan Williams  * Intel specific definitions for NVDIMM Firmware Interface Table - NFIT
50ead1118SDan Williams  */
60ead1118SDan Williams #ifndef _NFIT_INTEL_H_
70ead1118SDan Williams #define _NFIT_INTEL_H_
80ead1118SDan Williams 
90ead1118SDan Williams #define ND_INTEL_SMART 1
100ead1118SDan Williams 
110ead1118SDan Williams #define ND_INTEL_SMART_SHUTDOWN_COUNT_VALID     (1 << 5)
120ead1118SDan Williams #define ND_INTEL_SMART_SHUTDOWN_VALID           (1 << 10)
130ead1118SDan Williams 
140ead1118SDan Williams struct nd_intel_smart {
150ead1118SDan Williams 	u32 status;
160ead1118SDan Williams 	union {
170ead1118SDan Williams 		struct {
180ead1118SDan Williams 			u32 flags;
190ead1118SDan Williams 			u8 reserved0[4];
200ead1118SDan Williams 			u8 health;
210ead1118SDan Williams 			u8 spares;
220ead1118SDan Williams 			u8 life_used;
230ead1118SDan Williams 			u8 alarm_flags;
240ead1118SDan Williams 			u16 media_temperature;
250ead1118SDan Williams 			u16 ctrl_temperature;
260ead1118SDan Williams 			u32 shutdown_count;
270ead1118SDan Williams 			u8 ait_status;
280ead1118SDan Williams 			u16 pmic_temperature;
290ead1118SDan Williams 			u8 reserved1[8];
300ead1118SDan Williams 			u8 shutdown_state;
310ead1118SDan Williams 			u32 vendor_size;
320ead1118SDan Williams 			u8 vendor_data[92];
330ead1118SDan Williams 		} __packed;
340ead1118SDan Williams 		u8 data[128];
350ead1118SDan Williams 	};
360ead1118SDan Williams } __packed;
370ead1118SDan Williams 
38f2989396SDave Jiang extern const struct nvdimm_security_ops *intel_security_ops;
39f2989396SDave Jiang 
40b3ed2ce0SDave Jiang #define ND_INTEL_STATUS_SIZE		4
41b3ed2ce0SDave Jiang #define ND_INTEL_PASSPHRASE_SIZE	32
42b3ed2ce0SDave Jiang 
43b3ed2ce0SDave Jiang #define ND_INTEL_STATUS_NOT_SUPPORTED	1
44b3ed2ce0SDave Jiang #define ND_INTEL_STATUS_RETRY		5
45b3ed2ce0SDave Jiang #define ND_INTEL_STATUS_NOT_READY	9
46b3ed2ce0SDave Jiang #define ND_INTEL_STATUS_INVALID_STATE	10
47b3ed2ce0SDave Jiang #define ND_INTEL_STATUS_INVALID_PASS	11
48b3ed2ce0SDave Jiang #define ND_INTEL_STATUS_OVERWRITE_UNSUPPORTED	0x10007
49b3ed2ce0SDave Jiang #define ND_INTEL_STATUS_OQUERY_INPROGRESS	0x10007
50b3ed2ce0SDave Jiang #define ND_INTEL_STATUS_OQUERY_SEQUENCE_ERR	0x20007
51b3ed2ce0SDave Jiang 
52b3ed2ce0SDave Jiang #define ND_INTEL_SEC_STATE_ENABLED	0x02
53b3ed2ce0SDave Jiang #define ND_INTEL_SEC_STATE_LOCKED	0x04
54b3ed2ce0SDave Jiang #define ND_INTEL_SEC_STATE_FROZEN	0x08
55b3ed2ce0SDave Jiang #define ND_INTEL_SEC_STATE_PLIMIT	0x10
56b3ed2ce0SDave Jiang #define ND_INTEL_SEC_STATE_UNSUPPORTED	0x20
57b3ed2ce0SDave Jiang #define ND_INTEL_SEC_STATE_OVERWRITE	0x40
58b3ed2ce0SDave Jiang 
59b3ed2ce0SDave Jiang #define ND_INTEL_SEC_ESTATE_ENABLED	0x01
60b3ed2ce0SDave Jiang #define ND_INTEL_SEC_ESTATE_PLIMIT	0x02
61b3ed2ce0SDave Jiang 
62b3ed2ce0SDave Jiang struct nd_intel_get_security_state {
63b3ed2ce0SDave Jiang 	u32 status;
64b3ed2ce0SDave Jiang 	u8 extended_state;
65b3ed2ce0SDave Jiang 	u8 reserved[3];
66b3ed2ce0SDave Jiang 	u8 state;
67b3ed2ce0SDave Jiang 	u8 reserved1[3];
68b3ed2ce0SDave Jiang } __packed;
69b3ed2ce0SDave Jiang 
70b3ed2ce0SDave Jiang struct nd_intel_set_passphrase {
71b3ed2ce0SDave Jiang 	u8 old_pass[ND_INTEL_PASSPHRASE_SIZE];
72b3ed2ce0SDave Jiang 	u8 new_pass[ND_INTEL_PASSPHRASE_SIZE];
73b3ed2ce0SDave Jiang 	u32 status;
74b3ed2ce0SDave Jiang } __packed;
75b3ed2ce0SDave Jiang 
76b3ed2ce0SDave Jiang struct nd_intel_unlock_unit {
77b3ed2ce0SDave Jiang 	u8 passphrase[ND_INTEL_PASSPHRASE_SIZE];
78b3ed2ce0SDave Jiang 	u32 status;
79b3ed2ce0SDave Jiang } __packed;
80b3ed2ce0SDave Jiang 
81b3ed2ce0SDave Jiang struct nd_intel_disable_passphrase {
82b3ed2ce0SDave Jiang 	u8 passphrase[ND_INTEL_PASSPHRASE_SIZE];
83b3ed2ce0SDave Jiang 	u32 status;
84b3ed2ce0SDave Jiang } __packed;
85b3ed2ce0SDave Jiang 
86b3ed2ce0SDave Jiang struct nd_intel_freeze_lock {
87b3ed2ce0SDave Jiang 	u32 status;
88b3ed2ce0SDave Jiang } __packed;
89b3ed2ce0SDave Jiang 
90b3ed2ce0SDave Jiang struct nd_intel_secure_erase {
91b3ed2ce0SDave Jiang 	u8 passphrase[ND_INTEL_PASSPHRASE_SIZE];
92b3ed2ce0SDave Jiang 	u32 status;
93b3ed2ce0SDave Jiang } __packed;
94b3ed2ce0SDave Jiang 
95b3ed2ce0SDave Jiang struct nd_intel_overwrite {
96b3ed2ce0SDave Jiang 	u8 passphrase[ND_INTEL_PASSPHRASE_SIZE];
97b3ed2ce0SDave Jiang 	u32 status;
98b3ed2ce0SDave Jiang } __packed;
99b3ed2ce0SDave Jiang 
100b3ed2ce0SDave Jiang struct nd_intel_query_overwrite {
101b3ed2ce0SDave Jiang 	u32 status;
102b3ed2ce0SDave Jiang } __packed;
103b3ed2ce0SDave Jiang 
104b3ed2ce0SDave Jiang struct nd_intel_set_master_passphrase {
105b3ed2ce0SDave Jiang 	u8 old_pass[ND_INTEL_PASSPHRASE_SIZE];
106b3ed2ce0SDave Jiang 	u8 new_pass[ND_INTEL_PASSPHRASE_SIZE];
107b3ed2ce0SDave Jiang 	u32 status;
108b3ed2ce0SDave Jiang } __packed;
109b3ed2ce0SDave Jiang 
110b3ed2ce0SDave Jiang struct nd_intel_master_secure_erase {
111b3ed2ce0SDave Jiang 	u8 passphrase[ND_INTEL_PASSPHRASE_SIZE];
112b3ed2ce0SDave Jiang 	u32 status;
113b3ed2ce0SDave Jiang } __packed;
1146450ddbdSDan Williams 
1156450ddbdSDan Williams #define ND_INTEL_FWA_IDLE 0
1166450ddbdSDan Williams #define ND_INTEL_FWA_ARMED 1
1176450ddbdSDan Williams #define ND_INTEL_FWA_BUSY 2
1186450ddbdSDan Williams 
1196450ddbdSDan Williams #define ND_INTEL_DIMM_FWA_NONE 0
1206450ddbdSDan Williams #define ND_INTEL_DIMM_FWA_NOTSTAGED 1
1216450ddbdSDan Williams #define ND_INTEL_DIMM_FWA_SUCCESS 2
1226450ddbdSDan Williams #define ND_INTEL_DIMM_FWA_NEEDRESET 3
1236450ddbdSDan Williams #define ND_INTEL_DIMM_FWA_MEDIAFAILED 4
1246450ddbdSDan Williams #define ND_INTEL_DIMM_FWA_ABORT 5
1256450ddbdSDan Williams #define ND_INTEL_DIMM_FWA_NOTSUPP 6
1266450ddbdSDan Williams #define ND_INTEL_DIMM_FWA_ERROR 7
1276450ddbdSDan Williams 
1286450ddbdSDan Williams struct nd_intel_fw_activate_dimminfo {
1296450ddbdSDan Williams 	u32 status;
1306450ddbdSDan Williams 	u16 result;
1316450ddbdSDan Williams 	u8 state;
1326450ddbdSDan Williams 	u8 reserved[7];
1336450ddbdSDan Williams } __packed;
1346450ddbdSDan Williams 
135916566aeSDan Williams #define ND_INTEL_DIMM_FWA_ARM 1
136916566aeSDan Williams #define ND_INTEL_DIMM_FWA_DISARM 0
137916566aeSDan Williams 
1386450ddbdSDan Williams struct nd_intel_fw_activate_arm {
1396450ddbdSDan Williams 	u8 activate_arm;
1406450ddbdSDan Williams 	u32 status;
1416450ddbdSDan Williams } __packed;
1426450ddbdSDan Williams 
1436450ddbdSDan Williams /* Root device command payloads */
1446450ddbdSDan Williams #define ND_INTEL_BUS_FWA_CAP_FWQUIESCE (1 << 0)
1456450ddbdSDan Williams #define ND_INTEL_BUS_FWA_CAP_OSQUIESCE (1 << 1)
1466450ddbdSDan Williams #define ND_INTEL_BUS_FWA_CAP_RESET     (1 << 2)
1476450ddbdSDan Williams 
1486450ddbdSDan Williams struct nd_intel_bus_fw_activate_businfo {
1496450ddbdSDan Williams 	u32 status;
1506450ddbdSDan Williams 	u16 reserved;
1516450ddbdSDan Williams 	u8 state;
1526450ddbdSDan Williams 	u8 capability;
1536450ddbdSDan Williams 	u64 activate_tmo;
1546450ddbdSDan Williams 	u64 cpu_quiesce_tmo;
1556450ddbdSDan Williams 	u64 io_quiesce_tmo;
1566450ddbdSDan Williams 	u64 max_quiesce_tmo;
1576450ddbdSDan Williams } __packed;
1586450ddbdSDan Williams 
1596450ddbdSDan Williams #define ND_INTEL_BUS_FWA_STATUS_NOARM  (6 | 1 << 16)
1606450ddbdSDan Williams #define ND_INTEL_BUS_FWA_STATUS_BUSY   (6 | 2 << 16)
1616450ddbdSDan Williams #define ND_INTEL_BUS_FWA_STATUS_NOFW   (6 | 3 << 16)
1626450ddbdSDan Williams #define ND_INTEL_BUS_FWA_STATUS_TMO    (6 | 4 << 16)
1636450ddbdSDan Williams #define ND_INTEL_BUS_FWA_STATUS_NOIDLE (6 | 5 << 16)
1646450ddbdSDan Williams #define ND_INTEL_BUS_FWA_STATUS_ABORT  (6 | 6 << 16)
1656450ddbdSDan Williams 
166916566aeSDan Williams #define ND_INTEL_BUS_FWA_IODEV_FORCE_IDLE (0)
167916566aeSDan Williams #define ND_INTEL_BUS_FWA_IODEV_OS_IDLE (1)
1686450ddbdSDan Williams struct nd_intel_bus_fw_activate {
1696450ddbdSDan Williams 	u8 iodev_state;
1706450ddbdSDan Williams 	u32 status;
1716450ddbdSDan Williams } __packed;
172*a1facc1fSDan Williams 
173*a1facc1fSDan Williams extern const struct nvdimm_fw_ops *intel_fw_ops;
174*a1facc1fSDan Williams extern const struct nvdimm_bus_fw_ops *intel_bus_fw_ops;
1750ead1118SDan Williams #endif
176