1*e65e175bSOded Gabbay /* SPDX-License-Identifier: GPL-2.0 2*e65e175bSOded Gabbay * 3*e65e175bSOded Gabbay * Copyright 2019 HabanaLabs, Ltd. 4*e65e175bSOded Gabbay * All Rights Reserved. 5*e65e175bSOded Gabbay * 6*e65e175bSOded Gabbay */ 7*e65e175bSOded Gabbay 8*e65e175bSOded Gabbay #ifndef GOYA_REG_MAP_H_ 9*e65e175bSOded Gabbay #define GOYA_REG_MAP_H_ 10*e65e175bSOded Gabbay 11*e65e175bSOded Gabbay /* 12*e65e175bSOded Gabbay * PSOC scratch-pad registers 13*e65e175bSOded Gabbay */ 14*e65e175bSOded Gabbay #define mmCPU_PQ_BASE_ADDR_LOW mmPSOC_GLOBAL_CONF_SCRATCHPAD_0 15*e65e175bSOded Gabbay #define mmCPU_PQ_BASE_ADDR_HIGH mmPSOC_GLOBAL_CONF_SCRATCHPAD_1 16*e65e175bSOded Gabbay #define mmCPU_EQ_BASE_ADDR_LOW mmPSOC_GLOBAL_CONF_SCRATCHPAD_2 17*e65e175bSOded Gabbay #define mmCPU_EQ_BASE_ADDR_HIGH mmPSOC_GLOBAL_CONF_SCRATCHPAD_3 18*e65e175bSOded Gabbay #define mmCPU_EQ_LENGTH mmPSOC_GLOBAL_CONF_SCRATCHPAD_4 19*e65e175bSOded Gabbay #define mmCPU_PQ_LENGTH mmPSOC_GLOBAL_CONF_SCRATCHPAD_5 20*e65e175bSOded Gabbay #define mmCPU_EQ_CI mmPSOC_GLOBAL_CONF_SCRATCHPAD_6 21*e65e175bSOded Gabbay #define mmCPU_PQ_INIT_STATUS mmPSOC_GLOBAL_CONF_SCRATCHPAD_7 22*e65e175bSOded Gabbay #define mmCPU_CQ_BASE_ADDR_LOW mmPSOC_GLOBAL_CONF_SCRATCHPAD_8 23*e65e175bSOded Gabbay #define mmCPU_CQ_BASE_ADDR_HIGH mmPSOC_GLOBAL_CONF_SCRATCHPAD_9 24*e65e175bSOded Gabbay #define mmCPU_CQ_LENGTH mmPSOC_GLOBAL_CONF_SCRATCHPAD_10 25*e65e175bSOded Gabbay #define mmCPU_BOOT_DEV_STS0 mmPSOC_GLOBAL_CONF_SCRATCHPAD_20 26*e65e175bSOded Gabbay #define mmCPU_BOOT_DEV_STS1 mmPSOC_GLOBAL_CONF_SCRATCHPAD_21 27*e65e175bSOded Gabbay #define mmFUSE_VER_OFFSET mmPSOC_GLOBAL_CONF_SCRATCHPAD_22 28*e65e175bSOded Gabbay #define mmCPU_CMD_STATUS_TO_HOST mmPSOC_GLOBAL_CONF_SCRATCHPAD_23 29*e65e175bSOded Gabbay #define mmCPU_BOOT_ERR0 mmPSOC_GLOBAL_CONF_SCRATCHPAD_24 30*e65e175bSOded Gabbay #define mmCPU_BOOT_ERR1 mmPSOC_GLOBAL_CONF_SCRATCHPAD_25 31*e65e175bSOded Gabbay #define mmUPD_STS mmPSOC_GLOBAL_CONF_SCRATCHPAD_26 32*e65e175bSOded Gabbay #define mmUPD_CMD mmPSOC_GLOBAL_CONF_SCRATCHPAD_27 33*e65e175bSOded Gabbay #define mmPREBOOT_VER_OFFSET mmPSOC_GLOBAL_CONF_SCRATCHPAD_28 34*e65e175bSOded Gabbay #define mmUBOOT_VER_OFFSET mmPSOC_GLOBAL_CONF_SCRATCHPAD_29 35*e65e175bSOded Gabbay #define mmRDWR_TEST mmPSOC_GLOBAL_CONF_SCRATCHPAD_30 36*e65e175bSOded Gabbay #define mmBTL_ID mmPSOC_GLOBAL_CONF_SCRATCHPAD_31 37*e65e175bSOded Gabbay 38*e65e175bSOded Gabbay #define mmHW_STATE mmPSOC_GLOBAL_CONF_APP_STATUS 39*e65e175bSOded Gabbay #define mmPSOC_GLOBAL_CONF_CPU_BOOT_STATUS mmPSOC_GLOBAL_CONF_WARM_REBOOT 40*e65e175bSOded Gabbay #define mmPSOC_GLOBAL_CONF_KMD_MSG_TO_CPU mmPSOC_GLOBAL_CONF_UBOOT_MAGIC 41*e65e175bSOded Gabbay #define mmUPD_PENDING_STS mmPSOC_GLOBAL_CONF_NON_RST_FLOPS_3 42*e65e175bSOded Gabbay 43*e65e175bSOded Gabbay #endif /* GOYA_REG_MAP_H_ */ 44