1e62d9491SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later
2b2f46fd8SDan Williams /*
3b2f46fd8SDan Williams * Copyright(c) 2007 Yuri Tikhonov <yur@emcraft.com>
4b2f46fd8SDan Williams * Copyright(c) 2009 Intel Corporation
5b2f46fd8SDan Williams */
6b2f46fd8SDan Williams #include <linux/kernel.h>
7b2f46fd8SDan Williams #include <linux/interrupt.h>
84bb33cc8SPaul Gortmaker #include <linux/module.h>
9b2f46fd8SDan Williams #include <linux/dma-mapping.h>
10b2f46fd8SDan Williams #include <linux/raid/pq.h>
11b2f46fd8SDan Williams #include <linux/async_tx.h>
125a0e3ad6STejun Heo #include <linux/gfp.h>
13b2f46fd8SDan Williams
14*0dee6cd2SRandy Dunlap /*
15*0dee6cd2SRandy Dunlap * struct pq_scribble_page - space to hold throwaway P or Q buffer for
16030b0772SDan Williams * synchronous gen_syndrome
17b2f46fd8SDan Williams */
18030b0772SDan Williams static struct page *pq_scribble_page;
19b2f46fd8SDan Williams
20b2f46fd8SDan Williams /* the struct page *blocks[] parameter passed to async_gen_syndrome()
21b2f46fd8SDan Williams * and async_syndrome_val() contains the 'P' destination address at
22b2f46fd8SDan Williams * blocks[disks-2] and the 'Q' destination address at blocks[disks-1]
23b2f46fd8SDan Williams *
24b2f46fd8SDan Williams * note: these are macros as they are used as lvalues
25b2f46fd8SDan Williams */
26b2f46fd8SDan Williams #define P(b, d) (b[d-2])
27b2f46fd8SDan Williams #define Q(b, d) (b[d-1])
28b2f46fd8SDan Williams
2989a7e2f7SKyle Spiers #define MAX_DISKS 255
3089a7e2f7SKyle Spiers
31*0dee6cd2SRandy Dunlap /*
32b2f46fd8SDan Williams * do_async_gen_syndrome - asynchronously calculate P and/or Q
33b2f46fd8SDan Williams */
34b2f46fd8SDan Williams static __async_inline struct dma_async_tx_descriptor *
do_async_gen_syndrome(struct dma_chan * chan,const unsigned char * scfs,int disks,struct dmaengine_unmap_data * unmap,enum dma_ctrl_flags dma_flags,struct async_submit_ctl * submit)357476bd79SDan Williams do_async_gen_syndrome(struct dma_chan *chan,
367476bd79SDan Williams const unsigned char *scfs, int disks,
377476bd79SDan Williams struct dmaengine_unmap_data *unmap,
387476bd79SDan Williams enum dma_ctrl_flags dma_flags,
39b2f46fd8SDan Williams struct async_submit_ctl *submit)
40b2f46fd8SDan Williams {
41b2f46fd8SDan Williams struct dma_async_tx_descriptor *tx = NULL;
42b2f46fd8SDan Williams struct dma_device *dma = chan->device;
43b2f46fd8SDan Williams enum async_tx_flags flags_orig = submit->flags;
44b2f46fd8SDan Williams dma_async_tx_callback cb_fn_orig = submit->cb_fn;
45b2f46fd8SDan Williams dma_async_tx_callback cb_param_orig = submit->cb_param;
46b2f46fd8SDan Williams int src_cnt = disks - 2;
47b2f46fd8SDan Williams unsigned short pq_src_cnt;
48b2f46fd8SDan Williams dma_addr_t dma_dest[2];
49b2f46fd8SDan Williams int src_off = 0;
50b2f46fd8SDan Williams
51b2f46fd8SDan Williams while (src_cnt > 0) {
52b2f46fd8SDan Williams submit->flags = flags_orig;
53b2f46fd8SDan Williams pq_src_cnt = min(src_cnt, dma_maxpq(dma, dma_flags));
54b2f46fd8SDan Williams /* if we are submitting additional pqs, leave the chain open,
55b2f46fd8SDan Williams * clear the callback parameters, and leave the destination
56b2f46fd8SDan Williams * buffers mapped
57b2f46fd8SDan Williams */
58b2f46fd8SDan Williams if (src_cnt > pq_src_cnt) {
59b2f46fd8SDan Williams submit->flags &= ~ASYNC_TX_ACK;
600403e382SDan Williams submit->flags |= ASYNC_TX_FENCE;
61b2f46fd8SDan Williams submit->cb_fn = NULL;
62b2f46fd8SDan Williams submit->cb_param = NULL;
63b2f46fd8SDan Williams } else {
64b2f46fd8SDan Williams submit->cb_fn = cb_fn_orig;
65b2f46fd8SDan Williams submit->cb_param = cb_param_orig;
66b2f46fd8SDan Williams if (cb_fn_orig)
67b2f46fd8SDan Williams dma_flags |= DMA_PREP_INTERRUPT;
68b2f46fd8SDan Williams }
69baae03a0SAnup Patel if (submit->flags & ASYNC_TX_FENCE)
70baae03a0SAnup Patel dma_flags |= DMA_PREP_FENCE;
71b2f46fd8SDan Williams
727476bd79SDan Williams /* Drivers force forward progress in case they can not provide
737476bd79SDan Williams * a descriptor
74b2f46fd8SDan Williams */
75b2f46fd8SDan Williams for (;;) {
767476bd79SDan Williams dma_dest[0] = unmap->addr[disks - 2];
777476bd79SDan Williams dma_dest[1] = unmap->addr[disks - 1];
78b2f46fd8SDan Williams tx = dma->device_prep_dma_pq(chan, dma_dest,
797476bd79SDan Williams &unmap->addr[src_off],
80b2f46fd8SDan Williams pq_src_cnt,
817476bd79SDan Williams &scfs[src_off], unmap->len,
82b2f46fd8SDan Williams dma_flags);
83b2f46fd8SDan Williams if (likely(tx))
84b2f46fd8SDan Williams break;
85b2f46fd8SDan Williams async_tx_quiesce(&submit->depend_tx);
86b2f46fd8SDan Williams dma_async_issue_pending(chan);
87b2f46fd8SDan Williams }
88b2f46fd8SDan Williams
897476bd79SDan Williams dma_set_unmap(tx, unmap);
90b2f46fd8SDan Williams async_tx_submit(chan, tx, submit);
91b2f46fd8SDan Williams submit->depend_tx = tx;
92b2f46fd8SDan Williams
93b2f46fd8SDan Williams /* drop completed sources */
94b2f46fd8SDan Williams src_cnt -= pq_src_cnt;
95b2f46fd8SDan Williams src_off += pq_src_cnt;
96b2f46fd8SDan Williams
97b2f46fd8SDan Williams dma_flags |= DMA_PREP_CONTINUE;
98b2f46fd8SDan Williams }
99b2f46fd8SDan Williams
100b2f46fd8SDan Williams return tx;
101b2f46fd8SDan Williams }
102b2f46fd8SDan Williams
103*0dee6cd2SRandy Dunlap /*
104b2f46fd8SDan Williams * do_sync_gen_syndrome - synchronously calculate a raid6 syndrome
105b2f46fd8SDan Williams */
106b2f46fd8SDan Williams static void
do_sync_gen_syndrome(struct page ** blocks,unsigned int * offsets,int disks,size_t len,struct async_submit_ctl * submit)107d69454bcSYufen Yu do_sync_gen_syndrome(struct page **blocks, unsigned int *offsets, int disks,
108b2f46fd8SDan Williams size_t len, struct async_submit_ctl *submit)
109b2f46fd8SDan Williams {
110b2f46fd8SDan Williams void **srcs;
111b2f46fd8SDan Williams int i;
112584acdd4SMarkus Stockhausen int start = -1, stop = disks - 3;
113b2f46fd8SDan Williams
114b2f46fd8SDan Williams if (submit->scribble)
115b2f46fd8SDan Williams srcs = submit->scribble;
116b2f46fd8SDan Williams else
117b2f46fd8SDan Williams srcs = (void **) blocks;
118b2f46fd8SDan Williams
119b2f46fd8SDan Williams for (i = 0; i < disks; i++) {
1205dd33c9aSNeilBrown if (blocks[i] == NULL) {
121b2f46fd8SDan Williams BUG_ON(i > disks - 3); /* P or Q can't be zero */
1225dd33c9aSNeilBrown srcs[i] = (void*)raid6_empty_zero_page;
123584acdd4SMarkus Stockhausen } else {
124d69454bcSYufen Yu srcs[i] = page_address(blocks[i]) + offsets[i];
125d69454bcSYufen Yu
126584acdd4SMarkus Stockhausen if (i < disks - 2) {
127584acdd4SMarkus Stockhausen stop = i;
128584acdd4SMarkus Stockhausen if (start == -1)
129584acdd4SMarkus Stockhausen start = i;
130b2f46fd8SDan Williams }
131584acdd4SMarkus Stockhausen }
132584acdd4SMarkus Stockhausen }
133584acdd4SMarkus Stockhausen if (submit->flags & ASYNC_TX_PQ_XOR_DST) {
134584acdd4SMarkus Stockhausen BUG_ON(!raid6_call.xor_syndrome);
135584acdd4SMarkus Stockhausen if (start >= 0)
136584acdd4SMarkus Stockhausen raid6_call.xor_syndrome(disks, start, stop, len, srcs);
137584acdd4SMarkus Stockhausen } else
138b2f46fd8SDan Williams raid6_call.gen_syndrome(disks, len, srcs);
139b2f46fd8SDan Williams async_tx_sync_epilog(submit);
140b2f46fd8SDan Williams }
141b2f46fd8SDan Williams
142d69454bcSYufen Yu static inline bool
is_dma_pq_aligned_offs(struct dma_device * dev,unsigned int * offs,int src_cnt,size_t len)143d69454bcSYufen Yu is_dma_pq_aligned_offs(struct dma_device *dev, unsigned int *offs,
144d69454bcSYufen Yu int src_cnt, size_t len)
145d69454bcSYufen Yu {
146d69454bcSYufen Yu int i;
147d69454bcSYufen Yu
148d69454bcSYufen Yu for (i = 0; i < src_cnt; i++) {
149d69454bcSYufen Yu if (!is_dma_pq_aligned(dev, offs[i], 0, len))
150d69454bcSYufen Yu return false;
151d69454bcSYufen Yu }
152d69454bcSYufen Yu return true;
153d69454bcSYufen Yu }
154d69454bcSYufen Yu
155b2f46fd8SDan Williams /**
156b2f46fd8SDan Williams * async_gen_syndrome - asynchronously calculate a raid6 syndrome
157b2f46fd8SDan Williams * @blocks: source blocks from idx 0..disks-3, P @ disks-2 and Q @ disks-1
158d69454bcSYufen Yu * @offsets: offset array into each block (src and dest) to start transaction
159b2f46fd8SDan Williams * @disks: number of blocks (including missing P or Q, see below)
160b2f46fd8SDan Williams * @len: length of operation in bytes
161b2f46fd8SDan Williams * @submit: submission/completion modifiers
162b2f46fd8SDan Williams *
163b2f46fd8SDan Williams * General note: This routine assumes a field of GF(2^8) with a
164b2f46fd8SDan Williams * primitive polynomial of 0x11d and a generator of {02}.
165b2f46fd8SDan Williams *
166b2f46fd8SDan Williams * 'disks' note: callers can optionally omit either P or Q (but not
167b2f46fd8SDan Williams * both) from the calculation by setting blocks[disks-2] or
168b2f46fd8SDan Williams * blocks[disks-1] to NULL. When P or Q is omitted 'len' must be <=
169b2f46fd8SDan Williams * PAGE_SIZE as a temporary buffer of this size is used in the
170b2f46fd8SDan Williams * synchronous path. 'disks' always accounts for both destination
1715676470fSDan Williams * buffers. If any source buffers (blocks[i] where i < disks - 2) are
1725676470fSDan Williams * set to NULL those buffers will be replaced with the raid6_zero_page
1735676470fSDan Williams * in the synchronous path and omitted in the hardware-asynchronous
1745676470fSDan Williams * path.
175b2f46fd8SDan Williams */
176b2f46fd8SDan Williams struct dma_async_tx_descriptor *
async_gen_syndrome(struct page ** blocks,unsigned int * offsets,int disks,size_t len,struct async_submit_ctl * submit)177d69454bcSYufen Yu async_gen_syndrome(struct page **blocks, unsigned int *offsets, int disks,
178b2f46fd8SDan Williams size_t len, struct async_submit_ctl *submit)
179b2f46fd8SDan Williams {
180b2f46fd8SDan Williams int src_cnt = disks - 2;
181b2f46fd8SDan Williams struct dma_chan *chan = async_tx_find_channel(submit, DMA_PQ,
182b2f46fd8SDan Williams &P(blocks, disks), 2,
183b2f46fd8SDan Williams blocks, src_cnt, len);
184b2f46fd8SDan Williams struct dma_device *device = chan ? chan->device : NULL;
1857476bd79SDan Williams struct dmaengine_unmap_data *unmap = NULL;
186b2f46fd8SDan Williams
18789a7e2f7SKyle Spiers BUG_ON(disks > MAX_DISKS || !(P(blocks, disks) || Q(blocks, disks)));
188b2f46fd8SDan Williams
1897476bd79SDan Williams if (device)
190b02bab6bSNeilBrown unmap = dmaengine_get_unmap_data(device->dev, disks, GFP_NOWAIT);
191b2f46fd8SDan Williams
192584acdd4SMarkus Stockhausen /* XORing P/Q is only implemented in software */
193584acdd4SMarkus Stockhausen if (unmap && !(submit->flags & ASYNC_TX_PQ_XOR_DST) &&
194b2f46fd8SDan Williams (src_cnt <= dma_maxpq(device, 0) ||
19583544ae9SDan Williams dma_maxpq(device, DMA_PREP_CONTINUE) > 0) &&
196d69454bcSYufen Yu is_dma_pq_aligned_offs(device, offsets, disks, len)) {
1977476bd79SDan Williams struct dma_async_tx_descriptor *tx;
1987476bd79SDan Williams enum dma_ctrl_flags dma_flags = 0;
19989a7e2f7SKyle Spiers unsigned char coefs[MAX_DISKS];
2007476bd79SDan Williams int i, j;
2017476bd79SDan Williams
202b2f46fd8SDan Williams /* run the p+q asynchronously */
203b2f46fd8SDan Williams pr_debug("%s: (async) disks: %d len: %zu\n",
204b2f46fd8SDan Williams __func__, disks, len);
2057476bd79SDan Williams
2067476bd79SDan Williams /* convert source addresses being careful to collapse 'empty'
2077476bd79SDan Williams * sources and update the coefficients accordingly
2087476bd79SDan Williams */
2097476bd79SDan Williams unmap->len = len;
2107476bd79SDan Williams for (i = 0, j = 0; i < src_cnt; i++) {
2117476bd79SDan Williams if (blocks[i] == NULL)
2127476bd79SDan Williams continue;
213d69454bcSYufen Yu unmap->addr[j] = dma_map_page(device->dev, blocks[i],
214d69454bcSYufen Yu offsets[i], len, DMA_TO_DEVICE);
2157476bd79SDan Williams coefs[j] = raid6_gfexp[i];
2167476bd79SDan Williams unmap->to_cnt++;
2177476bd79SDan Williams j++;
218b2f46fd8SDan Williams }
219b2f46fd8SDan Williams
2207476bd79SDan Williams /*
2217476bd79SDan Williams * DMAs use destinations as sources,
2227476bd79SDan Williams * so use BIDIRECTIONAL mapping
2237476bd79SDan Williams */
2247476bd79SDan Williams unmap->bidi_cnt++;
2257476bd79SDan Williams if (P(blocks, disks))
2267476bd79SDan Williams unmap->addr[j++] = dma_map_page(device->dev, P(blocks, disks),
227d69454bcSYufen Yu P(offsets, disks),
228d69454bcSYufen Yu len, DMA_BIDIRECTIONAL);
2297476bd79SDan Williams else {
2307476bd79SDan Williams unmap->addr[j++] = 0;
2317476bd79SDan Williams dma_flags |= DMA_PREP_PQ_DISABLE_P;
2327476bd79SDan Williams }
2337476bd79SDan Williams
2347476bd79SDan Williams unmap->bidi_cnt++;
2357476bd79SDan Williams if (Q(blocks, disks))
2367476bd79SDan Williams unmap->addr[j++] = dma_map_page(device->dev, Q(blocks, disks),
237d69454bcSYufen Yu Q(offsets, disks),
238d69454bcSYufen Yu len, DMA_BIDIRECTIONAL);
2397476bd79SDan Williams else {
2407476bd79SDan Williams unmap->addr[j++] = 0;
2417476bd79SDan Williams dma_flags |= DMA_PREP_PQ_DISABLE_Q;
2427476bd79SDan Williams }
2437476bd79SDan Williams
2447476bd79SDan Williams tx = do_async_gen_syndrome(chan, coefs, j, unmap, dma_flags, submit);
2457476bd79SDan Williams dmaengine_unmap_put(unmap);
2467476bd79SDan Williams return tx;
2477476bd79SDan Williams }
2487476bd79SDan Williams
2497476bd79SDan Williams dmaengine_unmap_put(unmap);
2507476bd79SDan Williams
251b2f46fd8SDan Williams /* run the pq synchronously */
252b2f46fd8SDan Williams pr_debug("%s: (sync) disks: %d len: %zu\n", __func__, disks, len);
253b2f46fd8SDan Williams
254b2f46fd8SDan Williams /* wait for any prerequisite operations */
255b2f46fd8SDan Williams async_tx_quiesce(&submit->depend_tx);
256b2f46fd8SDan Williams
257b2f46fd8SDan Williams if (!P(blocks, disks)) {
258030b0772SDan Williams P(blocks, disks) = pq_scribble_page;
259d69454bcSYufen Yu P(offsets, disks) = 0;
260b2f46fd8SDan Williams }
261b2f46fd8SDan Williams if (!Q(blocks, disks)) {
262030b0772SDan Williams Q(blocks, disks) = pq_scribble_page;
263d69454bcSYufen Yu Q(offsets, disks) = 0;
264b2f46fd8SDan Williams }
265d69454bcSYufen Yu do_sync_gen_syndrome(blocks, offsets, disks, len, submit);
266b2f46fd8SDan Williams
267b2f46fd8SDan Williams return NULL;
268b2f46fd8SDan Williams }
269b2f46fd8SDan Williams EXPORT_SYMBOL_GPL(async_gen_syndrome);
270b2f46fd8SDan Williams
2717b3cc2b1SDan Williams static inline struct dma_chan *
pq_val_chan(struct async_submit_ctl * submit,struct page ** blocks,int disks,size_t len)2727b3cc2b1SDan Williams pq_val_chan(struct async_submit_ctl *submit, struct page **blocks, int disks, size_t len)
2737b3cc2b1SDan Williams {
2747b3cc2b1SDan Williams #ifdef CONFIG_ASYNC_TX_DISABLE_PQ_VAL_DMA
2757b3cc2b1SDan Williams return NULL;
2767b3cc2b1SDan Williams #endif
2777b3cc2b1SDan Williams return async_tx_find_channel(submit, DMA_PQ_VAL, NULL, 0, blocks,
2787b3cc2b1SDan Williams disks, len);
2797b3cc2b1SDan Williams }
2807b3cc2b1SDan Williams
281b2f46fd8SDan Williams /**
282b2f46fd8SDan Williams * async_syndrome_val - asynchronously validate a raid6 syndrome
283b2f46fd8SDan Williams * @blocks: source blocks from idx 0..disks-3, P @ disks-2 and Q @ disks-1
284*0dee6cd2SRandy Dunlap * @offsets: common offset into each block (src and dest) to start transaction
285b2f46fd8SDan Williams * @disks: number of blocks (including missing P or Q, see below)
286b2f46fd8SDan Williams * @len: length of operation in bytes
287b2f46fd8SDan Williams * @pqres: on val failure SUM_CHECK_P_RESULT and/or SUM_CHECK_Q_RESULT are set
288b2f46fd8SDan Williams * @spare: temporary result buffer for the synchronous case
289d69454bcSYufen Yu * @s_off: spare buffer page offset
290b2f46fd8SDan Williams * @submit: submission / completion modifiers
291b2f46fd8SDan Williams *
292b2f46fd8SDan Williams * The same notes from async_gen_syndrome apply to the 'blocks',
293b2f46fd8SDan Williams * and 'disks' parameters of this routine. The synchronous path
294b2f46fd8SDan Williams * requires a temporary result buffer and submit->scribble to be
295b2f46fd8SDan Williams * specified.
296b2f46fd8SDan Williams */
297b2f46fd8SDan Williams struct dma_async_tx_descriptor *
async_syndrome_val(struct page ** blocks,unsigned int * offsets,int disks,size_t len,enum sum_check_flags * pqres,struct page * spare,unsigned int s_off,struct async_submit_ctl * submit)298d69454bcSYufen Yu async_syndrome_val(struct page **blocks, unsigned int *offsets, int disks,
299b2f46fd8SDan Williams size_t len, enum sum_check_flags *pqres, struct page *spare,
300d69454bcSYufen Yu unsigned int s_off, struct async_submit_ctl *submit)
301b2f46fd8SDan Williams {
3027b3cc2b1SDan Williams struct dma_chan *chan = pq_val_chan(submit, blocks, disks, len);
303b2f46fd8SDan Williams struct dma_device *device = chan ? chan->device : NULL;
304b2f46fd8SDan Williams struct dma_async_tx_descriptor *tx;
30589a7e2f7SKyle Spiers unsigned char coefs[MAX_DISKS];
306b2f46fd8SDan Williams enum dma_ctrl_flags dma_flags = submit->cb_fn ? DMA_PREP_INTERRUPT : 0;
3071786b943SDan Williams struct dmaengine_unmap_data *unmap = NULL;
308b2f46fd8SDan Williams
30989a7e2f7SKyle Spiers BUG_ON(disks < 4 || disks > MAX_DISKS);
310b2f46fd8SDan Williams
3111786b943SDan Williams if (device)
312b02bab6bSNeilBrown unmap = dmaengine_get_unmap_data(device->dev, disks, GFP_NOWAIT);
313b2f46fd8SDan Williams
3141786b943SDan Williams if (unmap && disks <= dma_maxpq(device, 0) &&
315d69454bcSYufen Yu is_dma_pq_aligned_offs(device, offsets, disks, len)) {
316b2f46fd8SDan Williams struct device *dev = device->dev;
3171786b943SDan Williams dma_addr_t pq[2];
3181786b943SDan Williams int i, j = 0, src_cnt = 0;
319b2f46fd8SDan Williams
320b2f46fd8SDan Williams pr_debug("%s: (async) disks: %d len: %zu\n",
321b2f46fd8SDan Williams __func__, disks, len);
3221786b943SDan Williams
3231786b943SDan Williams unmap->len = len;
3241786b943SDan Williams for (i = 0; i < disks-2; i++)
3251786b943SDan Williams if (likely(blocks[i])) {
3261786b943SDan Williams unmap->addr[j] = dma_map_page(dev, blocks[i],
327d69454bcSYufen Yu offsets[i], len,
3281786b943SDan Williams DMA_TO_DEVICE);
3291786b943SDan Williams coefs[j] = raid6_gfexp[i];
3301786b943SDan Williams unmap->to_cnt++;
3311786b943SDan Williams src_cnt++;
3321786b943SDan Williams j++;
3331786b943SDan Williams }
3341786b943SDan Williams
3351786b943SDan Williams if (!P(blocks, disks)) {
3361786b943SDan Williams pq[0] = 0;
337b2f46fd8SDan Williams dma_flags |= DMA_PREP_PQ_DISABLE_P;
3381786b943SDan Williams } else {
339b2141e69SNeilBrown pq[0] = dma_map_page(dev, P(blocks, disks),
340d69454bcSYufen Yu P(offsets, disks), len,
341b2141e69SNeilBrown DMA_TO_DEVICE);
3421786b943SDan Williams unmap->addr[j++] = pq[0];
3431786b943SDan Williams unmap->to_cnt++;
3441786b943SDan Williams }
3451786b943SDan Williams if (!Q(blocks, disks)) {
3461786b943SDan Williams pq[1] = 0;
347b2f46fd8SDan Williams dma_flags |= DMA_PREP_PQ_DISABLE_Q;
3481786b943SDan Williams } else {
349b2141e69SNeilBrown pq[1] = dma_map_page(dev, Q(blocks, disks),
350d69454bcSYufen Yu Q(offsets, disks), len,
351b2141e69SNeilBrown DMA_TO_DEVICE);
3521786b943SDan Williams unmap->addr[j++] = pq[1];
3531786b943SDan Williams unmap->to_cnt++;
3541786b943SDan Williams }
355b2141e69SNeilBrown
3560403e382SDan Williams if (submit->flags & ASYNC_TX_FENCE)
3570403e382SDan Williams dma_flags |= DMA_PREP_FENCE;
358b2f46fd8SDan Williams for (;;) {
3591786b943SDan Williams tx = device->device_prep_dma_pq_val(chan, pq,
3601786b943SDan Williams unmap->addr,
361b2141e69SNeilBrown src_cnt,
362b2141e69SNeilBrown coefs,
363b2f46fd8SDan Williams len, pqres,
364b2f46fd8SDan Williams dma_flags);
365b2f46fd8SDan Williams if (likely(tx))
366b2f46fd8SDan Williams break;
367b2f46fd8SDan Williams async_tx_quiesce(&submit->depend_tx);
368b2f46fd8SDan Williams dma_async_issue_pending(chan);
369b2f46fd8SDan Williams }
3701786b943SDan Williams
3711786b943SDan Williams dma_set_unmap(tx, unmap);
372b2f46fd8SDan Williams async_tx_submit(chan, tx, submit);
373b2f46fd8SDan Williams } else {
374b2f46fd8SDan Williams struct page *p_src = P(blocks, disks);
375d69454bcSYufen Yu unsigned int p_off = P(offsets, disks);
376b2f46fd8SDan Williams struct page *q_src = Q(blocks, disks);
377d69454bcSYufen Yu unsigned int q_off = Q(offsets, disks);
378b2f46fd8SDan Williams enum async_tx_flags flags_orig = submit->flags;
379b2f46fd8SDan Williams dma_async_tx_callback cb_fn_orig = submit->cb_fn;
380b2f46fd8SDan Williams void *scribble = submit->scribble;
381b2f46fd8SDan Williams void *cb_param_orig = submit->cb_param;
382b2f46fd8SDan Williams void *p, *q, *s;
383b2f46fd8SDan Williams
384b2f46fd8SDan Williams pr_debug("%s: (sync) disks: %d len: %zu\n",
385b2f46fd8SDan Williams __func__, disks, len);
386b2f46fd8SDan Williams
387b2f46fd8SDan Williams /* caller must provide a temporary result buffer and
388b2f46fd8SDan Williams * allow the input parameters to be preserved
389b2f46fd8SDan Williams */
390b2f46fd8SDan Williams BUG_ON(!spare || !scribble);
391b2f46fd8SDan Williams
392b2f46fd8SDan Williams /* wait for any prerequisite operations */
393b2f46fd8SDan Williams async_tx_quiesce(&submit->depend_tx);
394b2f46fd8SDan Williams
395b2f46fd8SDan Williams /* recompute p and/or q into the temporary buffer and then
396b2f46fd8SDan Williams * check to see the result matches the current value
397b2f46fd8SDan Williams */
398b2f46fd8SDan Williams tx = NULL;
399b2f46fd8SDan Williams *pqres = 0;
400b2f46fd8SDan Williams if (p_src) {
401b2f46fd8SDan Williams init_async_submit(submit, ASYNC_TX_XOR_ZERO_DST, NULL,
402b2f46fd8SDan Williams NULL, NULL, scribble);
403d69454bcSYufen Yu tx = async_xor_offs(spare, s_off,
404d69454bcSYufen Yu blocks, offsets, disks-2, len, submit);
405b2f46fd8SDan Williams async_tx_quiesce(&tx);
406d69454bcSYufen Yu p = page_address(p_src) + p_off;
407d69454bcSYufen Yu s = page_address(spare) + s_off;
408b2f46fd8SDan Williams *pqres |= !!memcmp(p, s, len) << SUM_CHECK_P;
409b2f46fd8SDan Williams }
410b2f46fd8SDan Williams
411b2f46fd8SDan Williams if (q_src) {
412b2f46fd8SDan Williams P(blocks, disks) = NULL;
413b2f46fd8SDan Williams Q(blocks, disks) = spare;
414d69454bcSYufen Yu Q(offsets, disks) = s_off;
415b2f46fd8SDan Williams init_async_submit(submit, 0, NULL, NULL, NULL, scribble);
416d69454bcSYufen Yu tx = async_gen_syndrome(blocks, offsets, disks,
417d69454bcSYufen Yu len, submit);
418b2f46fd8SDan Williams async_tx_quiesce(&tx);
419d69454bcSYufen Yu q = page_address(q_src) + q_off;
420d69454bcSYufen Yu s = page_address(spare) + s_off;
421b2f46fd8SDan Williams *pqres |= !!memcmp(q, s, len) << SUM_CHECK_Q;
422b2f46fd8SDan Williams }
423b2f46fd8SDan Williams
424b2f46fd8SDan Williams /* restore P, Q and submit */
425b2f46fd8SDan Williams P(blocks, disks) = p_src;
426d69454bcSYufen Yu P(offsets, disks) = p_off;
427b2f46fd8SDan Williams Q(blocks, disks) = q_src;
428d69454bcSYufen Yu Q(offsets, disks) = q_off;
429b2f46fd8SDan Williams
430b2f46fd8SDan Williams submit->cb_fn = cb_fn_orig;
431b2f46fd8SDan Williams submit->cb_param = cb_param_orig;
432b2f46fd8SDan Williams submit->flags = flags_orig;
433b2f46fd8SDan Williams async_tx_sync_epilog(submit);
434c8475090SJustin Maggard tx = NULL;
435b2f46fd8SDan Williams }
436c8475090SJustin Maggard dmaengine_unmap_put(unmap);
437c8475090SJustin Maggard
438c8475090SJustin Maggard return tx;
439b2f46fd8SDan Williams }
440b2f46fd8SDan Williams EXPORT_SYMBOL_GPL(async_syndrome_val);
441b2f46fd8SDan Williams
async_pq_init(void)442b2f46fd8SDan Williams static int __init async_pq_init(void)
443b2f46fd8SDan Williams {
444030b0772SDan Williams pq_scribble_page = alloc_page(GFP_KERNEL);
445b2f46fd8SDan Williams
446030b0772SDan Williams if (pq_scribble_page)
447b2f46fd8SDan Williams return 0;
448b2f46fd8SDan Williams
449b2f46fd8SDan Williams pr_err("%s: failed to allocate required spare page\n", __func__);
450b2f46fd8SDan Williams
451b2f46fd8SDan Williams return -ENOMEM;
452b2f46fd8SDan Williams }
453b2f46fd8SDan Williams
async_pq_exit(void)454b2f46fd8SDan Williams static void __exit async_pq_exit(void)
455b2f46fd8SDan Williams {
45695813b8fSJoonsoo Kim __free_page(pq_scribble_page);
457b2f46fd8SDan Williams }
458b2f46fd8SDan Williams
459b2f46fd8SDan Williams module_init(async_pq_init);
460b2f46fd8SDan Williams module_exit(async_pq_exit);
461b2f46fd8SDan Williams
462b2f46fd8SDan Williams MODULE_DESCRIPTION("asynchronous raid6 syndrome generation/validation");
463b2f46fd8SDan Williams MODULE_LICENSE("GPL");
464