xref: /openbmc/linux/arch/xtensa/mm/misc.S (revision d5cb9783536a41df9f9cba5b0a1d78047ed787f7)
1/*
2 * arch/xtensa/mm/misc.S
3 *
4 * Miscellaneous assembly functions.
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License.  See the file "COPYING" in the main directory of this archive
8 * for more details.
9 *
10 * Copyright (C) 2001 - 2005 Tensilica Inc.
11 *
12 * Chris Zankel	<chris@zankel.net>
13 */
14
15/* Note: we might want to implement some of the loops as zero-overhead-loops,
16 *	 where applicable and if supported by the processor.
17 */
18
19#include <linux/linkage.h>
20#include <asm/page.h>
21#include <asm/pgtable.h>
22
23#include <xtensa/cacheasm.h>
24#include <xtensa/cacheattrasm.h>
25
26/* clear_page (page) */
27
28ENTRY(clear_page)
29	entry	a1, 16
30	addi	a4, a2, PAGE_SIZE
31	movi	a3, 0
32
331:	s32i	a3, a2, 0
34	s32i	a3, a2, 4
35	s32i	a3, a2, 8
36	s32i	a3, a2, 12
37	s32i	a3, a2, 16
38	s32i	a3, a2, 20
39	s32i	a3, a2, 24
40	s32i	a3, a2, 28
41	addi	a2, a2, 32
42	blt	a2, a4, 1b
43
44	retw
45
46/*
47 * copy_page (void *to, void *from)
48 *                  a2        a3
49 */
50
51ENTRY(copy_page)
52	entry	a1, 16
53	addi	a4, a2, PAGE_SIZE
54
551:	l32i	a5, a3, 0
56	l32i	a6, a3, 4
57	l32i	a7, a3, 8
58	s32i	a5, a2, 0
59	s32i	a6, a2, 4
60	s32i	a7, a2, 8
61	l32i	a5, a3, 12
62	l32i	a6, a3, 16
63	l32i	a7, a3, 20
64	s32i	a5, a2, 12
65	s32i	a6, a2, 16
66	s32i	a7, a2, 20
67	l32i	a5, a3, 24
68	l32i	a6, a3, 28
69	s32i	a5, a2, 24
70	s32i	a6, a2, 28
71	addi	a2, a2, 32
72	addi	a3, a3, 32
73	blt	a2, a4, 1b
74
75	retw
76
77
78/*
79 * void __flush_invalidate_cache_all(void)
80 */
81
82ENTRY(__flush_invalidate_cache_all)
83	entry	sp, 16
84	dcache_writeback_inv_all a2, a3
85	icache_invalidate_all a2, a3
86	retw
87
88/*
89 * void __invalidate_icache_all(void)
90 */
91
92ENTRY(__invalidate_icache_all)
93	entry	sp, 16
94	icache_invalidate_all a2, a3
95	retw
96
97/*
98 * void __flush_invalidate_dcache_all(void)
99 */
100
101ENTRY(__flush_invalidate_dcache_all)
102	entry	sp, 16
103	dcache_writeback_inv_all a2, a3
104	retw
105
106
107/*
108 * void __flush_invalidate_cache_range(ulong start, ulong size)
109 */
110
111ENTRY(__flush_invalidate_cache_range)
112	entry	sp, 16
113	mov	a4, a2
114	mov	a5, a3
115	dcache_writeback_inv_region a4, a5, a6
116	icache_invalidate_region a2, a3, a4
117	retw
118
119/*
120 * void __invalidate_icache_page(ulong start)
121 */
122
123ENTRY(__invalidate_icache_page)
124	entry	sp, 16
125	movi	a3, PAGE_SIZE
126	icache_invalidate_region a2, a3, a4
127	retw
128
129/*
130 * void __invalidate_dcache_page(ulong start)
131 */
132
133ENTRY(__invalidate_dcache_page)
134	entry	sp, 16
135	movi	a3, PAGE_SIZE
136	dcache_invalidate_region a2, a3, a4
137	retw
138
139/*
140 * void __invalidate_icache_range(ulong start, ulong size)
141 */
142
143ENTRY(__invalidate_icache_range)
144	entry	sp, 16
145	icache_invalidate_region a2, a3, a4
146	retw
147
148/*
149 * void __invalidate_dcache_range(ulong start, ulong size)
150 */
151
152ENTRY(__invalidate_dcache_range)
153	entry	sp, 16
154	dcache_invalidate_region a2, a3, a4
155	retw
156
157/*
158 * void __flush_dcache_page(ulong start)
159 */
160
161ENTRY(__flush_dcache_page)
162	entry	sp, 16
163	movi	a3, PAGE_SIZE
164	dcache_writeback_region a2, a3, a4
165	retw
166
167/*
168 * void __flush_invalidate_dcache_page(ulong start)
169 */
170
171ENTRY(__flush_invalidate_dcache_page)
172	entry	sp, 16
173	movi	a3, PAGE_SIZE
174	dcache_writeback_inv_region a2, a3, a4
175	retw
176
177/*
178 * void __flush_invalidate_dcache_range(ulong start, ulong size)
179 */
180
181ENTRY(__flush_invalidate_dcache_range)
182	entry	sp, 16
183	dcache_writeback_inv_region a2, a3, a4
184	retw
185
186/*
187 * void __invalidate_dcache_all(void)
188 */
189
190ENTRY(__invalidate_dcache_all)
191	entry	sp, 16
192	dcache_invalidate_all a2, a3
193	retw
194
195/*
196 * void __flush_invalidate_dcache_page_phys(ulong start)
197 */
198
199ENTRY(__flush_invalidate_dcache_page_phys)
200	entry	sp, 16
201
202	movi	a3, XCHAL_DCACHE_SIZE
203	movi	a4, PAGE_MASK | 1
204	addi	a2, a2, 1
205
2061:	addi	a3, a3, -XCHAL_DCACHE_LINESIZE
207
208	ldct	a6, a3
209	dsync
210	and	a6, a6, a4
211	beq	a6, a2, 2f
212	bgeui	a3, 2, 1b
213	retw
214
2152:	diwbi	a3, 0
216	bgeui	a3, 2, 1b
217	retw
218
219ENTRY(check_dcache_low0)
220	entry	sp, 16
221
222	movi	a3, XCHAL_DCACHE_SIZE / 4
223	movi	a4, PAGE_MASK | 1
224	addi	a2, a2, 1
225
2261:	addi	a3, a3, -XCHAL_DCACHE_LINESIZE
227
228	ldct	a6, a3
229	dsync
230	and	a6, a6, a4
231	beq	a6, a2, 2f
232	bgeui	a3, 2, 1b
233	retw
234
2352:	j 2b
236
237ENTRY(check_dcache_high0)
238	entry	sp, 16
239
240	movi	a5, XCHAL_DCACHE_SIZE / 4
241	movi	a3, XCHAL_DCACHE_SIZE / 2
242	movi	a4, PAGE_MASK | 1
243	addi	a2, a2, 1
244
2451:	addi	a3, a3, -XCHAL_DCACHE_LINESIZE
246	addi	a5, a5, -XCHAL_DCACHE_LINESIZE
247
248	ldct	a6, a3
249	dsync
250	and	a6, a6, a4
251	beq	a6, a2, 2f
252	bgeui	a5, 2, 1b
253	retw
254
2552:	j 2b
256
257ENTRY(check_dcache_low1)
258	entry	sp, 16
259
260	movi	a5, XCHAL_DCACHE_SIZE / 4
261	movi	a3, XCHAL_DCACHE_SIZE * 3 / 4
262	movi	a4, PAGE_MASK | 1
263	addi	a2, a2, 1
264
2651:	addi	a3, a3, -XCHAL_DCACHE_LINESIZE
266	addi	a5, a5, -XCHAL_DCACHE_LINESIZE
267
268	ldct	a6, a3
269	dsync
270	and	a6, a6, a4
271	beq	a6, a2, 2f
272	bgeui	a5, 2, 1b
273	retw
274
2752:	j 2b
276
277ENTRY(check_dcache_high1)
278	entry	sp, 16
279
280	movi	a5, XCHAL_DCACHE_SIZE / 4
281	movi	a3, XCHAL_DCACHE_SIZE
282	movi	a4, PAGE_MASK | 1
283	addi	a2, a2, 1
284
2851:	addi	a3, a3, -XCHAL_DCACHE_LINESIZE
286	addi	a5, a5, -XCHAL_DCACHE_LINESIZE
287
288	ldct	a6, a3
289	dsync
290	and	a6, a6, a4
291	beq	a6, a2, 2f
292	bgeui	a5, 2, 1b
293	retw
294
2952:	j 2b
296
297
298/*
299 * void __invalidate_icache_page_phys(ulong start)
300 */
301
302ENTRY(__invalidate_icache_page_phys)
303	entry	sp, 16
304
305	movi	a3, XCHAL_ICACHE_SIZE
306	movi	a4, PAGE_MASK | 1
307	addi	a2, a2, 1
308
3091:	addi	a3, a3, -XCHAL_ICACHE_LINESIZE
310
311	lict	a6, a3
312	isync
313	and	a6, a6, a4
314	beq	a6, a2, 2f
315	bgeui	a3, 2, 1b
316	retw
317
3182:	iii	a3, 0
319	bgeui	a3, 2, 1b
320	retw
321
322
323#if 0
324
325	movi	a3, XCHAL_DCACHE_WAYS - 1
326	movi	a4, PAGE_SIZE
327
3281:	mov	a5, a2
329	add	a6, a2, a4
330
3312:	diwbi	a5, 0
332	diwbi	a5, XCHAL_DCACHE_LINESIZE
333	diwbi	a5, XCHAL_DCACHE_LINESIZE * 2
334	diwbi	a5, XCHAL_DCACHE_LINESIZE * 3
335
336	addi	a5, a5, XCHAL_DCACHE_LINESIZE * 4
337	blt	a5, a6, 2b
338
339	addi	a3, a3, -1
340	addi	a2, a2, XCHAL_DCACHE_SIZE / XCHAL_DCACHE_WAYS
341	bgez	a3, 1b
342
343	retw
344
345ENTRY(__invalidate_icache_page_index)
346	entry	sp, 16
347
348	movi	a3, XCHAL_ICACHE_WAYS - 1
349	movi	a4, PAGE_SIZE
350
3511:	mov	a5, a2
352	add	a6, a2, a4
353
3542:	iii	a5, 0
355	iii	a5, XCHAL_ICACHE_LINESIZE
356	iii	a5, XCHAL_ICACHE_LINESIZE * 2
357	iii	a5, XCHAL_ICACHE_LINESIZE * 3
358
359	addi	a5, a5, XCHAL_ICACHE_LINESIZE * 4
360	blt	a5, a6, 2b
361
362	addi	a3, a3, -1
363	addi	a2, a2, XCHAL_ICACHE_SIZE / XCHAL_ICACHE_WAYS
364	bgez	a3, 2b
365
366	retw
367
368#endif
369
370
371
372
373
374
375