1 /* 2 * arch/xtensa/kernel/setup.c 3 * 4 * This file is subject to the terms and conditions of the GNU General Public 5 * License. See the file "COPYING" in the main directory of this archive 6 * for more details. 7 * 8 * Copyright (C) 1995 Linus Torvalds 9 * Copyright (C) 2001 - 2005 Tensilica Inc. 10 * Copyright (C) 2014 - 2016 Cadence Design Systems Inc. 11 * 12 * Chris Zankel <chris@zankel.net> 13 * Joe Taylor <joe@tensilica.com, joetylr@yahoo.com> 14 * Kevin Chea 15 * Marc Gauthier<marc@tensilica.com> <marc@alumni.uwaterloo.ca> 16 */ 17 18 #include <linux/errno.h> 19 #include <linux/init.h> 20 #include <linux/mm.h> 21 #include <linux/proc_fs.h> 22 #include <linux/screen_info.h> 23 #include <linux/kernel.h> 24 #include <linux/percpu.h> 25 #include <linux/reboot.h> 26 #include <linux/cpu.h> 27 #include <linux/of.h> 28 #include <linux/of_fdt.h> 29 30 #if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE) 31 # include <linux/console.h> 32 #endif 33 34 #ifdef CONFIG_PROC_FS 35 # include <linux/seq_file.h> 36 #endif 37 38 #include <asm/bootparam.h> 39 #include <asm/kasan.h> 40 #include <asm/mmu_context.h> 41 #include <asm/page.h> 42 #include <asm/param.h> 43 #include <asm/platform.h> 44 #include <asm/processor.h> 45 #include <asm/sections.h> 46 #include <asm/setup.h> 47 #include <asm/smp.h> 48 #include <asm/sysmem.h> 49 #include <asm/timex.h> 50 #include <asm/traps.h> 51 52 #if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE) 53 struct screen_info screen_info = { 54 .orig_x = 0, 55 .orig_y = 24, 56 .orig_video_cols = 80, 57 .orig_video_lines = 24, 58 .orig_video_isVGA = 1, 59 .orig_video_points = 16, 60 }; 61 #endif 62 63 #ifdef CONFIG_BLK_DEV_INITRD 64 extern unsigned long initrd_start; 65 extern unsigned long initrd_end; 66 extern int initrd_below_start_ok; 67 #endif 68 69 #ifdef CONFIG_USE_OF 70 void *dtb_start = __dtb_start; 71 #endif 72 73 extern unsigned long loops_per_jiffy; 74 75 /* Command line specified as configuration option. */ 76 77 static char __initdata command_line[COMMAND_LINE_SIZE]; 78 79 #ifdef CONFIG_CMDLINE_BOOL 80 static char default_command_line[COMMAND_LINE_SIZE] __initdata = CONFIG_CMDLINE; 81 #endif 82 83 #ifdef CONFIG_PARSE_BOOTPARAM 84 /* 85 * Boot parameter parsing. 86 * 87 * The Xtensa port uses a list of variable-sized tags to pass data to 88 * the kernel. The first tag must be a BP_TAG_FIRST tag for the list 89 * to be recognised. The list is terminated with a zero-sized 90 * BP_TAG_LAST tag. 91 */ 92 93 typedef struct tagtable { 94 u32 tag; 95 int (*parse)(const bp_tag_t*); 96 } tagtable_t; 97 98 #define __tagtable(tag, fn) static tagtable_t __tagtable_##fn \ 99 __section(".taglist") __attribute__((used)) = { tag, fn } 100 101 /* parse current tag */ 102 103 static int __init parse_tag_mem(const bp_tag_t *tag) 104 { 105 struct bp_meminfo *mi = (struct bp_meminfo *)(tag->data); 106 107 if (mi->type != MEMORY_TYPE_CONVENTIONAL) 108 return -1; 109 110 return memblock_add(mi->start, mi->end - mi->start); 111 } 112 113 __tagtable(BP_TAG_MEMORY, parse_tag_mem); 114 115 #ifdef CONFIG_BLK_DEV_INITRD 116 117 static int __init parse_tag_initrd(const bp_tag_t* tag) 118 { 119 struct bp_meminfo *mi = (struct bp_meminfo *)(tag->data); 120 121 initrd_start = (unsigned long)__va(mi->start); 122 initrd_end = (unsigned long)__va(mi->end); 123 124 return 0; 125 } 126 127 __tagtable(BP_TAG_INITRD, parse_tag_initrd); 128 129 #endif /* CONFIG_BLK_DEV_INITRD */ 130 131 #ifdef CONFIG_USE_OF 132 133 static int __init parse_tag_fdt(const bp_tag_t *tag) 134 { 135 dtb_start = __va(tag->data[0]); 136 return 0; 137 } 138 139 __tagtable(BP_TAG_FDT, parse_tag_fdt); 140 141 #endif /* CONFIG_USE_OF */ 142 143 static int __init parse_tag_cmdline(const bp_tag_t* tag) 144 { 145 strscpy(command_line, (char *)(tag->data), COMMAND_LINE_SIZE); 146 return 0; 147 } 148 149 __tagtable(BP_TAG_COMMAND_LINE, parse_tag_cmdline); 150 151 static int __init parse_bootparam(const bp_tag_t* tag) 152 { 153 extern tagtable_t __tagtable_begin, __tagtable_end; 154 tagtable_t *t; 155 156 /* Boot parameters must start with a BP_TAG_FIRST tag. */ 157 158 if (tag->id != BP_TAG_FIRST) { 159 pr_warn("Invalid boot parameters!\n"); 160 return 0; 161 } 162 163 tag = (bp_tag_t*)((unsigned long)tag + sizeof(bp_tag_t) + tag->size); 164 165 /* Parse all tags. */ 166 167 while (tag != NULL && tag->id != BP_TAG_LAST) { 168 for (t = &__tagtable_begin; t < &__tagtable_end; t++) { 169 if (tag->id == t->tag) { 170 t->parse(tag); 171 break; 172 } 173 } 174 if (t == &__tagtable_end) 175 pr_warn("Ignoring tag 0x%08x\n", tag->id); 176 tag = (bp_tag_t*)((unsigned long)(tag + 1) + tag->size); 177 } 178 179 return 0; 180 } 181 #else 182 static int __init parse_bootparam(const bp_tag_t *tag) 183 { 184 pr_info("Ignoring boot parameters at %p\n", tag); 185 return 0; 186 } 187 #endif 188 189 #ifdef CONFIG_USE_OF 190 191 #if !XCHAL_HAVE_PTP_MMU || XCHAL_HAVE_SPANNING_WAY 192 unsigned long xtensa_kio_paddr = XCHAL_KIO_DEFAULT_PADDR; 193 EXPORT_SYMBOL(xtensa_kio_paddr); 194 195 static int __init xtensa_dt_io_area(unsigned long node, const char *uname, 196 int depth, void *data) 197 { 198 const __be32 *ranges; 199 int len; 200 201 if (depth > 1) 202 return 0; 203 204 if (!of_flat_dt_is_compatible(node, "simple-bus")) 205 return 0; 206 207 ranges = of_get_flat_dt_prop(node, "ranges", &len); 208 if (!ranges) 209 return 1; 210 if (len == 0) 211 return 1; 212 213 xtensa_kio_paddr = of_read_ulong(ranges+1, 1); 214 /* round down to nearest 256MB boundary */ 215 xtensa_kio_paddr &= 0xf0000000; 216 217 init_kio(); 218 219 return 1; 220 } 221 #else 222 static int __init xtensa_dt_io_area(unsigned long node, const char *uname, 223 int depth, void *data) 224 { 225 return 1; 226 } 227 #endif 228 229 void __init early_init_devtree(void *params) 230 { 231 early_init_dt_scan(params); 232 of_scan_flat_dt(xtensa_dt_io_area, NULL); 233 234 if (!command_line[0]) 235 strscpy(command_line, boot_command_line, COMMAND_LINE_SIZE); 236 } 237 238 #endif /* CONFIG_USE_OF */ 239 240 /* 241 * Initialize architecture. (Early stage) 242 */ 243 244 void __init init_arch(bp_tag_t *bp_start) 245 { 246 /* Initialize basic exception handling if configuration may need it */ 247 248 if (IS_ENABLED(CONFIG_KASAN)) 249 early_trap_init(); 250 251 /* Initialize MMU. */ 252 253 init_mmu(); 254 255 /* Initialize initial KASAN shadow map */ 256 257 kasan_early_init(); 258 259 /* Parse boot parameters */ 260 261 if (bp_start) 262 parse_bootparam(bp_start); 263 264 #ifdef CONFIG_USE_OF 265 early_init_devtree(dtb_start); 266 #endif 267 268 #ifdef CONFIG_CMDLINE_BOOL 269 if (!command_line[0]) 270 strscpy(command_line, default_command_line, COMMAND_LINE_SIZE); 271 #endif 272 273 /* Early hook for platforms */ 274 275 platform_init(bp_start); 276 } 277 278 /* 279 * Initialize system. Setup memory and reserve regions. 280 */ 281 282 static inline int __init_memblock mem_reserve(unsigned long start, 283 unsigned long end) 284 { 285 return memblock_reserve(start, end - start); 286 } 287 288 void __init setup_arch(char **cmdline_p) 289 { 290 pr_info("config ID: %08x:%08x\n", 291 xtensa_get_sr(SREG_EPC), xtensa_get_sr(SREG_EXCSAVE)); 292 if (xtensa_get_sr(SREG_EPC) != XCHAL_HW_CONFIGID0 || 293 xtensa_get_sr(SREG_EXCSAVE) != XCHAL_HW_CONFIGID1) 294 pr_info("built for config ID: %08x:%08x\n", 295 XCHAL_HW_CONFIGID0, XCHAL_HW_CONFIGID1); 296 297 *cmdline_p = command_line; 298 platform_setup(cmdline_p); 299 strscpy(boot_command_line, *cmdline_p, COMMAND_LINE_SIZE); 300 301 /* Reserve some memory regions */ 302 303 #ifdef CONFIG_BLK_DEV_INITRD 304 if (initrd_start < initrd_end && 305 !mem_reserve(__pa(initrd_start), __pa(initrd_end))) 306 initrd_below_start_ok = 1; 307 else 308 initrd_start = 0; 309 #endif 310 311 mem_reserve(__pa(_stext), __pa(_end)); 312 #ifdef CONFIG_XIP_KERNEL 313 mem_reserve(__pa(_xip_start), __pa(_xip_end)); 314 #endif 315 316 #ifdef CONFIG_VECTORS_ADDR 317 #ifdef SUPPORT_WINDOWED 318 mem_reserve(__pa(_WindowVectors_text_start), 319 __pa(_WindowVectors_text_end)); 320 #endif 321 322 mem_reserve(__pa(_DebugInterruptVector_text_start), 323 __pa(_DebugInterruptVector_text_end)); 324 325 mem_reserve(__pa(_KernelExceptionVector_text_start), 326 __pa(_KernelExceptionVector_text_end)); 327 328 mem_reserve(__pa(_UserExceptionVector_text_start), 329 __pa(_UserExceptionVector_text_end)); 330 331 mem_reserve(__pa(_DoubleExceptionVector_text_start), 332 __pa(_DoubleExceptionVector_text_end)); 333 334 mem_reserve(__pa(_exception_text_start), 335 __pa(_exception_text_end)); 336 #if XCHAL_EXCM_LEVEL >= 2 337 mem_reserve(__pa(_Level2InterruptVector_text_start), 338 __pa(_Level2InterruptVector_text_end)); 339 #endif 340 #if XCHAL_EXCM_LEVEL >= 3 341 mem_reserve(__pa(_Level3InterruptVector_text_start), 342 __pa(_Level3InterruptVector_text_end)); 343 #endif 344 #if XCHAL_EXCM_LEVEL >= 4 345 mem_reserve(__pa(_Level4InterruptVector_text_start), 346 __pa(_Level4InterruptVector_text_end)); 347 #endif 348 #if XCHAL_EXCM_LEVEL >= 5 349 mem_reserve(__pa(_Level5InterruptVector_text_start), 350 __pa(_Level5InterruptVector_text_end)); 351 #endif 352 #if XCHAL_EXCM_LEVEL >= 6 353 mem_reserve(__pa(_Level6InterruptVector_text_start), 354 __pa(_Level6InterruptVector_text_end)); 355 #endif 356 357 #endif /* CONFIG_VECTORS_ADDR */ 358 359 #ifdef CONFIG_SECONDARY_RESET_VECTOR 360 mem_reserve(__pa(_SecondaryResetVector_text_start), 361 __pa(_SecondaryResetVector_text_end)); 362 #endif 363 parse_early_param(); 364 bootmem_init(); 365 kasan_init(); 366 unflatten_and_copy_device_tree(); 367 368 #ifdef CONFIG_SMP 369 smp_init_cpus(); 370 #endif 371 372 paging_init(); 373 zones_init(); 374 375 #ifdef CONFIG_VT 376 # if defined(CONFIG_VGA_CONSOLE) 377 conswitchp = &vga_con; 378 # endif 379 #endif 380 } 381 382 static DEFINE_PER_CPU(struct cpu, cpu_data); 383 384 static int __init topology_init(void) 385 { 386 int i; 387 388 for_each_possible_cpu(i) { 389 struct cpu *cpu = &per_cpu(cpu_data, i); 390 cpu->hotpluggable = !!i; 391 register_cpu(cpu, i); 392 } 393 394 return 0; 395 } 396 subsys_initcall(topology_init); 397 398 void cpu_reset(void) 399 { 400 #if XCHAL_HAVE_PTP_MMU && IS_ENABLED(CONFIG_MMU) 401 local_irq_disable(); 402 /* 403 * We have full MMU: all autoload ways, ways 7, 8 and 9 of DTLB must 404 * be flushed. 405 * Way 4 is not currently used by linux. 406 * Ways 5 and 6 shall not be touched on MMUv2 as they are hardwired. 407 * Way 5 shall be flushed and way 6 shall be set to identity mapping 408 * on MMUv3. 409 */ 410 local_flush_tlb_all(); 411 invalidate_page_directory(); 412 #if XCHAL_HAVE_SPANNING_WAY 413 /* MMU v3 */ 414 { 415 unsigned long vaddr = (unsigned long)cpu_reset; 416 unsigned long paddr = __pa(vaddr); 417 unsigned long tmpaddr = vaddr + SZ_512M; 418 unsigned long tmp0, tmp1, tmp2, tmp3; 419 420 /* 421 * Find a place for the temporary mapping. It must not be 422 * in the same 512MB region with vaddr or paddr, otherwise 423 * there may be multihit exception either on entry to the 424 * temporary mapping, or on entry to the identity mapping. 425 * (512MB is the biggest page size supported by TLB.) 426 */ 427 while (((tmpaddr ^ paddr) & -SZ_512M) == 0) 428 tmpaddr += SZ_512M; 429 430 /* Invalidate mapping in the selected temporary area */ 431 if (itlb_probe(tmpaddr) & BIT(ITLB_HIT_BIT)) 432 invalidate_itlb_entry(itlb_probe(tmpaddr)); 433 if (itlb_probe(tmpaddr + PAGE_SIZE) & BIT(ITLB_HIT_BIT)) 434 invalidate_itlb_entry(itlb_probe(tmpaddr + PAGE_SIZE)); 435 436 /* 437 * Map two consecutive pages starting at the physical address 438 * of this function to the temporary mapping area. 439 */ 440 write_itlb_entry(__pte((paddr & PAGE_MASK) | 441 _PAGE_HW_VALID | 442 _PAGE_HW_EXEC | 443 _PAGE_CA_BYPASS), 444 tmpaddr & PAGE_MASK); 445 write_itlb_entry(__pte(((paddr & PAGE_MASK) + PAGE_SIZE) | 446 _PAGE_HW_VALID | 447 _PAGE_HW_EXEC | 448 _PAGE_CA_BYPASS), 449 (tmpaddr & PAGE_MASK) + PAGE_SIZE); 450 451 /* Reinitialize TLB */ 452 __asm__ __volatile__ ("movi %0, 1f\n\t" 453 "movi %3, 2f\n\t" 454 "add %0, %0, %4\n\t" 455 "add %3, %3, %5\n\t" 456 "jx %0\n" 457 /* 458 * No literal, data or stack access 459 * below this point 460 */ 461 "1:\n\t" 462 /* Initialize *tlbcfg */ 463 "movi %0, 0\n\t" 464 "wsr %0, itlbcfg\n\t" 465 "wsr %0, dtlbcfg\n\t" 466 /* Invalidate TLB way 5 */ 467 "movi %0, 4\n\t" 468 "movi %1, 5\n" 469 "1:\n\t" 470 "iitlb %1\n\t" 471 "idtlb %1\n\t" 472 "add %1, %1, %6\n\t" 473 "addi %0, %0, -1\n\t" 474 "bnez %0, 1b\n\t" 475 /* Initialize TLB way 6 */ 476 "movi %0, 7\n\t" 477 "addi %1, %9, 3\n\t" 478 "addi %2, %9, 6\n" 479 "1:\n\t" 480 "witlb %1, %2\n\t" 481 "wdtlb %1, %2\n\t" 482 "add %1, %1, %7\n\t" 483 "add %2, %2, %7\n\t" 484 "addi %0, %0, -1\n\t" 485 "bnez %0, 1b\n\t" 486 "isync\n\t" 487 /* Jump to identity mapping */ 488 "jx %3\n" 489 "2:\n\t" 490 /* Complete way 6 initialization */ 491 "witlb %1, %2\n\t" 492 "wdtlb %1, %2\n\t" 493 /* Invalidate temporary mapping */ 494 "sub %0, %9, %7\n\t" 495 "iitlb %0\n\t" 496 "add %0, %0, %8\n\t" 497 "iitlb %0" 498 : "=&a"(tmp0), "=&a"(tmp1), "=&a"(tmp2), 499 "=&a"(tmp3) 500 : "a"(tmpaddr - vaddr), 501 "a"(paddr - vaddr), 502 "a"(SZ_128M), "a"(SZ_512M), 503 "a"(PAGE_SIZE), 504 "a"((tmpaddr + SZ_512M) & PAGE_MASK) 505 : "memory"); 506 } 507 #endif 508 #endif 509 __asm__ __volatile__ ("movi a2, 0\n\t" 510 "wsr a2, icountlevel\n\t" 511 "movi a2, 0\n\t" 512 "wsr a2, icount\n\t" 513 #if XCHAL_NUM_IBREAK > 0 514 "wsr a2, ibreakenable\n\t" 515 #endif 516 #if XCHAL_HAVE_LOOPS 517 "wsr a2, lcount\n\t" 518 #endif 519 "movi a2, 0x1f\n\t" 520 "wsr a2, ps\n\t" 521 "isync\n\t" 522 "jx %0\n\t" 523 : 524 : "a" (XCHAL_RESET_VECTOR_VADDR) 525 : "a2"); 526 for (;;) 527 ; 528 } 529 530 void machine_restart(char * cmd) 531 { 532 local_irq_disable(); 533 smp_send_stop(); 534 do_kernel_restart(cmd); 535 pr_err("Reboot failed -- System halted\n"); 536 while (1) 537 cpu_relax(); 538 } 539 540 void machine_halt(void) 541 { 542 local_irq_disable(); 543 smp_send_stop(); 544 do_kernel_power_off(); 545 while (1) 546 cpu_relax(); 547 } 548 549 void machine_power_off(void) 550 { 551 local_irq_disable(); 552 smp_send_stop(); 553 do_kernel_power_off(); 554 while (1) 555 cpu_relax(); 556 } 557 #ifdef CONFIG_PROC_FS 558 559 /* 560 * Display some core information through /proc/cpuinfo. 561 */ 562 563 static int 564 c_show(struct seq_file *f, void *slot) 565 { 566 /* high-level stuff */ 567 seq_printf(f, "CPU count\t: %u\n" 568 "CPU list\t: %*pbl\n" 569 "vendor_id\t: Tensilica\n" 570 "model\t\t: Xtensa " XCHAL_HW_VERSION_NAME "\n" 571 "core ID\t\t: " XCHAL_CORE_ID "\n" 572 "build ID\t: 0x%x\n" 573 "config ID\t: %08x:%08x\n" 574 "byte order\t: %s\n" 575 "cpu MHz\t\t: %lu.%02lu\n" 576 "bogomips\t: %lu.%02lu\n", 577 num_online_cpus(), 578 cpumask_pr_args(cpu_online_mask), 579 XCHAL_BUILD_UNIQUE_ID, 580 xtensa_get_sr(SREG_EPC), xtensa_get_sr(SREG_EXCSAVE), 581 XCHAL_HAVE_BE ? "big" : "little", 582 ccount_freq/1000000, 583 (ccount_freq/10000) % 100, 584 loops_per_jiffy/(500000/HZ), 585 (loops_per_jiffy/(5000/HZ)) % 100); 586 seq_puts(f, "flags\t\t: " 587 #if XCHAL_HAVE_NMI 588 "nmi " 589 #endif 590 #if XCHAL_HAVE_DEBUG 591 "debug " 592 # if XCHAL_HAVE_OCD 593 "ocd " 594 # endif 595 #if XCHAL_HAVE_TRAX 596 "trax " 597 #endif 598 #if XCHAL_NUM_PERF_COUNTERS 599 "perf " 600 #endif 601 #endif 602 #if XCHAL_HAVE_DENSITY 603 "density " 604 #endif 605 #if XCHAL_HAVE_BOOLEANS 606 "boolean " 607 #endif 608 #if XCHAL_HAVE_LOOPS 609 "loop " 610 #endif 611 #if XCHAL_HAVE_NSA 612 "nsa " 613 #endif 614 #if XCHAL_HAVE_MINMAX 615 "minmax " 616 #endif 617 #if XCHAL_HAVE_SEXT 618 "sext " 619 #endif 620 #if XCHAL_HAVE_CLAMPS 621 "clamps " 622 #endif 623 #if XCHAL_HAVE_MAC16 624 "mac16 " 625 #endif 626 #if XCHAL_HAVE_MUL16 627 "mul16 " 628 #endif 629 #if XCHAL_HAVE_MUL32 630 "mul32 " 631 #endif 632 #if XCHAL_HAVE_MUL32_HIGH 633 "mul32h " 634 #endif 635 #if XCHAL_HAVE_FP 636 "fpu " 637 #endif 638 #if XCHAL_HAVE_S32C1I 639 "s32c1i " 640 #endif 641 #if XCHAL_HAVE_EXCLUSIVE 642 "exclusive " 643 #endif 644 "\n"); 645 646 /* Registers. */ 647 seq_printf(f,"physical aregs\t: %d\n" 648 "misc regs\t: %d\n" 649 "ibreak\t\t: %d\n" 650 "dbreak\t\t: %d\n" 651 "perf counters\t: %d\n", 652 XCHAL_NUM_AREGS, 653 XCHAL_NUM_MISC_REGS, 654 XCHAL_NUM_IBREAK, 655 XCHAL_NUM_DBREAK, 656 XCHAL_NUM_PERF_COUNTERS); 657 658 659 /* Interrupt. */ 660 seq_printf(f,"num ints\t: %d\n" 661 "ext ints\t: %d\n" 662 "int levels\t: %d\n" 663 "timers\t\t: %d\n" 664 "debug level\t: %d\n", 665 XCHAL_NUM_INTERRUPTS, 666 XCHAL_NUM_EXTINTERRUPTS, 667 XCHAL_NUM_INTLEVELS, 668 XCHAL_NUM_TIMERS, 669 XCHAL_DEBUGLEVEL); 670 671 /* Cache */ 672 seq_printf(f,"icache line size: %d\n" 673 "icache ways\t: %d\n" 674 "icache size\t: %d\n" 675 "icache flags\t: " 676 #if XCHAL_ICACHE_LINE_LOCKABLE 677 "lock " 678 #endif 679 "\n" 680 "dcache line size: %d\n" 681 "dcache ways\t: %d\n" 682 "dcache size\t: %d\n" 683 "dcache flags\t: " 684 #if XCHAL_DCACHE_IS_WRITEBACK 685 "writeback " 686 #endif 687 #if XCHAL_DCACHE_LINE_LOCKABLE 688 "lock " 689 #endif 690 "\n", 691 XCHAL_ICACHE_LINESIZE, 692 XCHAL_ICACHE_WAYS, 693 XCHAL_ICACHE_SIZE, 694 XCHAL_DCACHE_LINESIZE, 695 XCHAL_DCACHE_WAYS, 696 XCHAL_DCACHE_SIZE); 697 698 return 0; 699 } 700 701 /* 702 * We show only CPU #0 info. 703 */ 704 static void * 705 c_start(struct seq_file *f, loff_t *pos) 706 { 707 return (*pos == 0) ? (void *)1 : NULL; 708 } 709 710 static void * 711 c_next(struct seq_file *f, void *v, loff_t *pos) 712 { 713 ++*pos; 714 return c_start(f, pos); 715 } 716 717 static void 718 c_stop(struct seq_file *f, void *v) 719 { 720 } 721 722 const struct seq_operations cpuinfo_op = 723 { 724 .start = c_start, 725 .next = c_next, 726 .stop = c_stop, 727 .show = c_show, 728 }; 729 730 #endif /* CONFIG_PROC_FS */ 731