xref: /openbmc/linux/arch/xtensa/kernel/setup.c (revision 49b424fedaf88d0fa9913082b8c1ccd012a8a972) 
1 /*
2  * arch/xtensa/kernel/setup.c
3  *
4  * This file is subject to the terms and conditions of the GNU General Public
5  * License.  See the file "COPYING" in the main directory of this archive
6  * for more details.
7  *
8  * Copyright (C) 1995  Linus Torvalds
9  * Copyright (C) 2001 - 2005  Tensilica Inc.
10  *
11  * Chris Zankel	<chris@zankel.net>
12  * Joe Taylor	<joe@tensilica.com, joetylr@yahoo.com>
13  * Kevin Chea
14  * Marc Gauthier<marc@tensilica.com> <marc@alumni.uwaterloo.ca>
15  */
16 
17 #include <linux/errno.h>
18 #include <linux/init.h>
19 #include <linux/mm.h>
20 #include <linux/proc_fs.h>
21 #include <linux/screen_info.h>
22 #include <linux/bootmem.h>
23 #include <linux/kernel.h>
24 #include <linux/percpu.h>
25 #include <linux/cpu.h>
26 #include <linux/of_fdt.h>
27 #include <linux/of_platform.h>
28 
29 #if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
30 # include <linux/console.h>
31 #endif
32 
33 #ifdef CONFIG_RTC
34 # include <linux/timex.h>
35 #endif
36 
37 #ifdef CONFIG_PROC_FS
38 # include <linux/seq_file.h>
39 #endif
40 
41 #include <asm/bootparam.h>
42 #include <asm/mmu_context.h>
43 #include <asm/pgtable.h>
44 #include <asm/processor.h>
45 #include <asm/timex.h>
46 #include <asm/platform.h>
47 #include <asm/page.h>
48 #include <asm/setup.h>
49 #include <asm/param.h>
50 #include <asm/traps.h>
51 #include <asm/smp.h>
52 
53 #include <platform/hardware.h>
54 
55 #if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
56 struct screen_info screen_info = { 0, 24, 0, 0, 0, 80, 0, 0, 0, 24, 1, 16};
57 #endif
58 
59 #ifdef CONFIG_BLK_DEV_FD
60 extern struct fd_ops no_fd_ops;
61 struct fd_ops *fd_ops;
62 #endif
63 
64 extern struct rtc_ops no_rtc_ops;
65 struct rtc_ops *rtc_ops;
66 
67 #ifdef CONFIG_BLK_DEV_INITRD
68 extern unsigned long initrd_start;
69 extern unsigned long initrd_end;
70 int initrd_is_mapped = 0;
71 extern int initrd_below_start_ok;
72 #endif
73 
74 #ifdef CONFIG_OF
75 extern u32 __dtb_start[];
76 void *dtb_start = __dtb_start;
77 #endif
78 
79 unsigned char aux_device_present;
80 extern unsigned long loops_per_jiffy;
81 
82 /* Command line specified as configuration option. */
83 
84 static char __initdata command_line[COMMAND_LINE_SIZE];
85 
86 #ifdef CONFIG_CMDLINE_BOOL
87 static char default_command_line[COMMAND_LINE_SIZE] __initdata = CONFIG_CMDLINE;
88 #endif
89 
90 sysmem_info_t __initdata sysmem;
91 
92 extern int mem_reserve(unsigned long, unsigned long, int);
93 extern void bootmem_init(void);
94 extern void zones_init(void);
95 
96 /*
97  * Boot parameter parsing.
98  *
99  * The Xtensa port uses a list of variable-sized tags to pass data to
100  * the kernel. The first tag must be a BP_TAG_FIRST tag for the list
101  * to be recognised. The list is terminated with a zero-sized
102  * BP_TAG_LAST tag.
103  */
104 
105 typedef struct tagtable {
106 	u32 tag;
107 	int (*parse)(const bp_tag_t*);
108 } tagtable_t;
109 
110 #define __tagtable(tag, fn) static tagtable_t __tagtable_##fn 		\
111 	__attribute__((used, section(".taglist"))) = { tag, fn }
112 
113 /* parse current tag */
114 
115 static int __init add_sysmem_bank(unsigned long type, unsigned long start,
116 		unsigned long end)
117 {
118 	if (sysmem.nr_banks >= SYSMEM_BANKS_MAX) {
119 		printk(KERN_WARNING
120 				"Ignoring memory bank 0x%08lx size %ldKB\n",
121 				start, end - start);
122 		return -EINVAL;
123 	}
124 	sysmem.bank[sysmem.nr_banks].type  = type;
125 	sysmem.bank[sysmem.nr_banks].start = PAGE_ALIGN(start);
126 	sysmem.bank[sysmem.nr_banks].end   = end & PAGE_MASK;
127 	sysmem.nr_banks++;
128 
129 	return 0;
130 }
131 
132 static int __init parse_tag_mem(const bp_tag_t *tag)
133 {
134 	meminfo_t *mi = (meminfo_t *)(tag->data);
135 
136 	if (mi->type != MEMORY_TYPE_CONVENTIONAL)
137 		return -1;
138 
139 	return add_sysmem_bank(mi->type, mi->start, mi->end);
140 }
141 
142 __tagtable(BP_TAG_MEMORY, parse_tag_mem);
143 
144 #ifdef CONFIG_BLK_DEV_INITRD
145 
146 static int __init parse_tag_initrd(const bp_tag_t* tag)
147 {
148 	meminfo_t* mi;
149 	mi = (meminfo_t*)(tag->data);
150 	initrd_start = (unsigned long)__va(mi->start);
151 	initrd_end = (unsigned long)__va(mi->end);
152 
153 	return 0;
154 }
155 
156 __tagtable(BP_TAG_INITRD, parse_tag_initrd);
157 
158 #ifdef CONFIG_OF
159 
160 static int __init parse_tag_fdt(const bp_tag_t *tag)
161 {
162 	dtb_start = __va(tag->data[0]);
163 	return 0;
164 }
165 
166 __tagtable(BP_TAG_FDT, parse_tag_fdt);
167 
168 #endif /* CONFIG_OF */
169 
170 #endif /* CONFIG_BLK_DEV_INITRD */
171 
172 static int __init parse_tag_cmdline(const bp_tag_t* tag)
173 {
174 	strlcpy(command_line, (char *)(tag->data), COMMAND_LINE_SIZE);
175 	return 0;
176 }
177 
178 __tagtable(BP_TAG_COMMAND_LINE, parse_tag_cmdline);
179 
180 static int __init parse_bootparam(const bp_tag_t* tag)
181 {
182 	extern tagtable_t __tagtable_begin, __tagtable_end;
183 	tagtable_t *t;
184 
185 	/* Boot parameters must start with a BP_TAG_FIRST tag. */
186 
187 	if (tag->id != BP_TAG_FIRST) {
188 		printk(KERN_WARNING "Invalid boot parameters!\n");
189 		return 0;
190 	}
191 
192 	tag = (bp_tag_t*)((unsigned long)tag + sizeof(bp_tag_t) + tag->size);
193 
194 	/* Parse all tags. */
195 
196 	while (tag != NULL && tag->id != BP_TAG_LAST) {
197 	 	for (t = &__tagtable_begin; t < &__tagtable_end; t++) {
198 			if (tag->id == t->tag) {
199 				t->parse(tag);
200 				break;
201 			}
202 		}
203 		if (t == &__tagtable_end)
204 			printk(KERN_WARNING "Ignoring tag "
205 			       "0x%08x\n", tag->id);
206 		tag = (bp_tag_t*)((unsigned long)(tag + 1) + tag->size);
207 	}
208 
209 	return 0;
210 }
211 
212 #ifdef CONFIG_OF
213 bool __initdata dt_memory_scan = false;
214 
215 void __init early_init_dt_add_memory_arch(u64 base, u64 size)
216 {
217 	if (!dt_memory_scan)
218 		return;
219 
220 	size &= PAGE_MASK;
221 	add_sysmem_bank(MEMORY_TYPE_CONVENTIONAL, base, base + size);
222 }
223 
224 void * __init early_init_dt_alloc_memory_arch(u64 size, u64 align)
225 {
226 	return __alloc_bootmem(size, align, 0);
227 }
228 
229 void __init early_init_devtree(void *params)
230 {
231 	if (sysmem.nr_banks == 0)
232 		dt_memory_scan = true;
233 
234 	early_init_dt_scan(params);
235 
236 	if (!command_line[0])
237 		strlcpy(command_line, boot_command_line, COMMAND_LINE_SIZE);
238 }
239 
240 static int __init xtensa_device_probe(void)
241 {
242 	of_platform_populate(NULL, NULL, NULL, NULL);
243 	return 0;
244 }
245 
246 device_initcall(xtensa_device_probe);
247 
248 #endif /* CONFIG_OF */
249 
250 /*
251  * Initialize architecture. (Early stage)
252  */
253 
254 void __init init_arch(bp_tag_t *bp_start)
255 {
256 	sysmem.nr_banks = 0;
257 
258 	/* Parse boot parameters */
259 
260 	if (bp_start)
261 		parse_bootparam(bp_start);
262 
263 #ifdef CONFIG_OF
264 	early_init_devtree(dtb_start);
265 #endif
266 
267 	if (sysmem.nr_banks == 0) {
268 		sysmem.nr_banks = 1;
269 		sysmem.bank[0].start = PLATFORM_DEFAULT_MEM_START;
270 		sysmem.bank[0].end = PLATFORM_DEFAULT_MEM_START
271 				     + PLATFORM_DEFAULT_MEM_SIZE;
272 	}
273 
274 #ifdef CONFIG_CMDLINE_BOOL
275 	if (!command_line[0])
276 		strlcpy(command_line, default_command_line, COMMAND_LINE_SIZE);
277 #endif
278 
279 	/* Early hook for platforms */
280 
281 	platform_init(bp_start);
282 
283 	/* Initialize MMU. */
284 
285 	init_mmu();
286 }
287 
288 /*
289  * Initialize system. Setup memory and reserve regions.
290  */
291 
292 extern char _end;
293 extern char _stext;
294 extern char _WindowVectors_text_start;
295 extern char _WindowVectors_text_end;
296 extern char _DebugInterruptVector_literal_start;
297 extern char _DebugInterruptVector_text_end;
298 extern char _KernelExceptionVector_literal_start;
299 extern char _KernelExceptionVector_text_end;
300 extern char _UserExceptionVector_literal_start;
301 extern char _UserExceptionVector_text_end;
302 extern char _DoubleExceptionVector_literal_start;
303 extern char _DoubleExceptionVector_text_end;
304 #if XCHAL_EXCM_LEVEL >= 2
305 extern char _Level2InterruptVector_text_start;
306 extern char _Level2InterruptVector_text_end;
307 #endif
308 #if XCHAL_EXCM_LEVEL >= 3
309 extern char _Level3InterruptVector_text_start;
310 extern char _Level3InterruptVector_text_end;
311 #endif
312 #if XCHAL_EXCM_LEVEL >= 4
313 extern char _Level4InterruptVector_text_start;
314 extern char _Level4InterruptVector_text_end;
315 #endif
316 #if XCHAL_EXCM_LEVEL >= 5
317 extern char _Level5InterruptVector_text_start;
318 extern char _Level5InterruptVector_text_end;
319 #endif
320 #if XCHAL_EXCM_LEVEL >= 6
321 extern char _Level6InterruptVector_text_start;
322 extern char _Level6InterruptVector_text_end;
323 #endif
324 
325 
326 
327 #ifdef CONFIG_S32C1I_SELFTEST
328 #if XCHAL_HAVE_S32C1I
329 
330 static int __initdata rcw_word, rcw_probe_pc, rcw_exc;
331 
332 /*
333  * Basic atomic compare-and-swap, that records PC of S32C1I for probing.
334  *
335  * If *v == cmp, set *v = set.  Return previous *v.
336  */
337 static inline int probed_compare_swap(int *v, int cmp, int set)
338 {
339 	int tmp;
340 
341 	__asm__ __volatile__(
342 			"	movi	%1, 1f\n"
343 			"	s32i	%1, %4, 0\n"
344 			"	wsr	%2, scompare1\n"
345 			"1:	s32c1i	%0, %3, 0\n"
346 			: "=a" (set), "=&a" (tmp)
347 			: "a" (cmp), "a" (v), "a" (&rcw_probe_pc), "0" (set)
348 			: "memory"
349 			);
350 	return set;
351 }
352 
353 /* Handle probed exception */
354 
355 static void __init do_probed_exception(struct pt_regs *regs,
356 		unsigned long exccause)
357 {
358 	if (regs->pc == rcw_probe_pc) {	/* exception on s32c1i ? */
359 		regs->pc += 3;		/* skip the s32c1i instruction */
360 		rcw_exc = exccause;
361 	} else {
362 		do_unhandled(regs, exccause);
363 	}
364 }
365 
366 /* Simple test of S32C1I (soc bringup assist) */
367 
368 static int __init check_s32c1i(void)
369 {
370 	int n, cause1, cause2;
371 	void *handbus, *handdata, *handaddr; /* temporarily saved handlers */
372 
373 	rcw_probe_pc = 0;
374 	handbus  = trap_set_handler(EXCCAUSE_LOAD_STORE_ERROR,
375 			do_probed_exception);
376 	handdata = trap_set_handler(EXCCAUSE_LOAD_STORE_DATA_ERROR,
377 			do_probed_exception);
378 	handaddr = trap_set_handler(EXCCAUSE_LOAD_STORE_ADDR_ERROR,
379 			do_probed_exception);
380 
381 	/* First try an S32C1I that does not store: */
382 	rcw_exc = 0;
383 	rcw_word = 1;
384 	n = probed_compare_swap(&rcw_word, 0, 2);
385 	cause1 = rcw_exc;
386 
387 	/* took exception? */
388 	if (cause1 != 0) {
389 		/* unclean exception? */
390 		if (n != 2 || rcw_word != 1)
391 			panic("S32C1I exception error");
392 	} else if (rcw_word != 1 || n != 1) {
393 		panic("S32C1I compare error");
394 	}
395 
396 	/* Then an S32C1I that stores: */
397 	rcw_exc = 0;
398 	rcw_word = 0x1234567;
399 	n = probed_compare_swap(&rcw_word, 0x1234567, 0xabcde);
400 	cause2 = rcw_exc;
401 
402 	if (cause2 != 0) {
403 		/* unclean exception? */
404 		if (n != 0xabcde || rcw_word != 0x1234567)
405 			panic("S32C1I exception error (b)");
406 	} else if (rcw_word != 0xabcde || n != 0x1234567) {
407 		panic("S32C1I store error");
408 	}
409 
410 	/* Verify consistency of exceptions: */
411 	if (cause1 || cause2) {
412 		pr_warn("S32C1I took exception %d, %d\n", cause1, cause2);
413 		/* If emulation of S32C1I upon bus error gets implemented,
414 		   we can get rid of this panic for single core (not SMP) */
415 		panic("S32C1I exceptions not currently supported");
416 	}
417 	if (cause1 != cause2)
418 		panic("inconsistent S32C1I exceptions");
419 
420 	trap_set_handler(EXCCAUSE_LOAD_STORE_ERROR, handbus);
421 	trap_set_handler(EXCCAUSE_LOAD_STORE_DATA_ERROR, handdata);
422 	trap_set_handler(EXCCAUSE_LOAD_STORE_ADDR_ERROR, handaddr);
423 	return 0;
424 }
425 
426 #else /* XCHAL_HAVE_S32C1I */
427 
428 /* This condition should not occur with a commercially deployed processor.
429    Display reminder for early engr test or demo chips / FPGA bitstreams */
430 static int __init check_s32c1i(void)
431 {
432 	pr_warn("Processor configuration lacks atomic compare-and-swap support!\n");
433 	return 0;
434 }
435 
436 #endif /* XCHAL_HAVE_S32C1I */
437 early_initcall(check_s32c1i);
438 #endif /* CONFIG_S32C1I_SELFTEST */
439 
440 
441 void __init setup_arch(char **cmdline_p)
442 {
443 	strlcpy(boot_command_line, command_line, COMMAND_LINE_SIZE);
444 	*cmdline_p = command_line;
445 
446 	/* Reserve some memory regions */
447 
448 #ifdef CONFIG_BLK_DEV_INITRD
449 	if (initrd_start < initrd_end) {
450 		initrd_is_mapped = mem_reserve(__pa(initrd_start),
451 					       __pa(initrd_end), 0);
452 		initrd_below_start_ok = 1;
453 	} else {
454 		initrd_start = 0;
455 	}
456 #endif
457 
458 	mem_reserve(__pa(&_stext),__pa(&_end), 1);
459 
460 	mem_reserve(__pa(&_WindowVectors_text_start),
461 		    __pa(&_WindowVectors_text_end), 0);
462 
463 	mem_reserve(__pa(&_DebugInterruptVector_literal_start),
464 		    __pa(&_DebugInterruptVector_text_end), 0);
465 
466 	mem_reserve(__pa(&_KernelExceptionVector_literal_start),
467 		    __pa(&_KernelExceptionVector_text_end), 0);
468 
469 	mem_reserve(__pa(&_UserExceptionVector_literal_start),
470 		    __pa(&_UserExceptionVector_text_end), 0);
471 
472 	mem_reserve(__pa(&_DoubleExceptionVector_literal_start),
473 		    __pa(&_DoubleExceptionVector_text_end), 0);
474 
475 #if XCHAL_EXCM_LEVEL >= 2
476 	mem_reserve(__pa(&_Level2InterruptVector_text_start),
477 		    __pa(&_Level2InterruptVector_text_end), 0);
478 #endif
479 #if XCHAL_EXCM_LEVEL >= 3
480 	mem_reserve(__pa(&_Level3InterruptVector_text_start),
481 		    __pa(&_Level3InterruptVector_text_end), 0);
482 #endif
483 #if XCHAL_EXCM_LEVEL >= 4
484 	mem_reserve(__pa(&_Level4InterruptVector_text_start),
485 		    __pa(&_Level4InterruptVector_text_end), 0);
486 #endif
487 #if XCHAL_EXCM_LEVEL >= 5
488 	mem_reserve(__pa(&_Level5InterruptVector_text_start),
489 		    __pa(&_Level5InterruptVector_text_end), 0);
490 #endif
491 #if XCHAL_EXCM_LEVEL >= 6
492 	mem_reserve(__pa(&_Level6InterruptVector_text_start),
493 		    __pa(&_Level6InterruptVector_text_end), 0);
494 #endif
495 
496 	bootmem_init();
497 
498 	unflatten_and_copy_device_tree();
499 
500 	platform_setup(cmdline_p);
501 
502 #ifdef CONFIG_SMP
503 	smp_init_cpus();
504 #endif
505 
506 	paging_init();
507 	zones_init();
508 
509 #ifdef CONFIG_VT
510 # if defined(CONFIG_VGA_CONSOLE)
511 	conswitchp = &vga_con;
512 # elif defined(CONFIG_DUMMY_CONSOLE)
513 	conswitchp = &dummy_con;
514 # endif
515 #endif
516 
517 #ifdef CONFIG_PCI
518 	platform_pcibios_init();
519 #endif
520 }
521 
522 static DEFINE_PER_CPU(struct cpu, cpu_data);
523 
524 static int __init topology_init(void)
525 {
526 	int i;
527 
528 	for_each_possible_cpu(i) {
529 		struct cpu *cpu = &per_cpu(cpu_data, i);
530 		cpu->hotpluggable = !!i;
531 		register_cpu(cpu, i);
532 	}
533 
534 	return 0;
535 }
536 subsys_initcall(topology_init);
537 
538 void machine_restart(char * cmd)
539 {
540 	platform_restart();
541 }
542 
543 void machine_halt(void)
544 {
545 	platform_halt();
546 	while (1);
547 }
548 
549 void machine_power_off(void)
550 {
551 	platform_power_off();
552 	while (1);
553 }
554 #ifdef CONFIG_PROC_FS
555 
556 /*
557  * Display some core information through /proc/cpuinfo.
558  */
559 
560 static int
561 c_show(struct seq_file *f, void *slot)
562 {
563 	char buf[NR_CPUS * 5];
564 
565 	cpulist_scnprintf(buf, sizeof(buf), cpu_online_mask);
566 	/* high-level stuff */
567 	seq_printf(f, "CPU count\t: %u\n"
568 		      "CPU list\t: %s\n"
569 		      "vendor_id\t: Tensilica\n"
570 		      "model\t\t: Xtensa " XCHAL_HW_VERSION_NAME "\n"
571 		      "core ID\t\t: " XCHAL_CORE_ID "\n"
572 		      "build ID\t: 0x%x\n"
573 		      "byte order\t: %s\n"
574 		      "cpu MHz\t\t: %lu.%02lu\n"
575 		      "bogomips\t: %lu.%02lu\n",
576 		      num_online_cpus(),
577 		      buf,
578 		      XCHAL_BUILD_UNIQUE_ID,
579 		      XCHAL_HAVE_BE ?  "big" : "little",
580 		      ccount_freq/1000000,
581 		      (ccount_freq/10000) % 100,
582 		      loops_per_jiffy/(500000/HZ),
583 		      (loops_per_jiffy/(5000/HZ)) % 100);
584 
585 	seq_printf(f,"flags\t\t: "
586 #if XCHAL_HAVE_NMI
587 		     "nmi "
588 #endif
589 #if XCHAL_HAVE_DEBUG
590 		     "debug "
591 # if XCHAL_HAVE_OCD
592 		     "ocd "
593 # endif
594 #endif
595 #if XCHAL_HAVE_DENSITY
596 	    	     "density "
597 #endif
598 #if XCHAL_HAVE_BOOLEANS
599 		     "boolean "
600 #endif
601 #if XCHAL_HAVE_LOOPS
602 		     "loop "
603 #endif
604 #if XCHAL_HAVE_NSA
605 		     "nsa "
606 #endif
607 #if XCHAL_HAVE_MINMAX
608 		     "minmax "
609 #endif
610 #if XCHAL_HAVE_SEXT
611 		     "sext "
612 #endif
613 #if XCHAL_HAVE_CLAMPS
614 		     "clamps "
615 #endif
616 #if XCHAL_HAVE_MAC16
617 		     "mac16 "
618 #endif
619 #if XCHAL_HAVE_MUL16
620 		     "mul16 "
621 #endif
622 #if XCHAL_HAVE_MUL32
623 		     "mul32 "
624 #endif
625 #if XCHAL_HAVE_MUL32_HIGH
626 		     "mul32h "
627 #endif
628 #if XCHAL_HAVE_FP
629 		     "fpu "
630 #endif
631 #if XCHAL_HAVE_S32C1I
632 		     "s32c1i "
633 #endif
634 		     "\n");
635 
636 	/* Registers. */
637 	seq_printf(f,"physical aregs\t: %d\n"
638 		     "misc regs\t: %d\n"
639 		     "ibreak\t\t: %d\n"
640 		     "dbreak\t\t: %d\n",
641 		     XCHAL_NUM_AREGS,
642 		     XCHAL_NUM_MISC_REGS,
643 		     XCHAL_NUM_IBREAK,
644 		     XCHAL_NUM_DBREAK);
645 
646 
647 	/* Interrupt. */
648 	seq_printf(f,"num ints\t: %d\n"
649 		     "ext ints\t: %d\n"
650 		     "int levels\t: %d\n"
651 		     "timers\t\t: %d\n"
652 		     "debug level\t: %d\n",
653 		     XCHAL_NUM_INTERRUPTS,
654 		     XCHAL_NUM_EXTINTERRUPTS,
655 		     XCHAL_NUM_INTLEVELS,
656 		     XCHAL_NUM_TIMERS,
657 		     XCHAL_DEBUGLEVEL);
658 
659 	/* Cache */
660 	seq_printf(f,"icache line size: %d\n"
661 		     "icache ways\t: %d\n"
662 		     "icache size\t: %d\n"
663 		     "icache flags\t: "
664 #if XCHAL_ICACHE_LINE_LOCKABLE
665 		     "lock "
666 #endif
667 		     "\n"
668 		     "dcache line size: %d\n"
669 		     "dcache ways\t: %d\n"
670 		     "dcache size\t: %d\n"
671 		     "dcache flags\t: "
672 #if XCHAL_DCACHE_IS_WRITEBACK
673 		     "writeback "
674 #endif
675 #if XCHAL_DCACHE_LINE_LOCKABLE
676 		     "lock "
677 #endif
678 		     "\n",
679 		     XCHAL_ICACHE_LINESIZE,
680 		     XCHAL_ICACHE_WAYS,
681 		     XCHAL_ICACHE_SIZE,
682 		     XCHAL_DCACHE_LINESIZE,
683 		     XCHAL_DCACHE_WAYS,
684 		     XCHAL_DCACHE_SIZE);
685 
686 	return 0;
687 }
688 
689 /*
690  * We show only CPU #0 info.
691  */
692 static void *
693 c_start(struct seq_file *f, loff_t *pos)
694 {
695 	return (*pos == 0) ? (void *)1 : NULL;
696 }
697 
698 static void *
699 c_next(struct seq_file *f, void *v, loff_t *pos)
700 {
701 	return NULL;
702 }
703 
704 static void
705 c_stop(struct seq_file *f, void *v)
706 {
707 }
708 
709 const struct seq_operations cpuinfo_op =
710 {
711 	.start	= c_start,
712 	.next	= c_next,
713 	.stop	= c_stop,
714 	.show	= c_show,
715 };
716 
717 #endif /* CONFIG_PROC_FS */
718