xref: /openbmc/linux/arch/x86/platform/intel-mid/pwr.c (revision 75bf465f0bc33e9b776a46d6a1b9b990f5fb7c37)
1*75a6faf6SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only
25823d089SAndy Shevchenko /*
35823d089SAndy Shevchenko  * Intel MID Power Management Unit (PWRMU) device driver
45823d089SAndy Shevchenko  *
55823d089SAndy Shevchenko  * Copyright (C) 2016, Intel Corporation
65823d089SAndy Shevchenko  *
75823d089SAndy Shevchenko  * Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
85823d089SAndy Shevchenko  *
95823d089SAndy Shevchenko  * Intel MID Power Management Unit device driver handles the South Complex PCI
105823d089SAndy Shevchenko  * devices such as GPDMA, SPI, I2C, PWM, and so on. By default PCI core
115823d089SAndy Shevchenko  * modifies bits in PMCSR register in the PCI configuration space. This is not
125823d089SAndy Shevchenko  * enough on some SoCs like Intel Tangier. In such case PCI core sets a new
135823d089SAndy Shevchenko  * power state of the device in question through a PM hook registered in struct
145823d089SAndy Shevchenko  * pci_platform_pm_ops (see drivers/pci/pci-mid.c).
155823d089SAndy Shevchenko  */
165823d089SAndy Shevchenko 
175823d089SAndy Shevchenko #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
185823d089SAndy Shevchenko 
195823d089SAndy Shevchenko #include <linux/delay.h>
205823d089SAndy Shevchenko #include <linux/errno.h>
215823d089SAndy Shevchenko #include <linux/interrupt.h>
225823d089SAndy Shevchenko #include <linux/kernel.h>
23cc3ae7b0SPaul Gortmaker #include <linux/export.h>
245823d089SAndy Shevchenko #include <linux/mutex.h>
255823d089SAndy Shevchenko #include <linux/pci.h>
265823d089SAndy Shevchenko 
275823d089SAndy Shevchenko #include <asm/intel-mid.h>
285823d089SAndy Shevchenko 
295823d089SAndy Shevchenko /* Registers */
305823d089SAndy Shevchenko #define PM_STS			0x00
315823d089SAndy Shevchenko #define PM_CMD			0x04
325823d089SAndy Shevchenko #define PM_ICS			0x08
335823d089SAndy Shevchenko #define PM_WKC(x)		(0x10 + (x) * 4)
345823d089SAndy Shevchenko #define PM_WKS(x)		(0x18 + (x) * 4)
355823d089SAndy Shevchenko #define PM_SSC(x)		(0x20 + (x) * 4)
365823d089SAndy Shevchenko #define PM_SSS(x)		(0x30 + (x) * 4)
375823d089SAndy Shevchenko 
385823d089SAndy Shevchenko /* Bits in PM_STS */
395823d089SAndy Shevchenko #define PM_STS_BUSY		(1 << 8)
405823d089SAndy Shevchenko 
415823d089SAndy Shevchenko /* Bits in PM_CMD */
425823d089SAndy Shevchenko #define PM_CMD_CMD(x)		((x) << 0)
435823d089SAndy Shevchenko #define PM_CMD_IOC		(1 << 8)
4470b5b18fSAndy Shevchenko #define PM_CMD_CM_NOP		(0 << 9)
4570b5b18fSAndy Shevchenko #define PM_CMD_CM_IMMEDIATE	(1 << 9)
4670b5b18fSAndy Shevchenko #define PM_CMD_CM_DELAY		(2 << 9)
4770b5b18fSAndy Shevchenko #define PM_CMD_CM_TRIGGER	(3 << 9)
48bda7b072SAndy Shevchenko 
49bda7b072SAndy Shevchenko /* System states */
50bda7b072SAndy Shevchenko #define PM_CMD_SYS_STATE_S5	(5 << 16)
51bda7b072SAndy Shevchenko 
52bda7b072SAndy Shevchenko /* Trigger variants */
53bda7b072SAndy Shevchenko #define PM_CMD_CFG_TRIGGER_NC	(3 << 19)
54bda7b072SAndy Shevchenko 
55bda7b072SAndy Shevchenko /* Message to wait for TRIGGER_NC case */
56bda7b072SAndy Shevchenko #define TRIGGER_NC_MSG_2	(2 << 22)
575823d089SAndy Shevchenko 
585823d089SAndy Shevchenko /* List of commands */
595823d089SAndy Shevchenko #define CMD_SET_CFG		0x01
605823d089SAndy Shevchenko 
615823d089SAndy Shevchenko /* Bits in PM_ICS */
625823d089SAndy Shevchenko #define PM_ICS_INT_STATUS(x)	((x) & 0xff)
635823d089SAndy Shevchenko #define PM_ICS_IE		(1 << 8)
645823d089SAndy Shevchenko #define PM_ICS_IP		(1 << 9)
655823d089SAndy Shevchenko #define PM_ICS_SW_INT_STS	(1 << 10)
665823d089SAndy Shevchenko 
675823d089SAndy Shevchenko /* List of interrupts */
685823d089SAndy Shevchenko #define INT_INVALID		0
695823d089SAndy Shevchenko #define INT_CMD_COMPLETE	1
705823d089SAndy Shevchenko #define INT_CMD_ERR		2
715823d089SAndy Shevchenko #define INT_WAKE_EVENT		3
725823d089SAndy Shevchenko #define INT_LSS_POWER_ERR	4
735823d089SAndy Shevchenko #define INT_S0iX_MSG_ERR	5
745823d089SAndy Shevchenko #define INT_NO_C6		6
755823d089SAndy Shevchenko #define INT_TRIGGER_ERR		7
765823d089SAndy Shevchenko #define INT_INACTIVITY		8
775823d089SAndy Shevchenko 
785823d089SAndy Shevchenko /* South Complex devices */
795823d089SAndy Shevchenko #define LSS_MAX_SHARED_DEVS	4
805823d089SAndy Shevchenko #define LSS_MAX_DEVS		64
815823d089SAndy Shevchenko 
825823d089SAndy Shevchenko #define LSS_WS_BITS		1	/* wake state width */
835823d089SAndy Shevchenko #define LSS_PWS_BITS		2	/* power state width */
845823d089SAndy Shevchenko 
855823d089SAndy Shevchenko /* Supported device IDs */
86ca22312dSAndy Shevchenko #define PCI_DEVICE_ID_PENWELL	0x0828
875823d089SAndy Shevchenko #define PCI_DEVICE_ID_TANGIER	0x11a1
885823d089SAndy Shevchenko 
895823d089SAndy Shevchenko struct mid_pwr_dev {
905823d089SAndy Shevchenko 	struct pci_dev *pdev;
915823d089SAndy Shevchenko 	pci_power_t state;
925823d089SAndy Shevchenko };
935823d089SAndy Shevchenko 
945823d089SAndy Shevchenko struct mid_pwr {
955823d089SAndy Shevchenko 	struct device *dev;
965823d089SAndy Shevchenko 	void __iomem *regs;
975823d089SAndy Shevchenko 	int irq;
985823d089SAndy Shevchenko 	bool available;
995823d089SAndy Shevchenko 
1005823d089SAndy Shevchenko 	struct mutex lock;
1015823d089SAndy Shevchenko 	struct mid_pwr_dev lss[LSS_MAX_DEVS][LSS_MAX_SHARED_DEVS];
1025823d089SAndy Shevchenko };
1035823d089SAndy Shevchenko 
1045823d089SAndy Shevchenko static struct mid_pwr *midpwr;
1055823d089SAndy Shevchenko 
mid_pwr_get_state(struct mid_pwr * pwr,int reg)1065823d089SAndy Shevchenko static u32 mid_pwr_get_state(struct mid_pwr *pwr, int reg)
1075823d089SAndy Shevchenko {
1085823d089SAndy Shevchenko 	return readl(pwr->regs + PM_SSS(reg));
1095823d089SAndy Shevchenko }
1105823d089SAndy Shevchenko 
mid_pwr_set_state(struct mid_pwr * pwr,int reg,u32 value)1115823d089SAndy Shevchenko static void mid_pwr_set_state(struct mid_pwr *pwr, int reg, u32 value)
1125823d089SAndy Shevchenko {
1135823d089SAndy Shevchenko 	writel(value, pwr->regs + PM_SSC(reg));
1145823d089SAndy Shevchenko }
1155823d089SAndy Shevchenko 
mid_pwr_set_wake(struct mid_pwr * pwr,int reg,u32 value)1165823d089SAndy Shevchenko static void mid_pwr_set_wake(struct mid_pwr *pwr, int reg, u32 value)
1175823d089SAndy Shevchenko {
1185823d089SAndy Shevchenko 	writel(value, pwr->regs + PM_WKC(reg));
1195823d089SAndy Shevchenko }
1205823d089SAndy Shevchenko 
mid_pwr_interrupt_disable(struct mid_pwr * pwr)1215823d089SAndy Shevchenko static void mid_pwr_interrupt_disable(struct mid_pwr *pwr)
1225823d089SAndy Shevchenko {
1235823d089SAndy Shevchenko 	writel(~PM_ICS_IE, pwr->regs + PM_ICS);
1245823d089SAndy Shevchenko }
1255823d089SAndy Shevchenko 
mid_pwr_is_busy(struct mid_pwr * pwr)1265823d089SAndy Shevchenko static bool mid_pwr_is_busy(struct mid_pwr *pwr)
1275823d089SAndy Shevchenko {
1285823d089SAndy Shevchenko 	return !!(readl(pwr->regs + PM_STS) & PM_STS_BUSY);
1295823d089SAndy Shevchenko }
1305823d089SAndy Shevchenko 
1315823d089SAndy Shevchenko /* Wait 500ms that the latest PWRMU command finished */
mid_pwr_wait(struct mid_pwr * pwr)1325823d089SAndy Shevchenko static int mid_pwr_wait(struct mid_pwr *pwr)
1335823d089SAndy Shevchenko {
1345823d089SAndy Shevchenko 	unsigned int count = 500000;
1355823d089SAndy Shevchenko 	bool busy;
1365823d089SAndy Shevchenko 
1375823d089SAndy Shevchenko 	do {
1385823d089SAndy Shevchenko 		busy = mid_pwr_is_busy(pwr);
1395823d089SAndy Shevchenko 		if (!busy)
1405823d089SAndy Shevchenko 			return 0;
1415823d089SAndy Shevchenko 		udelay(1);
1425823d089SAndy Shevchenko 	} while (--count);
1435823d089SAndy Shevchenko 
1445823d089SAndy Shevchenko 	return -EBUSY;
1455823d089SAndy Shevchenko }
1465823d089SAndy Shevchenko 
mid_pwr_wait_for_cmd(struct mid_pwr * pwr,u8 cmd)1475823d089SAndy Shevchenko static int mid_pwr_wait_for_cmd(struct mid_pwr *pwr, u8 cmd)
1485823d089SAndy Shevchenko {
14970b5b18fSAndy Shevchenko 	writel(PM_CMD_CMD(cmd) | PM_CMD_CM_IMMEDIATE, pwr->regs + PM_CMD);
1505823d089SAndy Shevchenko 	return mid_pwr_wait(pwr);
1515823d089SAndy Shevchenko }
1525823d089SAndy Shevchenko 
__update_power_state(struct mid_pwr * pwr,int reg,int bit,int new)1535823d089SAndy Shevchenko static int __update_power_state(struct mid_pwr *pwr, int reg, int bit, int new)
1545823d089SAndy Shevchenko {
1555823d089SAndy Shevchenko 	int curstate;
1565823d089SAndy Shevchenko 	u32 power;
1575823d089SAndy Shevchenko 	int ret;
1585823d089SAndy Shevchenko 
1595823d089SAndy Shevchenko 	/* Check if the device is already in desired state */
1605823d089SAndy Shevchenko 	power = mid_pwr_get_state(pwr, reg);
1615823d089SAndy Shevchenko 	curstate = (power >> bit) & 3;
1625823d089SAndy Shevchenko 	if (curstate == new)
1635823d089SAndy Shevchenko 		return 0;
1645823d089SAndy Shevchenko 
1655823d089SAndy Shevchenko 	/* Update the power state */
1665823d089SAndy Shevchenko 	mid_pwr_set_state(pwr, reg, (power & ~(3 << bit)) | (new << bit));
1675823d089SAndy Shevchenko 
1685823d089SAndy Shevchenko 	/* Send command to SCU */
1695823d089SAndy Shevchenko 	ret = mid_pwr_wait_for_cmd(pwr, CMD_SET_CFG);
1705823d089SAndy Shevchenko 	if (ret)
1715823d089SAndy Shevchenko 		return ret;
1725823d089SAndy Shevchenko 
1735823d089SAndy Shevchenko 	/* Check if the device is already in desired state */
1745823d089SAndy Shevchenko 	power = mid_pwr_get_state(pwr, reg);
1755823d089SAndy Shevchenko 	curstate = (power >> bit) & 3;
1765823d089SAndy Shevchenko 	if (curstate != new)
1775823d089SAndy Shevchenko 		return -EAGAIN;
1785823d089SAndy Shevchenko 
1795823d089SAndy Shevchenko 	return 0;
1805823d089SAndy Shevchenko }
1815823d089SAndy Shevchenko 
__find_weakest_power_state(struct mid_pwr_dev * lss,struct pci_dev * pdev,pci_power_t state)1825823d089SAndy Shevchenko static pci_power_t __find_weakest_power_state(struct mid_pwr_dev *lss,
1835823d089SAndy Shevchenko 					      struct pci_dev *pdev,
1845823d089SAndy Shevchenko 					      pci_power_t state)
1855823d089SAndy Shevchenko {
1865823d089SAndy Shevchenko 	pci_power_t weakest = PCI_D3hot;
1875823d089SAndy Shevchenko 	unsigned int j;
1885823d089SAndy Shevchenko 
1895823d089SAndy Shevchenko 	/* Find device in cache or first free cell */
1905823d089SAndy Shevchenko 	for (j = 0; j < LSS_MAX_SHARED_DEVS; j++) {
1915823d089SAndy Shevchenko 		if (lss[j].pdev == pdev || !lss[j].pdev)
1925823d089SAndy Shevchenko 			break;
1935823d089SAndy Shevchenko 	}
1945823d089SAndy Shevchenko 
1955823d089SAndy Shevchenko 	/* Store the desired state in cache */
1965823d089SAndy Shevchenko 	if (j < LSS_MAX_SHARED_DEVS) {
1975823d089SAndy Shevchenko 		lss[j].pdev = pdev;
1985823d089SAndy Shevchenko 		lss[j].state = state;
1995823d089SAndy Shevchenko 	} else {
2005823d089SAndy Shevchenko 		dev_WARN(&pdev->dev, "No room for device in PWRMU LSS cache\n");
2015823d089SAndy Shevchenko 		weakest = state;
2025823d089SAndy Shevchenko 	}
2035823d089SAndy Shevchenko 
2045823d089SAndy Shevchenko 	/* Find the power state we may use */
2055823d089SAndy Shevchenko 	for (j = 0; j < LSS_MAX_SHARED_DEVS; j++) {
2065823d089SAndy Shevchenko 		if (lss[j].state < weakest)
2075823d089SAndy Shevchenko 			weakest = lss[j].state;
2085823d089SAndy Shevchenko 	}
2095823d089SAndy Shevchenko 
2105823d089SAndy Shevchenko 	return weakest;
2115823d089SAndy Shevchenko }
2125823d089SAndy Shevchenko 
__set_power_state(struct mid_pwr * pwr,struct pci_dev * pdev,pci_power_t state,int id,int reg,int bit)2135823d089SAndy Shevchenko static int __set_power_state(struct mid_pwr *pwr, struct pci_dev *pdev,
2145823d089SAndy Shevchenko 			     pci_power_t state, int id, int reg, int bit)
2155823d089SAndy Shevchenko {
2165823d089SAndy Shevchenko 	const char *name;
2175823d089SAndy Shevchenko 	int ret;
2185823d089SAndy Shevchenko 
2195823d089SAndy Shevchenko 	state = __find_weakest_power_state(pwr->lss[id], pdev, state);
2205823d089SAndy Shevchenko 	name = pci_power_name(state);
2215823d089SAndy Shevchenko 
2225823d089SAndy Shevchenko 	ret = __update_power_state(pwr, reg, bit, (__force int)state);
2235823d089SAndy Shevchenko 	if (ret) {
2245823d089SAndy Shevchenko 		dev_warn(&pdev->dev, "Can't set power state %s: %d\n", name, ret);
2255823d089SAndy Shevchenko 		return ret;
2265823d089SAndy Shevchenko 	}
2275823d089SAndy Shevchenko 
2285823d089SAndy Shevchenko 	dev_vdbg(&pdev->dev, "Set power state %s\n", name);
2295823d089SAndy Shevchenko 	return 0;
2305823d089SAndy Shevchenko }
2315823d089SAndy Shevchenko 
mid_pwr_set_power_state(struct mid_pwr * pwr,struct pci_dev * pdev,pci_power_t state)2325823d089SAndy Shevchenko static int mid_pwr_set_power_state(struct mid_pwr *pwr, struct pci_dev *pdev,
2335823d089SAndy Shevchenko 				   pci_power_t state)
2345823d089SAndy Shevchenko {
2355823d089SAndy Shevchenko 	int id, reg, bit;
2365823d089SAndy Shevchenko 	int ret;
2375823d089SAndy Shevchenko 
2385823d089SAndy Shevchenko 	id = intel_mid_pwr_get_lss_id(pdev);
2395823d089SAndy Shevchenko 	if (id < 0)
2405823d089SAndy Shevchenko 		return id;
2415823d089SAndy Shevchenko 
2425823d089SAndy Shevchenko 	reg = (id * LSS_PWS_BITS) / 32;
2435823d089SAndy Shevchenko 	bit = (id * LSS_PWS_BITS) % 32;
2445823d089SAndy Shevchenko 
2455823d089SAndy Shevchenko 	/* We support states between PCI_D0 and PCI_D3hot */
2465823d089SAndy Shevchenko 	if (state < PCI_D0)
2475823d089SAndy Shevchenko 		state = PCI_D0;
2485823d089SAndy Shevchenko 	if (state > PCI_D3hot)
2495823d089SAndy Shevchenko 		state = PCI_D3hot;
2505823d089SAndy Shevchenko 
2515823d089SAndy Shevchenko 	mutex_lock(&pwr->lock);
2525823d089SAndy Shevchenko 	ret = __set_power_state(pwr, pdev, state, id, reg, bit);
2535823d089SAndy Shevchenko 	mutex_unlock(&pwr->lock);
2545823d089SAndy Shevchenko 	return ret;
2555823d089SAndy Shevchenko }
2565823d089SAndy Shevchenko 
intel_mid_pci_set_power_state(struct pci_dev * pdev,pci_power_t state)2575823d089SAndy Shevchenko int intel_mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state)
2585823d089SAndy Shevchenko {
2595823d089SAndy Shevchenko 	struct mid_pwr *pwr = midpwr;
2605823d089SAndy Shevchenko 	int ret = 0;
2615823d089SAndy Shevchenko 
2625823d089SAndy Shevchenko 	might_sleep();
2635823d089SAndy Shevchenko 
2645823d089SAndy Shevchenko 	if (pwr && pwr->available)
2655823d089SAndy Shevchenko 		ret = mid_pwr_set_power_state(pwr, pdev, state);
2665823d089SAndy Shevchenko 	dev_vdbg(&pdev->dev, "set_power_state() returns %d\n", ret);
2675823d089SAndy Shevchenko 
2685823d089SAndy Shevchenko 	return 0;
2695823d089SAndy Shevchenko }
2705823d089SAndy Shevchenko 
intel_mid_pci_get_power_state(struct pci_dev * pdev)271e8a6123eSLukas Wunner pci_power_t intel_mid_pci_get_power_state(struct pci_dev *pdev)
272e8a6123eSLukas Wunner {
273e8a6123eSLukas Wunner 	struct mid_pwr *pwr = midpwr;
274e8a6123eSLukas Wunner 	int id, reg, bit;
275e8a6123eSLukas Wunner 	u32 power;
276e8a6123eSLukas Wunner 
277e8a6123eSLukas Wunner 	if (!pwr || !pwr->available)
278e8a6123eSLukas Wunner 		return PCI_UNKNOWN;
279e8a6123eSLukas Wunner 
280e8a6123eSLukas Wunner 	id = intel_mid_pwr_get_lss_id(pdev);
281e8a6123eSLukas Wunner 	if (id < 0)
282e8a6123eSLukas Wunner 		return PCI_UNKNOWN;
283e8a6123eSLukas Wunner 
284e8a6123eSLukas Wunner 	reg = (id * LSS_PWS_BITS) / 32;
285e8a6123eSLukas Wunner 	bit = (id * LSS_PWS_BITS) % 32;
286e8a6123eSLukas Wunner 	power = mid_pwr_get_state(pwr, reg);
287e8a6123eSLukas Wunner 	return (__force pci_power_t)((power >> bit) & 3);
288e8a6123eSLukas Wunner }
289e8a6123eSLukas Wunner 
intel_mid_pwr_power_off(void)290bda7b072SAndy Shevchenko void intel_mid_pwr_power_off(void)
291bda7b072SAndy Shevchenko {
292bda7b072SAndy Shevchenko 	struct mid_pwr *pwr = midpwr;
293bda7b072SAndy Shevchenko 	u32 cmd = PM_CMD_SYS_STATE_S5 |
294bda7b072SAndy Shevchenko 		  PM_CMD_CMD(CMD_SET_CFG) |
295bda7b072SAndy Shevchenko 		  PM_CMD_CM_TRIGGER |
296bda7b072SAndy Shevchenko 		  PM_CMD_CFG_TRIGGER_NC |
297bda7b072SAndy Shevchenko 		  TRIGGER_NC_MSG_2;
298bda7b072SAndy Shevchenko 
299bda7b072SAndy Shevchenko 	/* Send command to SCU */
300bda7b072SAndy Shevchenko 	writel(cmd, pwr->regs + PM_CMD);
301bda7b072SAndy Shevchenko 	mid_pwr_wait(pwr);
302bda7b072SAndy Shevchenko }
303bda7b072SAndy Shevchenko 
intel_mid_pwr_get_lss_id(struct pci_dev * pdev)3045823d089SAndy Shevchenko int intel_mid_pwr_get_lss_id(struct pci_dev *pdev)
3055823d089SAndy Shevchenko {
3065823d089SAndy Shevchenko 	int vndr;
3075823d089SAndy Shevchenko 	u8 id;
3085823d089SAndy Shevchenko 
3095823d089SAndy Shevchenko 	/*
3105823d089SAndy Shevchenko 	 * Mapping to PWRMU index is kept in the Logical SubSystem ID byte of
3115823d089SAndy Shevchenko 	 * Vendor capability.
3125823d089SAndy Shevchenko 	 */
3135823d089SAndy Shevchenko 	vndr = pci_find_capability(pdev, PCI_CAP_ID_VNDR);
3145823d089SAndy Shevchenko 	if (!vndr)
3155823d089SAndy Shevchenko 		return -EINVAL;
3165823d089SAndy Shevchenko 
3175823d089SAndy Shevchenko 	/* Read the Logical SubSystem ID byte */
3185823d089SAndy Shevchenko 	pci_read_config_byte(pdev, vndr + INTEL_MID_PWR_LSS_OFFSET, &id);
3195823d089SAndy Shevchenko 	if (!(id & INTEL_MID_PWR_LSS_TYPE))
3205823d089SAndy Shevchenko 		return -ENODEV;
3215823d089SAndy Shevchenko 
3225823d089SAndy Shevchenko 	id &= ~INTEL_MID_PWR_LSS_TYPE;
3235823d089SAndy Shevchenko 	if (id >= LSS_MAX_DEVS)
3245823d089SAndy Shevchenko 		return -ERANGE;
3255823d089SAndy Shevchenko 
3265823d089SAndy Shevchenko 	return id;
3275823d089SAndy Shevchenko }
3285823d089SAndy Shevchenko 
mid_pwr_irq_handler(int irq,void * dev_id)3295823d089SAndy Shevchenko static irqreturn_t mid_pwr_irq_handler(int irq, void *dev_id)
3305823d089SAndy Shevchenko {
3315823d089SAndy Shevchenko 	struct mid_pwr *pwr = dev_id;
3325823d089SAndy Shevchenko 	u32 ics;
3335823d089SAndy Shevchenko 
3345823d089SAndy Shevchenko 	ics = readl(pwr->regs + PM_ICS);
3355823d089SAndy Shevchenko 	if (!(ics & PM_ICS_IP))
3365823d089SAndy Shevchenko 		return IRQ_NONE;
3375823d089SAndy Shevchenko 
3385823d089SAndy Shevchenko 	writel(ics | PM_ICS_IP, pwr->regs + PM_ICS);
3395823d089SAndy Shevchenko 
3405823d089SAndy Shevchenko 	dev_warn(pwr->dev, "Unexpected IRQ: %#x\n", PM_ICS_INT_STATUS(ics));
3415823d089SAndy Shevchenko 	return IRQ_HANDLED;
3425823d089SAndy Shevchenko }
3435823d089SAndy Shevchenko 
3445823d089SAndy Shevchenko struct mid_pwr_device_info {
3455823d089SAndy Shevchenko 	int (*set_initial_state)(struct mid_pwr *pwr);
3465823d089SAndy Shevchenko };
3475823d089SAndy Shevchenko 
mid_pwr_probe(struct pci_dev * pdev,const struct pci_device_id * id)3485823d089SAndy Shevchenko static int mid_pwr_probe(struct pci_dev *pdev, const struct pci_device_id *id)
3495823d089SAndy Shevchenko {
3505823d089SAndy Shevchenko 	struct mid_pwr_device_info *info = (void *)id->driver_data;
3515823d089SAndy Shevchenko 	struct device *dev = &pdev->dev;
3525823d089SAndy Shevchenko 	struct mid_pwr *pwr;
3535823d089SAndy Shevchenko 	int ret;
3545823d089SAndy Shevchenko 
3555823d089SAndy Shevchenko 	ret = pcim_enable_device(pdev);
3565823d089SAndy Shevchenko 	if (ret < 0) {
3575823d089SAndy Shevchenko 		dev_err(&pdev->dev, "error: could not enable device\n");
3585823d089SAndy Shevchenko 		return ret;
3595823d089SAndy Shevchenko 	}
3605823d089SAndy Shevchenko 
3615823d089SAndy Shevchenko 	ret = pcim_iomap_regions(pdev, 1 << 0, pci_name(pdev));
3625823d089SAndy Shevchenko 	if (ret) {
3635823d089SAndy Shevchenko 		dev_err(&pdev->dev, "I/O memory remapping failed\n");
3645823d089SAndy Shevchenko 		return ret;
3655823d089SAndy Shevchenko 	}
3665823d089SAndy Shevchenko 
3675823d089SAndy Shevchenko 	pwr = devm_kzalloc(dev, sizeof(*pwr), GFP_KERNEL);
3685823d089SAndy Shevchenko 	if (!pwr)
3695823d089SAndy Shevchenko 		return -ENOMEM;
3705823d089SAndy Shevchenko 
3715823d089SAndy Shevchenko 	pwr->dev = dev;
3725823d089SAndy Shevchenko 	pwr->regs = pcim_iomap_table(pdev)[0];
3735823d089SAndy Shevchenko 	pwr->irq = pdev->irq;
3745823d089SAndy Shevchenko 
3755823d089SAndy Shevchenko 	mutex_init(&pwr->lock);
3765823d089SAndy Shevchenko 
3775823d089SAndy Shevchenko 	/* Disable interrupts */
3785823d089SAndy Shevchenko 	mid_pwr_interrupt_disable(pwr);
3795823d089SAndy Shevchenko 
3805823d089SAndy Shevchenko 	if (info && info->set_initial_state) {
3815823d089SAndy Shevchenko 		ret = info->set_initial_state(pwr);
3825823d089SAndy Shevchenko 		if (ret)
3835823d089SAndy Shevchenko 			dev_warn(dev, "Can't set initial state: %d\n", ret);
3845823d089SAndy Shevchenko 	}
3855823d089SAndy Shevchenko 
3865823d089SAndy Shevchenko 	ret = devm_request_irq(dev, pdev->irq, mid_pwr_irq_handler,
3875823d089SAndy Shevchenko 			       IRQF_NO_SUSPEND, pci_name(pdev), pwr);
3885823d089SAndy Shevchenko 	if (ret)
3895823d089SAndy Shevchenko 		return ret;
3905823d089SAndy Shevchenko 
3915823d089SAndy Shevchenko 	pwr->available = true;
3925823d089SAndy Shevchenko 	midpwr = pwr;
3935823d089SAndy Shevchenko 
3945823d089SAndy Shevchenko 	pci_set_drvdata(pdev, pwr);
3955823d089SAndy Shevchenko 	return 0;
3965823d089SAndy Shevchenko }
3975823d089SAndy Shevchenko 
mid_set_initial_state(struct mid_pwr * pwr,const u32 * states)398f43ea76cSAndy Shevchenko static int mid_set_initial_state(struct mid_pwr *pwr, const u32 *states)
3995823d089SAndy Shevchenko {
4005823d089SAndy Shevchenko 	unsigned int i, j;
4015823d089SAndy Shevchenko 	int ret;
4025823d089SAndy Shevchenko 
4035823d089SAndy Shevchenko 	/*
4045823d089SAndy Shevchenko 	 * Enable wake events.
4055823d089SAndy Shevchenko 	 *
4065823d089SAndy Shevchenko 	 * PWRMU supports up to 32 sources for wake up the system. Ungate them
4075823d089SAndy Shevchenko 	 * all here.
4085823d089SAndy Shevchenko 	 */
4095823d089SAndy Shevchenko 	mid_pwr_set_wake(pwr, 0, 0xffffffff);
4105823d089SAndy Shevchenko 	mid_pwr_set_wake(pwr, 1, 0xffffffff);
4115823d089SAndy Shevchenko 
4125823d089SAndy Shevchenko 	/*
4135823d089SAndy Shevchenko 	 * Power off South Complex devices.
4145823d089SAndy Shevchenko 	 *
4155823d089SAndy Shevchenko 	 * There is a map (see a note below) of 64 devices with 2 bits per each
4165823d089SAndy Shevchenko 	 * on 32-bit HW registers. The following calls set all devices to one
4175823d089SAndy Shevchenko 	 * known initial state, i.e. PCI_D3hot. This is done in conjunction
4185823d089SAndy Shevchenko 	 * with PMCSR setting in arch/x86/pci/intel_mid_pci.c.
4195823d089SAndy Shevchenko 	 *
4205823d089SAndy Shevchenko 	 * NOTE: The actual device mapping is provided by a platform at run
4215823d089SAndy Shevchenko 	 * time using vendor capability of PCI configuration space.
4225823d089SAndy Shevchenko 	 */
423f43ea76cSAndy Shevchenko 	mid_pwr_set_state(pwr, 0, states[0]);
424f43ea76cSAndy Shevchenko 	mid_pwr_set_state(pwr, 1, states[1]);
425f43ea76cSAndy Shevchenko 	mid_pwr_set_state(pwr, 2, states[2]);
426f43ea76cSAndy Shevchenko 	mid_pwr_set_state(pwr, 3, states[3]);
4275823d089SAndy Shevchenko 
4285823d089SAndy Shevchenko 	/* Send command to SCU */
4295823d089SAndy Shevchenko 	ret = mid_pwr_wait_for_cmd(pwr, CMD_SET_CFG);
4305823d089SAndy Shevchenko 	if (ret)
4315823d089SAndy Shevchenko 		return ret;
4325823d089SAndy Shevchenko 
4335823d089SAndy Shevchenko 	for (i = 0; i < LSS_MAX_DEVS; i++) {
4345823d089SAndy Shevchenko 		for (j = 0; j < LSS_MAX_SHARED_DEVS; j++)
4355823d089SAndy Shevchenko 			pwr->lss[i][j].state = PCI_D3hot;
4365823d089SAndy Shevchenko 	}
4375823d089SAndy Shevchenko 
4385823d089SAndy Shevchenko 	return 0;
4395823d089SAndy Shevchenko }
4405823d089SAndy Shevchenko 
pnw_set_initial_state(struct mid_pwr * pwr)441f43ea76cSAndy Shevchenko static int pnw_set_initial_state(struct mid_pwr *pwr)
442f43ea76cSAndy Shevchenko {
443f43ea76cSAndy Shevchenko 	/* On Penwell SRAM must stay powered on */
4443308376aSColin Ian King 	static const u32 states[] = {
445f43ea76cSAndy Shevchenko 		0xf00fffff,		/* PM_SSC(0) */
446f43ea76cSAndy Shevchenko 		0xffffffff,		/* PM_SSC(1) */
447f43ea76cSAndy Shevchenko 		0xffffffff,		/* PM_SSC(2) */
448f43ea76cSAndy Shevchenko 		0xffffffff,		/* PM_SSC(3) */
449f43ea76cSAndy Shevchenko 	};
450f43ea76cSAndy Shevchenko 	return mid_set_initial_state(pwr, states);
451f43ea76cSAndy Shevchenko }
452f43ea76cSAndy Shevchenko 
tng_set_initial_state(struct mid_pwr * pwr)453f43ea76cSAndy Shevchenko static int tng_set_initial_state(struct mid_pwr *pwr)
454f43ea76cSAndy Shevchenko {
4553308376aSColin Ian King 	static const u32 states[] = {
456f43ea76cSAndy Shevchenko 		0xffffffff,		/* PM_SSC(0) */
457f43ea76cSAndy Shevchenko 		0xffffffff,		/* PM_SSC(1) */
458f43ea76cSAndy Shevchenko 		0xffffffff,		/* PM_SSC(2) */
459f43ea76cSAndy Shevchenko 		0xffffffff,		/* PM_SSC(3) */
460f43ea76cSAndy Shevchenko 	};
461f43ea76cSAndy Shevchenko 	return mid_set_initial_state(pwr, states);
462f43ea76cSAndy Shevchenko }
463f43ea76cSAndy Shevchenko 
464f43ea76cSAndy Shevchenko static const struct mid_pwr_device_info pnw_info = {
465f43ea76cSAndy Shevchenko 	.set_initial_state = pnw_set_initial_state,
466f43ea76cSAndy Shevchenko };
467f43ea76cSAndy Shevchenko 
468f43ea76cSAndy Shevchenko static const struct mid_pwr_device_info tng_info = {
469f43ea76cSAndy Shevchenko 	.set_initial_state = tng_set_initial_state,
4705823d089SAndy Shevchenko };
4715823d089SAndy Shevchenko 
4728e522e1dSAndy Shevchenko /* This table should be in sync with the one in drivers/pci/pci-mid.c */
4735823d089SAndy Shevchenko static const struct pci_device_id mid_pwr_pci_ids[] = {
474f43ea76cSAndy Shevchenko 	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_PENWELL), (kernel_ulong_t)&pnw_info },
475f43ea76cSAndy Shevchenko 	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_TANGIER), (kernel_ulong_t)&tng_info },
4765823d089SAndy Shevchenko 	{}
4775823d089SAndy Shevchenko };
4785823d089SAndy Shevchenko 
4795823d089SAndy Shevchenko static struct pci_driver mid_pwr_pci_driver = {
4805823d089SAndy Shevchenko 	.name		= "intel_mid_pwr",
4815823d089SAndy Shevchenko 	.probe		= mid_pwr_probe,
4825823d089SAndy Shevchenko 	.id_table	= mid_pwr_pci_ids,
4835823d089SAndy Shevchenko };
4845823d089SAndy Shevchenko 
4855823d089SAndy Shevchenko builtin_pci_driver(mid_pwr_pci_driver);
486