1 /* 2 * mmconfig-shared.c - Low-level direct PCI config space access via 3 * MMCONFIG - common code between i386 and x86-64. 4 * 5 * This code does: 6 * - known chipset handling 7 * - ACPI decoding and validation 8 * 9 * Per-architecture code takes care of the mappings and accesses 10 * themselves. 11 */ 12 13 #include <linux/pci.h> 14 #include <linux/init.h> 15 #include <linux/acpi.h> 16 #include <linux/sfi_acpi.h> 17 #include <linux/bitmap.h> 18 #include <linux/dmi.h> 19 #include <linux/sort.h> 20 #include <asm/e820.h> 21 #include <asm/pci_x86.h> 22 #include <asm/acpi.h> 23 24 #define PREFIX "PCI: " 25 26 /* Indicate if the mmcfg resources have been placed into the resource table. */ 27 static int __initdata pci_mmcfg_resources_inserted; 28 29 static __init int extend_mmcfg(int num) 30 { 31 struct acpi_mcfg_allocation *new; 32 int new_num = pci_mmcfg_config_num + num; 33 34 new = kzalloc(sizeof(pci_mmcfg_config[0]) * new_num, GFP_KERNEL); 35 if (!new) 36 return -1; 37 38 if (pci_mmcfg_config) { 39 memcpy(new, pci_mmcfg_config, 40 sizeof(pci_mmcfg_config[0]) * new_num); 41 kfree(pci_mmcfg_config); 42 } 43 pci_mmcfg_config = new; 44 45 return 0; 46 } 47 48 static __init void fill_one_mmcfg(u64 addr, int segment, int start, int end) 49 { 50 int i = pci_mmcfg_config_num; 51 52 pci_mmcfg_config_num++; 53 pci_mmcfg_config[i].address = addr; 54 pci_mmcfg_config[i].pci_segment = segment; 55 pci_mmcfg_config[i].start_bus_number = start; 56 pci_mmcfg_config[i].end_bus_number = end; 57 } 58 59 static const char __init *pci_mmcfg_e7520(void) 60 { 61 u32 win; 62 raw_pci_ops->read(0, 0, PCI_DEVFN(0, 0), 0xce, 2, &win); 63 64 win = win & 0xf000; 65 if (win == 0x0000 || win == 0xf000) 66 return NULL; 67 68 if (extend_mmcfg(1) == -1) 69 return NULL; 70 71 fill_one_mmcfg(win << 16, 0, 0, 255); 72 73 return "Intel Corporation E7520 Memory Controller Hub"; 74 } 75 76 static const char __init *pci_mmcfg_intel_945(void) 77 { 78 u32 pciexbar, mask = 0, len = 0; 79 80 raw_pci_ops->read(0, 0, PCI_DEVFN(0, 0), 0x48, 4, &pciexbar); 81 82 /* Enable bit */ 83 if (!(pciexbar & 1)) 84 return NULL; 85 86 /* Size bits */ 87 switch ((pciexbar >> 1) & 3) { 88 case 0: 89 mask = 0xf0000000U; 90 len = 0x10000000U; 91 break; 92 case 1: 93 mask = 0xf8000000U; 94 len = 0x08000000U; 95 break; 96 case 2: 97 mask = 0xfc000000U; 98 len = 0x04000000U; 99 break; 100 default: 101 return NULL; 102 } 103 104 /* Errata #2, things break when not aligned on a 256Mb boundary */ 105 /* Can only happen in 64M/128M mode */ 106 107 if ((pciexbar & mask) & 0x0fffffffU) 108 return NULL; 109 110 /* Don't hit the APIC registers and their friends */ 111 if ((pciexbar & mask) >= 0xf0000000U) 112 return NULL; 113 114 if (extend_mmcfg(1) == -1) 115 return NULL; 116 117 fill_one_mmcfg(pciexbar & mask, 0, 0, (len >> 20) - 1); 118 119 return "Intel Corporation 945G/GZ/P/PL Express Memory Controller Hub"; 120 } 121 122 static const char __init *pci_mmcfg_amd_fam10h(void) 123 { 124 u32 low, high, address; 125 u64 base, msr; 126 int i; 127 unsigned segnbits = 0, busnbits; 128 129 if (!(pci_probe & PCI_CHECK_ENABLE_AMD_MMCONF)) 130 return NULL; 131 132 address = MSR_FAM10H_MMIO_CONF_BASE; 133 if (rdmsr_safe(address, &low, &high)) 134 return NULL; 135 136 msr = high; 137 msr <<= 32; 138 msr |= low; 139 140 /* mmconfig is not enable */ 141 if (!(msr & FAM10H_MMIO_CONF_ENABLE)) 142 return NULL; 143 144 base = msr & (FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT); 145 146 busnbits = (msr >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) & 147 FAM10H_MMIO_CONF_BUSRANGE_MASK; 148 149 /* 150 * only handle bus 0 ? 151 * need to skip it 152 */ 153 if (!busnbits) 154 return NULL; 155 156 if (busnbits > 8) { 157 segnbits = busnbits - 8; 158 busnbits = 8; 159 } 160 161 if (extend_mmcfg(1 << segnbits) == -1) 162 return NULL; 163 164 for (i = 0; i < (1 << segnbits); i++) 165 fill_one_mmcfg(base + (1<<28) * i, i, 0, (1 << busnbits) - 1); 166 167 return "AMD Family 10h NB"; 168 } 169 170 static bool __initdata mcp55_checked; 171 static const char __init *pci_mmcfg_nvidia_mcp55(void) 172 { 173 int bus; 174 int mcp55_mmconf_found = 0; 175 176 static const u32 extcfg_regnum = 0x90; 177 static const u32 extcfg_regsize = 4; 178 static const u32 extcfg_enable_mask = 1<<31; 179 static const u32 extcfg_start_mask = 0xff<<16; 180 static const int extcfg_start_shift = 16; 181 static const u32 extcfg_size_mask = 0x3<<28; 182 static const int extcfg_size_shift = 28; 183 static const int extcfg_sizebus[] = {0x100, 0x80, 0x40, 0x20}; 184 static const u32 extcfg_base_mask[] = {0x7ff8, 0x7ffc, 0x7ffe, 0x7fff}; 185 static const int extcfg_base_lshift = 25; 186 187 /* 188 * do check if amd fam10h already took over 189 */ 190 if (!acpi_disabled || pci_mmcfg_config_num || mcp55_checked) 191 return NULL; 192 193 mcp55_checked = true; 194 for (bus = 0; bus < 256; bus++) { 195 u64 base; 196 u32 l, extcfg; 197 u16 vendor, device; 198 int start, size_index, end; 199 200 raw_pci_ops->read(0, bus, PCI_DEVFN(0, 0), 0, 4, &l); 201 vendor = l & 0xffff; 202 device = (l >> 16) & 0xffff; 203 204 if (PCI_VENDOR_ID_NVIDIA != vendor || 0x0369 != device) 205 continue; 206 207 raw_pci_ops->read(0, bus, PCI_DEVFN(0, 0), extcfg_regnum, 208 extcfg_regsize, &extcfg); 209 210 if (!(extcfg & extcfg_enable_mask)) 211 continue; 212 213 if (extend_mmcfg(1) == -1) 214 continue; 215 216 size_index = (extcfg & extcfg_size_mask) >> extcfg_size_shift; 217 base = extcfg & extcfg_base_mask[size_index]; 218 /* base could > 4G */ 219 base <<= extcfg_base_lshift; 220 start = (extcfg & extcfg_start_mask) >> extcfg_start_shift; 221 end = start + extcfg_sizebus[size_index] - 1; 222 fill_one_mmcfg(base, 0, start, end); 223 mcp55_mmconf_found++; 224 } 225 226 if (!mcp55_mmconf_found) 227 return NULL; 228 229 return "nVidia MCP55"; 230 } 231 232 struct pci_mmcfg_hostbridge_probe { 233 u32 bus; 234 u32 devfn; 235 u32 vendor; 236 u32 device; 237 const char *(*probe)(void); 238 }; 239 240 static struct pci_mmcfg_hostbridge_probe pci_mmcfg_probes[] __initdata = { 241 { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_INTEL, 242 PCI_DEVICE_ID_INTEL_E7520_MCH, pci_mmcfg_e7520 }, 243 { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_INTEL, 244 PCI_DEVICE_ID_INTEL_82945G_HB, pci_mmcfg_intel_945 }, 245 { 0, PCI_DEVFN(0x18, 0), PCI_VENDOR_ID_AMD, 246 0x1200, pci_mmcfg_amd_fam10h }, 247 { 0xff, PCI_DEVFN(0, 0), PCI_VENDOR_ID_AMD, 248 0x1200, pci_mmcfg_amd_fam10h }, 249 { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_NVIDIA, 250 0x0369, pci_mmcfg_nvidia_mcp55 }, 251 }; 252 253 static int __init cmp_mmcfg(const void *x1, const void *x2) 254 { 255 const typeof(pci_mmcfg_config[0]) *m1 = x1; 256 const typeof(pci_mmcfg_config[0]) *m2 = x2; 257 int start1, start2; 258 259 start1 = m1->start_bus_number; 260 start2 = m2->start_bus_number; 261 262 return start1 - start2; 263 } 264 265 static void __init pci_mmcfg_check_end_bus_number(void) 266 { 267 int i; 268 typeof(pci_mmcfg_config[0]) *cfg, *cfgx; 269 270 /* sort them at first */ 271 sort(pci_mmcfg_config, pci_mmcfg_config_num, 272 sizeof(pci_mmcfg_config[0]), cmp_mmcfg, NULL); 273 274 /* last one*/ 275 if (pci_mmcfg_config_num > 0) { 276 i = pci_mmcfg_config_num - 1; 277 cfg = &pci_mmcfg_config[i]; 278 if (cfg->end_bus_number < cfg->start_bus_number) 279 cfg->end_bus_number = 255; 280 } 281 282 /* don't overlap please */ 283 for (i = 0; i < pci_mmcfg_config_num - 1; i++) { 284 cfg = &pci_mmcfg_config[i]; 285 cfgx = &pci_mmcfg_config[i+1]; 286 287 if (cfg->end_bus_number < cfg->start_bus_number) 288 cfg->end_bus_number = 255; 289 290 if (cfg->end_bus_number >= cfgx->start_bus_number) 291 cfg->end_bus_number = cfgx->start_bus_number - 1; 292 } 293 } 294 295 static int __init pci_mmcfg_check_hostbridge(void) 296 { 297 u32 l; 298 u32 bus, devfn; 299 u16 vendor, device; 300 int i; 301 const char *name; 302 303 if (!raw_pci_ops) 304 return 0; 305 306 pci_mmcfg_config_num = 0; 307 pci_mmcfg_config = NULL; 308 309 for (i = 0; i < ARRAY_SIZE(pci_mmcfg_probes); i++) { 310 bus = pci_mmcfg_probes[i].bus; 311 devfn = pci_mmcfg_probes[i].devfn; 312 raw_pci_ops->read(0, bus, devfn, 0, 4, &l); 313 vendor = l & 0xffff; 314 device = (l >> 16) & 0xffff; 315 316 name = NULL; 317 if (pci_mmcfg_probes[i].vendor == vendor && 318 pci_mmcfg_probes[i].device == device) 319 name = pci_mmcfg_probes[i].probe(); 320 321 if (name) 322 printk(KERN_INFO "PCI: Found %s with MMCONFIG support.\n", 323 name); 324 } 325 326 /* some end_bus_number is crazy, fix it */ 327 pci_mmcfg_check_end_bus_number(); 328 329 return pci_mmcfg_config_num != 0; 330 } 331 332 static void __init pci_mmcfg_insert_resources(void) 333 { 334 #define PCI_MMCFG_RESOURCE_NAME_LEN 24 335 int i; 336 struct resource *res; 337 char *names; 338 unsigned num_buses; 339 340 res = kcalloc(PCI_MMCFG_RESOURCE_NAME_LEN + sizeof(*res), 341 pci_mmcfg_config_num, GFP_KERNEL); 342 if (!res) { 343 printk(KERN_ERR "PCI: Unable to allocate MMCONFIG resources\n"); 344 return; 345 } 346 347 names = (void *)&res[pci_mmcfg_config_num]; 348 for (i = 0; i < pci_mmcfg_config_num; i++, res++) { 349 struct acpi_mcfg_allocation *cfg = &pci_mmcfg_config[i]; 350 num_buses = cfg->end_bus_number - cfg->start_bus_number + 1; 351 res->name = names; 352 snprintf(names, PCI_MMCFG_RESOURCE_NAME_LEN, 353 "PCI MMCONFIG %u [%02x-%02x]", cfg->pci_segment, 354 cfg->start_bus_number, cfg->end_bus_number); 355 res->start = cfg->address + (cfg->start_bus_number << 20); 356 res->end = res->start + (num_buses << 20) - 1; 357 res->flags = IORESOURCE_MEM | IORESOURCE_BUSY; 358 insert_resource(&iomem_resource, res); 359 names += PCI_MMCFG_RESOURCE_NAME_LEN; 360 } 361 362 /* Mark that the resources have been inserted. */ 363 pci_mmcfg_resources_inserted = 1; 364 } 365 366 static acpi_status __init check_mcfg_resource(struct acpi_resource *res, 367 void *data) 368 { 369 struct resource *mcfg_res = data; 370 struct acpi_resource_address64 address; 371 acpi_status status; 372 373 if (res->type == ACPI_RESOURCE_TYPE_FIXED_MEMORY32) { 374 struct acpi_resource_fixed_memory32 *fixmem32 = 375 &res->data.fixed_memory32; 376 if (!fixmem32) 377 return AE_OK; 378 if ((mcfg_res->start >= fixmem32->address) && 379 (mcfg_res->end < (fixmem32->address + 380 fixmem32->address_length))) { 381 mcfg_res->flags = 1; 382 return AE_CTRL_TERMINATE; 383 } 384 } 385 if ((res->type != ACPI_RESOURCE_TYPE_ADDRESS32) && 386 (res->type != ACPI_RESOURCE_TYPE_ADDRESS64)) 387 return AE_OK; 388 389 status = acpi_resource_to_address64(res, &address); 390 if (ACPI_FAILURE(status) || 391 (address.address_length <= 0) || 392 (address.resource_type != ACPI_MEMORY_RANGE)) 393 return AE_OK; 394 395 if ((mcfg_res->start >= address.minimum) && 396 (mcfg_res->end < (address.minimum + address.address_length))) { 397 mcfg_res->flags = 1; 398 return AE_CTRL_TERMINATE; 399 } 400 return AE_OK; 401 } 402 403 static acpi_status __init find_mboard_resource(acpi_handle handle, u32 lvl, 404 void *context, void **rv) 405 { 406 struct resource *mcfg_res = context; 407 408 acpi_walk_resources(handle, METHOD_NAME__CRS, 409 check_mcfg_resource, context); 410 411 if (mcfg_res->flags) 412 return AE_CTRL_TERMINATE; 413 414 return AE_OK; 415 } 416 417 static int __init is_acpi_reserved(u64 start, u64 end, unsigned not_used) 418 { 419 struct resource mcfg_res; 420 421 mcfg_res.start = start; 422 mcfg_res.end = end - 1; 423 mcfg_res.flags = 0; 424 425 acpi_get_devices("PNP0C01", find_mboard_resource, &mcfg_res, NULL); 426 427 if (!mcfg_res.flags) 428 acpi_get_devices("PNP0C02", find_mboard_resource, &mcfg_res, 429 NULL); 430 431 return mcfg_res.flags; 432 } 433 434 typedef int (*check_reserved_t)(u64 start, u64 end, unsigned type); 435 436 static int __init is_mmconf_reserved(check_reserved_t is_reserved, 437 u64 addr, u64 size, int i, 438 typeof(pci_mmcfg_config[0]) *cfg, int with_e820) 439 { 440 u64 old_size = size; 441 int valid = 0; 442 443 while (!is_reserved(addr, addr + size, E820_RESERVED)) { 444 size >>= 1; 445 if (size < (16UL<<20)) 446 break; 447 } 448 449 if (size >= (16UL<<20) || size == old_size) { 450 printk(KERN_NOTICE 451 "PCI: MCFG area at %Lx reserved in %s\n", 452 addr, with_e820?"E820":"ACPI motherboard resources"); 453 valid = 1; 454 455 if (old_size != size) { 456 /* update end_bus_number */ 457 cfg->end_bus_number = cfg->start_bus_number + ((size>>20) - 1); 458 printk(KERN_NOTICE "PCI: updated MCFG configuration %d: base %lx " 459 "segment %hu buses %u - %u\n", 460 i, (unsigned long)cfg->address, cfg->pci_segment, 461 (unsigned int)cfg->start_bus_number, 462 (unsigned int)cfg->end_bus_number); 463 } 464 } 465 466 return valid; 467 } 468 469 static void __init pci_mmcfg_reject_broken(int early) 470 { 471 typeof(pci_mmcfg_config[0]) *cfg; 472 int i; 473 474 if ((pci_mmcfg_config_num == 0) || 475 (pci_mmcfg_config == NULL) || 476 (pci_mmcfg_config[0].address == 0)) 477 return; 478 479 for (i = 0; i < pci_mmcfg_config_num; i++) { 480 int valid = 0; 481 u64 addr, size; 482 483 cfg = &pci_mmcfg_config[i]; 484 addr = cfg->start_bus_number; 485 addr <<= 20; 486 addr += cfg->address; 487 size = cfg->end_bus_number + 1 - cfg->start_bus_number; 488 size <<= 20; 489 printk(KERN_NOTICE "PCI: MCFG configuration %d: base %lx " 490 "segment %hu buses %u - %u\n", 491 i, (unsigned long)cfg->address, cfg->pci_segment, 492 (unsigned int)cfg->start_bus_number, 493 (unsigned int)cfg->end_bus_number); 494 495 if (!early && !acpi_disabled) 496 valid = is_mmconf_reserved(is_acpi_reserved, addr, size, i, cfg, 0); 497 498 if (valid) 499 continue; 500 501 if (!early) 502 printk(KERN_ERR "PCI: BIOS Bug: MCFG area at %Lx is not" 503 " reserved in ACPI motherboard resources\n", 504 cfg->address); 505 506 /* Don't try to do this check unless configuration 507 type 1 is available. how about type 2 ?*/ 508 if (raw_pci_ops) 509 valid = is_mmconf_reserved(e820_all_mapped, addr, size, i, cfg, 1); 510 511 if (!valid) 512 goto reject; 513 } 514 515 return; 516 517 reject: 518 printk(KERN_INFO "PCI: Not using MMCONFIG.\n"); 519 pci_mmcfg_arch_free(); 520 kfree(pci_mmcfg_config); 521 pci_mmcfg_config = NULL; 522 pci_mmcfg_config_num = 0; 523 } 524 525 static int __initdata known_bridge; 526 527 /* The physical address of the MMCONFIG aperture. Set from ACPI tables. */ 528 struct acpi_mcfg_allocation *pci_mmcfg_config; 529 int pci_mmcfg_config_num; 530 531 static int __init acpi_mcfg_check_entry(struct acpi_table_mcfg *mcfg, 532 struct acpi_mcfg_allocation *cfg) 533 { 534 int year; 535 536 if (cfg->address < 0xFFFFFFFF) 537 return 0; 538 539 if (!strcmp(mcfg->header.oem_id, "SGI")) 540 return 0; 541 542 if (mcfg->header.revision >= 1) { 543 if (dmi_get_date(DMI_BIOS_DATE, &year, NULL, NULL) && 544 year >= 2010) 545 return 0; 546 } 547 548 printk(KERN_ERR PREFIX "MCFG region for %04x:%02x-%02x at %#llx " 549 "is above 4GB, ignored\n", cfg->pci_segment, 550 cfg->start_bus_number, cfg->end_bus_number, cfg->address); 551 return -EINVAL; 552 } 553 554 static int __init pci_parse_mcfg(struct acpi_table_header *header) 555 { 556 struct acpi_table_mcfg *mcfg; 557 unsigned long i; 558 int config_size; 559 560 if (!header) 561 return -EINVAL; 562 563 mcfg = (struct acpi_table_mcfg *)header; 564 565 /* how many config structures do we have */ 566 pci_mmcfg_config_num = 0; 567 i = header->length - sizeof(struct acpi_table_mcfg); 568 while (i >= sizeof(struct acpi_mcfg_allocation)) { 569 ++pci_mmcfg_config_num; 570 i -= sizeof(struct acpi_mcfg_allocation); 571 }; 572 if (pci_mmcfg_config_num == 0) { 573 printk(KERN_ERR PREFIX "MMCONFIG has no entries\n"); 574 return -ENODEV; 575 } 576 577 config_size = pci_mmcfg_config_num * sizeof(*pci_mmcfg_config); 578 pci_mmcfg_config = kmalloc(config_size, GFP_KERNEL); 579 if (!pci_mmcfg_config) { 580 printk(KERN_WARNING PREFIX 581 "No memory for MCFG config tables\n"); 582 return -ENOMEM; 583 } 584 585 memcpy(pci_mmcfg_config, &mcfg[1], config_size); 586 587 for (i = 0; i < pci_mmcfg_config_num; ++i) { 588 if (acpi_mcfg_check_entry(mcfg, &pci_mmcfg_config[i])) { 589 kfree(pci_mmcfg_config); 590 pci_mmcfg_config_num = 0; 591 return -ENODEV; 592 } 593 } 594 595 return 0; 596 } 597 598 static void __init __pci_mmcfg_init(int early) 599 { 600 /* MMCONFIG disabled */ 601 if ((pci_probe & PCI_PROBE_MMCONF) == 0) 602 return; 603 604 /* MMCONFIG already enabled */ 605 if (!early && !(pci_probe & PCI_PROBE_MASK & ~PCI_PROBE_MMCONF)) 606 return; 607 608 /* for late to exit */ 609 if (known_bridge) 610 return; 611 612 if (early) { 613 if (pci_mmcfg_check_hostbridge()) 614 known_bridge = 1; 615 } 616 617 if (!known_bridge) 618 acpi_sfi_table_parse(ACPI_SIG_MCFG, pci_parse_mcfg); 619 620 pci_mmcfg_reject_broken(early); 621 622 if ((pci_mmcfg_config_num == 0) || 623 (pci_mmcfg_config == NULL) || 624 (pci_mmcfg_config[0].address == 0)) 625 return; 626 627 if (pci_mmcfg_arch_init()) 628 pci_probe = (pci_probe & ~PCI_PROBE_MASK) | PCI_PROBE_MMCONF; 629 else { 630 /* 631 * Signal not to attempt to insert mmcfg resources because 632 * the architecture mmcfg setup could not initialize. 633 */ 634 pci_mmcfg_resources_inserted = 1; 635 } 636 } 637 638 void __init pci_mmcfg_early_init(void) 639 { 640 __pci_mmcfg_init(1); 641 } 642 643 void __init pci_mmcfg_late_init(void) 644 { 645 __pci_mmcfg_init(0); 646 } 647 648 static int __init pci_mmcfg_late_insert_resources(void) 649 { 650 /* 651 * If resources are already inserted or we are not using MMCONFIG, 652 * don't insert the resources. 653 */ 654 if ((pci_mmcfg_resources_inserted == 1) || 655 (pci_probe & PCI_PROBE_MMCONF) == 0 || 656 (pci_mmcfg_config_num == 0) || 657 (pci_mmcfg_config == NULL) || 658 (pci_mmcfg_config[0].address == 0)) 659 return 1; 660 661 /* 662 * Attempt to insert the mmcfg resources but not with the busy flag 663 * marked so it won't cause request errors when __request_region is 664 * called. 665 */ 666 pci_mmcfg_insert_resources(); 667 668 return 0; 669 } 670 671 /* 672 * Perform MMCONFIG resource insertion after PCI initialization to allow for 673 * misprogrammed MCFG tables that state larger sizes but actually conflict 674 * with other system resources. 675 */ 676 late_initcall(pci_mmcfg_late_insert_resources); 677