1 /* 2 * Low-Level PCI Access for i386 machines 3 * 4 * Copyright 1993, 1994 Drew Eckhardt 5 * Visionary Computing 6 * (Unix and Linux consulting and custom programming) 7 * Drew@Colorado.EDU 8 * +1 (303) 786-7975 9 * 10 * Drew's work was sponsored by: 11 * iX Multiuser Multitasking Magazine 12 * Hannover, Germany 13 * hm@ix.de 14 * 15 * Copyright 1997--2000 Martin Mares <mj@ucw.cz> 16 * 17 * For more information, please consult the following manuals (look at 18 * http://www.pcisig.com/ for how to get them): 19 * 20 * PCI BIOS Specification 21 * PCI Local Bus Specification 22 * PCI to PCI Bridge Specification 23 * PCI System Design Guide 24 * 25 */ 26 27 #include <linux/types.h> 28 #include <linux/kernel.h> 29 #include <linux/pci.h> 30 #include <linux/init.h> 31 #include <linux/ioport.h> 32 #include <linux/errno.h> 33 #include <linux/bootmem.h> 34 35 #include <asm/pat.h> 36 #include <asm/e820.h> 37 #include <asm/pci_x86.h> 38 #include <asm/io_apic.h> 39 40 41 static int 42 skip_isa_ioresource_align(struct pci_dev *dev) { 43 44 if ((pci_probe & PCI_CAN_SKIP_ISA_ALIGN) && 45 !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA)) 46 return 1; 47 return 0; 48 } 49 50 /* 51 * We need to avoid collisions with `mirrored' VGA ports 52 * and other strange ISA hardware, so we always want the 53 * addresses to be allocated in the 0x000-0x0ff region 54 * modulo 0x400. 55 * 56 * Why? Because some silly external IO cards only decode 57 * the low 10 bits of the IO address. The 0x00-0xff region 58 * is reserved for motherboard devices that decode all 16 59 * bits, so it's ok to allocate at, say, 0x2800-0x28ff, 60 * but we want to try to avoid allocating at 0x2900-0x2bff 61 * which might have be mirrored at 0x0100-0x03ff.. 62 */ 63 void 64 pcibios_align_resource(void *data, struct resource *res, 65 resource_size_t size, resource_size_t align) 66 { 67 struct pci_dev *dev = data; 68 69 if (res->flags & IORESOURCE_IO) { 70 resource_size_t start = res->start; 71 72 if (skip_isa_ioresource_align(dev)) 73 return; 74 if (start & 0x300) { 75 start = (start + 0x3ff) & ~0x3ff; 76 res->start = start; 77 } 78 } 79 } 80 EXPORT_SYMBOL(pcibios_align_resource); 81 82 /* 83 * Handle resources of PCI devices. If the world were perfect, we could 84 * just allocate all the resource regions and do nothing more. It isn't. 85 * On the other hand, we cannot just re-allocate all devices, as it would 86 * require us to know lots of host bridge internals. So we attempt to 87 * keep as much of the original configuration as possible, but tweak it 88 * when it's found to be wrong. 89 * 90 * Known BIOS problems we have to work around: 91 * - I/O or memory regions not configured 92 * - regions configured, but not enabled in the command register 93 * - bogus I/O addresses above 64K used 94 * - expansion ROMs left enabled (this may sound harmless, but given 95 * the fact the PCI specs explicitly allow address decoders to be 96 * shared between expansion ROMs and other resource regions, it's 97 * at least dangerous) 98 * 99 * Our solution: 100 * (1) Allocate resources for all buses behind PCI-to-PCI bridges. 101 * This gives us fixed barriers on where we can allocate. 102 * (2) Allocate resources for all enabled devices. If there is 103 * a collision, just mark the resource as unallocated. Also 104 * disable expansion ROMs during this step. 105 * (3) Try to allocate resources for disabled devices. If the 106 * resources were assigned correctly, everything goes well, 107 * if they weren't, they won't disturb allocation of other 108 * resources. 109 * (4) Assign new addresses to resources which were either 110 * not configured at all or misconfigured. If explicitly 111 * requested by the user, configure expansion ROM address 112 * as well. 113 */ 114 115 static void __init pcibios_allocate_bus_resources(struct list_head *bus_list) 116 { 117 struct pci_bus *bus; 118 struct pci_dev *dev; 119 int idx; 120 struct resource *r; 121 122 /* Depth-First Search on bus tree */ 123 list_for_each_entry(bus, bus_list, node) { 124 if ((dev = bus->self)) { 125 for (idx = PCI_BRIDGE_RESOURCES; 126 idx < PCI_NUM_RESOURCES; idx++) { 127 r = &dev->resource[idx]; 128 if (!r->flags) 129 continue; 130 if (!r->start || 131 pci_claim_resource(dev, idx) < 0) { 132 dev_info(&dev->dev, 133 "can't reserve window %pR\n", 134 r); 135 /* 136 * Something is wrong with the region. 137 * Invalidate the resource to prevent 138 * child resource allocations in this 139 * range. 140 */ 141 r->flags = 0; 142 } 143 } 144 } 145 pcibios_allocate_bus_resources(&bus->children); 146 } 147 } 148 149 struct pci_check_idx_range { 150 int start; 151 int end; 152 }; 153 154 static void __init pcibios_allocate_resources(int pass) 155 { 156 struct pci_dev *dev = NULL; 157 int idx, disabled, i; 158 u16 command; 159 struct resource *r; 160 161 struct pci_check_idx_range idx_range[] = { 162 { PCI_STD_RESOURCES, PCI_STD_RESOURCE_END }, 163 #ifdef CONFIG_PCI_IOV 164 { PCI_IOV_RESOURCES, PCI_IOV_RESOURCE_END }, 165 #endif 166 }; 167 168 for_each_pci_dev(dev) { 169 pci_read_config_word(dev, PCI_COMMAND, &command); 170 for (i = 0; i < ARRAY_SIZE(idx_range); i++) 171 for (idx = idx_range[i].start; idx <= idx_range[i].end; idx++) { 172 r = &dev->resource[idx]; 173 if (r->parent) /* Already allocated */ 174 continue; 175 if (!r->start) /* Address not assigned at all */ 176 continue; 177 if (r->flags & IORESOURCE_IO) 178 disabled = !(command & PCI_COMMAND_IO); 179 else 180 disabled = !(command & PCI_COMMAND_MEMORY); 181 if (pass == disabled) { 182 dev_dbg(&dev->dev, 183 "BAR %d: reserving %pr (d=%d, p=%d)\n", 184 idx, r, disabled, pass); 185 if (pci_claim_resource(dev, idx) < 0) { 186 dev_info(&dev->dev, 187 "can't reserve %pR\n", r); 188 /* We'll assign a new address later */ 189 r->end -= r->start; 190 r->start = 0; 191 } 192 } 193 } 194 if (!pass) { 195 r = &dev->resource[PCI_ROM_RESOURCE]; 196 if (r->flags & IORESOURCE_ROM_ENABLE) { 197 /* Turn the ROM off, leave the resource region, 198 * but keep it unregistered. */ 199 u32 reg; 200 dev_dbg(&dev->dev, "disabling ROM %pR\n", r); 201 r->flags &= ~IORESOURCE_ROM_ENABLE; 202 pci_read_config_dword(dev, 203 dev->rom_base_reg, ®); 204 pci_write_config_dword(dev, dev->rom_base_reg, 205 reg & ~PCI_ROM_ADDRESS_ENABLE); 206 } 207 } 208 } 209 } 210 211 static int __init pcibios_assign_resources(void) 212 { 213 struct pci_dev *dev = NULL; 214 struct resource *r; 215 216 if (!(pci_probe & PCI_ASSIGN_ROMS)) { 217 /* 218 * Try to use BIOS settings for ROMs, otherwise let 219 * pci_assign_unassigned_resources() allocate the new 220 * addresses. 221 */ 222 for_each_pci_dev(dev) { 223 r = &dev->resource[PCI_ROM_RESOURCE]; 224 if (!r->flags || !r->start) 225 continue; 226 if (pci_claim_resource(dev, PCI_ROM_RESOURCE) < 0) { 227 r->end -= r->start; 228 r->start = 0; 229 } 230 } 231 } 232 233 pci_assign_unassigned_resources(); 234 235 return 0; 236 } 237 238 void __init pcibios_resource_survey(void) 239 { 240 DBG("PCI: Allocating resources\n"); 241 pcibios_allocate_bus_resources(&pci_root_buses); 242 pcibios_allocate_resources(0); 243 pcibios_allocate_resources(1); 244 245 e820_reserve_resources_late(); 246 /* 247 * Insert the IO APIC resources after PCI initialization has 248 * occured to handle IO APICS that are mapped in on a BAR in 249 * PCI space, but before trying to assign unassigned pci res. 250 */ 251 ioapic_insert_resources(); 252 } 253 254 /** 255 * called in fs_initcall (one below subsys_initcall), 256 * give a chance for motherboard reserve resources 257 */ 258 fs_initcall(pcibios_assign_resources); 259 260 void __weak x86_pci_root_bus_res_quirks(struct pci_bus *b) 261 { 262 } 263 264 /* 265 * If we set up a device for bus mastering, we need to check the latency 266 * timer as certain crappy BIOSes forget to set it properly. 267 */ 268 unsigned int pcibios_max_latency = 255; 269 270 void pcibios_set_master(struct pci_dev *dev) 271 { 272 u8 lat; 273 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat); 274 if (lat < 16) 275 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency; 276 else if (lat > pcibios_max_latency) 277 lat = pcibios_max_latency; 278 else 279 return; 280 dev_printk(KERN_DEBUG, &dev->dev, "setting latency timer to %d\n", lat); 281 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat); 282 } 283 284 static const struct vm_operations_struct pci_mmap_ops = { 285 .access = generic_access_phys, 286 }; 287 288 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, 289 enum pci_mmap_state mmap_state, int write_combine) 290 { 291 unsigned long prot; 292 293 /* I/O space cannot be accessed via normal processor loads and 294 * stores on this platform. 295 */ 296 if (mmap_state == pci_mmap_io) 297 return -EINVAL; 298 299 prot = pgprot_val(vma->vm_page_prot); 300 301 /* 302 * Return error if pat is not enabled and write_combine is requested. 303 * Caller can followup with UC MINUS request and add a WC mtrr if there 304 * is a free mtrr slot. 305 */ 306 if (!pat_enabled && write_combine) 307 return -EINVAL; 308 309 if (pat_enabled && write_combine) 310 prot |= _PAGE_CACHE_WC; 311 else if (pat_enabled || boot_cpu_data.x86 > 3) 312 /* 313 * ioremap() and ioremap_nocache() defaults to UC MINUS for now. 314 * To avoid attribute conflicts, request UC MINUS here 315 * aswell. 316 */ 317 prot |= _PAGE_CACHE_UC_MINUS; 318 319 vma->vm_page_prot = __pgprot(prot); 320 321 if (io_remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, 322 vma->vm_end - vma->vm_start, 323 vma->vm_page_prot)) 324 return -EAGAIN; 325 326 vma->vm_ops = &pci_mmap_ops; 327 328 return 0; 329 } 330