1*da957e11SThomas Gleixner /*---------------------------------------------------------------------------+ 2*da957e11SThomas Gleixner | status_w.h | 3*da957e11SThomas Gleixner | | 4*da957e11SThomas Gleixner | Copyright (C) 1992,1993 | 5*da957e11SThomas Gleixner | W. Metzenthen, 22 Parker St, Ormond, Vic 3163, | 6*da957e11SThomas Gleixner | Australia. E-mail billm@vaxc.cc.monash.edu.au | 7*da957e11SThomas Gleixner | | 8*da957e11SThomas Gleixner +---------------------------------------------------------------------------*/ 9*da957e11SThomas Gleixner 10*da957e11SThomas Gleixner #ifndef _STATUS_H_ 11*da957e11SThomas Gleixner #define _STATUS_H_ 12*da957e11SThomas Gleixner 13*da957e11SThomas Gleixner #include "fpu_emu.h" /* for definition of PECULIAR_486 */ 14*da957e11SThomas Gleixner 15*da957e11SThomas Gleixner #ifdef __ASSEMBLY__ 16*da957e11SThomas Gleixner #define Const__(x) $##x 17*da957e11SThomas Gleixner #else 18*da957e11SThomas Gleixner #define Const__(x) x 19*da957e11SThomas Gleixner #endif 20*da957e11SThomas Gleixner 21*da957e11SThomas Gleixner #define SW_Backward Const__(0x8000) /* backward compatibility */ 22*da957e11SThomas Gleixner #define SW_C3 Const__(0x4000) /* condition bit 3 */ 23*da957e11SThomas Gleixner #define SW_Top Const__(0x3800) /* top of stack */ 24*da957e11SThomas Gleixner #define SW_Top_Shift Const__(11) /* shift for top of stack bits */ 25*da957e11SThomas Gleixner #define SW_C2 Const__(0x0400) /* condition bit 2 */ 26*da957e11SThomas Gleixner #define SW_C1 Const__(0x0200) /* condition bit 1 */ 27*da957e11SThomas Gleixner #define SW_C0 Const__(0x0100) /* condition bit 0 */ 28*da957e11SThomas Gleixner #define SW_Summary Const__(0x0080) /* exception summary */ 29*da957e11SThomas Gleixner #define SW_Stack_Fault Const__(0x0040) /* stack fault */ 30*da957e11SThomas Gleixner #define SW_Precision Const__(0x0020) /* loss of precision */ 31*da957e11SThomas Gleixner #define SW_Underflow Const__(0x0010) /* underflow */ 32*da957e11SThomas Gleixner #define SW_Overflow Const__(0x0008) /* overflow */ 33*da957e11SThomas Gleixner #define SW_Zero_Div Const__(0x0004) /* divide by zero */ 34*da957e11SThomas Gleixner #define SW_Denorm_Op Const__(0x0002) /* denormalized operand */ 35*da957e11SThomas Gleixner #define SW_Invalid Const__(0x0001) /* invalid operation */ 36*da957e11SThomas Gleixner 37*da957e11SThomas Gleixner #define SW_Exc_Mask Const__(0x27f) /* Status word exception bit mask */ 38*da957e11SThomas Gleixner 39*da957e11SThomas Gleixner #ifndef __ASSEMBLY__ 40*da957e11SThomas Gleixner 41*da957e11SThomas Gleixner #define COMP_A_gt_B 1 42*da957e11SThomas Gleixner #define COMP_A_eq_B 2 43*da957e11SThomas Gleixner #define COMP_A_lt_B 3 44*da957e11SThomas Gleixner #define COMP_No_Comp 4 45*da957e11SThomas Gleixner #define COMP_Denormal 0x20 46*da957e11SThomas Gleixner #define COMP_NaN 0x40 47*da957e11SThomas Gleixner #define COMP_SNaN 0x80 48*da957e11SThomas Gleixner 49*da957e11SThomas Gleixner #define status_word() \ 50*da957e11SThomas Gleixner ((partial_status & ~SW_Top & 0xffff) | ((top << SW_Top_Shift) & SW_Top)) 51*da957e11SThomas Gleixner static inline void setcc(int cc) 52*da957e11SThomas Gleixner { 53*da957e11SThomas Gleixner partial_status &= ~(SW_C0|SW_C1|SW_C2|SW_C3); 54*da957e11SThomas Gleixner partial_status |= (cc) & (SW_C0|SW_C1|SW_C2|SW_C3); 55*da957e11SThomas Gleixner } 56*da957e11SThomas Gleixner 57*da957e11SThomas Gleixner #ifdef PECULIAR_486 58*da957e11SThomas Gleixner /* Default, this conveys no information, but an 80486 does it. */ 59*da957e11SThomas Gleixner /* Clear the SW_C1 bit, "other bits undefined". */ 60*da957e11SThomas Gleixner # define clear_C1() { partial_status &= ~SW_C1; } 61*da957e11SThomas Gleixner # else 62*da957e11SThomas Gleixner # define clear_C1() 63*da957e11SThomas Gleixner #endif /* PECULIAR_486 */ 64*da957e11SThomas Gleixner 65*da957e11SThomas Gleixner #endif /* __ASSEMBLY__ */ 66*da957e11SThomas Gleixner 67*da957e11SThomas Gleixner #endif /* _STATUS_H_ */ 68