1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Kernel-based Virtual Machine driver for Linux 4 * 5 * derived from drivers/kvm/kvm_main.c 6 * 7 * Copyright (C) 2006 Qumranet, Inc. 8 * Copyright (C) 2008 Qumranet, Inc. 9 * Copyright IBM Corporation, 2008 10 * Copyright 2010 Red Hat, Inc. and/or its affiliates. 11 * 12 * Authors: 13 * Avi Kivity <avi@qumranet.com> 14 * Yaniv Kamay <yaniv@qumranet.com> 15 * Amit Shah <amit.shah@qumranet.com> 16 * Ben-Ami Yassour <benami@il.ibm.com> 17 */ 18 19 #include <linux/kvm_host.h> 20 #include "irq.h" 21 #include "ioapic.h" 22 #include "mmu.h" 23 #include "i8254.h" 24 #include "tss.h" 25 #include "kvm_cache_regs.h" 26 #include "kvm_emulate.h" 27 #include "x86.h" 28 #include "cpuid.h" 29 #include "pmu.h" 30 #include "hyperv.h" 31 #include "lapic.h" 32 #include "xen.h" 33 34 #include <linux/clocksource.h> 35 #include <linux/interrupt.h> 36 #include <linux/kvm.h> 37 #include <linux/fs.h> 38 #include <linux/vmalloc.h> 39 #include <linux/export.h> 40 #include <linux/moduleparam.h> 41 #include <linux/mman.h> 42 #include <linux/highmem.h> 43 #include <linux/iommu.h> 44 #include <linux/intel-iommu.h> 45 #include <linux/cpufreq.h> 46 #include <linux/user-return-notifier.h> 47 #include <linux/srcu.h> 48 #include <linux/slab.h> 49 #include <linux/perf_event.h> 50 #include <linux/uaccess.h> 51 #include <linux/hash.h> 52 #include <linux/pci.h> 53 #include <linux/timekeeper_internal.h> 54 #include <linux/pvclock_gtod.h> 55 #include <linux/kvm_irqfd.h> 56 #include <linux/irqbypass.h> 57 #include <linux/sched/stat.h> 58 #include <linux/sched/isolation.h> 59 #include <linux/mem_encrypt.h> 60 #include <linux/entry-kvm.h> 61 #include <linux/suspend.h> 62 63 #include <trace/events/kvm.h> 64 65 #include <asm/debugreg.h> 66 #include <asm/msr.h> 67 #include <asm/desc.h> 68 #include <asm/mce.h> 69 #include <asm/pkru.h> 70 #include <linux/kernel_stat.h> 71 #include <asm/fpu/api.h> 72 #include <asm/fpu/xcr.h> 73 #include <asm/fpu/xstate.h> 74 #include <asm/pvclock.h> 75 #include <asm/div64.h> 76 #include <asm/irq_remapping.h> 77 #include <asm/mshyperv.h> 78 #include <asm/hypervisor.h> 79 #include <asm/tlbflush.h> 80 #include <asm/intel_pt.h> 81 #include <asm/emulate_prefix.h> 82 #include <asm/sgx.h> 83 #include <clocksource/hyperv_timer.h> 84 85 #define CREATE_TRACE_POINTS 86 #include "trace.h" 87 88 #define MAX_IO_MSRS 256 89 #define KVM_MAX_MCE_BANKS 32 90 u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P; 91 EXPORT_SYMBOL_GPL(kvm_mce_cap_supported); 92 93 #define ERR_PTR_USR(e) ((void __user *)ERR_PTR(e)) 94 95 #define emul_to_vcpu(ctxt) \ 96 ((struct kvm_vcpu *)(ctxt)->vcpu) 97 98 /* EFER defaults: 99 * - enable syscall per default because its emulated by KVM 100 * - enable LME and LMA per default on 64 bit KVM 101 */ 102 #ifdef CONFIG_X86_64 103 static 104 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA)); 105 #else 106 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE); 107 #endif 108 109 static u64 __read_mostly cr4_reserved_bits = CR4_RESERVED_BITS; 110 111 #define KVM_EXIT_HYPERCALL_VALID_MASK (1 << KVM_HC_MAP_GPA_RANGE) 112 113 #define KVM_CAP_PMU_VALID_MASK KVM_PMU_CAP_DISABLE 114 115 #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \ 116 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK) 117 118 static void update_cr8_intercept(struct kvm_vcpu *vcpu); 119 static void process_nmi(struct kvm_vcpu *vcpu); 120 static void process_smi(struct kvm_vcpu *vcpu); 121 static void enter_smm(struct kvm_vcpu *vcpu); 122 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags); 123 static void store_regs(struct kvm_vcpu *vcpu); 124 static int sync_regs(struct kvm_vcpu *vcpu); 125 static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu); 126 127 static int __set_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2); 128 static void __get_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2); 129 130 struct kvm_x86_ops kvm_x86_ops __read_mostly; 131 132 #define KVM_X86_OP(func) \ 133 DEFINE_STATIC_CALL_NULL(kvm_x86_##func, \ 134 *(((struct kvm_x86_ops *)0)->func)); 135 #define KVM_X86_OP_OPTIONAL KVM_X86_OP 136 #define KVM_X86_OP_OPTIONAL_RET0 KVM_X86_OP 137 #include <asm/kvm-x86-ops.h> 138 EXPORT_STATIC_CALL_GPL(kvm_x86_get_cs_db_l_bits); 139 EXPORT_STATIC_CALL_GPL(kvm_x86_cache_reg); 140 141 static bool __read_mostly ignore_msrs = 0; 142 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR); 143 144 bool __read_mostly report_ignored_msrs = true; 145 module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR); 146 EXPORT_SYMBOL_GPL(report_ignored_msrs); 147 148 unsigned int min_timer_period_us = 200; 149 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR); 150 151 static bool __read_mostly kvmclock_periodic_sync = true; 152 module_param(kvmclock_periodic_sync, bool, S_IRUGO); 153 154 bool __read_mostly kvm_has_tsc_control; 155 EXPORT_SYMBOL_GPL(kvm_has_tsc_control); 156 u32 __read_mostly kvm_max_guest_tsc_khz; 157 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz); 158 u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits; 159 EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits); 160 u64 __read_mostly kvm_max_tsc_scaling_ratio; 161 EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio); 162 u64 __read_mostly kvm_default_tsc_scaling_ratio; 163 EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio); 164 bool __read_mostly kvm_has_bus_lock_exit; 165 EXPORT_SYMBOL_GPL(kvm_has_bus_lock_exit); 166 167 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */ 168 static u32 __read_mostly tsc_tolerance_ppm = 250; 169 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR); 170 171 /* 172 * lapic timer advance (tscdeadline mode only) in nanoseconds. '-1' enables 173 * adaptive tuning starting from default advancement of 1000ns. '0' disables 174 * advancement entirely. Any other value is used as-is and disables adaptive 175 * tuning, i.e. allows privileged userspace to set an exact advancement time. 176 */ 177 static int __read_mostly lapic_timer_advance_ns = -1; 178 module_param(lapic_timer_advance_ns, int, S_IRUGO | S_IWUSR); 179 180 static bool __read_mostly vector_hashing = true; 181 module_param(vector_hashing, bool, S_IRUGO); 182 183 bool __read_mostly enable_vmware_backdoor = false; 184 module_param(enable_vmware_backdoor, bool, S_IRUGO); 185 EXPORT_SYMBOL_GPL(enable_vmware_backdoor); 186 187 static bool __read_mostly force_emulation_prefix = false; 188 module_param(force_emulation_prefix, bool, S_IRUGO); 189 190 int __read_mostly pi_inject_timer = -1; 191 module_param(pi_inject_timer, bint, S_IRUGO | S_IWUSR); 192 193 /* Enable/disable PMU virtualization */ 194 bool __read_mostly enable_pmu = true; 195 EXPORT_SYMBOL_GPL(enable_pmu); 196 module_param(enable_pmu, bool, 0444); 197 198 bool __read_mostly eager_page_split = true; 199 module_param(eager_page_split, bool, 0644); 200 201 /* 202 * Restoring the host value for MSRs that are only consumed when running in 203 * usermode, e.g. SYSCALL MSRs and TSC_AUX, can be deferred until the CPU 204 * returns to userspace, i.e. the kernel can run with the guest's value. 205 */ 206 #define KVM_MAX_NR_USER_RETURN_MSRS 16 207 208 struct kvm_user_return_msrs { 209 struct user_return_notifier urn; 210 bool registered; 211 struct kvm_user_return_msr_values { 212 u64 host; 213 u64 curr; 214 } values[KVM_MAX_NR_USER_RETURN_MSRS]; 215 }; 216 217 u32 __read_mostly kvm_nr_uret_msrs; 218 EXPORT_SYMBOL_GPL(kvm_nr_uret_msrs); 219 static u32 __read_mostly kvm_uret_msrs_list[KVM_MAX_NR_USER_RETURN_MSRS]; 220 static struct kvm_user_return_msrs __percpu *user_return_msrs; 221 222 #define KVM_SUPPORTED_XCR0 (XFEATURE_MASK_FP | XFEATURE_MASK_SSE \ 223 | XFEATURE_MASK_YMM | XFEATURE_MASK_BNDREGS \ 224 | XFEATURE_MASK_BNDCSR | XFEATURE_MASK_AVX512 \ 225 | XFEATURE_MASK_PKRU | XFEATURE_MASK_XTILE) 226 227 u64 __read_mostly host_efer; 228 EXPORT_SYMBOL_GPL(host_efer); 229 230 bool __read_mostly allow_smaller_maxphyaddr = 0; 231 EXPORT_SYMBOL_GPL(allow_smaller_maxphyaddr); 232 233 bool __read_mostly enable_apicv = true; 234 EXPORT_SYMBOL_GPL(enable_apicv); 235 236 u64 __read_mostly host_xss; 237 EXPORT_SYMBOL_GPL(host_xss); 238 u64 __read_mostly supported_xss; 239 EXPORT_SYMBOL_GPL(supported_xss); 240 241 const struct _kvm_stats_desc kvm_vm_stats_desc[] = { 242 KVM_GENERIC_VM_STATS(), 243 STATS_DESC_COUNTER(VM, mmu_shadow_zapped), 244 STATS_DESC_COUNTER(VM, mmu_pte_write), 245 STATS_DESC_COUNTER(VM, mmu_pde_zapped), 246 STATS_DESC_COUNTER(VM, mmu_flooded), 247 STATS_DESC_COUNTER(VM, mmu_recycled), 248 STATS_DESC_COUNTER(VM, mmu_cache_miss), 249 STATS_DESC_ICOUNTER(VM, mmu_unsync), 250 STATS_DESC_ICOUNTER(VM, pages_4k), 251 STATS_DESC_ICOUNTER(VM, pages_2m), 252 STATS_DESC_ICOUNTER(VM, pages_1g), 253 STATS_DESC_ICOUNTER(VM, nx_lpage_splits), 254 STATS_DESC_PCOUNTER(VM, max_mmu_rmap_size), 255 STATS_DESC_PCOUNTER(VM, max_mmu_page_hash_collisions) 256 }; 257 258 const struct kvm_stats_header kvm_vm_stats_header = { 259 .name_size = KVM_STATS_NAME_SIZE, 260 .num_desc = ARRAY_SIZE(kvm_vm_stats_desc), 261 .id_offset = sizeof(struct kvm_stats_header), 262 .desc_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE, 263 .data_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE + 264 sizeof(kvm_vm_stats_desc), 265 }; 266 267 const struct _kvm_stats_desc kvm_vcpu_stats_desc[] = { 268 KVM_GENERIC_VCPU_STATS(), 269 STATS_DESC_COUNTER(VCPU, pf_fixed), 270 STATS_DESC_COUNTER(VCPU, pf_guest), 271 STATS_DESC_COUNTER(VCPU, tlb_flush), 272 STATS_DESC_COUNTER(VCPU, invlpg), 273 STATS_DESC_COUNTER(VCPU, exits), 274 STATS_DESC_COUNTER(VCPU, io_exits), 275 STATS_DESC_COUNTER(VCPU, mmio_exits), 276 STATS_DESC_COUNTER(VCPU, signal_exits), 277 STATS_DESC_COUNTER(VCPU, irq_window_exits), 278 STATS_DESC_COUNTER(VCPU, nmi_window_exits), 279 STATS_DESC_COUNTER(VCPU, l1d_flush), 280 STATS_DESC_COUNTER(VCPU, halt_exits), 281 STATS_DESC_COUNTER(VCPU, request_irq_exits), 282 STATS_DESC_COUNTER(VCPU, irq_exits), 283 STATS_DESC_COUNTER(VCPU, host_state_reload), 284 STATS_DESC_COUNTER(VCPU, fpu_reload), 285 STATS_DESC_COUNTER(VCPU, insn_emulation), 286 STATS_DESC_COUNTER(VCPU, insn_emulation_fail), 287 STATS_DESC_COUNTER(VCPU, hypercalls), 288 STATS_DESC_COUNTER(VCPU, irq_injections), 289 STATS_DESC_COUNTER(VCPU, nmi_injections), 290 STATS_DESC_COUNTER(VCPU, req_event), 291 STATS_DESC_COUNTER(VCPU, nested_run), 292 STATS_DESC_COUNTER(VCPU, directed_yield_attempted), 293 STATS_DESC_COUNTER(VCPU, directed_yield_successful), 294 STATS_DESC_ICOUNTER(VCPU, guest_mode) 295 }; 296 297 const struct kvm_stats_header kvm_vcpu_stats_header = { 298 .name_size = KVM_STATS_NAME_SIZE, 299 .num_desc = ARRAY_SIZE(kvm_vcpu_stats_desc), 300 .id_offset = sizeof(struct kvm_stats_header), 301 .desc_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE, 302 .data_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE + 303 sizeof(kvm_vcpu_stats_desc), 304 }; 305 306 u64 __read_mostly host_xcr0; 307 u64 __read_mostly supported_xcr0; 308 EXPORT_SYMBOL_GPL(supported_xcr0); 309 310 static struct kmem_cache *x86_emulator_cache; 311 312 /* 313 * When called, it means the previous get/set msr reached an invalid msr. 314 * Return true if we want to ignore/silent this failed msr access. 315 */ 316 static bool kvm_msr_ignored_check(u32 msr, u64 data, bool write) 317 { 318 const char *op = write ? "wrmsr" : "rdmsr"; 319 320 if (ignore_msrs) { 321 if (report_ignored_msrs) 322 kvm_pr_unimpl("ignored %s: 0x%x data 0x%llx\n", 323 op, msr, data); 324 /* Mask the error */ 325 return true; 326 } else { 327 kvm_debug_ratelimited("unhandled %s: 0x%x data 0x%llx\n", 328 op, msr, data); 329 return false; 330 } 331 } 332 333 static struct kmem_cache *kvm_alloc_emulator_cache(void) 334 { 335 unsigned int useroffset = offsetof(struct x86_emulate_ctxt, src); 336 unsigned int size = sizeof(struct x86_emulate_ctxt); 337 338 return kmem_cache_create_usercopy("x86_emulator", size, 339 __alignof__(struct x86_emulate_ctxt), 340 SLAB_ACCOUNT, useroffset, 341 size - useroffset, NULL); 342 } 343 344 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt); 345 346 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu) 347 { 348 int i; 349 for (i = 0; i < ASYNC_PF_PER_VCPU; i++) 350 vcpu->arch.apf.gfns[i] = ~0; 351 } 352 353 static void kvm_on_user_return(struct user_return_notifier *urn) 354 { 355 unsigned slot; 356 struct kvm_user_return_msrs *msrs 357 = container_of(urn, struct kvm_user_return_msrs, urn); 358 struct kvm_user_return_msr_values *values; 359 unsigned long flags; 360 361 /* 362 * Disabling irqs at this point since the following code could be 363 * interrupted and executed through kvm_arch_hardware_disable() 364 */ 365 local_irq_save(flags); 366 if (msrs->registered) { 367 msrs->registered = false; 368 user_return_notifier_unregister(urn); 369 } 370 local_irq_restore(flags); 371 for (slot = 0; slot < kvm_nr_uret_msrs; ++slot) { 372 values = &msrs->values[slot]; 373 if (values->host != values->curr) { 374 wrmsrl(kvm_uret_msrs_list[slot], values->host); 375 values->curr = values->host; 376 } 377 } 378 } 379 380 static int kvm_probe_user_return_msr(u32 msr) 381 { 382 u64 val; 383 int ret; 384 385 preempt_disable(); 386 ret = rdmsrl_safe(msr, &val); 387 if (ret) 388 goto out; 389 ret = wrmsrl_safe(msr, val); 390 out: 391 preempt_enable(); 392 return ret; 393 } 394 395 int kvm_add_user_return_msr(u32 msr) 396 { 397 BUG_ON(kvm_nr_uret_msrs >= KVM_MAX_NR_USER_RETURN_MSRS); 398 399 if (kvm_probe_user_return_msr(msr)) 400 return -1; 401 402 kvm_uret_msrs_list[kvm_nr_uret_msrs] = msr; 403 return kvm_nr_uret_msrs++; 404 } 405 EXPORT_SYMBOL_GPL(kvm_add_user_return_msr); 406 407 int kvm_find_user_return_msr(u32 msr) 408 { 409 int i; 410 411 for (i = 0; i < kvm_nr_uret_msrs; ++i) { 412 if (kvm_uret_msrs_list[i] == msr) 413 return i; 414 } 415 return -1; 416 } 417 EXPORT_SYMBOL_GPL(kvm_find_user_return_msr); 418 419 static void kvm_user_return_msr_cpu_online(void) 420 { 421 unsigned int cpu = smp_processor_id(); 422 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu); 423 u64 value; 424 int i; 425 426 for (i = 0; i < kvm_nr_uret_msrs; ++i) { 427 rdmsrl_safe(kvm_uret_msrs_list[i], &value); 428 msrs->values[i].host = value; 429 msrs->values[i].curr = value; 430 } 431 } 432 433 int kvm_set_user_return_msr(unsigned slot, u64 value, u64 mask) 434 { 435 unsigned int cpu = smp_processor_id(); 436 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu); 437 int err; 438 439 value = (value & mask) | (msrs->values[slot].host & ~mask); 440 if (value == msrs->values[slot].curr) 441 return 0; 442 err = wrmsrl_safe(kvm_uret_msrs_list[slot], value); 443 if (err) 444 return 1; 445 446 msrs->values[slot].curr = value; 447 if (!msrs->registered) { 448 msrs->urn.on_user_return = kvm_on_user_return; 449 user_return_notifier_register(&msrs->urn); 450 msrs->registered = true; 451 } 452 return 0; 453 } 454 EXPORT_SYMBOL_GPL(kvm_set_user_return_msr); 455 456 static void drop_user_return_notifiers(void) 457 { 458 unsigned int cpu = smp_processor_id(); 459 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu); 460 461 if (msrs->registered) 462 kvm_on_user_return(&msrs->urn); 463 } 464 465 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu) 466 { 467 return vcpu->arch.apic_base; 468 } 469 EXPORT_SYMBOL_GPL(kvm_get_apic_base); 470 471 enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu) 472 { 473 return kvm_apic_mode(kvm_get_apic_base(vcpu)); 474 } 475 EXPORT_SYMBOL_GPL(kvm_get_apic_mode); 476 477 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 478 { 479 enum lapic_mode old_mode = kvm_get_apic_mode(vcpu); 480 enum lapic_mode new_mode = kvm_apic_mode(msr_info->data); 481 u64 reserved_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu) | 0x2ff | 482 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE); 483 484 if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID) 485 return 1; 486 if (!msr_info->host_initiated) { 487 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC) 488 return 1; 489 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC) 490 return 1; 491 } 492 493 kvm_lapic_set_base(vcpu, msr_info->data); 494 kvm_recalculate_apic_map(vcpu->kvm); 495 return 0; 496 } 497 EXPORT_SYMBOL_GPL(kvm_set_apic_base); 498 499 /* 500 * Handle a fault on a hardware virtualization (VMX or SVM) instruction. 501 * 502 * Hardware virtualization extension instructions may fault if a reboot turns 503 * off virtualization while processes are running. Usually after catching the 504 * fault we just panic; during reboot instead the instruction is ignored. 505 */ 506 noinstr void kvm_spurious_fault(void) 507 { 508 /* Fault while not rebooting. We want the trace. */ 509 BUG_ON(!kvm_rebooting); 510 } 511 EXPORT_SYMBOL_GPL(kvm_spurious_fault); 512 513 #define EXCPT_BENIGN 0 514 #define EXCPT_CONTRIBUTORY 1 515 #define EXCPT_PF 2 516 517 static int exception_class(int vector) 518 { 519 switch (vector) { 520 case PF_VECTOR: 521 return EXCPT_PF; 522 case DE_VECTOR: 523 case TS_VECTOR: 524 case NP_VECTOR: 525 case SS_VECTOR: 526 case GP_VECTOR: 527 return EXCPT_CONTRIBUTORY; 528 default: 529 break; 530 } 531 return EXCPT_BENIGN; 532 } 533 534 #define EXCPT_FAULT 0 535 #define EXCPT_TRAP 1 536 #define EXCPT_ABORT 2 537 #define EXCPT_INTERRUPT 3 538 539 static int exception_type(int vector) 540 { 541 unsigned int mask; 542 543 if (WARN_ON(vector > 31 || vector == NMI_VECTOR)) 544 return EXCPT_INTERRUPT; 545 546 mask = 1 << vector; 547 548 /* #DB is trap, as instruction watchpoints are handled elsewhere */ 549 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR))) 550 return EXCPT_TRAP; 551 552 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR))) 553 return EXCPT_ABORT; 554 555 /* Reserved exceptions will result in fault */ 556 return EXCPT_FAULT; 557 } 558 559 void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu) 560 { 561 unsigned nr = vcpu->arch.exception.nr; 562 bool has_payload = vcpu->arch.exception.has_payload; 563 unsigned long payload = vcpu->arch.exception.payload; 564 565 if (!has_payload) 566 return; 567 568 switch (nr) { 569 case DB_VECTOR: 570 /* 571 * "Certain debug exceptions may clear bit 0-3. The 572 * remaining contents of the DR6 register are never 573 * cleared by the processor". 574 */ 575 vcpu->arch.dr6 &= ~DR_TRAP_BITS; 576 /* 577 * In order to reflect the #DB exception payload in guest 578 * dr6, three components need to be considered: active low 579 * bit, FIXED_1 bits and active high bits (e.g. DR6_BD, 580 * DR6_BS and DR6_BT) 581 * DR6_ACTIVE_LOW contains the FIXED_1 and active low bits. 582 * In the target guest dr6: 583 * FIXED_1 bits should always be set. 584 * Active low bits should be cleared if 1-setting in payload. 585 * Active high bits should be set if 1-setting in payload. 586 * 587 * Note, the payload is compatible with the pending debug 588 * exceptions/exit qualification under VMX, that active_low bits 589 * are active high in payload. 590 * So they need to be flipped for DR6. 591 */ 592 vcpu->arch.dr6 |= DR6_ACTIVE_LOW; 593 vcpu->arch.dr6 |= payload; 594 vcpu->arch.dr6 ^= payload & DR6_ACTIVE_LOW; 595 596 /* 597 * The #DB payload is defined as compatible with the 'pending 598 * debug exceptions' field under VMX, not DR6. While bit 12 is 599 * defined in the 'pending debug exceptions' field (enabled 600 * breakpoint), it is reserved and must be zero in DR6. 601 */ 602 vcpu->arch.dr6 &= ~BIT(12); 603 break; 604 case PF_VECTOR: 605 vcpu->arch.cr2 = payload; 606 break; 607 } 608 609 vcpu->arch.exception.has_payload = false; 610 vcpu->arch.exception.payload = 0; 611 } 612 EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload); 613 614 static void kvm_multiple_exception(struct kvm_vcpu *vcpu, 615 unsigned nr, bool has_error, u32 error_code, 616 bool has_payload, unsigned long payload, bool reinject) 617 { 618 u32 prev_nr; 619 int class1, class2; 620 621 kvm_make_request(KVM_REQ_EVENT, vcpu); 622 623 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) { 624 queue: 625 if (reinject) { 626 /* 627 * On vmentry, vcpu->arch.exception.pending is only 628 * true if an event injection was blocked by 629 * nested_run_pending. In that case, however, 630 * vcpu_enter_guest requests an immediate exit, 631 * and the guest shouldn't proceed far enough to 632 * need reinjection. 633 */ 634 WARN_ON_ONCE(vcpu->arch.exception.pending); 635 vcpu->arch.exception.injected = true; 636 if (WARN_ON_ONCE(has_payload)) { 637 /* 638 * A reinjected event has already 639 * delivered its payload. 640 */ 641 has_payload = false; 642 payload = 0; 643 } 644 } else { 645 vcpu->arch.exception.pending = true; 646 vcpu->arch.exception.injected = false; 647 } 648 vcpu->arch.exception.has_error_code = has_error; 649 vcpu->arch.exception.nr = nr; 650 vcpu->arch.exception.error_code = error_code; 651 vcpu->arch.exception.has_payload = has_payload; 652 vcpu->arch.exception.payload = payload; 653 if (!is_guest_mode(vcpu)) 654 kvm_deliver_exception_payload(vcpu); 655 return; 656 } 657 658 /* to check exception */ 659 prev_nr = vcpu->arch.exception.nr; 660 if (prev_nr == DF_VECTOR) { 661 /* triple fault -> shutdown */ 662 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 663 return; 664 } 665 class1 = exception_class(prev_nr); 666 class2 = exception_class(nr); 667 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY) 668 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) { 669 /* 670 * Generate double fault per SDM Table 5-5. Set 671 * exception.pending = true so that the double fault 672 * can trigger a nested vmexit. 673 */ 674 vcpu->arch.exception.pending = true; 675 vcpu->arch.exception.injected = false; 676 vcpu->arch.exception.has_error_code = true; 677 vcpu->arch.exception.nr = DF_VECTOR; 678 vcpu->arch.exception.error_code = 0; 679 vcpu->arch.exception.has_payload = false; 680 vcpu->arch.exception.payload = 0; 681 } else 682 /* replace previous exception with a new one in a hope 683 that instruction re-execution will regenerate lost 684 exception */ 685 goto queue; 686 } 687 688 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr) 689 { 690 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false); 691 } 692 EXPORT_SYMBOL_GPL(kvm_queue_exception); 693 694 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr) 695 { 696 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true); 697 } 698 EXPORT_SYMBOL_GPL(kvm_requeue_exception); 699 700 void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr, 701 unsigned long payload) 702 { 703 kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false); 704 } 705 EXPORT_SYMBOL_GPL(kvm_queue_exception_p); 706 707 static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr, 708 u32 error_code, unsigned long payload) 709 { 710 kvm_multiple_exception(vcpu, nr, true, error_code, 711 true, payload, false); 712 } 713 714 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err) 715 { 716 if (err) 717 kvm_inject_gp(vcpu, 0); 718 else 719 return kvm_skip_emulated_instruction(vcpu); 720 721 return 1; 722 } 723 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp); 724 725 static int complete_emulated_insn_gp(struct kvm_vcpu *vcpu, int err) 726 { 727 if (err) { 728 kvm_inject_gp(vcpu, 0); 729 return 1; 730 } 731 732 return kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE | EMULTYPE_SKIP | 733 EMULTYPE_COMPLETE_USER_EXIT); 734 } 735 736 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) 737 { 738 ++vcpu->stat.pf_guest; 739 vcpu->arch.exception.nested_apf = 740 is_guest_mode(vcpu) && fault->async_page_fault; 741 if (vcpu->arch.exception.nested_apf) { 742 vcpu->arch.apf.nested_apf_token = fault->address; 743 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code); 744 } else { 745 kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code, 746 fault->address); 747 } 748 } 749 EXPORT_SYMBOL_GPL(kvm_inject_page_fault); 750 751 bool kvm_inject_emulated_page_fault(struct kvm_vcpu *vcpu, 752 struct x86_exception *fault) 753 { 754 struct kvm_mmu *fault_mmu; 755 WARN_ON_ONCE(fault->vector != PF_VECTOR); 756 757 fault_mmu = fault->nested_page_fault ? vcpu->arch.mmu : 758 vcpu->arch.walk_mmu; 759 760 /* 761 * Invalidate the TLB entry for the faulting address, if it exists, 762 * else the access will fault indefinitely (and to emulate hardware). 763 */ 764 if ((fault->error_code & PFERR_PRESENT_MASK) && 765 !(fault->error_code & PFERR_RSVD_MASK)) 766 kvm_mmu_invalidate_gva(vcpu, fault_mmu, fault->address, 767 fault_mmu->root_hpa); 768 769 fault_mmu->inject_page_fault(vcpu, fault); 770 return fault->nested_page_fault; 771 } 772 EXPORT_SYMBOL_GPL(kvm_inject_emulated_page_fault); 773 774 void kvm_inject_nmi(struct kvm_vcpu *vcpu) 775 { 776 atomic_inc(&vcpu->arch.nmi_queued); 777 kvm_make_request(KVM_REQ_NMI, vcpu); 778 } 779 EXPORT_SYMBOL_GPL(kvm_inject_nmi); 780 781 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) 782 { 783 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false); 784 } 785 EXPORT_SYMBOL_GPL(kvm_queue_exception_e); 786 787 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) 788 { 789 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true); 790 } 791 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e); 792 793 /* 794 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue 795 * a #GP and return false. 796 */ 797 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl) 798 { 799 if (static_call(kvm_x86_get_cpl)(vcpu) <= required_cpl) 800 return true; 801 kvm_queue_exception_e(vcpu, GP_VECTOR, 0); 802 return false; 803 } 804 EXPORT_SYMBOL_GPL(kvm_require_cpl); 805 806 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr) 807 { 808 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE)) 809 return true; 810 811 kvm_queue_exception(vcpu, UD_VECTOR); 812 return false; 813 } 814 EXPORT_SYMBOL_GPL(kvm_require_dr); 815 816 static inline u64 pdptr_rsvd_bits(struct kvm_vcpu *vcpu) 817 { 818 return vcpu->arch.reserved_gpa_bits | rsvd_bits(5, 8) | rsvd_bits(1, 2); 819 } 820 821 /* 822 * Load the pae pdptrs. Return 1 if they are all valid, 0 otherwise. 823 */ 824 int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3) 825 { 826 struct kvm_mmu *mmu = vcpu->arch.walk_mmu; 827 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT; 828 gpa_t real_gpa; 829 int i; 830 int ret; 831 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)]; 832 833 /* 834 * If the MMU is nested, CR3 holds an L2 GPA and needs to be translated 835 * to an L1 GPA. 836 */ 837 real_gpa = kvm_translate_gpa(vcpu, mmu, gfn_to_gpa(pdpt_gfn), 838 PFERR_USER_MASK | PFERR_WRITE_MASK, NULL); 839 if (real_gpa == UNMAPPED_GVA) 840 return 0; 841 842 /* Note the offset, PDPTRs are 32 byte aligned when using PAE paging. */ 843 ret = kvm_vcpu_read_guest_page(vcpu, gpa_to_gfn(real_gpa), pdpte, 844 cr3 & GENMASK(11, 5), sizeof(pdpte)); 845 if (ret < 0) 846 return 0; 847 848 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) { 849 if ((pdpte[i] & PT_PRESENT_MASK) && 850 (pdpte[i] & pdptr_rsvd_bits(vcpu))) { 851 return 0; 852 } 853 } 854 855 /* 856 * Marking VCPU_EXREG_PDPTR dirty doesn't work for !tdp_enabled. 857 * Shadow page roots need to be reconstructed instead. 858 */ 859 if (!tdp_enabled && memcmp(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs))) 860 kvm_mmu_free_roots(vcpu, mmu, KVM_MMU_ROOT_CURRENT); 861 862 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs)); 863 kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR); 864 kvm_make_request(KVM_REQ_LOAD_MMU_PGD, vcpu); 865 vcpu->arch.pdptrs_from_userspace = false; 866 867 return 1; 868 } 869 EXPORT_SYMBOL_GPL(load_pdptrs); 870 871 void kvm_post_set_cr0(struct kvm_vcpu *vcpu, unsigned long old_cr0, unsigned long cr0) 872 { 873 if ((cr0 ^ old_cr0) & X86_CR0_PG) { 874 kvm_clear_async_pf_completion_queue(vcpu); 875 kvm_async_pf_hash_reset(vcpu); 876 } 877 878 if ((cr0 ^ old_cr0) & KVM_MMU_CR0_ROLE_BITS) 879 kvm_mmu_reset_context(vcpu); 880 881 if (((cr0 ^ old_cr0) & X86_CR0_CD) && 882 kvm_arch_has_noncoherent_dma(vcpu->kvm) && 883 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED)) 884 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL); 885 } 886 EXPORT_SYMBOL_GPL(kvm_post_set_cr0); 887 888 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) 889 { 890 unsigned long old_cr0 = kvm_read_cr0(vcpu); 891 892 cr0 |= X86_CR0_ET; 893 894 #ifdef CONFIG_X86_64 895 if (cr0 & 0xffffffff00000000UL) 896 return 1; 897 #endif 898 899 cr0 &= ~CR0_RESERVED_BITS; 900 901 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) 902 return 1; 903 904 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) 905 return 1; 906 907 #ifdef CONFIG_X86_64 908 if ((vcpu->arch.efer & EFER_LME) && !is_paging(vcpu) && 909 (cr0 & X86_CR0_PG)) { 910 int cs_db, cs_l; 911 912 if (!is_pae(vcpu)) 913 return 1; 914 static_call(kvm_x86_get_cs_db_l_bits)(vcpu, &cs_db, &cs_l); 915 if (cs_l) 916 return 1; 917 } 918 #endif 919 if (!(vcpu->arch.efer & EFER_LME) && (cr0 & X86_CR0_PG) && 920 is_pae(vcpu) && ((cr0 ^ old_cr0) & X86_CR0_PDPTR_BITS) && 921 !load_pdptrs(vcpu, kvm_read_cr3(vcpu))) 922 return 1; 923 924 if (!(cr0 & X86_CR0_PG) && 925 (is_64_bit_mode(vcpu) || kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))) 926 return 1; 927 928 static_call(kvm_x86_set_cr0)(vcpu, cr0); 929 930 kvm_post_set_cr0(vcpu, old_cr0, cr0); 931 932 return 0; 933 } 934 EXPORT_SYMBOL_GPL(kvm_set_cr0); 935 936 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw) 937 { 938 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f)); 939 } 940 EXPORT_SYMBOL_GPL(kvm_lmsw); 941 942 void kvm_load_guest_xsave_state(struct kvm_vcpu *vcpu) 943 { 944 if (vcpu->arch.guest_state_protected) 945 return; 946 947 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) { 948 949 if (vcpu->arch.xcr0 != host_xcr0) 950 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0); 951 952 if (vcpu->arch.xsaves_enabled && 953 vcpu->arch.ia32_xss != host_xss) 954 wrmsrl(MSR_IA32_XSS, vcpu->arch.ia32_xss); 955 } 956 957 if (static_cpu_has(X86_FEATURE_PKU) && 958 (kvm_read_cr4_bits(vcpu, X86_CR4_PKE) || 959 (vcpu->arch.xcr0 & XFEATURE_MASK_PKRU)) && 960 vcpu->arch.pkru != vcpu->arch.host_pkru) 961 write_pkru(vcpu->arch.pkru); 962 } 963 EXPORT_SYMBOL_GPL(kvm_load_guest_xsave_state); 964 965 void kvm_load_host_xsave_state(struct kvm_vcpu *vcpu) 966 { 967 if (vcpu->arch.guest_state_protected) 968 return; 969 970 if (static_cpu_has(X86_FEATURE_PKU) && 971 (kvm_read_cr4_bits(vcpu, X86_CR4_PKE) || 972 (vcpu->arch.xcr0 & XFEATURE_MASK_PKRU))) { 973 vcpu->arch.pkru = rdpkru(); 974 if (vcpu->arch.pkru != vcpu->arch.host_pkru) 975 write_pkru(vcpu->arch.host_pkru); 976 } 977 978 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) { 979 980 if (vcpu->arch.xcr0 != host_xcr0) 981 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0); 982 983 if (vcpu->arch.xsaves_enabled && 984 vcpu->arch.ia32_xss != host_xss) 985 wrmsrl(MSR_IA32_XSS, host_xss); 986 } 987 988 } 989 EXPORT_SYMBOL_GPL(kvm_load_host_xsave_state); 990 991 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) 992 { 993 u64 xcr0 = xcr; 994 u64 old_xcr0 = vcpu->arch.xcr0; 995 u64 valid_bits; 996 997 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */ 998 if (index != XCR_XFEATURE_ENABLED_MASK) 999 return 1; 1000 if (!(xcr0 & XFEATURE_MASK_FP)) 1001 return 1; 1002 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE)) 1003 return 1; 1004 1005 /* 1006 * Do not allow the guest to set bits that we do not support 1007 * saving. However, xcr0 bit 0 is always set, even if the 1008 * emulated CPU does not support XSAVE (see kvm_vcpu_reset()). 1009 */ 1010 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP; 1011 if (xcr0 & ~valid_bits) 1012 return 1; 1013 1014 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) != 1015 (!(xcr0 & XFEATURE_MASK_BNDCSR))) 1016 return 1; 1017 1018 if (xcr0 & XFEATURE_MASK_AVX512) { 1019 if (!(xcr0 & XFEATURE_MASK_YMM)) 1020 return 1; 1021 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512) 1022 return 1; 1023 } 1024 1025 if ((xcr0 & XFEATURE_MASK_XTILE) && 1026 ((xcr0 & XFEATURE_MASK_XTILE) != XFEATURE_MASK_XTILE)) 1027 return 1; 1028 1029 vcpu->arch.xcr0 = xcr0; 1030 1031 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND) 1032 kvm_update_cpuid_runtime(vcpu); 1033 return 0; 1034 } 1035 1036 int kvm_emulate_xsetbv(struct kvm_vcpu *vcpu) 1037 { 1038 if (static_call(kvm_x86_get_cpl)(vcpu) != 0 || 1039 __kvm_set_xcr(vcpu, kvm_rcx_read(vcpu), kvm_read_edx_eax(vcpu))) { 1040 kvm_inject_gp(vcpu, 0); 1041 return 1; 1042 } 1043 1044 return kvm_skip_emulated_instruction(vcpu); 1045 } 1046 EXPORT_SYMBOL_GPL(kvm_emulate_xsetbv); 1047 1048 bool kvm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) 1049 { 1050 if (cr4 & cr4_reserved_bits) 1051 return false; 1052 1053 if (cr4 & vcpu->arch.cr4_guest_rsvd_bits) 1054 return false; 1055 1056 return static_call(kvm_x86_is_valid_cr4)(vcpu, cr4); 1057 } 1058 EXPORT_SYMBOL_GPL(kvm_is_valid_cr4); 1059 1060 void kvm_post_set_cr4(struct kvm_vcpu *vcpu, unsigned long old_cr4, unsigned long cr4) 1061 { 1062 /* 1063 * If any role bit is changed, the MMU needs to be reset. 1064 * 1065 * If CR4.PCIDE is changed 1 -> 0, the guest TLB must be flushed. 1066 * If CR4.PCIDE is changed 0 -> 1, there is no need to flush the TLB 1067 * according to the SDM; however, stale prev_roots could be reused 1068 * incorrectly in the future after a MOV to CR3 with NOFLUSH=1, so we 1069 * free them all. KVM_REQ_MMU_RELOAD is fit for the both cases; it 1070 * is slow, but changing CR4.PCIDE is a rare case. 1071 * 1072 * If CR4.PGE is changed, the guest TLB must be flushed. 1073 * 1074 * Note: resetting MMU is a superset of KVM_REQ_MMU_RELOAD and 1075 * KVM_REQ_MMU_RELOAD is a superset of KVM_REQ_TLB_FLUSH_GUEST, hence 1076 * the usage of "else if". 1077 */ 1078 if ((cr4 ^ old_cr4) & KVM_MMU_CR4_ROLE_BITS) 1079 kvm_mmu_reset_context(vcpu); 1080 else if ((cr4 ^ old_cr4) & X86_CR4_PCIDE) 1081 kvm_make_request(KVM_REQ_MMU_RELOAD, vcpu); 1082 else if ((cr4 ^ old_cr4) & X86_CR4_PGE) 1083 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu); 1084 } 1085 EXPORT_SYMBOL_GPL(kvm_post_set_cr4); 1086 1087 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) 1088 { 1089 unsigned long old_cr4 = kvm_read_cr4(vcpu); 1090 1091 if (!kvm_is_valid_cr4(vcpu, cr4)) 1092 return 1; 1093 1094 if (is_long_mode(vcpu)) { 1095 if (!(cr4 & X86_CR4_PAE)) 1096 return 1; 1097 if ((cr4 ^ old_cr4) & X86_CR4_LA57) 1098 return 1; 1099 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE) 1100 && ((cr4 ^ old_cr4) & X86_CR4_PDPTR_BITS) 1101 && !load_pdptrs(vcpu, kvm_read_cr3(vcpu))) 1102 return 1; 1103 1104 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) { 1105 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID)) 1106 return 1; 1107 1108 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */ 1109 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu)) 1110 return 1; 1111 } 1112 1113 static_call(kvm_x86_set_cr4)(vcpu, cr4); 1114 1115 kvm_post_set_cr4(vcpu, old_cr4, cr4); 1116 1117 return 0; 1118 } 1119 EXPORT_SYMBOL_GPL(kvm_set_cr4); 1120 1121 static void kvm_invalidate_pcid(struct kvm_vcpu *vcpu, unsigned long pcid) 1122 { 1123 struct kvm_mmu *mmu = vcpu->arch.mmu; 1124 unsigned long roots_to_free = 0; 1125 int i; 1126 1127 /* 1128 * MOV CR3 and INVPCID are usually not intercepted when using TDP, but 1129 * this is reachable when running EPT=1 and unrestricted_guest=0, and 1130 * also via the emulator. KVM's TDP page tables are not in the scope of 1131 * the invalidation, but the guest's TLB entries need to be flushed as 1132 * the CPU may have cached entries in its TLB for the target PCID. 1133 */ 1134 if (unlikely(tdp_enabled)) { 1135 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu); 1136 return; 1137 } 1138 1139 /* 1140 * If neither the current CR3 nor any of the prev_roots use the given 1141 * PCID, then nothing needs to be done here because a resync will 1142 * happen anyway before switching to any other CR3. 1143 */ 1144 if (kvm_get_active_pcid(vcpu) == pcid) { 1145 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu); 1146 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); 1147 } 1148 1149 /* 1150 * If PCID is disabled, there is no need to free prev_roots even if the 1151 * PCIDs for them are also 0, because MOV to CR3 always flushes the TLB 1152 * with PCIDE=0. 1153 */ 1154 if (!kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) 1155 return; 1156 1157 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) 1158 if (kvm_get_pcid(vcpu, mmu->prev_roots[i].pgd) == pcid) 1159 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i); 1160 1161 kvm_mmu_free_roots(vcpu, mmu, roots_to_free); 1162 } 1163 1164 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) 1165 { 1166 bool skip_tlb_flush = false; 1167 unsigned long pcid = 0; 1168 #ifdef CONFIG_X86_64 1169 bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE); 1170 1171 if (pcid_enabled) { 1172 skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH; 1173 cr3 &= ~X86_CR3_PCID_NOFLUSH; 1174 pcid = cr3 & X86_CR3_PCID_MASK; 1175 } 1176 #endif 1177 1178 /* PDPTRs are always reloaded for PAE paging. */ 1179 if (cr3 == kvm_read_cr3(vcpu) && !is_pae_paging(vcpu)) 1180 goto handle_tlb_flush; 1181 1182 /* 1183 * Do not condition the GPA check on long mode, this helper is used to 1184 * stuff CR3, e.g. for RSM emulation, and there is no guarantee that 1185 * the current vCPU mode is accurate. 1186 */ 1187 if (kvm_vcpu_is_illegal_gpa(vcpu, cr3)) 1188 return 1; 1189 1190 if (is_pae_paging(vcpu) && !load_pdptrs(vcpu, cr3)) 1191 return 1; 1192 1193 if (cr3 != kvm_read_cr3(vcpu)) 1194 kvm_mmu_new_pgd(vcpu, cr3); 1195 1196 vcpu->arch.cr3 = cr3; 1197 kvm_register_mark_dirty(vcpu, VCPU_EXREG_CR3); 1198 /* Do not call post_set_cr3, we do not get here for confidential guests. */ 1199 1200 handle_tlb_flush: 1201 /* 1202 * A load of CR3 that flushes the TLB flushes only the current PCID, 1203 * even if PCID is disabled, in which case PCID=0 is flushed. It's a 1204 * moot point in the end because _disabling_ PCID will flush all PCIDs, 1205 * and it's impossible to use a non-zero PCID when PCID is disabled, 1206 * i.e. only PCID=0 can be relevant. 1207 */ 1208 if (!skip_tlb_flush) 1209 kvm_invalidate_pcid(vcpu, pcid); 1210 1211 return 0; 1212 } 1213 EXPORT_SYMBOL_GPL(kvm_set_cr3); 1214 1215 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8) 1216 { 1217 if (cr8 & CR8_RESERVED_BITS) 1218 return 1; 1219 if (lapic_in_kernel(vcpu)) 1220 kvm_lapic_set_tpr(vcpu, cr8); 1221 else 1222 vcpu->arch.cr8 = cr8; 1223 return 0; 1224 } 1225 EXPORT_SYMBOL_GPL(kvm_set_cr8); 1226 1227 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu) 1228 { 1229 if (lapic_in_kernel(vcpu)) 1230 return kvm_lapic_get_cr8(vcpu); 1231 else 1232 return vcpu->arch.cr8; 1233 } 1234 EXPORT_SYMBOL_GPL(kvm_get_cr8); 1235 1236 static void kvm_update_dr0123(struct kvm_vcpu *vcpu) 1237 { 1238 int i; 1239 1240 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) { 1241 for (i = 0; i < KVM_NR_DB_REGS; i++) 1242 vcpu->arch.eff_db[i] = vcpu->arch.db[i]; 1243 } 1244 } 1245 1246 void kvm_update_dr7(struct kvm_vcpu *vcpu) 1247 { 1248 unsigned long dr7; 1249 1250 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) 1251 dr7 = vcpu->arch.guest_debug_dr7; 1252 else 1253 dr7 = vcpu->arch.dr7; 1254 static_call(kvm_x86_set_dr7)(vcpu, dr7); 1255 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED; 1256 if (dr7 & DR7_BP_EN_MASK) 1257 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED; 1258 } 1259 EXPORT_SYMBOL_GPL(kvm_update_dr7); 1260 1261 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu) 1262 { 1263 u64 fixed = DR6_FIXED_1; 1264 1265 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM)) 1266 fixed |= DR6_RTM; 1267 1268 if (!guest_cpuid_has(vcpu, X86_FEATURE_BUS_LOCK_DETECT)) 1269 fixed |= DR6_BUS_LOCK; 1270 return fixed; 1271 } 1272 1273 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) 1274 { 1275 size_t size = ARRAY_SIZE(vcpu->arch.db); 1276 1277 switch (dr) { 1278 case 0 ... 3: 1279 vcpu->arch.db[array_index_nospec(dr, size)] = val; 1280 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) 1281 vcpu->arch.eff_db[dr] = val; 1282 break; 1283 case 4: 1284 case 6: 1285 if (!kvm_dr6_valid(val)) 1286 return 1; /* #GP */ 1287 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu); 1288 break; 1289 case 5: 1290 default: /* 7 */ 1291 if (!kvm_dr7_valid(val)) 1292 return 1; /* #GP */ 1293 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1; 1294 kvm_update_dr7(vcpu); 1295 break; 1296 } 1297 1298 return 0; 1299 } 1300 EXPORT_SYMBOL_GPL(kvm_set_dr); 1301 1302 void kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val) 1303 { 1304 size_t size = ARRAY_SIZE(vcpu->arch.db); 1305 1306 switch (dr) { 1307 case 0 ... 3: 1308 *val = vcpu->arch.db[array_index_nospec(dr, size)]; 1309 break; 1310 case 4: 1311 case 6: 1312 *val = vcpu->arch.dr6; 1313 break; 1314 case 5: 1315 default: /* 7 */ 1316 *val = vcpu->arch.dr7; 1317 break; 1318 } 1319 } 1320 EXPORT_SYMBOL_GPL(kvm_get_dr); 1321 1322 int kvm_emulate_rdpmc(struct kvm_vcpu *vcpu) 1323 { 1324 u32 ecx = kvm_rcx_read(vcpu); 1325 u64 data; 1326 1327 if (kvm_pmu_rdpmc(vcpu, ecx, &data)) { 1328 kvm_inject_gp(vcpu, 0); 1329 return 1; 1330 } 1331 1332 kvm_rax_write(vcpu, (u32)data); 1333 kvm_rdx_write(vcpu, data >> 32); 1334 return kvm_skip_emulated_instruction(vcpu); 1335 } 1336 EXPORT_SYMBOL_GPL(kvm_emulate_rdpmc); 1337 1338 /* 1339 * List of msr numbers which we expose to userspace through KVM_GET_MSRS 1340 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST. 1341 * 1342 * The three MSR lists(msrs_to_save, emulated_msrs, msr_based_features) 1343 * extract the supported MSRs from the related const lists. 1344 * msrs_to_save is selected from the msrs_to_save_all to reflect the 1345 * capabilities of the host cpu. This capabilities test skips MSRs that are 1346 * kvm-specific. Those are put in emulated_msrs_all; filtering of emulated_msrs 1347 * may depend on host virtualization features rather than host cpu features. 1348 */ 1349 1350 static const u32 msrs_to_save_all[] = { 1351 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, 1352 MSR_STAR, 1353 #ifdef CONFIG_X86_64 1354 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR, 1355 #endif 1356 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA, 1357 MSR_IA32_FEAT_CTL, MSR_IA32_BNDCFGS, MSR_TSC_AUX, 1358 MSR_IA32_SPEC_CTRL, 1359 MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH, 1360 MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK, 1361 MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B, 1362 MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B, 1363 MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B, 1364 MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B, 1365 MSR_IA32_UMWAIT_CONTROL, 1366 1367 MSR_ARCH_PERFMON_FIXED_CTR0, MSR_ARCH_PERFMON_FIXED_CTR1, 1368 MSR_ARCH_PERFMON_FIXED_CTR0 + 2, 1369 MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_CORE_PERF_GLOBAL_STATUS, 1370 MSR_CORE_PERF_GLOBAL_CTRL, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 1371 MSR_ARCH_PERFMON_PERFCTR0, MSR_ARCH_PERFMON_PERFCTR1, 1372 MSR_ARCH_PERFMON_PERFCTR0 + 2, MSR_ARCH_PERFMON_PERFCTR0 + 3, 1373 MSR_ARCH_PERFMON_PERFCTR0 + 4, MSR_ARCH_PERFMON_PERFCTR0 + 5, 1374 MSR_ARCH_PERFMON_PERFCTR0 + 6, MSR_ARCH_PERFMON_PERFCTR0 + 7, 1375 MSR_ARCH_PERFMON_PERFCTR0 + 8, MSR_ARCH_PERFMON_PERFCTR0 + 9, 1376 MSR_ARCH_PERFMON_PERFCTR0 + 10, MSR_ARCH_PERFMON_PERFCTR0 + 11, 1377 MSR_ARCH_PERFMON_PERFCTR0 + 12, MSR_ARCH_PERFMON_PERFCTR0 + 13, 1378 MSR_ARCH_PERFMON_PERFCTR0 + 14, MSR_ARCH_PERFMON_PERFCTR0 + 15, 1379 MSR_ARCH_PERFMON_PERFCTR0 + 16, MSR_ARCH_PERFMON_PERFCTR0 + 17, 1380 MSR_ARCH_PERFMON_EVENTSEL0, MSR_ARCH_PERFMON_EVENTSEL1, 1381 MSR_ARCH_PERFMON_EVENTSEL0 + 2, MSR_ARCH_PERFMON_EVENTSEL0 + 3, 1382 MSR_ARCH_PERFMON_EVENTSEL0 + 4, MSR_ARCH_PERFMON_EVENTSEL0 + 5, 1383 MSR_ARCH_PERFMON_EVENTSEL0 + 6, MSR_ARCH_PERFMON_EVENTSEL0 + 7, 1384 MSR_ARCH_PERFMON_EVENTSEL0 + 8, MSR_ARCH_PERFMON_EVENTSEL0 + 9, 1385 MSR_ARCH_PERFMON_EVENTSEL0 + 10, MSR_ARCH_PERFMON_EVENTSEL0 + 11, 1386 MSR_ARCH_PERFMON_EVENTSEL0 + 12, MSR_ARCH_PERFMON_EVENTSEL0 + 13, 1387 MSR_ARCH_PERFMON_EVENTSEL0 + 14, MSR_ARCH_PERFMON_EVENTSEL0 + 15, 1388 MSR_ARCH_PERFMON_EVENTSEL0 + 16, MSR_ARCH_PERFMON_EVENTSEL0 + 17, 1389 1390 MSR_K7_EVNTSEL0, MSR_K7_EVNTSEL1, MSR_K7_EVNTSEL2, MSR_K7_EVNTSEL3, 1391 MSR_K7_PERFCTR0, MSR_K7_PERFCTR1, MSR_K7_PERFCTR2, MSR_K7_PERFCTR3, 1392 MSR_F15H_PERF_CTL0, MSR_F15H_PERF_CTL1, MSR_F15H_PERF_CTL2, 1393 MSR_F15H_PERF_CTL3, MSR_F15H_PERF_CTL4, MSR_F15H_PERF_CTL5, 1394 MSR_F15H_PERF_CTR0, MSR_F15H_PERF_CTR1, MSR_F15H_PERF_CTR2, 1395 MSR_F15H_PERF_CTR3, MSR_F15H_PERF_CTR4, MSR_F15H_PERF_CTR5, 1396 MSR_IA32_XFD, MSR_IA32_XFD_ERR, 1397 }; 1398 1399 static u32 msrs_to_save[ARRAY_SIZE(msrs_to_save_all)]; 1400 static unsigned num_msrs_to_save; 1401 1402 static const u32 emulated_msrs_all[] = { 1403 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK, 1404 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW, 1405 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL, 1406 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC, 1407 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY, 1408 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2, 1409 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL, 1410 HV_X64_MSR_RESET, 1411 HV_X64_MSR_VP_INDEX, 1412 HV_X64_MSR_VP_RUNTIME, 1413 HV_X64_MSR_SCONTROL, 1414 HV_X64_MSR_STIMER0_CONFIG, 1415 HV_X64_MSR_VP_ASSIST_PAGE, 1416 HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL, 1417 HV_X64_MSR_TSC_EMULATION_STATUS, 1418 HV_X64_MSR_SYNDBG_OPTIONS, 1419 HV_X64_MSR_SYNDBG_CONTROL, HV_X64_MSR_SYNDBG_STATUS, 1420 HV_X64_MSR_SYNDBG_SEND_BUFFER, HV_X64_MSR_SYNDBG_RECV_BUFFER, 1421 HV_X64_MSR_SYNDBG_PENDING_BUFFER, 1422 1423 MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME, 1424 MSR_KVM_PV_EOI_EN, MSR_KVM_ASYNC_PF_INT, MSR_KVM_ASYNC_PF_ACK, 1425 1426 MSR_IA32_TSC_ADJUST, 1427 MSR_IA32_TSC_DEADLINE, 1428 MSR_IA32_ARCH_CAPABILITIES, 1429 MSR_IA32_PERF_CAPABILITIES, 1430 MSR_IA32_MISC_ENABLE, 1431 MSR_IA32_MCG_STATUS, 1432 MSR_IA32_MCG_CTL, 1433 MSR_IA32_MCG_EXT_CTL, 1434 MSR_IA32_SMBASE, 1435 MSR_SMI_COUNT, 1436 MSR_PLATFORM_INFO, 1437 MSR_MISC_FEATURES_ENABLES, 1438 MSR_AMD64_VIRT_SPEC_CTRL, 1439 MSR_AMD64_TSC_RATIO, 1440 MSR_IA32_POWER_CTL, 1441 MSR_IA32_UCODE_REV, 1442 1443 /* 1444 * The following list leaves out MSRs whose values are determined 1445 * by arch/x86/kvm/vmx/nested.c based on CPUID or other MSRs. 1446 * We always support the "true" VMX control MSRs, even if the host 1447 * processor does not, so I am putting these registers here rather 1448 * than in msrs_to_save_all. 1449 */ 1450 MSR_IA32_VMX_BASIC, 1451 MSR_IA32_VMX_TRUE_PINBASED_CTLS, 1452 MSR_IA32_VMX_TRUE_PROCBASED_CTLS, 1453 MSR_IA32_VMX_TRUE_EXIT_CTLS, 1454 MSR_IA32_VMX_TRUE_ENTRY_CTLS, 1455 MSR_IA32_VMX_MISC, 1456 MSR_IA32_VMX_CR0_FIXED0, 1457 MSR_IA32_VMX_CR4_FIXED0, 1458 MSR_IA32_VMX_VMCS_ENUM, 1459 MSR_IA32_VMX_PROCBASED_CTLS2, 1460 MSR_IA32_VMX_EPT_VPID_CAP, 1461 MSR_IA32_VMX_VMFUNC, 1462 1463 MSR_K7_HWCR, 1464 MSR_KVM_POLL_CONTROL, 1465 }; 1466 1467 static u32 emulated_msrs[ARRAY_SIZE(emulated_msrs_all)]; 1468 static unsigned num_emulated_msrs; 1469 1470 /* 1471 * List of msr numbers which are used to expose MSR-based features that 1472 * can be used by a hypervisor to validate requested CPU features. 1473 */ 1474 static const u32 msr_based_features_all[] = { 1475 MSR_IA32_VMX_BASIC, 1476 MSR_IA32_VMX_TRUE_PINBASED_CTLS, 1477 MSR_IA32_VMX_PINBASED_CTLS, 1478 MSR_IA32_VMX_TRUE_PROCBASED_CTLS, 1479 MSR_IA32_VMX_PROCBASED_CTLS, 1480 MSR_IA32_VMX_TRUE_EXIT_CTLS, 1481 MSR_IA32_VMX_EXIT_CTLS, 1482 MSR_IA32_VMX_TRUE_ENTRY_CTLS, 1483 MSR_IA32_VMX_ENTRY_CTLS, 1484 MSR_IA32_VMX_MISC, 1485 MSR_IA32_VMX_CR0_FIXED0, 1486 MSR_IA32_VMX_CR0_FIXED1, 1487 MSR_IA32_VMX_CR4_FIXED0, 1488 MSR_IA32_VMX_CR4_FIXED1, 1489 MSR_IA32_VMX_VMCS_ENUM, 1490 MSR_IA32_VMX_PROCBASED_CTLS2, 1491 MSR_IA32_VMX_EPT_VPID_CAP, 1492 MSR_IA32_VMX_VMFUNC, 1493 1494 MSR_F10H_DECFG, 1495 MSR_IA32_UCODE_REV, 1496 MSR_IA32_ARCH_CAPABILITIES, 1497 MSR_IA32_PERF_CAPABILITIES, 1498 }; 1499 1500 static u32 msr_based_features[ARRAY_SIZE(msr_based_features_all)]; 1501 static unsigned int num_msr_based_features; 1502 1503 static u64 kvm_get_arch_capabilities(void) 1504 { 1505 u64 data = 0; 1506 1507 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) 1508 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, data); 1509 1510 /* 1511 * If nx_huge_pages is enabled, KVM's shadow paging will ensure that 1512 * the nested hypervisor runs with NX huge pages. If it is not, 1513 * L1 is anyway vulnerable to ITLB_MULTIHIT exploits from other 1514 * L1 guests, so it need not worry about its own (L2) guests. 1515 */ 1516 data |= ARCH_CAP_PSCHANGE_MC_NO; 1517 1518 /* 1519 * If we're doing cache flushes (either "always" or "cond") 1520 * we will do one whenever the guest does a vmlaunch/vmresume. 1521 * If an outer hypervisor is doing the cache flush for us 1522 * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that 1523 * capability to the guest too, and if EPT is disabled we're not 1524 * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will 1525 * require a nested hypervisor to do a flush of its own. 1526 */ 1527 if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER) 1528 data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH; 1529 1530 if (!boot_cpu_has_bug(X86_BUG_CPU_MELTDOWN)) 1531 data |= ARCH_CAP_RDCL_NO; 1532 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) 1533 data |= ARCH_CAP_SSB_NO; 1534 if (!boot_cpu_has_bug(X86_BUG_MDS)) 1535 data |= ARCH_CAP_MDS_NO; 1536 1537 if (!boot_cpu_has(X86_FEATURE_RTM)) { 1538 /* 1539 * If RTM=0 because the kernel has disabled TSX, the host might 1540 * have TAA_NO or TSX_CTRL. Clear TAA_NO (the guest sees RTM=0 1541 * and therefore knows that there cannot be TAA) but keep 1542 * TSX_CTRL: some buggy userspaces leave it set on tsx=on hosts, 1543 * and we want to allow migrating those guests to tsx=off hosts. 1544 */ 1545 data &= ~ARCH_CAP_TAA_NO; 1546 } else if (!boot_cpu_has_bug(X86_BUG_TAA)) { 1547 data |= ARCH_CAP_TAA_NO; 1548 } else { 1549 /* 1550 * Nothing to do here; we emulate TSX_CTRL if present on the 1551 * host so the guest can choose between disabling TSX or 1552 * using VERW to clear CPU buffers. 1553 */ 1554 } 1555 1556 return data; 1557 } 1558 1559 static int kvm_get_msr_feature(struct kvm_msr_entry *msr) 1560 { 1561 switch (msr->index) { 1562 case MSR_IA32_ARCH_CAPABILITIES: 1563 msr->data = kvm_get_arch_capabilities(); 1564 break; 1565 case MSR_IA32_UCODE_REV: 1566 rdmsrl_safe(msr->index, &msr->data); 1567 break; 1568 default: 1569 return static_call(kvm_x86_get_msr_feature)(msr); 1570 } 1571 return 0; 1572 } 1573 1574 static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data) 1575 { 1576 struct kvm_msr_entry msr; 1577 int r; 1578 1579 msr.index = index; 1580 r = kvm_get_msr_feature(&msr); 1581 1582 if (r == KVM_MSR_RET_INVALID) { 1583 /* Unconditionally clear the output for simplicity */ 1584 *data = 0; 1585 if (kvm_msr_ignored_check(index, 0, false)) 1586 r = 0; 1587 } 1588 1589 if (r) 1590 return r; 1591 1592 *data = msr.data; 1593 1594 return 0; 1595 } 1596 1597 static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) 1598 { 1599 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT)) 1600 return false; 1601 1602 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM)) 1603 return false; 1604 1605 if (efer & (EFER_LME | EFER_LMA) && 1606 !guest_cpuid_has(vcpu, X86_FEATURE_LM)) 1607 return false; 1608 1609 if (efer & EFER_NX && !guest_cpuid_has(vcpu, X86_FEATURE_NX)) 1610 return false; 1611 1612 return true; 1613 1614 } 1615 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) 1616 { 1617 if (efer & efer_reserved_bits) 1618 return false; 1619 1620 return __kvm_valid_efer(vcpu, efer); 1621 } 1622 EXPORT_SYMBOL_GPL(kvm_valid_efer); 1623 1624 static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 1625 { 1626 u64 old_efer = vcpu->arch.efer; 1627 u64 efer = msr_info->data; 1628 int r; 1629 1630 if (efer & efer_reserved_bits) 1631 return 1; 1632 1633 if (!msr_info->host_initiated) { 1634 if (!__kvm_valid_efer(vcpu, efer)) 1635 return 1; 1636 1637 if (is_paging(vcpu) && 1638 (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME)) 1639 return 1; 1640 } 1641 1642 efer &= ~EFER_LMA; 1643 efer |= vcpu->arch.efer & EFER_LMA; 1644 1645 r = static_call(kvm_x86_set_efer)(vcpu, efer); 1646 if (r) { 1647 WARN_ON(r > 0); 1648 return r; 1649 } 1650 1651 if ((efer ^ old_efer) & KVM_MMU_EFER_ROLE_BITS) 1652 kvm_mmu_reset_context(vcpu); 1653 1654 return 0; 1655 } 1656 1657 void kvm_enable_efer_bits(u64 mask) 1658 { 1659 efer_reserved_bits &= ~mask; 1660 } 1661 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits); 1662 1663 bool kvm_msr_allowed(struct kvm_vcpu *vcpu, u32 index, u32 type) 1664 { 1665 struct kvm_x86_msr_filter *msr_filter; 1666 struct msr_bitmap_range *ranges; 1667 struct kvm *kvm = vcpu->kvm; 1668 bool allowed; 1669 int idx; 1670 u32 i; 1671 1672 /* x2APIC MSRs do not support filtering. */ 1673 if (index >= 0x800 && index <= 0x8ff) 1674 return true; 1675 1676 idx = srcu_read_lock(&kvm->srcu); 1677 1678 msr_filter = srcu_dereference(kvm->arch.msr_filter, &kvm->srcu); 1679 if (!msr_filter) { 1680 allowed = true; 1681 goto out; 1682 } 1683 1684 allowed = msr_filter->default_allow; 1685 ranges = msr_filter->ranges; 1686 1687 for (i = 0; i < msr_filter->count; i++) { 1688 u32 start = ranges[i].base; 1689 u32 end = start + ranges[i].nmsrs; 1690 u32 flags = ranges[i].flags; 1691 unsigned long *bitmap = ranges[i].bitmap; 1692 1693 if ((index >= start) && (index < end) && (flags & type)) { 1694 allowed = !!test_bit(index - start, bitmap); 1695 break; 1696 } 1697 } 1698 1699 out: 1700 srcu_read_unlock(&kvm->srcu, idx); 1701 1702 return allowed; 1703 } 1704 EXPORT_SYMBOL_GPL(kvm_msr_allowed); 1705 1706 /* 1707 * Write @data into the MSR specified by @index. Select MSR specific fault 1708 * checks are bypassed if @host_initiated is %true. 1709 * Returns 0 on success, non-0 otherwise. 1710 * Assumes vcpu_load() was already called. 1711 */ 1712 static int __kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data, 1713 bool host_initiated) 1714 { 1715 struct msr_data msr; 1716 1717 if (!host_initiated && !kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_WRITE)) 1718 return KVM_MSR_RET_FILTERED; 1719 1720 switch (index) { 1721 case MSR_FS_BASE: 1722 case MSR_GS_BASE: 1723 case MSR_KERNEL_GS_BASE: 1724 case MSR_CSTAR: 1725 case MSR_LSTAR: 1726 if (is_noncanonical_address(data, vcpu)) 1727 return 1; 1728 break; 1729 case MSR_IA32_SYSENTER_EIP: 1730 case MSR_IA32_SYSENTER_ESP: 1731 /* 1732 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if 1733 * non-canonical address is written on Intel but not on 1734 * AMD (which ignores the top 32-bits, because it does 1735 * not implement 64-bit SYSENTER). 1736 * 1737 * 64-bit code should hence be able to write a non-canonical 1738 * value on AMD. Making the address canonical ensures that 1739 * vmentry does not fail on Intel after writing a non-canonical 1740 * value, and that something deterministic happens if the guest 1741 * invokes 64-bit SYSENTER. 1742 */ 1743 data = get_canonical(data, vcpu_virt_addr_bits(vcpu)); 1744 break; 1745 case MSR_TSC_AUX: 1746 if (!kvm_is_supported_user_return_msr(MSR_TSC_AUX)) 1747 return 1; 1748 1749 if (!host_initiated && 1750 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP) && 1751 !guest_cpuid_has(vcpu, X86_FEATURE_RDPID)) 1752 return 1; 1753 1754 /* 1755 * Per Intel's SDM, bits 63:32 are reserved, but AMD's APM has 1756 * incomplete and conflicting architectural behavior. Current 1757 * AMD CPUs completely ignore bits 63:32, i.e. they aren't 1758 * reserved and always read as zeros. Enforce Intel's reserved 1759 * bits check if and only if the guest CPU is Intel, and clear 1760 * the bits in all other cases. This ensures cross-vendor 1761 * migration will provide consistent behavior for the guest. 1762 */ 1763 if (guest_cpuid_is_intel(vcpu) && (data >> 32) != 0) 1764 return 1; 1765 1766 data = (u32)data; 1767 break; 1768 } 1769 1770 msr.data = data; 1771 msr.index = index; 1772 msr.host_initiated = host_initiated; 1773 1774 return static_call(kvm_x86_set_msr)(vcpu, &msr); 1775 } 1776 1777 static int kvm_set_msr_ignored_check(struct kvm_vcpu *vcpu, 1778 u32 index, u64 data, bool host_initiated) 1779 { 1780 int ret = __kvm_set_msr(vcpu, index, data, host_initiated); 1781 1782 if (ret == KVM_MSR_RET_INVALID) 1783 if (kvm_msr_ignored_check(index, data, true)) 1784 ret = 0; 1785 1786 return ret; 1787 } 1788 1789 /* 1790 * Read the MSR specified by @index into @data. Select MSR specific fault 1791 * checks are bypassed if @host_initiated is %true. 1792 * Returns 0 on success, non-0 otherwise. 1793 * Assumes vcpu_load() was already called. 1794 */ 1795 int __kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data, 1796 bool host_initiated) 1797 { 1798 struct msr_data msr; 1799 int ret; 1800 1801 if (!host_initiated && !kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_READ)) 1802 return KVM_MSR_RET_FILTERED; 1803 1804 switch (index) { 1805 case MSR_TSC_AUX: 1806 if (!kvm_is_supported_user_return_msr(MSR_TSC_AUX)) 1807 return 1; 1808 1809 if (!host_initiated && 1810 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP) && 1811 !guest_cpuid_has(vcpu, X86_FEATURE_RDPID)) 1812 return 1; 1813 break; 1814 } 1815 1816 msr.index = index; 1817 msr.host_initiated = host_initiated; 1818 1819 ret = static_call(kvm_x86_get_msr)(vcpu, &msr); 1820 if (!ret) 1821 *data = msr.data; 1822 return ret; 1823 } 1824 1825 static int kvm_get_msr_ignored_check(struct kvm_vcpu *vcpu, 1826 u32 index, u64 *data, bool host_initiated) 1827 { 1828 int ret = __kvm_get_msr(vcpu, index, data, host_initiated); 1829 1830 if (ret == KVM_MSR_RET_INVALID) { 1831 /* Unconditionally clear *data for simplicity */ 1832 *data = 0; 1833 if (kvm_msr_ignored_check(index, 0, false)) 1834 ret = 0; 1835 } 1836 1837 return ret; 1838 } 1839 1840 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data) 1841 { 1842 return kvm_get_msr_ignored_check(vcpu, index, data, false); 1843 } 1844 EXPORT_SYMBOL_GPL(kvm_get_msr); 1845 1846 int kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data) 1847 { 1848 return kvm_set_msr_ignored_check(vcpu, index, data, false); 1849 } 1850 EXPORT_SYMBOL_GPL(kvm_set_msr); 1851 1852 static void complete_userspace_rdmsr(struct kvm_vcpu *vcpu) 1853 { 1854 if (!vcpu->run->msr.error) { 1855 kvm_rax_write(vcpu, (u32)vcpu->run->msr.data); 1856 kvm_rdx_write(vcpu, vcpu->run->msr.data >> 32); 1857 } 1858 } 1859 1860 static int complete_emulated_msr_access(struct kvm_vcpu *vcpu) 1861 { 1862 return complete_emulated_insn_gp(vcpu, vcpu->run->msr.error); 1863 } 1864 1865 static int complete_emulated_rdmsr(struct kvm_vcpu *vcpu) 1866 { 1867 complete_userspace_rdmsr(vcpu); 1868 return complete_emulated_msr_access(vcpu); 1869 } 1870 1871 static int complete_fast_msr_access(struct kvm_vcpu *vcpu) 1872 { 1873 return static_call(kvm_x86_complete_emulated_msr)(vcpu, vcpu->run->msr.error); 1874 } 1875 1876 static int complete_fast_rdmsr(struct kvm_vcpu *vcpu) 1877 { 1878 complete_userspace_rdmsr(vcpu); 1879 return complete_fast_msr_access(vcpu); 1880 } 1881 1882 static u64 kvm_msr_reason(int r) 1883 { 1884 switch (r) { 1885 case KVM_MSR_RET_INVALID: 1886 return KVM_MSR_EXIT_REASON_UNKNOWN; 1887 case KVM_MSR_RET_FILTERED: 1888 return KVM_MSR_EXIT_REASON_FILTER; 1889 default: 1890 return KVM_MSR_EXIT_REASON_INVAL; 1891 } 1892 } 1893 1894 static int kvm_msr_user_space(struct kvm_vcpu *vcpu, u32 index, 1895 u32 exit_reason, u64 data, 1896 int (*completion)(struct kvm_vcpu *vcpu), 1897 int r) 1898 { 1899 u64 msr_reason = kvm_msr_reason(r); 1900 1901 /* Check if the user wanted to know about this MSR fault */ 1902 if (!(vcpu->kvm->arch.user_space_msr_mask & msr_reason)) 1903 return 0; 1904 1905 vcpu->run->exit_reason = exit_reason; 1906 vcpu->run->msr.error = 0; 1907 memset(vcpu->run->msr.pad, 0, sizeof(vcpu->run->msr.pad)); 1908 vcpu->run->msr.reason = msr_reason; 1909 vcpu->run->msr.index = index; 1910 vcpu->run->msr.data = data; 1911 vcpu->arch.complete_userspace_io = completion; 1912 1913 return 1; 1914 } 1915 1916 int kvm_emulate_rdmsr(struct kvm_vcpu *vcpu) 1917 { 1918 u32 ecx = kvm_rcx_read(vcpu); 1919 u64 data; 1920 int r; 1921 1922 r = kvm_get_msr(vcpu, ecx, &data); 1923 1924 if (!r) { 1925 trace_kvm_msr_read(ecx, data); 1926 1927 kvm_rax_write(vcpu, data & -1u); 1928 kvm_rdx_write(vcpu, (data >> 32) & -1u); 1929 } else { 1930 /* MSR read failed? See if we should ask user space */ 1931 if (kvm_msr_user_space(vcpu, ecx, KVM_EXIT_X86_RDMSR, 0, 1932 complete_fast_rdmsr, r)) 1933 return 0; 1934 trace_kvm_msr_read_ex(ecx); 1935 } 1936 1937 return static_call(kvm_x86_complete_emulated_msr)(vcpu, r); 1938 } 1939 EXPORT_SYMBOL_GPL(kvm_emulate_rdmsr); 1940 1941 int kvm_emulate_wrmsr(struct kvm_vcpu *vcpu) 1942 { 1943 u32 ecx = kvm_rcx_read(vcpu); 1944 u64 data = kvm_read_edx_eax(vcpu); 1945 int r; 1946 1947 r = kvm_set_msr(vcpu, ecx, data); 1948 1949 if (!r) { 1950 trace_kvm_msr_write(ecx, data); 1951 } else { 1952 /* MSR write failed? See if we should ask user space */ 1953 if (kvm_msr_user_space(vcpu, ecx, KVM_EXIT_X86_WRMSR, data, 1954 complete_fast_msr_access, r)) 1955 return 0; 1956 /* Signal all other negative errors to userspace */ 1957 if (r < 0) 1958 return r; 1959 trace_kvm_msr_write_ex(ecx, data); 1960 } 1961 1962 return static_call(kvm_x86_complete_emulated_msr)(vcpu, r); 1963 } 1964 EXPORT_SYMBOL_GPL(kvm_emulate_wrmsr); 1965 1966 int kvm_emulate_as_nop(struct kvm_vcpu *vcpu) 1967 { 1968 return kvm_skip_emulated_instruction(vcpu); 1969 } 1970 EXPORT_SYMBOL_GPL(kvm_emulate_as_nop); 1971 1972 int kvm_emulate_invd(struct kvm_vcpu *vcpu) 1973 { 1974 /* Treat an INVD instruction as a NOP and just skip it. */ 1975 return kvm_emulate_as_nop(vcpu); 1976 } 1977 EXPORT_SYMBOL_GPL(kvm_emulate_invd); 1978 1979 int kvm_emulate_mwait(struct kvm_vcpu *vcpu) 1980 { 1981 pr_warn_once("kvm: MWAIT instruction emulated as NOP!\n"); 1982 return kvm_emulate_as_nop(vcpu); 1983 } 1984 EXPORT_SYMBOL_GPL(kvm_emulate_mwait); 1985 1986 int kvm_handle_invalid_op(struct kvm_vcpu *vcpu) 1987 { 1988 kvm_queue_exception(vcpu, UD_VECTOR); 1989 return 1; 1990 } 1991 EXPORT_SYMBOL_GPL(kvm_handle_invalid_op); 1992 1993 int kvm_emulate_monitor(struct kvm_vcpu *vcpu) 1994 { 1995 pr_warn_once("kvm: MONITOR instruction emulated as NOP!\n"); 1996 return kvm_emulate_as_nop(vcpu); 1997 } 1998 EXPORT_SYMBOL_GPL(kvm_emulate_monitor); 1999 2000 static inline bool kvm_vcpu_exit_request(struct kvm_vcpu *vcpu) 2001 { 2002 xfer_to_guest_mode_prepare(); 2003 return vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu) || 2004 xfer_to_guest_mode_work_pending(); 2005 } 2006 2007 /* 2008 * The fast path for frequent and performance sensitive wrmsr emulation, 2009 * i.e. the sending of IPI, sending IPI early in the VM-Exit flow reduces 2010 * the latency of virtual IPI by avoiding the expensive bits of transitioning 2011 * from guest to host, e.g. reacquiring KVM's SRCU lock. In contrast to the 2012 * other cases which must be called after interrupts are enabled on the host. 2013 */ 2014 static int handle_fastpath_set_x2apic_icr_irqoff(struct kvm_vcpu *vcpu, u64 data) 2015 { 2016 if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(vcpu->arch.apic)) 2017 return 1; 2018 2019 if (((data & APIC_SHORT_MASK) == APIC_DEST_NOSHORT) && 2020 ((data & APIC_DEST_MASK) == APIC_DEST_PHYSICAL) && 2021 ((data & APIC_MODE_MASK) == APIC_DM_FIXED) && 2022 ((u32)(data >> 32) != X2APIC_BROADCAST)) { 2023 2024 data &= ~(1 << 12); 2025 kvm_apic_send_ipi(vcpu->arch.apic, (u32)data, (u32)(data >> 32)); 2026 kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR2, (u32)(data >> 32)); 2027 kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR, (u32)data); 2028 trace_kvm_apic_write(APIC_ICR, (u32)data); 2029 return 0; 2030 } 2031 2032 return 1; 2033 } 2034 2035 static int handle_fastpath_set_tscdeadline(struct kvm_vcpu *vcpu, u64 data) 2036 { 2037 if (!kvm_can_use_hv_timer(vcpu)) 2038 return 1; 2039 2040 kvm_set_lapic_tscdeadline_msr(vcpu, data); 2041 return 0; 2042 } 2043 2044 fastpath_t handle_fastpath_set_msr_irqoff(struct kvm_vcpu *vcpu) 2045 { 2046 u32 msr = kvm_rcx_read(vcpu); 2047 u64 data; 2048 fastpath_t ret = EXIT_FASTPATH_NONE; 2049 2050 switch (msr) { 2051 case APIC_BASE_MSR + (APIC_ICR >> 4): 2052 data = kvm_read_edx_eax(vcpu); 2053 if (!handle_fastpath_set_x2apic_icr_irqoff(vcpu, data)) { 2054 kvm_skip_emulated_instruction(vcpu); 2055 ret = EXIT_FASTPATH_EXIT_HANDLED; 2056 } 2057 break; 2058 case MSR_IA32_TSC_DEADLINE: 2059 data = kvm_read_edx_eax(vcpu); 2060 if (!handle_fastpath_set_tscdeadline(vcpu, data)) { 2061 kvm_skip_emulated_instruction(vcpu); 2062 ret = EXIT_FASTPATH_REENTER_GUEST; 2063 } 2064 break; 2065 default: 2066 break; 2067 } 2068 2069 if (ret != EXIT_FASTPATH_NONE) 2070 trace_kvm_msr_write(msr, data); 2071 2072 return ret; 2073 } 2074 EXPORT_SYMBOL_GPL(handle_fastpath_set_msr_irqoff); 2075 2076 /* 2077 * Adapt set_msr() to msr_io()'s calling convention 2078 */ 2079 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) 2080 { 2081 return kvm_get_msr_ignored_check(vcpu, index, data, true); 2082 } 2083 2084 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) 2085 { 2086 return kvm_set_msr_ignored_check(vcpu, index, *data, true); 2087 } 2088 2089 #ifdef CONFIG_X86_64 2090 struct pvclock_clock { 2091 int vclock_mode; 2092 u64 cycle_last; 2093 u64 mask; 2094 u32 mult; 2095 u32 shift; 2096 u64 base_cycles; 2097 u64 offset; 2098 }; 2099 2100 struct pvclock_gtod_data { 2101 seqcount_t seq; 2102 2103 struct pvclock_clock clock; /* extract of a clocksource struct */ 2104 struct pvclock_clock raw_clock; /* extract of a clocksource struct */ 2105 2106 ktime_t offs_boot; 2107 u64 wall_time_sec; 2108 }; 2109 2110 static struct pvclock_gtod_data pvclock_gtod_data; 2111 2112 static void update_pvclock_gtod(struct timekeeper *tk) 2113 { 2114 struct pvclock_gtod_data *vdata = &pvclock_gtod_data; 2115 2116 write_seqcount_begin(&vdata->seq); 2117 2118 /* copy pvclock gtod data */ 2119 vdata->clock.vclock_mode = tk->tkr_mono.clock->vdso_clock_mode; 2120 vdata->clock.cycle_last = tk->tkr_mono.cycle_last; 2121 vdata->clock.mask = tk->tkr_mono.mask; 2122 vdata->clock.mult = tk->tkr_mono.mult; 2123 vdata->clock.shift = tk->tkr_mono.shift; 2124 vdata->clock.base_cycles = tk->tkr_mono.xtime_nsec; 2125 vdata->clock.offset = tk->tkr_mono.base; 2126 2127 vdata->raw_clock.vclock_mode = tk->tkr_raw.clock->vdso_clock_mode; 2128 vdata->raw_clock.cycle_last = tk->tkr_raw.cycle_last; 2129 vdata->raw_clock.mask = tk->tkr_raw.mask; 2130 vdata->raw_clock.mult = tk->tkr_raw.mult; 2131 vdata->raw_clock.shift = tk->tkr_raw.shift; 2132 vdata->raw_clock.base_cycles = tk->tkr_raw.xtime_nsec; 2133 vdata->raw_clock.offset = tk->tkr_raw.base; 2134 2135 vdata->wall_time_sec = tk->xtime_sec; 2136 2137 vdata->offs_boot = tk->offs_boot; 2138 2139 write_seqcount_end(&vdata->seq); 2140 } 2141 2142 static s64 get_kvmclock_base_ns(void) 2143 { 2144 /* Count up from boot time, but with the frequency of the raw clock. */ 2145 return ktime_to_ns(ktime_add(ktime_get_raw(), pvclock_gtod_data.offs_boot)); 2146 } 2147 #else 2148 static s64 get_kvmclock_base_ns(void) 2149 { 2150 /* Master clock not used, so we can just use CLOCK_BOOTTIME. */ 2151 return ktime_get_boottime_ns(); 2152 } 2153 #endif 2154 2155 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock, int sec_hi_ofs) 2156 { 2157 int version; 2158 int r; 2159 struct pvclock_wall_clock wc; 2160 u32 wc_sec_hi; 2161 u64 wall_nsec; 2162 2163 if (!wall_clock) 2164 return; 2165 2166 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version)); 2167 if (r) 2168 return; 2169 2170 if (version & 1) 2171 ++version; /* first time write, random junk */ 2172 2173 ++version; 2174 2175 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version))) 2176 return; 2177 2178 /* 2179 * The guest calculates current wall clock time by adding 2180 * system time (updated by kvm_guest_time_update below) to the 2181 * wall clock specified here. We do the reverse here. 2182 */ 2183 wall_nsec = ktime_get_real_ns() - get_kvmclock_ns(kvm); 2184 2185 wc.nsec = do_div(wall_nsec, 1000000000); 2186 wc.sec = (u32)wall_nsec; /* overflow in 2106 guest time */ 2187 wc.version = version; 2188 2189 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc)); 2190 2191 if (sec_hi_ofs) { 2192 wc_sec_hi = wall_nsec >> 32; 2193 kvm_write_guest(kvm, wall_clock + sec_hi_ofs, 2194 &wc_sec_hi, sizeof(wc_sec_hi)); 2195 } 2196 2197 version++; 2198 kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); 2199 } 2200 2201 static void kvm_write_system_time(struct kvm_vcpu *vcpu, gpa_t system_time, 2202 bool old_msr, bool host_initiated) 2203 { 2204 struct kvm_arch *ka = &vcpu->kvm->arch; 2205 2206 if (vcpu->vcpu_id == 0 && !host_initiated) { 2207 if (ka->boot_vcpu_runs_old_kvmclock != old_msr) 2208 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 2209 2210 ka->boot_vcpu_runs_old_kvmclock = old_msr; 2211 } 2212 2213 vcpu->arch.time = system_time; 2214 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); 2215 2216 /* we verify if the enable bit is set... */ 2217 vcpu->arch.pv_time_enabled = false; 2218 if (!(system_time & 1)) 2219 return; 2220 2221 if (!kvm_gfn_to_hva_cache_init(vcpu->kvm, 2222 &vcpu->arch.pv_time, system_time & ~1ULL, 2223 sizeof(struct pvclock_vcpu_time_info))) 2224 vcpu->arch.pv_time_enabled = true; 2225 2226 return; 2227 } 2228 2229 static uint32_t div_frac(uint32_t dividend, uint32_t divisor) 2230 { 2231 do_shl32_div32(dividend, divisor); 2232 return dividend; 2233 } 2234 2235 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz, 2236 s8 *pshift, u32 *pmultiplier) 2237 { 2238 uint64_t scaled64; 2239 int32_t shift = 0; 2240 uint64_t tps64; 2241 uint32_t tps32; 2242 2243 tps64 = base_hz; 2244 scaled64 = scaled_hz; 2245 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) { 2246 tps64 >>= 1; 2247 shift--; 2248 } 2249 2250 tps32 = (uint32_t)tps64; 2251 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) { 2252 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000) 2253 scaled64 >>= 1; 2254 else 2255 tps32 <<= 1; 2256 shift++; 2257 } 2258 2259 *pshift = shift; 2260 *pmultiplier = div_frac(scaled64, tps32); 2261 } 2262 2263 #ifdef CONFIG_X86_64 2264 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0); 2265 #endif 2266 2267 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz); 2268 static unsigned long max_tsc_khz; 2269 2270 static u32 adjust_tsc_khz(u32 khz, s32 ppm) 2271 { 2272 u64 v = (u64)khz * (1000000 + ppm); 2273 do_div(v, 1000000); 2274 return v; 2275 } 2276 2277 static void kvm_vcpu_write_tsc_multiplier(struct kvm_vcpu *vcpu, u64 l1_multiplier); 2278 2279 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale) 2280 { 2281 u64 ratio; 2282 2283 /* Guest TSC same frequency as host TSC? */ 2284 if (!scale) { 2285 kvm_vcpu_write_tsc_multiplier(vcpu, kvm_default_tsc_scaling_ratio); 2286 return 0; 2287 } 2288 2289 /* TSC scaling supported? */ 2290 if (!kvm_has_tsc_control) { 2291 if (user_tsc_khz > tsc_khz) { 2292 vcpu->arch.tsc_catchup = 1; 2293 vcpu->arch.tsc_always_catchup = 1; 2294 return 0; 2295 } else { 2296 pr_warn_ratelimited("user requested TSC rate below hardware speed\n"); 2297 return -1; 2298 } 2299 } 2300 2301 /* TSC scaling required - calculate ratio */ 2302 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits, 2303 user_tsc_khz, tsc_khz); 2304 2305 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) { 2306 pr_warn_ratelimited("Invalid TSC scaling ratio - virtual-tsc-khz=%u\n", 2307 user_tsc_khz); 2308 return -1; 2309 } 2310 2311 kvm_vcpu_write_tsc_multiplier(vcpu, ratio); 2312 return 0; 2313 } 2314 2315 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz) 2316 { 2317 u32 thresh_lo, thresh_hi; 2318 int use_scaling = 0; 2319 2320 /* tsc_khz can be zero if TSC calibration fails */ 2321 if (user_tsc_khz == 0) { 2322 /* set tsc_scaling_ratio to a safe value */ 2323 kvm_vcpu_write_tsc_multiplier(vcpu, kvm_default_tsc_scaling_ratio); 2324 return -1; 2325 } 2326 2327 /* Compute a scale to convert nanoseconds in TSC cycles */ 2328 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC, 2329 &vcpu->arch.virtual_tsc_shift, 2330 &vcpu->arch.virtual_tsc_mult); 2331 vcpu->arch.virtual_tsc_khz = user_tsc_khz; 2332 2333 /* 2334 * Compute the variation in TSC rate which is acceptable 2335 * within the range of tolerance and decide if the 2336 * rate being applied is within that bounds of the hardware 2337 * rate. If so, no scaling or compensation need be done. 2338 */ 2339 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm); 2340 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm); 2341 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) { 2342 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi); 2343 use_scaling = 1; 2344 } 2345 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling); 2346 } 2347 2348 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns) 2349 { 2350 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec, 2351 vcpu->arch.virtual_tsc_mult, 2352 vcpu->arch.virtual_tsc_shift); 2353 tsc += vcpu->arch.this_tsc_write; 2354 return tsc; 2355 } 2356 2357 static inline int gtod_is_based_on_tsc(int mode) 2358 { 2359 return mode == VDSO_CLOCKMODE_TSC || mode == VDSO_CLOCKMODE_HVCLOCK; 2360 } 2361 2362 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu) 2363 { 2364 #ifdef CONFIG_X86_64 2365 bool vcpus_matched; 2366 struct kvm_arch *ka = &vcpu->kvm->arch; 2367 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 2368 2369 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == 2370 atomic_read(&vcpu->kvm->online_vcpus)); 2371 2372 /* 2373 * Once the masterclock is enabled, always perform request in 2374 * order to update it. 2375 * 2376 * In order to enable masterclock, the host clocksource must be TSC 2377 * and the vcpus need to have matched TSCs. When that happens, 2378 * perform request to enable masterclock. 2379 */ 2380 if (ka->use_master_clock || 2381 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched)) 2382 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 2383 2384 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc, 2385 atomic_read(&vcpu->kvm->online_vcpus), 2386 ka->use_master_clock, gtod->clock.vclock_mode); 2387 #endif 2388 } 2389 2390 /* 2391 * Multiply tsc by a fixed point number represented by ratio. 2392 * 2393 * The most significant 64-N bits (mult) of ratio represent the 2394 * integral part of the fixed point number; the remaining N bits 2395 * (frac) represent the fractional part, ie. ratio represents a fixed 2396 * point number (mult + frac * 2^(-N)). 2397 * 2398 * N equals to kvm_tsc_scaling_ratio_frac_bits. 2399 */ 2400 static inline u64 __scale_tsc(u64 ratio, u64 tsc) 2401 { 2402 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits); 2403 } 2404 2405 u64 kvm_scale_tsc(u64 tsc, u64 ratio) 2406 { 2407 u64 _tsc = tsc; 2408 2409 if (ratio != kvm_default_tsc_scaling_ratio) 2410 _tsc = __scale_tsc(ratio, tsc); 2411 2412 return _tsc; 2413 } 2414 EXPORT_SYMBOL_GPL(kvm_scale_tsc); 2415 2416 static u64 kvm_compute_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc) 2417 { 2418 u64 tsc; 2419 2420 tsc = kvm_scale_tsc(rdtsc(), vcpu->arch.l1_tsc_scaling_ratio); 2421 2422 return target_tsc - tsc; 2423 } 2424 2425 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc) 2426 { 2427 return vcpu->arch.l1_tsc_offset + 2428 kvm_scale_tsc(host_tsc, vcpu->arch.l1_tsc_scaling_ratio); 2429 } 2430 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc); 2431 2432 u64 kvm_calc_nested_tsc_offset(u64 l1_offset, u64 l2_offset, u64 l2_multiplier) 2433 { 2434 u64 nested_offset; 2435 2436 if (l2_multiplier == kvm_default_tsc_scaling_ratio) 2437 nested_offset = l1_offset; 2438 else 2439 nested_offset = mul_s64_u64_shr((s64) l1_offset, l2_multiplier, 2440 kvm_tsc_scaling_ratio_frac_bits); 2441 2442 nested_offset += l2_offset; 2443 return nested_offset; 2444 } 2445 EXPORT_SYMBOL_GPL(kvm_calc_nested_tsc_offset); 2446 2447 u64 kvm_calc_nested_tsc_multiplier(u64 l1_multiplier, u64 l2_multiplier) 2448 { 2449 if (l2_multiplier != kvm_default_tsc_scaling_ratio) 2450 return mul_u64_u64_shr(l1_multiplier, l2_multiplier, 2451 kvm_tsc_scaling_ratio_frac_bits); 2452 2453 return l1_multiplier; 2454 } 2455 EXPORT_SYMBOL_GPL(kvm_calc_nested_tsc_multiplier); 2456 2457 static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 l1_offset) 2458 { 2459 trace_kvm_write_tsc_offset(vcpu->vcpu_id, 2460 vcpu->arch.l1_tsc_offset, 2461 l1_offset); 2462 2463 vcpu->arch.l1_tsc_offset = l1_offset; 2464 2465 /* 2466 * If we are here because L1 chose not to trap WRMSR to TSC then 2467 * according to the spec this should set L1's TSC (as opposed to 2468 * setting L1's offset for L2). 2469 */ 2470 if (is_guest_mode(vcpu)) 2471 vcpu->arch.tsc_offset = kvm_calc_nested_tsc_offset( 2472 l1_offset, 2473 static_call(kvm_x86_get_l2_tsc_offset)(vcpu), 2474 static_call(kvm_x86_get_l2_tsc_multiplier)(vcpu)); 2475 else 2476 vcpu->arch.tsc_offset = l1_offset; 2477 2478 static_call(kvm_x86_write_tsc_offset)(vcpu, vcpu->arch.tsc_offset); 2479 } 2480 2481 static void kvm_vcpu_write_tsc_multiplier(struct kvm_vcpu *vcpu, u64 l1_multiplier) 2482 { 2483 vcpu->arch.l1_tsc_scaling_ratio = l1_multiplier; 2484 2485 /* Userspace is changing the multiplier while L2 is active */ 2486 if (is_guest_mode(vcpu)) 2487 vcpu->arch.tsc_scaling_ratio = kvm_calc_nested_tsc_multiplier( 2488 l1_multiplier, 2489 static_call(kvm_x86_get_l2_tsc_multiplier)(vcpu)); 2490 else 2491 vcpu->arch.tsc_scaling_ratio = l1_multiplier; 2492 2493 if (kvm_has_tsc_control) 2494 static_call(kvm_x86_write_tsc_multiplier)( 2495 vcpu, vcpu->arch.tsc_scaling_ratio); 2496 } 2497 2498 static inline bool kvm_check_tsc_unstable(void) 2499 { 2500 #ifdef CONFIG_X86_64 2501 /* 2502 * TSC is marked unstable when we're running on Hyper-V, 2503 * 'TSC page' clocksource is good. 2504 */ 2505 if (pvclock_gtod_data.clock.vclock_mode == VDSO_CLOCKMODE_HVCLOCK) 2506 return false; 2507 #endif 2508 return check_tsc_unstable(); 2509 } 2510 2511 /* 2512 * Infers attempts to synchronize the guest's tsc from host writes. Sets the 2513 * offset for the vcpu and tracks the TSC matching generation that the vcpu 2514 * participates in. 2515 */ 2516 static void __kvm_synchronize_tsc(struct kvm_vcpu *vcpu, u64 offset, u64 tsc, 2517 u64 ns, bool matched) 2518 { 2519 struct kvm *kvm = vcpu->kvm; 2520 2521 lockdep_assert_held(&kvm->arch.tsc_write_lock); 2522 2523 /* 2524 * We also track th most recent recorded KHZ, write and time to 2525 * allow the matching interval to be extended at each write. 2526 */ 2527 kvm->arch.last_tsc_nsec = ns; 2528 kvm->arch.last_tsc_write = tsc; 2529 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz; 2530 kvm->arch.last_tsc_offset = offset; 2531 2532 vcpu->arch.last_guest_tsc = tsc; 2533 2534 kvm_vcpu_write_tsc_offset(vcpu, offset); 2535 2536 if (!matched) { 2537 /* 2538 * We split periods of matched TSC writes into generations. 2539 * For each generation, we track the original measured 2540 * nanosecond time, offset, and write, so if TSCs are in 2541 * sync, we can match exact offset, and if not, we can match 2542 * exact software computation in compute_guest_tsc() 2543 * 2544 * These values are tracked in kvm->arch.cur_xxx variables. 2545 */ 2546 kvm->arch.cur_tsc_generation++; 2547 kvm->arch.cur_tsc_nsec = ns; 2548 kvm->arch.cur_tsc_write = tsc; 2549 kvm->arch.cur_tsc_offset = offset; 2550 kvm->arch.nr_vcpus_matched_tsc = 0; 2551 } else if (vcpu->arch.this_tsc_generation != kvm->arch.cur_tsc_generation) { 2552 kvm->arch.nr_vcpus_matched_tsc++; 2553 } 2554 2555 /* Keep track of which generation this VCPU has synchronized to */ 2556 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation; 2557 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec; 2558 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write; 2559 2560 kvm_track_tsc_matching(vcpu); 2561 } 2562 2563 static void kvm_synchronize_tsc(struct kvm_vcpu *vcpu, u64 data) 2564 { 2565 struct kvm *kvm = vcpu->kvm; 2566 u64 offset, ns, elapsed; 2567 unsigned long flags; 2568 bool matched = false; 2569 bool synchronizing = false; 2570 2571 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags); 2572 offset = kvm_compute_l1_tsc_offset(vcpu, data); 2573 ns = get_kvmclock_base_ns(); 2574 elapsed = ns - kvm->arch.last_tsc_nsec; 2575 2576 if (vcpu->arch.virtual_tsc_khz) { 2577 if (data == 0) { 2578 /* 2579 * detection of vcpu initialization -- need to sync 2580 * with other vCPUs. This particularly helps to keep 2581 * kvm_clock stable after CPU hotplug 2582 */ 2583 synchronizing = true; 2584 } else { 2585 u64 tsc_exp = kvm->arch.last_tsc_write + 2586 nsec_to_cycles(vcpu, elapsed); 2587 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL; 2588 /* 2589 * Special case: TSC write with a small delta (1 second) 2590 * of virtual cycle time against real time is 2591 * interpreted as an attempt to synchronize the CPU. 2592 */ 2593 synchronizing = data < tsc_exp + tsc_hz && 2594 data + tsc_hz > tsc_exp; 2595 } 2596 } 2597 2598 /* 2599 * For a reliable TSC, we can match TSC offsets, and for an unstable 2600 * TSC, we add elapsed time in this computation. We could let the 2601 * compensation code attempt to catch up if we fall behind, but 2602 * it's better to try to match offsets from the beginning. 2603 */ 2604 if (synchronizing && 2605 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) { 2606 if (!kvm_check_tsc_unstable()) { 2607 offset = kvm->arch.cur_tsc_offset; 2608 } else { 2609 u64 delta = nsec_to_cycles(vcpu, elapsed); 2610 data += delta; 2611 offset = kvm_compute_l1_tsc_offset(vcpu, data); 2612 } 2613 matched = true; 2614 } 2615 2616 __kvm_synchronize_tsc(vcpu, offset, data, ns, matched); 2617 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags); 2618 } 2619 2620 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, 2621 s64 adjustment) 2622 { 2623 u64 tsc_offset = vcpu->arch.l1_tsc_offset; 2624 kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment); 2625 } 2626 2627 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment) 2628 { 2629 if (vcpu->arch.l1_tsc_scaling_ratio != kvm_default_tsc_scaling_ratio) 2630 WARN_ON(adjustment < 0); 2631 adjustment = kvm_scale_tsc((u64) adjustment, 2632 vcpu->arch.l1_tsc_scaling_ratio); 2633 adjust_tsc_offset_guest(vcpu, adjustment); 2634 } 2635 2636 #ifdef CONFIG_X86_64 2637 2638 static u64 read_tsc(void) 2639 { 2640 u64 ret = (u64)rdtsc_ordered(); 2641 u64 last = pvclock_gtod_data.clock.cycle_last; 2642 2643 if (likely(ret >= last)) 2644 return ret; 2645 2646 /* 2647 * GCC likes to generate cmov here, but this branch is extremely 2648 * predictable (it's just a function of time and the likely is 2649 * very likely) and there's a data dependence, so force GCC 2650 * to generate a branch instead. I don't barrier() because 2651 * we don't actually need a barrier, and if this function 2652 * ever gets inlined it will generate worse code. 2653 */ 2654 asm volatile (""); 2655 return last; 2656 } 2657 2658 static inline u64 vgettsc(struct pvclock_clock *clock, u64 *tsc_timestamp, 2659 int *mode) 2660 { 2661 long v; 2662 u64 tsc_pg_val; 2663 2664 switch (clock->vclock_mode) { 2665 case VDSO_CLOCKMODE_HVCLOCK: 2666 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(), 2667 tsc_timestamp); 2668 if (tsc_pg_val != U64_MAX) { 2669 /* TSC page valid */ 2670 *mode = VDSO_CLOCKMODE_HVCLOCK; 2671 v = (tsc_pg_val - clock->cycle_last) & 2672 clock->mask; 2673 } else { 2674 /* TSC page invalid */ 2675 *mode = VDSO_CLOCKMODE_NONE; 2676 } 2677 break; 2678 case VDSO_CLOCKMODE_TSC: 2679 *mode = VDSO_CLOCKMODE_TSC; 2680 *tsc_timestamp = read_tsc(); 2681 v = (*tsc_timestamp - clock->cycle_last) & 2682 clock->mask; 2683 break; 2684 default: 2685 *mode = VDSO_CLOCKMODE_NONE; 2686 } 2687 2688 if (*mode == VDSO_CLOCKMODE_NONE) 2689 *tsc_timestamp = v = 0; 2690 2691 return v * clock->mult; 2692 } 2693 2694 static int do_monotonic_raw(s64 *t, u64 *tsc_timestamp) 2695 { 2696 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 2697 unsigned long seq; 2698 int mode; 2699 u64 ns; 2700 2701 do { 2702 seq = read_seqcount_begin(>od->seq); 2703 ns = gtod->raw_clock.base_cycles; 2704 ns += vgettsc(>od->raw_clock, tsc_timestamp, &mode); 2705 ns >>= gtod->raw_clock.shift; 2706 ns += ktime_to_ns(ktime_add(gtod->raw_clock.offset, gtod->offs_boot)); 2707 } while (unlikely(read_seqcount_retry(>od->seq, seq))); 2708 *t = ns; 2709 2710 return mode; 2711 } 2712 2713 static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp) 2714 { 2715 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 2716 unsigned long seq; 2717 int mode; 2718 u64 ns; 2719 2720 do { 2721 seq = read_seqcount_begin(>od->seq); 2722 ts->tv_sec = gtod->wall_time_sec; 2723 ns = gtod->clock.base_cycles; 2724 ns += vgettsc(>od->clock, tsc_timestamp, &mode); 2725 ns >>= gtod->clock.shift; 2726 } while (unlikely(read_seqcount_retry(>od->seq, seq))); 2727 2728 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns); 2729 ts->tv_nsec = ns; 2730 2731 return mode; 2732 } 2733 2734 /* returns true if host is using TSC based clocksource */ 2735 static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp) 2736 { 2737 /* checked again under seqlock below */ 2738 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode)) 2739 return false; 2740 2741 return gtod_is_based_on_tsc(do_monotonic_raw(kernel_ns, 2742 tsc_timestamp)); 2743 } 2744 2745 /* returns true if host is using TSC based clocksource */ 2746 static bool kvm_get_walltime_and_clockread(struct timespec64 *ts, 2747 u64 *tsc_timestamp) 2748 { 2749 /* checked again under seqlock below */ 2750 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode)) 2751 return false; 2752 2753 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp)); 2754 } 2755 #endif 2756 2757 /* 2758 * 2759 * Assuming a stable TSC across physical CPUS, and a stable TSC 2760 * across virtual CPUs, the following condition is possible. 2761 * Each numbered line represents an event visible to both 2762 * CPUs at the next numbered event. 2763 * 2764 * "timespecX" represents host monotonic time. "tscX" represents 2765 * RDTSC value. 2766 * 2767 * VCPU0 on CPU0 | VCPU1 on CPU1 2768 * 2769 * 1. read timespec0,tsc0 2770 * 2. | timespec1 = timespec0 + N 2771 * | tsc1 = tsc0 + M 2772 * 3. transition to guest | transition to guest 2773 * 4. ret0 = timespec0 + (rdtsc - tsc0) | 2774 * 5. | ret1 = timespec1 + (rdtsc - tsc1) 2775 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M)) 2776 * 2777 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity: 2778 * 2779 * - ret0 < ret1 2780 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M)) 2781 * ... 2782 * - 0 < N - M => M < N 2783 * 2784 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not 2785 * always the case (the difference between two distinct xtime instances 2786 * might be smaller then the difference between corresponding TSC reads, 2787 * when updating guest vcpus pvclock areas). 2788 * 2789 * To avoid that problem, do not allow visibility of distinct 2790 * system_timestamp/tsc_timestamp values simultaneously: use a master 2791 * copy of host monotonic time values. Update that master copy 2792 * in lockstep. 2793 * 2794 * Rely on synchronization of host TSCs and guest TSCs for monotonicity. 2795 * 2796 */ 2797 2798 static void pvclock_update_vm_gtod_copy(struct kvm *kvm) 2799 { 2800 #ifdef CONFIG_X86_64 2801 struct kvm_arch *ka = &kvm->arch; 2802 int vclock_mode; 2803 bool host_tsc_clocksource, vcpus_matched; 2804 2805 lockdep_assert_held(&kvm->arch.tsc_write_lock); 2806 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == 2807 atomic_read(&kvm->online_vcpus)); 2808 2809 /* 2810 * If the host uses TSC clock, then passthrough TSC as stable 2811 * to the guest. 2812 */ 2813 host_tsc_clocksource = kvm_get_time_and_clockread( 2814 &ka->master_kernel_ns, 2815 &ka->master_cycle_now); 2816 2817 ka->use_master_clock = host_tsc_clocksource && vcpus_matched 2818 && !ka->backwards_tsc_observed 2819 && !ka->boot_vcpu_runs_old_kvmclock; 2820 2821 if (ka->use_master_clock) 2822 atomic_set(&kvm_guest_has_master_clock, 1); 2823 2824 vclock_mode = pvclock_gtod_data.clock.vclock_mode; 2825 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode, 2826 vcpus_matched); 2827 #endif 2828 } 2829 2830 static void kvm_make_mclock_inprogress_request(struct kvm *kvm) 2831 { 2832 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS); 2833 } 2834 2835 static void __kvm_start_pvclock_update(struct kvm *kvm) 2836 { 2837 raw_spin_lock_irq(&kvm->arch.tsc_write_lock); 2838 write_seqcount_begin(&kvm->arch.pvclock_sc); 2839 } 2840 2841 static void kvm_start_pvclock_update(struct kvm *kvm) 2842 { 2843 kvm_make_mclock_inprogress_request(kvm); 2844 2845 /* no guest entries from this point */ 2846 __kvm_start_pvclock_update(kvm); 2847 } 2848 2849 static void kvm_end_pvclock_update(struct kvm *kvm) 2850 { 2851 struct kvm_arch *ka = &kvm->arch; 2852 struct kvm_vcpu *vcpu; 2853 unsigned long i; 2854 2855 write_seqcount_end(&ka->pvclock_sc); 2856 raw_spin_unlock_irq(&ka->tsc_write_lock); 2857 kvm_for_each_vcpu(i, vcpu, kvm) 2858 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 2859 2860 /* guest entries allowed */ 2861 kvm_for_each_vcpu(i, vcpu, kvm) 2862 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu); 2863 } 2864 2865 static void kvm_update_masterclock(struct kvm *kvm) 2866 { 2867 kvm_hv_invalidate_tsc_page(kvm); 2868 kvm_start_pvclock_update(kvm); 2869 pvclock_update_vm_gtod_copy(kvm); 2870 kvm_end_pvclock_update(kvm); 2871 } 2872 2873 /* Called within read_seqcount_begin/retry for kvm->pvclock_sc. */ 2874 static void __get_kvmclock(struct kvm *kvm, struct kvm_clock_data *data) 2875 { 2876 struct kvm_arch *ka = &kvm->arch; 2877 struct pvclock_vcpu_time_info hv_clock; 2878 2879 /* both __this_cpu_read() and rdtsc() should be on the same cpu */ 2880 get_cpu(); 2881 2882 data->flags = 0; 2883 if (ka->use_master_clock && __this_cpu_read(cpu_tsc_khz)) { 2884 #ifdef CONFIG_X86_64 2885 struct timespec64 ts; 2886 2887 if (kvm_get_walltime_and_clockread(&ts, &data->host_tsc)) { 2888 data->realtime = ts.tv_nsec + NSEC_PER_SEC * ts.tv_sec; 2889 data->flags |= KVM_CLOCK_REALTIME | KVM_CLOCK_HOST_TSC; 2890 } else 2891 #endif 2892 data->host_tsc = rdtsc(); 2893 2894 data->flags |= KVM_CLOCK_TSC_STABLE; 2895 hv_clock.tsc_timestamp = ka->master_cycle_now; 2896 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset; 2897 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL, 2898 &hv_clock.tsc_shift, 2899 &hv_clock.tsc_to_system_mul); 2900 data->clock = __pvclock_read_cycles(&hv_clock, data->host_tsc); 2901 } else { 2902 data->clock = get_kvmclock_base_ns() + ka->kvmclock_offset; 2903 } 2904 2905 put_cpu(); 2906 } 2907 2908 static void get_kvmclock(struct kvm *kvm, struct kvm_clock_data *data) 2909 { 2910 struct kvm_arch *ka = &kvm->arch; 2911 unsigned seq; 2912 2913 do { 2914 seq = read_seqcount_begin(&ka->pvclock_sc); 2915 __get_kvmclock(kvm, data); 2916 } while (read_seqcount_retry(&ka->pvclock_sc, seq)); 2917 } 2918 2919 u64 get_kvmclock_ns(struct kvm *kvm) 2920 { 2921 struct kvm_clock_data data; 2922 2923 get_kvmclock(kvm, &data); 2924 return data.clock; 2925 } 2926 2927 static void kvm_setup_pvclock_page(struct kvm_vcpu *v, 2928 struct gfn_to_hva_cache *cache, 2929 unsigned int offset) 2930 { 2931 struct kvm_vcpu_arch *vcpu = &v->arch; 2932 struct pvclock_vcpu_time_info guest_hv_clock; 2933 2934 if (unlikely(kvm_read_guest_offset_cached(v->kvm, cache, 2935 &guest_hv_clock, offset, sizeof(guest_hv_clock)))) 2936 return; 2937 2938 /* This VCPU is paused, but it's legal for a guest to read another 2939 * VCPU's kvmclock, so we really have to follow the specification where 2940 * it says that version is odd if data is being modified, and even after 2941 * it is consistent. 2942 * 2943 * Version field updates must be kept separate. This is because 2944 * kvm_write_guest_cached might use a "rep movs" instruction, and 2945 * writes within a string instruction are weakly ordered. So there 2946 * are three writes overall. 2947 * 2948 * As a small optimization, only write the version field in the first 2949 * and third write. The vcpu->pv_time cache is still valid, because the 2950 * version field is the first in the struct. 2951 */ 2952 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0); 2953 2954 if (guest_hv_clock.version & 1) 2955 ++guest_hv_clock.version; /* first time write, random junk */ 2956 2957 vcpu->hv_clock.version = guest_hv_clock.version + 1; 2958 kvm_write_guest_offset_cached(v->kvm, cache, 2959 &vcpu->hv_clock, offset, 2960 sizeof(vcpu->hv_clock.version)); 2961 2962 smp_wmb(); 2963 2964 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */ 2965 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED); 2966 2967 if (vcpu->pvclock_set_guest_stopped_request) { 2968 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED; 2969 vcpu->pvclock_set_guest_stopped_request = false; 2970 } 2971 2972 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock); 2973 2974 kvm_write_guest_offset_cached(v->kvm, cache, 2975 &vcpu->hv_clock, offset, 2976 sizeof(vcpu->hv_clock)); 2977 2978 smp_wmb(); 2979 2980 vcpu->hv_clock.version++; 2981 kvm_write_guest_offset_cached(v->kvm, cache, 2982 &vcpu->hv_clock, offset, 2983 sizeof(vcpu->hv_clock.version)); 2984 } 2985 2986 static int kvm_guest_time_update(struct kvm_vcpu *v) 2987 { 2988 unsigned long flags, tgt_tsc_khz; 2989 unsigned seq; 2990 struct kvm_vcpu_arch *vcpu = &v->arch; 2991 struct kvm_arch *ka = &v->kvm->arch; 2992 s64 kernel_ns; 2993 u64 tsc_timestamp, host_tsc; 2994 u8 pvclock_flags; 2995 bool use_master_clock; 2996 2997 kernel_ns = 0; 2998 host_tsc = 0; 2999 3000 /* 3001 * If the host uses TSC clock, then passthrough TSC as stable 3002 * to the guest. 3003 */ 3004 do { 3005 seq = read_seqcount_begin(&ka->pvclock_sc); 3006 use_master_clock = ka->use_master_clock; 3007 if (use_master_clock) { 3008 host_tsc = ka->master_cycle_now; 3009 kernel_ns = ka->master_kernel_ns; 3010 } 3011 } while (read_seqcount_retry(&ka->pvclock_sc, seq)); 3012 3013 /* Keep irq disabled to prevent changes to the clock */ 3014 local_irq_save(flags); 3015 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz); 3016 if (unlikely(tgt_tsc_khz == 0)) { 3017 local_irq_restore(flags); 3018 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); 3019 return 1; 3020 } 3021 if (!use_master_clock) { 3022 host_tsc = rdtsc(); 3023 kernel_ns = get_kvmclock_base_ns(); 3024 } 3025 3026 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc); 3027 3028 /* 3029 * We may have to catch up the TSC to match elapsed wall clock 3030 * time for two reasons, even if kvmclock is used. 3031 * 1) CPU could have been running below the maximum TSC rate 3032 * 2) Broken TSC compensation resets the base at each VCPU 3033 * entry to avoid unknown leaps of TSC even when running 3034 * again on the same CPU. This may cause apparent elapsed 3035 * time to disappear, and the guest to stand still or run 3036 * very slowly. 3037 */ 3038 if (vcpu->tsc_catchup) { 3039 u64 tsc = compute_guest_tsc(v, kernel_ns); 3040 if (tsc > tsc_timestamp) { 3041 adjust_tsc_offset_guest(v, tsc - tsc_timestamp); 3042 tsc_timestamp = tsc; 3043 } 3044 } 3045 3046 local_irq_restore(flags); 3047 3048 /* With all the info we got, fill in the values */ 3049 3050 if (kvm_has_tsc_control) 3051 tgt_tsc_khz = kvm_scale_tsc(tgt_tsc_khz, 3052 v->arch.l1_tsc_scaling_ratio); 3053 3054 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) { 3055 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL, 3056 &vcpu->hv_clock.tsc_shift, 3057 &vcpu->hv_clock.tsc_to_system_mul); 3058 vcpu->hw_tsc_khz = tgt_tsc_khz; 3059 } 3060 3061 vcpu->hv_clock.tsc_timestamp = tsc_timestamp; 3062 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset; 3063 vcpu->last_guest_tsc = tsc_timestamp; 3064 3065 /* If the host uses TSC clocksource, then it is stable */ 3066 pvclock_flags = 0; 3067 if (use_master_clock) 3068 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT; 3069 3070 vcpu->hv_clock.flags = pvclock_flags; 3071 3072 if (vcpu->pv_time_enabled) 3073 kvm_setup_pvclock_page(v, &vcpu->pv_time, 0); 3074 if (vcpu->xen.vcpu_info_set) 3075 kvm_setup_pvclock_page(v, &vcpu->xen.vcpu_info_cache, 3076 offsetof(struct compat_vcpu_info, time)); 3077 if (vcpu->xen.vcpu_time_info_set) 3078 kvm_setup_pvclock_page(v, &vcpu->xen.vcpu_time_info_cache, 0); 3079 if (!v->vcpu_idx) 3080 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock); 3081 return 0; 3082 } 3083 3084 /* 3085 * kvmclock updates which are isolated to a given vcpu, such as 3086 * vcpu->cpu migration, should not allow system_timestamp from 3087 * the rest of the vcpus to remain static. Otherwise ntp frequency 3088 * correction applies to one vcpu's system_timestamp but not 3089 * the others. 3090 * 3091 * So in those cases, request a kvmclock update for all vcpus. 3092 * We need to rate-limit these requests though, as they can 3093 * considerably slow guests that have a large number of vcpus. 3094 * The time for a remote vcpu to update its kvmclock is bound 3095 * by the delay we use to rate-limit the updates. 3096 */ 3097 3098 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100) 3099 3100 static void kvmclock_update_fn(struct work_struct *work) 3101 { 3102 unsigned long i; 3103 struct delayed_work *dwork = to_delayed_work(work); 3104 struct kvm_arch *ka = container_of(dwork, struct kvm_arch, 3105 kvmclock_update_work); 3106 struct kvm *kvm = container_of(ka, struct kvm, arch); 3107 struct kvm_vcpu *vcpu; 3108 3109 kvm_for_each_vcpu(i, vcpu, kvm) { 3110 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 3111 kvm_vcpu_kick(vcpu); 3112 } 3113 } 3114 3115 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v) 3116 { 3117 struct kvm *kvm = v->kvm; 3118 3119 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); 3120 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 3121 KVMCLOCK_UPDATE_DELAY); 3122 } 3123 3124 #define KVMCLOCK_SYNC_PERIOD (300 * HZ) 3125 3126 static void kvmclock_sync_fn(struct work_struct *work) 3127 { 3128 struct delayed_work *dwork = to_delayed_work(work); 3129 struct kvm_arch *ka = container_of(dwork, struct kvm_arch, 3130 kvmclock_sync_work); 3131 struct kvm *kvm = container_of(ka, struct kvm, arch); 3132 3133 if (!kvmclock_periodic_sync) 3134 return; 3135 3136 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0); 3137 schedule_delayed_work(&kvm->arch.kvmclock_sync_work, 3138 KVMCLOCK_SYNC_PERIOD); 3139 } 3140 3141 /* 3142 * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP. 3143 */ 3144 static bool can_set_mci_status(struct kvm_vcpu *vcpu) 3145 { 3146 /* McStatusWrEn enabled? */ 3147 if (guest_cpuid_is_amd_or_hygon(vcpu)) 3148 return !!(vcpu->arch.msr_hwcr & BIT_ULL(18)); 3149 3150 return false; 3151 } 3152 3153 static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 3154 { 3155 u64 mcg_cap = vcpu->arch.mcg_cap; 3156 unsigned bank_num = mcg_cap & 0xff; 3157 u32 msr = msr_info->index; 3158 u64 data = msr_info->data; 3159 3160 switch (msr) { 3161 case MSR_IA32_MCG_STATUS: 3162 vcpu->arch.mcg_status = data; 3163 break; 3164 case MSR_IA32_MCG_CTL: 3165 if (!(mcg_cap & MCG_CTL_P) && 3166 (data || !msr_info->host_initiated)) 3167 return 1; 3168 if (data != 0 && data != ~(u64)0) 3169 return 1; 3170 vcpu->arch.mcg_ctl = data; 3171 break; 3172 default: 3173 if (msr >= MSR_IA32_MC0_CTL && 3174 msr < MSR_IA32_MCx_CTL(bank_num)) { 3175 u32 offset = array_index_nospec( 3176 msr - MSR_IA32_MC0_CTL, 3177 MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL); 3178 3179 /* only 0 or all 1s can be written to IA32_MCi_CTL 3180 * some Linux kernels though clear bit 10 in bank 4 to 3181 * workaround a BIOS/GART TBL issue on AMD K8s, ignore 3182 * this to avoid an uncatched #GP in the guest 3183 */ 3184 if ((offset & 0x3) == 0 && 3185 data != 0 && (data | (1 << 10)) != ~(u64)0) 3186 return -1; 3187 3188 /* MCi_STATUS */ 3189 if (!msr_info->host_initiated && 3190 (offset & 0x3) == 1 && data != 0) { 3191 if (!can_set_mci_status(vcpu)) 3192 return -1; 3193 } 3194 3195 vcpu->arch.mce_banks[offset] = data; 3196 break; 3197 } 3198 return 1; 3199 } 3200 return 0; 3201 } 3202 3203 static inline bool kvm_pv_async_pf_enabled(struct kvm_vcpu *vcpu) 3204 { 3205 u64 mask = KVM_ASYNC_PF_ENABLED | KVM_ASYNC_PF_DELIVERY_AS_INT; 3206 3207 return (vcpu->arch.apf.msr_en_val & mask) == mask; 3208 } 3209 3210 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data) 3211 { 3212 gpa_t gpa = data & ~0x3f; 3213 3214 /* Bits 4:5 are reserved, Should be zero */ 3215 if (data & 0x30) 3216 return 1; 3217 3218 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_VMEXIT) && 3219 (data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT)) 3220 return 1; 3221 3222 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT) && 3223 (data & KVM_ASYNC_PF_DELIVERY_AS_INT)) 3224 return 1; 3225 3226 if (!lapic_in_kernel(vcpu)) 3227 return data ? 1 : 0; 3228 3229 vcpu->arch.apf.msr_en_val = data; 3230 3231 if (!kvm_pv_async_pf_enabled(vcpu)) { 3232 kvm_clear_async_pf_completion_queue(vcpu); 3233 kvm_async_pf_hash_reset(vcpu); 3234 return 0; 3235 } 3236 3237 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa, 3238 sizeof(u64))) 3239 return 1; 3240 3241 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS); 3242 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT; 3243 3244 kvm_async_pf_wakeup_all(vcpu); 3245 3246 return 0; 3247 } 3248 3249 static int kvm_pv_enable_async_pf_int(struct kvm_vcpu *vcpu, u64 data) 3250 { 3251 /* Bits 8-63 are reserved */ 3252 if (data >> 8) 3253 return 1; 3254 3255 if (!lapic_in_kernel(vcpu)) 3256 return 1; 3257 3258 vcpu->arch.apf.msr_int_val = data; 3259 3260 vcpu->arch.apf.vec = data & KVM_ASYNC_PF_VEC_MASK; 3261 3262 return 0; 3263 } 3264 3265 static void kvmclock_reset(struct kvm_vcpu *vcpu) 3266 { 3267 vcpu->arch.pv_time_enabled = false; 3268 vcpu->arch.time = 0; 3269 } 3270 3271 static void kvm_vcpu_flush_tlb_all(struct kvm_vcpu *vcpu) 3272 { 3273 ++vcpu->stat.tlb_flush; 3274 static_call(kvm_x86_flush_tlb_all)(vcpu); 3275 } 3276 3277 static void kvm_vcpu_flush_tlb_guest(struct kvm_vcpu *vcpu) 3278 { 3279 ++vcpu->stat.tlb_flush; 3280 3281 if (!tdp_enabled) { 3282 /* 3283 * A TLB flush on behalf of the guest is equivalent to 3284 * INVPCID(all), toggling CR4.PGE, etc., which requires 3285 * a forced sync of the shadow page tables. Ensure all the 3286 * roots are synced and the guest TLB in hardware is clean. 3287 */ 3288 kvm_mmu_sync_roots(vcpu); 3289 kvm_mmu_sync_prev_roots(vcpu); 3290 } 3291 3292 static_call(kvm_x86_flush_tlb_guest)(vcpu); 3293 } 3294 3295 3296 static inline void kvm_vcpu_flush_tlb_current(struct kvm_vcpu *vcpu) 3297 { 3298 ++vcpu->stat.tlb_flush; 3299 static_call(kvm_x86_flush_tlb_current)(vcpu); 3300 } 3301 3302 /* 3303 * Service "local" TLB flush requests, which are specific to the current MMU 3304 * context. In addition to the generic event handling in vcpu_enter_guest(), 3305 * TLB flushes that are targeted at an MMU context also need to be serviced 3306 * prior before nested VM-Enter/VM-Exit. 3307 */ 3308 void kvm_service_local_tlb_flush_requests(struct kvm_vcpu *vcpu) 3309 { 3310 if (kvm_check_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu)) 3311 kvm_vcpu_flush_tlb_current(vcpu); 3312 3313 if (kvm_check_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu)) 3314 kvm_vcpu_flush_tlb_guest(vcpu); 3315 } 3316 EXPORT_SYMBOL_GPL(kvm_service_local_tlb_flush_requests); 3317 3318 static void record_steal_time(struct kvm_vcpu *vcpu) 3319 { 3320 struct gfn_to_hva_cache *ghc = &vcpu->arch.st.cache; 3321 struct kvm_steal_time __user *st; 3322 struct kvm_memslots *slots; 3323 u64 steal; 3324 u32 version; 3325 3326 if (kvm_xen_msr_enabled(vcpu->kvm)) { 3327 kvm_xen_runstate_set_running(vcpu); 3328 return; 3329 } 3330 3331 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) 3332 return; 3333 3334 if (WARN_ON_ONCE(current->mm != vcpu->kvm->mm)) 3335 return; 3336 3337 slots = kvm_memslots(vcpu->kvm); 3338 3339 if (unlikely(slots->generation != ghc->generation || 3340 kvm_is_error_hva(ghc->hva) || !ghc->memslot)) { 3341 gfn_t gfn = vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS; 3342 3343 /* We rely on the fact that it fits in a single page. */ 3344 BUILD_BUG_ON((sizeof(*st) - 1) & KVM_STEAL_VALID_BITS); 3345 3346 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, ghc, gfn, sizeof(*st)) || 3347 kvm_is_error_hva(ghc->hva) || !ghc->memslot) 3348 return; 3349 } 3350 3351 st = (struct kvm_steal_time __user *)ghc->hva; 3352 /* 3353 * Doing a TLB flush here, on the guest's behalf, can avoid 3354 * expensive IPIs. 3355 */ 3356 if (guest_pv_has(vcpu, KVM_FEATURE_PV_TLB_FLUSH)) { 3357 u8 st_preempted = 0; 3358 int err = -EFAULT; 3359 3360 if (!user_access_begin(st, sizeof(*st))) 3361 return; 3362 3363 asm volatile("1: xchgb %0, %2\n" 3364 "xor %1, %1\n" 3365 "2:\n" 3366 _ASM_EXTABLE_UA(1b, 2b) 3367 : "+q" (st_preempted), 3368 "+&r" (err), 3369 "+m" (st->preempted)); 3370 if (err) 3371 goto out; 3372 3373 user_access_end(); 3374 3375 vcpu->arch.st.preempted = 0; 3376 3377 trace_kvm_pv_tlb_flush(vcpu->vcpu_id, 3378 st_preempted & KVM_VCPU_FLUSH_TLB); 3379 if (st_preempted & KVM_VCPU_FLUSH_TLB) 3380 kvm_vcpu_flush_tlb_guest(vcpu); 3381 3382 if (!user_access_begin(st, sizeof(*st))) 3383 goto dirty; 3384 } else { 3385 if (!user_access_begin(st, sizeof(*st))) 3386 return; 3387 3388 unsafe_put_user(0, &st->preempted, out); 3389 vcpu->arch.st.preempted = 0; 3390 } 3391 3392 unsafe_get_user(version, &st->version, out); 3393 if (version & 1) 3394 version += 1; /* first time write, random junk */ 3395 3396 version += 1; 3397 unsafe_put_user(version, &st->version, out); 3398 3399 smp_wmb(); 3400 3401 unsafe_get_user(steal, &st->steal, out); 3402 steal += current->sched_info.run_delay - 3403 vcpu->arch.st.last_steal; 3404 vcpu->arch.st.last_steal = current->sched_info.run_delay; 3405 unsafe_put_user(steal, &st->steal, out); 3406 3407 version += 1; 3408 unsafe_put_user(version, &st->version, out); 3409 3410 out: 3411 user_access_end(); 3412 dirty: 3413 mark_page_dirty_in_slot(vcpu->kvm, ghc->memslot, gpa_to_gfn(ghc->gpa)); 3414 } 3415 3416 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 3417 { 3418 bool pr = false; 3419 u32 msr = msr_info->index; 3420 u64 data = msr_info->data; 3421 3422 if (msr && msr == vcpu->kvm->arch.xen_hvm_config.msr) 3423 return kvm_xen_write_hypercall_page(vcpu, data); 3424 3425 switch (msr) { 3426 case MSR_AMD64_NB_CFG: 3427 case MSR_IA32_UCODE_WRITE: 3428 case MSR_VM_HSAVE_PA: 3429 case MSR_AMD64_PATCH_LOADER: 3430 case MSR_AMD64_BU_CFG2: 3431 case MSR_AMD64_DC_CFG: 3432 case MSR_F15H_EX_CFG: 3433 break; 3434 3435 case MSR_IA32_UCODE_REV: 3436 if (msr_info->host_initiated) 3437 vcpu->arch.microcode_version = data; 3438 break; 3439 case MSR_IA32_ARCH_CAPABILITIES: 3440 if (!msr_info->host_initiated) 3441 return 1; 3442 vcpu->arch.arch_capabilities = data; 3443 break; 3444 case MSR_IA32_PERF_CAPABILITIES: { 3445 struct kvm_msr_entry msr_ent = {.index = msr, .data = 0}; 3446 3447 if (!msr_info->host_initiated) 3448 return 1; 3449 if (kvm_get_msr_feature(&msr_ent)) 3450 return 1; 3451 if (data & ~msr_ent.data) 3452 return 1; 3453 3454 vcpu->arch.perf_capabilities = data; 3455 3456 return 0; 3457 } 3458 case MSR_EFER: 3459 return set_efer(vcpu, msr_info); 3460 case MSR_K7_HWCR: 3461 data &= ~(u64)0x40; /* ignore flush filter disable */ 3462 data &= ~(u64)0x100; /* ignore ignne emulation enable */ 3463 data &= ~(u64)0x8; /* ignore TLB cache disable */ 3464 3465 /* Handle McStatusWrEn */ 3466 if (data == BIT_ULL(18)) { 3467 vcpu->arch.msr_hwcr = data; 3468 } else if (data != 0) { 3469 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n", 3470 data); 3471 return 1; 3472 } 3473 break; 3474 case MSR_FAM10H_MMIO_CONF_BASE: 3475 if (data != 0) { 3476 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: " 3477 "0x%llx\n", data); 3478 return 1; 3479 } 3480 break; 3481 case 0x200 ... 0x2ff: 3482 return kvm_mtrr_set_msr(vcpu, msr, data); 3483 case MSR_IA32_APICBASE: 3484 return kvm_set_apic_base(vcpu, msr_info); 3485 case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff: 3486 return kvm_x2apic_msr_write(vcpu, msr, data); 3487 case MSR_IA32_TSC_DEADLINE: 3488 kvm_set_lapic_tscdeadline_msr(vcpu, data); 3489 break; 3490 case MSR_IA32_TSC_ADJUST: 3491 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) { 3492 if (!msr_info->host_initiated) { 3493 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr; 3494 adjust_tsc_offset_guest(vcpu, adj); 3495 /* Before back to guest, tsc_timestamp must be adjusted 3496 * as well, otherwise guest's percpu pvclock time could jump. 3497 */ 3498 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 3499 } 3500 vcpu->arch.ia32_tsc_adjust_msr = data; 3501 } 3502 break; 3503 case MSR_IA32_MISC_ENABLE: 3504 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) && 3505 ((vcpu->arch.ia32_misc_enable_msr ^ data) & MSR_IA32_MISC_ENABLE_MWAIT)) { 3506 if (!guest_cpuid_has(vcpu, X86_FEATURE_XMM3)) 3507 return 1; 3508 vcpu->arch.ia32_misc_enable_msr = data; 3509 kvm_update_cpuid_runtime(vcpu); 3510 } else { 3511 vcpu->arch.ia32_misc_enable_msr = data; 3512 } 3513 break; 3514 case MSR_IA32_SMBASE: 3515 if (!msr_info->host_initiated) 3516 return 1; 3517 vcpu->arch.smbase = data; 3518 break; 3519 case MSR_IA32_POWER_CTL: 3520 vcpu->arch.msr_ia32_power_ctl = data; 3521 break; 3522 case MSR_IA32_TSC: 3523 if (msr_info->host_initiated) { 3524 kvm_synchronize_tsc(vcpu, data); 3525 } else { 3526 u64 adj = kvm_compute_l1_tsc_offset(vcpu, data) - vcpu->arch.l1_tsc_offset; 3527 adjust_tsc_offset_guest(vcpu, adj); 3528 vcpu->arch.ia32_tsc_adjust_msr += adj; 3529 } 3530 break; 3531 case MSR_IA32_XSS: 3532 if (!msr_info->host_initiated && 3533 !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES)) 3534 return 1; 3535 /* 3536 * KVM supports exposing PT to the guest, but does not support 3537 * IA32_XSS[bit 8]. Guests have to use RDMSR/WRMSR rather than 3538 * XSAVES/XRSTORS to save/restore PT MSRs. 3539 */ 3540 if (data & ~supported_xss) 3541 return 1; 3542 vcpu->arch.ia32_xss = data; 3543 kvm_update_cpuid_runtime(vcpu); 3544 break; 3545 case MSR_SMI_COUNT: 3546 if (!msr_info->host_initiated) 3547 return 1; 3548 vcpu->arch.smi_count = data; 3549 break; 3550 case MSR_KVM_WALL_CLOCK_NEW: 3551 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) 3552 return 1; 3553 3554 vcpu->kvm->arch.wall_clock = data; 3555 kvm_write_wall_clock(vcpu->kvm, data, 0); 3556 break; 3557 case MSR_KVM_WALL_CLOCK: 3558 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) 3559 return 1; 3560 3561 vcpu->kvm->arch.wall_clock = data; 3562 kvm_write_wall_clock(vcpu->kvm, data, 0); 3563 break; 3564 case MSR_KVM_SYSTEM_TIME_NEW: 3565 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) 3566 return 1; 3567 3568 kvm_write_system_time(vcpu, data, false, msr_info->host_initiated); 3569 break; 3570 case MSR_KVM_SYSTEM_TIME: 3571 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) 3572 return 1; 3573 3574 kvm_write_system_time(vcpu, data, true, msr_info->host_initiated); 3575 break; 3576 case MSR_KVM_ASYNC_PF_EN: 3577 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF)) 3578 return 1; 3579 3580 if (kvm_pv_enable_async_pf(vcpu, data)) 3581 return 1; 3582 break; 3583 case MSR_KVM_ASYNC_PF_INT: 3584 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT)) 3585 return 1; 3586 3587 if (kvm_pv_enable_async_pf_int(vcpu, data)) 3588 return 1; 3589 break; 3590 case MSR_KVM_ASYNC_PF_ACK: 3591 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT)) 3592 return 1; 3593 if (data & 0x1) { 3594 vcpu->arch.apf.pageready_pending = false; 3595 kvm_check_async_pf_completion(vcpu); 3596 } 3597 break; 3598 case MSR_KVM_STEAL_TIME: 3599 if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME)) 3600 return 1; 3601 3602 if (unlikely(!sched_info_on())) 3603 return 1; 3604 3605 if (data & KVM_STEAL_RESERVED_MASK) 3606 return 1; 3607 3608 vcpu->arch.st.msr_val = data; 3609 3610 if (!(data & KVM_MSR_ENABLED)) 3611 break; 3612 3613 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); 3614 3615 break; 3616 case MSR_KVM_PV_EOI_EN: 3617 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI)) 3618 return 1; 3619 3620 if (kvm_lapic_set_pv_eoi(vcpu, data, sizeof(u8))) 3621 return 1; 3622 break; 3623 3624 case MSR_KVM_POLL_CONTROL: 3625 if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL)) 3626 return 1; 3627 3628 /* only enable bit supported */ 3629 if (data & (-1ULL << 1)) 3630 return 1; 3631 3632 vcpu->arch.msr_kvm_poll_control = data; 3633 break; 3634 3635 case MSR_IA32_MCG_CTL: 3636 case MSR_IA32_MCG_STATUS: 3637 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: 3638 return set_msr_mce(vcpu, msr_info); 3639 3640 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: 3641 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: 3642 pr = true; 3643 fallthrough; 3644 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: 3645 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: 3646 if (kvm_pmu_is_valid_msr(vcpu, msr)) 3647 return kvm_pmu_set_msr(vcpu, msr_info); 3648 3649 if (pr || data != 0) 3650 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: " 3651 "0x%x data 0x%llx\n", msr, data); 3652 break; 3653 case MSR_K7_CLK_CTL: 3654 /* 3655 * Ignore all writes to this no longer documented MSR. 3656 * Writes are only relevant for old K7 processors, 3657 * all pre-dating SVM, but a recommended workaround from 3658 * AMD for these chips. It is possible to specify the 3659 * affected processor models on the command line, hence 3660 * the need to ignore the workaround. 3661 */ 3662 break; 3663 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: 3664 case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER: 3665 case HV_X64_MSR_SYNDBG_OPTIONS: 3666 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: 3667 case HV_X64_MSR_CRASH_CTL: 3668 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT: 3669 case HV_X64_MSR_REENLIGHTENMENT_CONTROL: 3670 case HV_X64_MSR_TSC_EMULATION_CONTROL: 3671 case HV_X64_MSR_TSC_EMULATION_STATUS: 3672 return kvm_hv_set_msr_common(vcpu, msr, data, 3673 msr_info->host_initiated); 3674 case MSR_IA32_BBL_CR_CTL3: 3675 /* Drop writes to this legacy MSR -- see rdmsr 3676 * counterpart for further detail. 3677 */ 3678 if (report_ignored_msrs) 3679 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n", 3680 msr, data); 3681 break; 3682 case MSR_AMD64_OSVW_ID_LENGTH: 3683 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 3684 return 1; 3685 vcpu->arch.osvw.length = data; 3686 break; 3687 case MSR_AMD64_OSVW_STATUS: 3688 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 3689 return 1; 3690 vcpu->arch.osvw.status = data; 3691 break; 3692 case MSR_PLATFORM_INFO: 3693 if (!msr_info->host_initiated || 3694 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) && 3695 cpuid_fault_enabled(vcpu))) 3696 return 1; 3697 vcpu->arch.msr_platform_info = data; 3698 break; 3699 case MSR_MISC_FEATURES_ENABLES: 3700 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT || 3701 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT && 3702 !supports_cpuid_fault(vcpu))) 3703 return 1; 3704 vcpu->arch.msr_misc_features_enables = data; 3705 break; 3706 #ifdef CONFIG_X86_64 3707 case MSR_IA32_XFD: 3708 if (!msr_info->host_initiated && 3709 !guest_cpuid_has(vcpu, X86_FEATURE_XFD)) 3710 return 1; 3711 3712 if (data & ~(XFEATURE_MASK_USER_DYNAMIC & 3713 vcpu->arch.guest_supported_xcr0)) 3714 return 1; 3715 3716 fpu_update_guest_xfd(&vcpu->arch.guest_fpu, data); 3717 break; 3718 case MSR_IA32_XFD_ERR: 3719 if (!msr_info->host_initiated && 3720 !guest_cpuid_has(vcpu, X86_FEATURE_XFD)) 3721 return 1; 3722 3723 if (data & ~(XFEATURE_MASK_USER_DYNAMIC & 3724 vcpu->arch.guest_supported_xcr0)) 3725 return 1; 3726 3727 vcpu->arch.guest_fpu.xfd_err = data; 3728 break; 3729 #endif 3730 default: 3731 if (kvm_pmu_is_valid_msr(vcpu, msr)) 3732 return kvm_pmu_set_msr(vcpu, msr_info); 3733 return KVM_MSR_RET_INVALID; 3734 } 3735 return 0; 3736 } 3737 EXPORT_SYMBOL_GPL(kvm_set_msr_common); 3738 3739 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host) 3740 { 3741 u64 data; 3742 u64 mcg_cap = vcpu->arch.mcg_cap; 3743 unsigned bank_num = mcg_cap & 0xff; 3744 3745 switch (msr) { 3746 case MSR_IA32_P5_MC_ADDR: 3747 case MSR_IA32_P5_MC_TYPE: 3748 data = 0; 3749 break; 3750 case MSR_IA32_MCG_CAP: 3751 data = vcpu->arch.mcg_cap; 3752 break; 3753 case MSR_IA32_MCG_CTL: 3754 if (!(mcg_cap & MCG_CTL_P) && !host) 3755 return 1; 3756 data = vcpu->arch.mcg_ctl; 3757 break; 3758 case MSR_IA32_MCG_STATUS: 3759 data = vcpu->arch.mcg_status; 3760 break; 3761 default: 3762 if (msr >= MSR_IA32_MC0_CTL && 3763 msr < MSR_IA32_MCx_CTL(bank_num)) { 3764 u32 offset = array_index_nospec( 3765 msr - MSR_IA32_MC0_CTL, 3766 MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL); 3767 3768 data = vcpu->arch.mce_banks[offset]; 3769 break; 3770 } 3771 return 1; 3772 } 3773 *pdata = data; 3774 return 0; 3775 } 3776 3777 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 3778 { 3779 switch (msr_info->index) { 3780 case MSR_IA32_PLATFORM_ID: 3781 case MSR_IA32_EBL_CR_POWERON: 3782 case MSR_IA32_LASTBRANCHFROMIP: 3783 case MSR_IA32_LASTBRANCHTOIP: 3784 case MSR_IA32_LASTINTFROMIP: 3785 case MSR_IA32_LASTINTTOIP: 3786 case MSR_AMD64_SYSCFG: 3787 case MSR_K8_TSEG_ADDR: 3788 case MSR_K8_TSEG_MASK: 3789 case MSR_VM_HSAVE_PA: 3790 case MSR_K8_INT_PENDING_MSG: 3791 case MSR_AMD64_NB_CFG: 3792 case MSR_FAM10H_MMIO_CONF_BASE: 3793 case MSR_AMD64_BU_CFG2: 3794 case MSR_IA32_PERF_CTL: 3795 case MSR_AMD64_DC_CFG: 3796 case MSR_F15H_EX_CFG: 3797 /* 3798 * Intel Sandy Bridge CPUs must support the RAPL (running average power 3799 * limit) MSRs. Just return 0, as we do not want to expose the host 3800 * data here. Do not conditionalize this on CPUID, as KVM does not do 3801 * so for existing CPU-specific MSRs. 3802 */ 3803 case MSR_RAPL_POWER_UNIT: 3804 case MSR_PP0_ENERGY_STATUS: /* Power plane 0 (core) */ 3805 case MSR_PP1_ENERGY_STATUS: /* Power plane 1 (graphics uncore) */ 3806 case MSR_PKG_ENERGY_STATUS: /* Total package */ 3807 case MSR_DRAM_ENERGY_STATUS: /* DRAM controller */ 3808 msr_info->data = 0; 3809 break; 3810 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5: 3811 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) 3812 return kvm_pmu_get_msr(vcpu, msr_info); 3813 if (!msr_info->host_initiated) 3814 return 1; 3815 msr_info->data = 0; 3816 break; 3817 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: 3818 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: 3819 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: 3820 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: 3821 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) 3822 return kvm_pmu_get_msr(vcpu, msr_info); 3823 msr_info->data = 0; 3824 break; 3825 case MSR_IA32_UCODE_REV: 3826 msr_info->data = vcpu->arch.microcode_version; 3827 break; 3828 case MSR_IA32_ARCH_CAPABILITIES: 3829 if (!msr_info->host_initiated && 3830 !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES)) 3831 return 1; 3832 msr_info->data = vcpu->arch.arch_capabilities; 3833 break; 3834 case MSR_IA32_PERF_CAPABILITIES: 3835 if (!msr_info->host_initiated && 3836 !guest_cpuid_has(vcpu, X86_FEATURE_PDCM)) 3837 return 1; 3838 msr_info->data = vcpu->arch.perf_capabilities; 3839 break; 3840 case MSR_IA32_POWER_CTL: 3841 msr_info->data = vcpu->arch.msr_ia32_power_ctl; 3842 break; 3843 case MSR_IA32_TSC: { 3844 /* 3845 * Intel SDM states that MSR_IA32_TSC read adds the TSC offset 3846 * even when not intercepted. AMD manual doesn't explicitly 3847 * state this but appears to behave the same. 3848 * 3849 * On userspace reads and writes, however, we unconditionally 3850 * return L1's TSC value to ensure backwards-compatible 3851 * behavior for migration. 3852 */ 3853 u64 offset, ratio; 3854 3855 if (msr_info->host_initiated) { 3856 offset = vcpu->arch.l1_tsc_offset; 3857 ratio = vcpu->arch.l1_tsc_scaling_ratio; 3858 } else { 3859 offset = vcpu->arch.tsc_offset; 3860 ratio = vcpu->arch.tsc_scaling_ratio; 3861 } 3862 3863 msr_info->data = kvm_scale_tsc(rdtsc(), ratio) + offset; 3864 break; 3865 } 3866 case MSR_MTRRcap: 3867 case 0x200 ... 0x2ff: 3868 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data); 3869 case 0xcd: /* fsb frequency */ 3870 msr_info->data = 3; 3871 break; 3872 /* 3873 * MSR_EBC_FREQUENCY_ID 3874 * Conservative value valid for even the basic CPU models. 3875 * Models 0,1: 000 in bits 23:21 indicating a bus speed of 3876 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz, 3877 * and 266MHz for model 3, or 4. Set Core Clock 3878 * Frequency to System Bus Frequency Ratio to 1 (bits 3879 * 31:24) even though these are only valid for CPU 3880 * models > 2, however guests may end up dividing or 3881 * multiplying by zero otherwise. 3882 */ 3883 case MSR_EBC_FREQUENCY_ID: 3884 msr_info->data = 1 << 24; 3885 break; 3886 case MSR_IA32_APICBASE: 3887 msr_info->data = kvm_get_apic_base(vcpu); 3888 break; 3889 case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff: 3890 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data); 3891 case MSR_IA32_TSC_DEADLINE: 3892 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu); 3893 break; 3894 case MSR_IA32_TSC_ADJUST: 3895 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr; 3896 break; 3897 case MSR_IA32_MISC_ENABLE: 3898 msr_info->data = vcpu->arch.ia32_misc_enable_msr; 3899 break; 3900 case MSR_IA32_SMBASE: 3901 if (!msr_info->host_initiated) 3902 return 1; 3903 msr_info->data = vcpu->arch.smbase; 3904 break; 3905 case MSR_SMI_COUNT: 3906 msr_info->data = vcpu->arch.smi_count; 3907 break; 3908 case MSR_IA32_PERF_STATUS: 3909 /* TSC increment by tick */ 3910 msr_info->data = 1000ULL; 3911 /* CPU multiplier */ 3912 msr_info->data |= (((uint64_t)4ULL) << 40); 3913 break; 3914 case MSR_EFER: 3915 msr_info->data = vcpu->arch.efer; 3916 break; 3917 case MSR_KVM_WALL_CLOCK: 3918 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) 3919 return 1; 3920 3921 msr_info->data = vcpu->kvm->arch.wall_clock; 3922 break; 3923 case MSR_KVM_WALL_CLOCK_NEW: 3924 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) 3925 return 1; 3926 3927 msr_info->data = vcpu->kvm->arch.wall_clock; 3928 break; 3929 case MSR_KVM_SYSTEM_TIME: 3930 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) 3931 return 1; 3932 3933 msr_info->data = vcpu->arch.time; 3934 break; 3935 case MSR_KVM_SYSTEM_TIME_NEW: 3936 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) 3937 return 1; 3938 3939 msr_info->data = vcpu->arch.time; 3940 break; 3941 case MSR_KVM_ASYNC_PF_EN: 3942 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF)) 3943 return 1; 3944 3945 msr_info->data = vcpu->arch.apf.msr_en_val; 3946 break; 3947 case MSR_KVM_ASYNC_PF_INT: 3948 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT)) 3949 return 1; 3950 3951 msr_info->data = vcpu->arch.apf.msr_int_val; 3952 break; 3953 case MSR_KVM_ASYNC_PF_ACK: 3954 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT)) 3955 return 1; 3956 3957 msr_info->data = 0; 3958 break; 3959 case MSR_KVM_STEAL_TIME: 3960 if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME)) 3961 return 1; 3962 3963 msr_info->data = vcpu->arch.st.msr_val; 3964 break; 3965 case MSR_KVM_PV_EOI_EN: 3966 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI)) 3967 return 1; 3968 3969 msr_info->data = vcpu->arch.pv_eoi.msr_val; 3970 break; 3971 case MSR_KVM_POLL_CONTROL: 3972 if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL)) 3973 return 1; 3974 3975 msr_info->data = vcpu->arch.msr_kvm_poll_control; 3976 break; 3977 case MSR_IA32_P5_MC_ADDR: 3978 case MSR_IA32_P5_MC_TYPE: 3979 case MSR_IA32_MCG_CAP: 3980 case MSR_IA32_MCG_CTL: 3981 case MSR_IA32_MCG_STATUS: 3982 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: 3983 return get_msr_mce(vcpu, msr_info->index, &msr_info->data, 3984 msr_info->host_initiated); 3985 case MSR_IA32_XSS: 3986 if (!msr_info->host_initiated && 3987 !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES)) 3988 return 1; 3989 msr_info->data = vcpu->arch.ia32_xss; 3990 break; 3991 case MSR_K7_CLK_CTL: 3992 /* 3993 * Provide expected ramp-up count for K7. All other 3994 * are set to zero, indicating minimum divisors for 3995 * every field. 3996 * 3997 * This prevents guest kernels on AMD host with CPU 3998 * type 6, model 8 and higher from exploding due to 3999 * the rdmsr failing. 4000 */ 4001 msr_info->data = 0x20000000; 4002 break; 4003 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: 4004 case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER: 4005 case HV_X64_MSR_SYNDBG_OPTIONS: 4006 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: 4007 case HV_X64_MSR_CRASH_CTL: 4008 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT: 4009 case HV_X64_MSR_REENLIGHTENMENT_CONTROL: 4010 case HV_X64_MSR_TSC_EMULATION_CONTROL: 4011 case HV_X64_MSR_TSC_EMULATION_STATUS: 4012 return kvm_hv_get_msr_common(vcpu, 4013 msr_info->index, &msr_info->data, 4014 msr_info->host_initiated); 4015 case MSR_IA32_BBL_CR_CTL3: 4016 /* This legacy MSR exists but isn't fully documented in current 4017 * silicon. It is however accessed by winxp in very narrow 4018 * scenarios where it sets bit #19, itself documented as 4019 * a "reserved" bit. Best effort attempt to source coherent 4020 * read data here should the balance of the register be 4021 * interpreted by the guest: 4022 * 4023 * L2 cache control register 3: 64GB range, 256KB size, 4024 * enabled, latency 0x1, configured 4025 */ 4026 msr_info->data = 0xbe702111; 4027 break; 4028 case MSR_AMD64_OSVW_ID_LENGTH: 4029 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 4030 return 1; 4031 msr_info->data = vcpu->arch.osvw.length; 4032 break; 4033 case MSR_AMD64_OSVW_STATUS: 4034 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 4035 return 1; 4036 msr_info->data = vcpu->arch.osvw.status; 4037 break; 4038 case MSR_PLATFORM_INFO: 4039 if (!msr_info->host_initiated && 4040 !vcpu->kvm->arch.guest_can_read_msr_platform_info) 4041 return 1; 4042 msr_info->data = vcpu->arch.msr_platform_info; 4043 break; 4044 case MSR_MISC_FEATURES_ENABLES: 4045 msr_info->data = vcpu->arch.msr_misc_features_enables; 4046 break; 4047 case MSR_K7_HWCR: 4048 msr_info->data = vcpu->arch.msr_hwcr; 4049 break; 4050 #ifdef CONFIG_X86_64 4051 case MSR_IA32_XFD: 4052 if (!msr_info->host_initiated && 4053 !guest_cpuid_has(vcpu, X86_FEATURE_XFD)) 4054 return 1; 4055 4056 msr_info->data = vcpu->arch.guest_fpu.fpstate->xfd; 4057 break; 4058 case MSR_IA32_XFD_ERR: 4059 if (!msr_info->host_initiated && 4060 !guest_cpuid_has(vcpu, X86_FEATURE_XFD)) 4061 return 1; 4062 4063 msr_info->data = vcpu->arch.guest_fpu.xfd_err; 4064 break; 4065 #endif 4066 default: 4067 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) 4068 return kvm_pmu_get_msr(vcpu, msr_info); 4069 return KVM_MSR_RET_INVALID; 4070 } 4071 return 0; 4072 } 4073 EXPORT_SYMBOL_GPL(kvm_get_msr_common); 4074 4075 /* 4076 * Read or write a bunch of msrs. All parameters are kernel addresses. 4077 * 4078 * @return number of msrs set successfully. 4079 */ 4080 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs, 4081 struct kvm_msr_entry *entries, 4082 int (*do_msr)(struct kvm_vcpu *vcpu, 4083 unsigned index, u64 *data)) 4084 { 4085 int i; 4086 4087 for (i = 0; i < msrs->nmsrs; ++i) 4088 if (do_msr(vcpu, entries[i].index, &entries[i].data)) 4089 break; 4090 4091 return i; 4092 } 4093 4094 /* 4095 * Read or write a bunch of msrs. Parameters are user addresses. 4096 * 4097 * @return number of msrs set successfully. 4098 */ 4099 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs, 4100 int (*do_msr)(struct kvm_vcpu *vcpu, 4101 unsigned index, u64 *data), 4102 int writeback) 4103 { 4104 struct kvm_msrs msrs; 4105 struct kvm_msr_entry *entries; 4106 int r, n; 4107 unsigned size; 4108 4109 r = -EFAULT; 4110 if (copy_from_user(&msrs, user_msrs, sizeof(msrs))) 4111 goto out; 4112 4113 r = -E2BIG; 4114 if (msrs.nmsrs >= MAX_IO_MSRS) 4115 goto out; 4116 4117 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs; 4118 entries = memdup_user(user_msrs->entries, size); 4119 if (IS_ERR(entries)) { 4120 r = PTR_ERR(entries); 4121 goto out; 4122 } 4123 4124 r = n = __msr_io(vcpu, &msrs, entries, do_msr); 4125 if (r < 0) 4126 goto out_free; 4127 4128 r = -EFAULT; 4129 if (writeback && copy_to_user(user_msrs->entries, entries, size)) 4130 goto out_free; 4131 4132 r = n; 4133 4134 out_free: 4135 kfree(entries); 4136 out: 4137 return r; 4138 } 4139 4140 static inline bool kvm_can_mwait_in_guest(void) 4141 { 4142 return boot_cpu_has(X86_FEATURE_MWAIT) && 4143 !boot_cpu_has_bug(X86_BUG_MONITOR) && 4144 boot_cpu_has(X86_FEATURE_ARAT); 4145 } 4146 4147 static int kvm_ioctl_get_supported_hv_cpuid(struct kvm_vcpu *vcpu, 4148 struct kvm_cpuid2 __user *cpuid_arg) 4149 { 4150 struct kvm_cpuid2 cpuid; 4151 int r; 4152 4153 r = -EFAULT; 4154 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 4155 return r; 4156 4157 r = kvm_get_hv_cpuid(vcpu, &cpuid, cpuid_arg->entries); 4158 if (r) 4159 return r; 4160 4161 r = -EFAULT; 4162 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) 4163 return r; 4164 4165 return 0; 4166 } 4167 4168 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext) 4169 { 4170 int r = 0; 4171 4172 switch (ext) { 4173 case KVM_CAP_IRQCHIP: 4174 case KVM_CAP_HLT: 4175 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL: 4176 case KVM_CAP_SET_TSS_ADDR: 4177 case KVM_CAP_EXT_CPUID: 4178 case KVM_CAP_EXT_EMUL_CPUID: 4179 case KVM_CAP_CLOCKSOURCE: 4180 case KVM_CAP_PIT: 4181 case KVM_CAP_NOP_IO_DELAY: 4182 case KVM_CAP_MP_STATE: 4183 case KVM_CAP_SYNC_MMU: 4184 case KVM_CAP_USER_NMI: 4185 case KVM_CAP_REINJECT_CONTROL: 4186 case KVM_CAP_IRQ_INJECT_STATUS: 4187 case KVM_CAP_IOEVENTFD: 4188 case KVM_CAP_IOEVENTFD_NO_LENGTH: 4189 case KVM_CAP_PIT2: 4190 case KVM_CAP_PIT_STATE2: 4191 case KVM_CAP_SET_IDENTITY_MAP_ADDR: 4192 case KVM_CAP_VCPU_EVENTS: 4193 case KVM_CAP_HYPERV: 4194 case KVM_CAP_HYPERV_VAPIC: 4195 case KVM_CAP_HYPERV_SPIN: 4196 case KVM_CAP_HYPERV_SYNIC: 4197 case KVM_CAP_HYPERV_SYNIC2: 4198 case KVM_CAP_HYPERV_VP_INDEX: 4199 case KVM_CAP_HYPERV_EVENTFD: 4200 case KVM_CAP_HYPERV_TLBFLUSH: 4201 case KVM_CAP_HYPERV_SEND_IPI: 4202 case KVM_CAP_HYPERV_CPUID: 4203 case KVM_CAP_HYPERV_ENFORCE_CPUID: 4204 case KVM_CAP_SYS_HYPERV_CPUID: 4205 case KVM_CAP_PCI_SEGMENT: 4206 case KVM_CAP_DEBUGREGS: 4207 case KVM_CAP_X86_ROBUST_SINGLESTEP: 4208 case KVM_CAP_XSAVE: 4209 case KVM_CAP_ASYNC_PF: 4210 case KVM_CAP_ASYNC_PF_INT: 4211 case KVM_CAP_GET_TSC_KHZ: 4212 case KVM_CAP_KVMCLOCK_CTRL: 4213 case KVM_CAP_READONLY_MEM: 4214 case KVM_CAP_HYPERV_TIME: 4215 case KVM_CAP_IOAPIC_POLARITY_IGNORED: 4216 case KVM_CAP_TSC_DEADLINE_TIMER: 4217 case KVM_CAP_DISABLE_QUIRKS: 4218 case KVM_CAP_SET_BOOT_CPU_ID: 4219 case KVM_CAP_SPLIT_IRQCHIP: 4220 case KVM_CAP_IMMEDIATE_EXIT: 4221 case KVM_CAP_PMU_EVENT_FILTER: 4222 case KVM_CAP_GET_MSR_FEATURES: 4223 case KVM_CAP_MSR_PLATFORM_INFO: 4224 case KVM_CAP_EXCEPTION_PAYLOAD: 4225 case KVM_CAP_SET_GUEST_DEBUG: 4226 case KVM_CAP_LAST_CPU: 4227 case KVM_CAP_X86_USER_SPACE_MSR: 4228 case KVM_CAP_X86_MSR_FILTER: 4229 case KVM_CAP_ENFORCE_PV_FEATURE_CPUID: 4230 #ifdef CONFIG_X86_SGX_KVM 4231 case KVM_CAP_SGX_ATTRIBUTE: 4232 #endif 4233 case KVM_CAP_VM_COPY_ENC_CONTEXT_FROM: 4234 case KVM_CAP_VM_MOVE_ENC_CONTEXT_FROM: 4235 case KVM_CAP_SREGS2: 4236 case KVM_CAP_EXIT_ON_EMULATION_FAILURE: 4237 case KVM_CAP_VCPU_ATTRIBUTES: 4238 case KVM_CAP_SYS_ATTRIBUTES: 4239 case KVM_CAP_VAPIC: 4240 r = 1; 4241 break; 4242 case KVM_CAP_EXIT_HYPERCALL: 4243 r = KVM_EXIT_HYPERCALL_VALID_MASK; 4244 break; 4245 case KVM_CAP_SET_GUEST_DEBUG2: 4246 return KVM_GUESTDBG_VALID_MASK; 4247 #ifdef CONFIG_KVM_XEN 4248 case KVM_CAP_XEN_HVM: 4249 r = KVM_XEN_HVM_CONFIG_HYPERCALL_MSR | 4250 KVM_XEN_HVM_CONFIG_INTERCEPT_HCALL | 4251 KVM_XEN_HVM_CONFIG_SHARED_INFO | 4252 KVM_XEN_HVM_CONFIG_EVTCHN_2LEVEL; 4253 if (sched_info_on()) 4254 r |= KVM_XEN_HVM_CONFIG_RUNSTATE; 4255 break; 4256 #endif 4257 case KVM_CAP_SYNC_REGS: 4258 r = KVM_SYNC_X86_VALID_FIELDS; 4259 break; 4260 case KVM_CAP_ADJUST_CLOCK: 4261 r = KVM_CLOCK_VALID_FLAGS; 4262 break; 4263 case KVM_CAP_X86_DISABLE_EXITS: 4264 r |= KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE | 4265 KVM_X86_DISABLE_EXITS_CSTATE; 4266 if(kvm_can_mwait_in_guest()) 4267 r |= KVM_X86_DISABLE_EXITS_MWAIT; 4268 break; 4269 case KVM_CAP_X86_SMM: 4270 /* SMBASE is usually relocated above 1M on modern chipsets, 4271 * and SMM handlers might indeed rely on 4G segment limits, 4272 * so do not report SMM to be available if real mode is 4273 * emulated via vm86 mode. Still, do not go to great lengths 4274 * to avoid userspace's usage of the feature, because it is a 4275 * fringe case that is not enabled except via specific settings 4276 * of the module parameters. 4277 */ 4278 r = static_call(kvm_x86_has_emulated_msr)(kvm, MSR_IA32_SMBASE); 4279 break; 4280 case KVM_CAP_NR_VCPUS: 4281 r = min_t(unsigned int, num_online_cpus(), KVM_MAX_VCPUS); 4282 break; 4283 case KVM_CAP_MAX_VCPUS: 4284 r = KVM_MAX_VCPUS; 4285 break; 4286 case KVM_CAP_MAX_VCPU_ID: 4287 r = KVM_MAX_VCPU_IDS; 4288 break; 4289 case KVM_CAP_PV_MMU: /* obsolete */ 4290 r = 0; 4291 break; 4292 case KVM_CAP_MCE: 4293 r = KVM_MAX_MCE_BANKS; 4294 break; 4295 case KVM_CAP_XCRS: 4296 r = boot_cpu_has(X86_FEATURE_XSAVE); 4297 break; 4298 case KVM_CAP_TSC_CONTROL: 4299 r = kvm_has_tsc_control; 4300 break; 4301 case KVM_CAP_X2APIC_API: 4302 r = KVM_X2APIC_API_VALID_FLAGS; 4303 break; 4304 case KVM_CAP_NESTED_STATE: 4305 r = kvm_x86_ops.nested_ops->get_state ? 4306 kvm_x86_ops.nested_ops->get_state(NULL, NULL, 0) : 0; 4307 break; 4308 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH: 4309 r = kvm_x86_ops.enable_direct_tlbflush != NULL; 4310 break; 4311 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS: 4312 r = kvm_x86_ops.nested_ops->enable_evmcs != NULL; 4313 break; 4314 case KVM_CAP_SMALLER_MAXPHYADDR: 4315 r = (int) allow_smaller_maxphyaddr; 4316 break; 4317 case KVM_CAP_STEAL_TIME: 4318 r = sched_info_on(); 4319 break; 4320 case KVM_CAP_X86_BUS_LOCK_EXIT: 4321 if (kvm_has_bus_lock_exit) 4322 r = KVM_BUS_LOCK_DETECTION_OFF | 4323 KVM_BUS_LOCK_DETECTION_EXIT; 4324 else 4325 r = 0; 4326 break; 4327 case KVM_CAP_XSAVE2: { 4328 u64 guest_perm = xstate_get_guest_group_perm(); 4329 4330 r = xstate_required_size(supported_xcr0 & guest_perm, false); 4331 if (r < sizeof(struct kvm_xsave)) 4332 r = sizeof(struct kvm_xsave); 4333 break; 4334 case KVM_CAP_PMU_CAPABILITY: 4335 r = enable_pmu ? KVM_CAP_PMU_VALID_MASK : 0; 4336 break; 4337 } 4338 default: 4339 break; 4340 } 4341 return r; 4342 } 4343 4344 static inline void __user *kvm_get_attr_addr(struct kvm_device_attr *attr) 4345 { 4346 void __user *uaddr = (void __user*)(unsigned long)attr->addr; 4347 4348 if ((u64)(unsigned long)uaddr != attr->addr) 4349 return ERR_PTR_USR(-EFAULT); 4350 return uaddr; 4351 } 4352 4353 static int kvm_x86_dev_get_attr(struct kvm_device_attr *attr) 4354 { 4355 u64 __user *uaddr = kvm_get_attr_addr(attr); 4356 4357 if (attr->group) 4358 return -ENXIO; 4359 4360 if (IS_ERR(uaddr)) 4361 return PTR_ERR(uaddr); 4362 4363 switch (attr->attr) { 4364 case KVM_X86_XCOMP_GUEST_SUPP: 4365 if (put_user(supported_xcr0, uaddr)) 4366 return -EFAULT; 4367 return 0; 4368 default: 4369 return -ENXIO; 4370 break; 4371 } 4372 } 4373 4374 static int kvm_x86_dev_has_attr(struct kvm_device_attr *attr) 4375 { 4376 if (attr->group) 4377 return -ENXIO; 4378 4379 switch (attr->attr) { 4380 case KVM_X86_XCOMP_GUEST_SUPP: 4381 return 0; 4382 default: 4383 return -ENXIO; 4384 } 4385 } 4386 4387 long kvm_arch_dev_ioctl(struct file *filp, 4388 unsigned int ioctl, unsigned long arg) 4389 { 4390 void __user *argp = (void __user *)arg; 4391 long r; 4392 4393 switch (ioctl) { 4394 case KVM_GET_MSR_INDEX_LIST: { 4395 struct kvm_msr_list __user *user_msr_list = argp; 4396 struct kvm_msr_list msr_list; 4397 unsigned n; 4398 4399 r = -EFAULT; 4400 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list))) 4401 goto out; 4402 n = msr_list.nmsrs; 4403 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs; 4404 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list))) 4405 goto out; 4406 r = -E2BIG; 4407 if (n < msr_list.nmsrs) 4408 goto out; 4409 r = -EFAULT; 4410 if (copy_to_user(user_msr_list->indices, &msrs_to_save, 4411 num_msrs_to_save * sizeof(u32))) 4412 goto out; 4413 if (copy_to_user(user_msr_list->indices + num_msrs_to_save, 4414 &emulated_msrs, 4415 num_emulated_msrs * sizeof(u32))) 4416 goto out; 4417 r = 0; 4418 break; 4419 } 4420 case KVM_GET_SUPPORTED_CPUID: 4421 case KVM_GET_EMULATED_CPUID: { 4422 struct kvm_cpuid2 __user *cpuid_arg = argp; 4423 struct kvm_cpuid2 cpuid; 4424 4425 r = -EFAULT; 4426 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 4427 goto out; 4428 4429 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries, 4430 ioctl); 4431 if (r) 4432 goto out; 4433 4434 r = -EFAULT; 4435 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) 4436 goto out; 4437 r = 0; 4438 break; 4439 } 4440 case KVM_X86_GET_MCE_CAP_SUPPORTED: 4441 r = -EFAULT; 4442 if (copy_to_user(argp, &kvm_mce_cap_supported, 4443 sizeof(kvm_mce_cap_supported))) 4444 goto out; 4445 r = 0; 4446 break; 4447 case KVM_GET_MSR_FEATURE_INDEX_LIST: { 4448 struct kvm_msr_list __user *user_msr_list = argp; 4449 struct kvm_msr_list msr_list; 4450 unsigned int n; 4451 4452 r = -EFAULT; 4453 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list))) 4454 goto out; 4455 n = msr_list.nmsrs; 4456 msr_list.nmsrs = num_msr_based_features; 4457 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list))) 4458 goto out; 4459 r = -E2BIG; 4460 if (n < msr_list.nmsrs) 4461 goto out; 4462 r = -EFAULT; 4463 if (copy_to_user(user_msr_list->indices, &msr_based_features, 4464 num_msr_based_features * sizeof(u32))) 4465 goto out; 4466 r = 0; 4467 break; 4468 } 4469 case KVM_GET_MSRS: 4470 r = msr_io(NULL, argp, do_get_msr_feature, 1); 4471 break; 4472 case KVM_GET_SUPPORTED_HV_CPUID: 4473 r = kvm_ioctl_get_supported_hv_cpuid(NULL, argp); 4474 break; 4475 case KVM_GET_DEVICE_ATTR: { 4476 struct kvm_device_attr attr; 4477 r = -EFAULT; 4478 if (copy_from_user(&attr, (void __user *)arg, sizeof(attr))) 4479 break; 4480 r = kvm_x86_dev_get_attr(&attr); 4481 break; 4482 } 4483 case KVM_HAS_DEVICE_ATTR: { 4484 struct kvm_device_attr attr; 4485 r = -EFAULT; 4486 if (copy_from_user(&attr, (void __user *)arg, sizeof(attr))) 4487 break; 4488 r = kvm_x86_dev_has_attr(&attr); 4489 break; 4490 } 4491 default: 4492 r = -EINVAL; 4493 break; 4494 } 4495 out: 4496 return r; 4497 } 4498 4499 static void wbinvd_ipi(void *garbage) 4500 { 4501 wbinvd(); 4502 } 4503 4504 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu) 4505 { 4506 return kvm_arch_has_noncoherent_dma(vcpu->kvm); 4507 } 4508 4509 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) 4510 { 4511 /* Address WBINVD may be executed by guest */ 4512 if (need_emulate_wbinvd(vcpu)) { 4513 if (static_call(kvm_x86_has_wbinvd_exit)()) 4514 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); 4515 else if (vcpu->cpu != -1 && vcpu->cpu != cpu) 4516 smp_call_function_single(vcpu->cpu, 4517 wbinvd_ipi, NULL, 1); 4518 } 4519 4520 static_call(kvm_x86_vcpu_load)(vcpu, cpu); 4521 4522 /* Save host pkru register if supported */ 4523 vcpu->arch.host_pkru = read_pkru(); 4524 4525 /* Apply any externally detected TSC adjustments (due to suspend) */ 4526 if (unlikely(vcpu->arch.tsc_offset_adjustment)) { 4527 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment); 4528 vcpu->arch.tsc_offset_adjustment = 0; 4529 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 4530 } 4531 4532 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) { 4533 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 : 4534 rdtsc() - vcpu->arch.last_host_tsc; 4535 if (tsc_delta < 0) 4536 mark_tsc_unstable("KVM discovered backwards TSC"); 4537 4538 if (kvm_check_tsc_unstable()) { 4539 u64 offset = kvm_compute_l1_tsc_offset(vcpu, 4540 vcpu->arch.last_guest_tsc); 4541 kvm_vcpu_write_tsc_offset(vcpu, offset); 4542 vcpu->arch.tsc_catchup = 1; 4543 } 4544 4545 if (kvm_lapic_hv_timer_in_use(vcpu)) 4546 kvm_lapic_restart_hv_timer(vcpu); 4547 4548 /* 4549 * On a host with synchronized TSC, there is no need to update 4550 * kvmclock on vcpu->cpu migration 4551 */ 4552 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1) 4553 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); 4554 if (vcpu->cpu != cpu) 4555 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu); 4556 vcpu->cpu = cpu; 4557 } 4558 4559 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); 4560 } 4561 4562 static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu) 4563 { 4564 struct gfn_to_hva_cache *ghc = &vcpu->arch.st.cache; 4565 struct kvm_steal_time __user *st; 4566 struct kvm_memslots *slots; 4567 static const u8 preempted = KVM_VCPU_PREEMPTED; 4568 4569 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) 4570 return; 4571 4572 if (vcpu->arch.st.preempted) 4573 return; 4574 4575 /* This happens on process exit */ 4576 if (unlikely(current->mm != vcpu->kvm->mm)) 4577 return; 4578 4579 slots = kvm_memslots(vcpu->kvm); 4580 4581 if (unlikely(slots->generation != ghc->generation || 4582 kvm_is_error_hva(ghc->hva) || !ghc->memslot)) 4583 return; 4584 4585 st = (struct kvm_steal_time __user *)ghc->hva; 4586 BUILD_BUG_ON(sizeof(st->preempted) != sizeof(preempted)); 4587 4588 if (!copy_to_user_nofault(&st->preempted, &preempted, sizeof(preempted))) 4589 vcpu->arch.st.preempted = KVM_VCPU_PREEMPTED; 4590 4591 mark_page_dirty_in_slot(vcpu->kvm, ghc->memslot, gpa_to_gfn(ghc->gpa)); 4592 } 4593 4594 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) 4595 { 4596 int idx; 4597 4598 if (vcpu->preempted && !vcpu->arch.guest_state_protected) 4599 vcpu->arch.preempted_in_kernel = !static_call(kvm_x86_get_cpl)(vcpu); 4600 4601 /* 4602 * Take the srcu lock as memslots will be accessed to check the gfn 4603 * cache generation against the memslots generation. 4604 */ 4605 idx = srcu_read_lock(&vcpu->kvm->srcu); 4606 if (kvm_xen_msr_enabled(vcpu->kvm)) 4607 kvm_xen_runstate_set_preempted(vcpu); 4608 else 4609 kvm_steal_time_set_preempted(vcpu); 4610 srcu_read_unlock(&vcpu->kvm->srcu, idx); 4611 4612 static_call(kvm_x86_vcpu_put)(vcpu); 4613 vcpu->arch.last_host_tsc = rdtsc(); 4614 } 4615 4616 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu, 4617 struct kvm_lapic_state *s) 4618 { 4619 static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu); 4620 4621 return kvm_apic_get_state(vcpu, s); 4622 } 4623 4624 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu, 4625 struct kvm_lapic_state *s) 4626 { 4627 int r; 4628 4629 r = kvm_apic_set_state(vcpu, s); 4630 if (r) 4631 return r; 4632 update_cr8_intercept(vcpu); 4633 4634 return 0; 4635 } 4636 4637 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu) 4638 { 4639 /* 4640 * We can accept userspace's request for interrupt injection 4641 * as long as we have a place to store the interrupt number. 4642 * The actual injection will happen when the CPU is able to 4643 * deliver the interrupt. 4644 */ 4645 if (kvm_cpu_has_extint(vcpu)) 4646 return false; 4647 4648 /* Acknowledging ExtINT does not happen if LINT0 is masked. */ 4649 return (!lapic_in_kernel(vcpu) || 4650 kvm_apic_accept_pic_intr(vcpu)); 4651 } 4652 4653 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu) 4654 { 4655 /* 4656 * Do not cause an interrupt window exit if an exception 4657 * is pending or an event needs reinjection; userspace 4658 * might want to inject the interrupt manually using KVM_SET_REGS 4659 * or KVM_SET_SREGS. For that to work, we must be at an 4660 * instruction boundary and with no events half-injected. 4661 */ 4662 return (kvm_arch_interrupt_allowed(vcpu) && 4663 kvm_cpu_accept_dm_intr(vcpu) && 4664 !kvm_event_needs_reinjection(vcpu) && 4665 !vcpu->arch.exception.pending); 4666 } 4667 4668 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, 4669 struct kvm_interrupt *irq) 4670 { 4671 if (irq->irq >= KVM_NR_INTERRUPTS) 4672 return -EINVAL; 4673 4674 if (!irqchip_in_kernel(vcpu->kvm)) { 4675 kvm_queue_interrupt(vcpu, irq->irq, false); 4676 kvm_make_request(KVM_REQ_EVENT, vcpu); 4677 return 0; 4678 } 4679 4680 /* 4681 * With in-kernel LAPIC, we only use this to inject EXTINT, so 4682 * fail for in-kernel 8259. 4683 */ 4684 if (pic_in_kernel(vcpu->kvm)) 4685 return -ENXIO; 4686 4687 if (vcpu->arch.pending_external_vector != -1) 4688 return -EEXIST; 4689 4690 vcpu->arch.pending_external_vector = irq->irq; 4691 kvm_make_request(KVM_REQ_EVENT, vcpu); 4692 return 0; 4693 } 4694 4695 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu) 4696 { 4697 kvm_inject_nmi(vcpu); 4698 4699 return 0; 4700 } 4701 4702 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu) 4703 { 4704 kvm_make_request(KVM_REQ_SMI, vcpu); 4705 4706 return 0; 4707 } 4708 4709 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu, 4710 struct kvm_tpr_access_ctl *tac) 4711 { 4712 if (tac->flags) 4713 return -EINVAL; 4714 vcpu->arch.tpr_access_reporting = !!tac->enabled; 4715 return 0; 4716 } 4717 4718 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu, 4719 u64 mcg_cap) 4720 { 4721 int r; 4722 unsigned bank_num = mcg_cap & 0xff, bank; 4723 4724 r = -EINVAL; 4725 if (!bank_num || bank_num > KVM_MAX_MCE_BANKS) 4726 goto out; 4727 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000)) 4728 goto out; 4729 r = 0; 4730 vcpu->arch.mcg_cap = mcg_cap; 4731 /* Init IA32_MCG_CTL to all 1s */ 4732 if (mcg_cap & MCG_CTL_P) 4733 vcpu->arch.mcg_ctl = ~(u64)0; 4734 /* Init IA32_MCi_CTL to all 1s */ 4735 for (bank = 0; bank < bank_num; bank++) 4736 vcpu->arch.mce_banks[bank*4] = ~(u64)0; 4737 4738 static_call(kvm_x86_setup_mce)(vcpu); 4739 out: 4740 return r; 4741 } 4742 4743 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu, 4744 struct kvm_x86_mce *mce) 4745 { 4746 u64 mcg_cap = vcpu->arch.mcg_cap; 4747 unsigned bank_num = mcg_cap & 0xff; 4748 u64 *banks = vcpu->arch.mce_banks; 4749 4750 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL)) 4751 return -EINVAL; 4752 /* 4753 * if IA32_MCG_CTL is not all 1s, the uncorrected error 4754 * reporting is disabled 4755 */ 4756 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) && 4757 vcpu->arch.mcg_ctl != ~(u64)0) 4758 return 0; 4759 banks += 4 * mce->bank; 4760 /* 4761 * if IA32_MCi_CTL is not all 1s, the uncorrected error 4762 * reporting is disabled for the bank 4763 */ 4764 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0) 4765 return 0; 4766 if (mce->status & MCI_STATUS_UC) { 4767 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) || 4768 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) { 4769 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 4770 return 0; 4771 } 4772 if (banks[1] & MCI_STATUS_VAL) 4773 mce->status |= MCI_STATUS_OVER; 4774 banks[2] = mce->addr; 4775 banks[3] = mce->misc; 4776 vcpu->arch.mcg_status = mce->mcg_status; 4777 banks[1] = mce->status; 4778 kvm_queue_exception(vcpu, MC_VECTOR); 4779 } else if (!(banks[1] & MCI_STATUS_VAL) 4780 || !(banks[1] & MCI_STATUS_UC)) { 4781 if (banks[1] & MCI_STATUS_VAL) 4782 mce->status |= MCI_STATUS_OVER; 4783 banks[2] = mce->addr; 4784 banks[3] = mce->misc; 4785 banks[1] = mce->status; 4786 } else 4787 banks[1] |= MCI_STATUS_OVER; 4788 return 0; 4789 } 4790 4791 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu, 4792 struct kvm_vcpu_events *events) 4793 { 4794 process_nmi(vcpu); 4795 4796 if (kvm_check_request(KVM_REQ_SMI, vcpu)) 4797 process_smi(vcpu); 4798 4799 /* 4800 * In guest mode, payload delivery should be deferred, 4801 * so that the L1 hypervisor can intercept #PF before 4802 * CR2 is modified (or intercept #DB before DR6 is 4803 * modified under nVMX). Unless the per-VM capability, 4804 * KVM_CAP_EXCEPTION_PAYLOAD, is set, we may not defer the delivery of 4805 * an exception payload and handle after a KVM_GET_VCPU_EVENTS. Since we 4806 * opportunistically defer the exception payload, deliver it if the 4807 * capability hasn't been requested before processing a 4808 * KVM_GET_VCPU_EVENTS. 4809 */ 4810 if (!vcpu->kvm->arch.exception_payload_enabled && 4811 vcpu->arch.exception.pending && vcpu->arch.exception.has_payload) 4812 kvm_deliver_exception_payload(vcpu); 4813 4814 /* 4815 * The API doesn't provide the instruction length for software 4816 * exceptions, so don't report them. As long as the guest RIP 4817 * isn't advanced, we should expect to encounter the exception 4818 * again. 4819 */ 4820 if (kvm_exception_is_soft(vcpu->arch.exception.nr)) { 4821 events->exception.injected = 0; 4822 events->exception.pending = 0; 4823 } else { 4824 events->exception.injected = vcpu->arch.exception.injected; 4825 events->exception.pending = vcpu->arch.exception.pending; 4826 /* 4827 * For ABI compatibility, deliberately conflate 4828 * pending and injected exceptions when 4829 * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled. 4830 */ 4831 if (!vcpu->kvm->arch.exception_payload_enabled) 4832 events->exception.injected |= 4833 vcpu->arch.exception.pending; 4834 } 4835 events->exception.nr = vcpu->arch.exception.nr; 4836 events->exception.has_error_code = vcpu->arch.exception.has_error_code; 4837 events->exception.error_code = vcpu->arch.exception.error_code; 4838 events->exception_has_payload = vcpu->arch.exception.has_payload; 4839 events->exception_payload = vcpu->arch.exception.payload; 4840 4841 events->interrupt.injected = 4842 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft; 4843 events->interrupt.nr = vcpu->arch.interrupt.nr; 4844 events->interrupt.soft = 0; 4845 events->interrupt.shadow = static_call(kvm_x86_get_interrupt_shadow)(vcpu); 4846 4847 events->nmi.injected = vcpu->arch.nmi_injected; 4848 events->nmi.pending = vcpu->arch.nmi_pending != 0; 4849 events->nmi.masked = static_call(kvm_x86_get_nmi_mask)(vcpu); 4850 events->nmi.pad = 0; 4851 4852 events->sipi_vector = 0; /* never valid when reporting to user space */ 4853 4854 events->smi.smm = is_smm(vcpu); 4855 events->smi.pending = vcpu->arch.smi_pending; 4856 events->smi.smm_inside_nmi = 4857 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK); 4858 events->smi.latched_init = kvm_lapic_latched_init(vcpu); 4859 4860 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING 4861 | KVM_VCPUEVENT_VALID_SHADOW 4862 | KVM_VCPUEVENT_VALID_SMM); 4863 if (vcpu->kvm->arch.exception_payload_enabled) 4864 events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD; 4865 4866 memset(&events->reserved, 0, sizeof(events->reserved)); 4867 } 4868 4869 static void kvm_smm_changed(struct kvm_vcpu *vcpu, bool entering_smm); 4870 4871 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu, 4872 struct kvm_vcpu_events *events) 4873 { 4874 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING 4875 | KVM_VCPUEVENT_VALID_SIPI_VECTOR 4876 | KVM_VCPUEVENT_VALID_SHADOW 4877 | KVM_VCPUEVENT_VALID_SMM 4878 | KVM_VCPUEVENT_VALID_PAYLOAD)) 4879 return -EINVAL; 4880 4881 if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) { 4882 if (!vcpu->kvm->arch.exception_payload_enabled) 4883 return -EINVAL; 4884 if (events->exception.pending) 4885 events->exception.injected = 0; 4886 else 4887 events->exception_has_payload = 0; 4888 } else { 4889 events->exception.pending = 0; 4890 events->exception_has_payload = 0; 4891 } 4892 4893 if ((events->exception.injected || events->exception.pending) && 4894 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR)) 4895 return -EINVAL; 4896 4897 /* INITs are latched while in SMM */ 4898 if (events->flags & KVM_VCPUEVENT_VALID_SMM && 4899 (events->smi.smm || events->smi.pending) && 4900 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) 4901 return -EINVAL; 4902 4903 process_nmi(vcpu); 4904 vcpu->arch.exception.injected = events->exception.injected; 4905 vcpu->arch.exception.pending = events->exception.pending; 4906 vcpu->arch.exception.nr = events->exception.nr; 4907 vcpu->arch.exception.has_error_code = events->exception.has_error_code; 4908 vcpu->arch.exception.error_code = events->exception.error_code; 4909 vcpu->arch.exception.has_payload = events->exception_has_payload; 4910 vcpu->arch.exception.payload = events->exception_payload; 4911 4912 vcpu->arch.interrupt.injected = events->interrupt.injected; 4913 vcpu->arch.interrupt.nr = events->interrupt.nr; 4914 vcpu->arch.interrupt.soft = events->interrupt.soft; 4915 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW) 4916 static_call(kvm_x86_set_interrupt_shadow)(vcpu, 4917 events->interrupt.shadow); 4918 4919 vcpu->arch.nmi_injected = events->nmi.injected; 4920 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING) 4921 vcpu->arch.nmi_pending = events->nmi.pending; 4922 static_call(kvm_x86_set_nmi_mask)(vcpu, events->nmi.masked); 4923 4924 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR && 4925 lapic_in_kernel(vcpu)) 4926 vcpu->arch.apic->sipi_vector = events->sipi_vector; 4927 4928 if (events->flags & KVM_VCPUEVENT_VALID_SMM) { 4929 if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) { 4930 kvm_x86_ops.nested_ops->leave_nested(vcpu); 4931 kvm_smm_changed(vcpu, events->smi.smm); 4932 } 4933 4934 vcpu->arch.smi_pending = events->smi.pending; 4935 4936 if (events->smi.smm) { 4937 if (events->smi.smm_inside_nmi) 4938 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; 4939 else 4940 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK; 4941 } 4942 4943 if (lapic_in_kernel(vcpu)) { 4944 if (events->smi.latched_init) 4945 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); 4946 else 4947 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); 4948 } 4949 } 4950 4951 kvm_make_request(KVM_REQ_EVENT, vcpu); 4952 4953 return 0; 4954 } 4955 4956 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu, 4957 struct kvm_debugregs *dbgregs) 4958 { 4959 unsigned long val; 4960 4961 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db)); 4962 kvm_get_dr(vcpu, 6, &val); 4963 dbgregs->dr6 = val; 4964 dbgregs->dr7 = vcpu->arch.dr7; 4965 dbgregs->flags = 0; 4966 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved)); 4967 } 4968 4969 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu, 4970 struct kvm_debugregs *dbgregs) 4971 { 4972 if (dbgregs->flags) 4973 return -EINVAL; 4974 4975 if (!kvm_dr6_valid(dbgregs->dr6)) 4976 return -EINVAL; 4977 if (!kvm_dr7_valid(dbgregs->dr7)) 4978 return -EINVAL; 4979 4980 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db)); 4981 kvm_update_dr0123(vcpu); 4982 vcpu->arch.dr6 = dbgregs->dr6; 4983 vcpu->arch.dr7 = dbgregs->dr7; 4984 kvm_update_dr7(vcpu); 4985 4986 return 0; 4987 } 4988 4989 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu, 4990 struct kvm_xsave *guest_xsave) 4991 { 4992 if (fpstate_is_confidential(&vcpu->arch.guest_fpu)) 4993 return; 4994 4995 fpu_copy_guest_fpstate_to_uabi(&vcpu->arch.guest_fpu, 4996 guest_xsave->region, 4997 sizeof(guest_xsave->region), 4998 vcpu->arch.pkru); 4999 } 5000 5001 static void kvm_vcpu_ioctl_x86_get_xsave2(struct kvm_vcpu *vcpu, 5002 u8 *state, unsigned int size) 5003 { 5004 if (fpstate_is_confidential(&vcpu->arch.guest_fpu)) 5005 return; 5006 5007 fpu_copy_guest_fpstate_to_uabi(&vcpu->arch.guest_fpu, 5008 state, size, vcpu->arch.pkru); 5009 } 5010 5011 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu, 5012 struct kvm_xsave *guest_xsave) 5013 { 5014 if (fpstate_is_confidential(&vcpu->arch.guest_fpu)) 5015 return 0; 5016 5017 return fpu_copy_uabi_to_guest_fpstate(&vcpu->arch.guest_fpu, 5018 guest_xsave->region, 5019 supported_xcr0, &vcpu->arch.pkru); 5020 } 5021 5022 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu, 5023 struct kvm_xcrs *guest_xcrs) 5024 { 5025 if (!boot_cpu_has(X86_FEATURE_XSAVE)) { 5026 guest_xcrs->nr_xcrs = 0; 5027 return; 5028 } 5029 5030 guest_xcrs->nr_xcrs = 1; 5031 guest_xcrs->flags = 0; 5032 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK; 5033 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0; 5034 } 5035 5036 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu, 5037 struct kvm_xcrs *guest_xcrs) 5038 { 5039 int i, r = 0; 5040 5041 if (!boot_cpu_has(X86_FEATURE_XSAVE)) 5042 return -EINVAL; 5043 5044 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags) 5045 return -EINVAL; 5046 5047 for (i = 0; i < guest_xcrs->nr_xcrs; i++) 5048 /* Only support XCR0 currently */ 5049 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) { 5050 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK, 5051 guest_xcrs->xcrs[i].value); 5052 break; 5053 } 5054 if (r) 5055 r = -EINVAL; 5056 return r; 5057 } 5058 5059 /* 5060 * kvm_set_guest_paused() indicates to the guest kernel that it has been 5061 * stopped by the hypervisor. This function will be called from the host only. 5062 * EINVAL is returned when the host attempts to set the flag for a guest that 5063 * does not support pv clocks. 5064 */ 5065 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu) 5066 { 5067 if (!vcpu->arch.pv_time_enabled) 5068 return -EINVAL; 5069 vcpu->arch.pvclock_set_guest_stopped_request = true; 5070 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 5071 return 0; 5072 } 5073 5074 static int kvm_arch_tsc_has_attr(struct kvm_vcpu *vcpu, 5075 struct kvm_device_attr *attr) 5076 { 5077 int r; 5078 5079 switch (attr->attr) { 5080 case KVM_VCPU_TSC_OFFSET: 5081 r = 0; 5082 break; 5083 default: 5084 r = -ENXIO; 5085 } 5086 5087 return r; 5088 } 5089 5090 static int kvm_arch_tsc_get_attr(struct kvm_vcpu *vcpu, 5091 struct kvm_device_attr *attr) 5092 { 5093 u64 __user *uaddr = kvm_get_attr_addr(attr); 5094 int r; 5095 5096 if (IS_ERR(uaddr)) 5097 return PTR_ERR(uaddr); 5098 5099 switch (attr->attr) { 5100 case KVM_VCPU_TSC_OFFSET: 5101 r = -EFAULT; 5102 if (put_user(vcpu->arch.l1_tsc_offset, uaddr)) 5103 break; 5104 r = 0; 5105 break; 5106 default: 5107 r = -ENXIO; 5108 } 5109 5110 return r; 5111 } 5112 5113 static int kvm_arch_tsc_set_attr(struct kvm_vcpu *vcpu, 5114 struct kvm_device_attr *attr) 5115 { 5116 u64 __user *uaddr = kvm_get_attr_addr(attr); 5117 struct kvm *kvm = vcpu->kvm; 5118 int r; 5119 5120 if (IS_ERR(uaddr)) 5121 return PTR_ERR(uaddr); 5122 5123 switch (attr->attr) { 5124 case KVM_VCPU_TSC_OFFSET: { 5125 u64 offset, tsc, ns; 5126 unsigned long flags; 5127 bool matched; 5128 5129 r = -EFAULT; 5130 if (get_user(offset, uaddr)) 5131 break; 5132 5133 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags); 5134 5135 matched = (vcpu->arch.virtual_tsc_khz && 5136 kvm->arch.last_tsc_khz == vcpu->arch.virtual_tsc_khz && 5137 kvm->arch.last_tsc_offset == offset); 5138 5139 tsc = kvm_scale_tsc(rdtsc(), vcpu->arch.l1_tsc_scaling_ratio) + offset; 5140 ns = get_kvmclock_base_ns(); 5141 5142 __kvm_synchronize_tsc(vcpu, offset, tsc, ns, matched); 5143 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags); 5144 5145 r = 0; 5146 break; 5147 } 5148 default: 5149 r = -ENXIO; 5150 } 5151 5152 return r; 5153 } 5154 5155 static int kvm_vcpu_ioctl_device_attr(struct kvm_vcpu *vcpu, 5156 unsigned int ioctl, 5157 void __user *argp) 5158 { 5159 struct kvm_device_attr attr; 5160 int r; 5161 5162 if (copy_from_user(&attr, argp, sizeof(attr))) 5163 return -EFAULT; 5164 5165 if (attr.group != KVM_VCPU_TSC_CTRL) 5166 return -ENXIO; 5167 5168 switch (ioctl) { 5169 case KVM_HAS_DEVICE_ATTR: 5170 r = kvm_arch_tsc_has_attr(vcpu, &attr); 5171 break; 5172 case KVM_GET_DEVICE_ATTR: 5173 r = kvm_arch_tsc_get_attr(vcpu, &attr); 5174 break; 5175 case KVM_SET_DEVICE_ATTR: 5176 r = kvm_arch_tsc_set_attr(vcpu, &attr); 5177 break; 5178 } 5179 5180 return r; 5181 } 5182 5183 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu, 5184 struct kvm_enable_cap *cap) 5185 { 5186 int r; 5187 uint16_t vmcs_version; 5188 void __user *user_ptr; 5189 5190 if (cap->flags) 5191 return -EINVAL; 5192 5193 switch (cap->cap) { 5194 case KVM_CAP_HYPERV_SYNIC2: 5195 if (cap->args[0]) 5196 return -EINVAL; 5197 fallthrough; 5198 5199 case KVM_CAP_HYPERV_SYNIC: 5200 if (!irqchip_in_kernel(vcpu->kvm)) 5201 return -EINVAL; 5202 return kvm_hv_activate_synic(vcpu, cap->cap == 5203 KVM_CAP_HYPERV_SYNIC2); 5204 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS: 5205 if (!kvm_x86_ops.nested_ops->enable_evmcs) 5206 return -ENOTTY; 5207 r = kvm_x86_ops.nested_ops->enable_evmcs(vcpu, &vmcs_version); 5208 if (!r) { 5209 user_ptr = (void __user *)(uintptr_t)cap->args[0]; 5210 if (copy_to_user(user_ptr, &vmcs_version, 5211 sizeof(vmcs_version))) 5212 r = -EFAULT; 5213 } 5214 return r; 5215 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH: 5216 if (!kvm_x86_ops.enable_direct_tlbflush) 5217 return -ENOTTY; 5218 5219 return static_call(kvm_x86_enable_direct_tlbflush)(vcpu); 5220 5221 case KVM_CAP_HYPERV_ENFORCE_CPUID: 5222 return kvm_hv_set_enforce_cpuid(vcpu, cap->args[0]); 5223 5224 case KVM_CAP_ENFORCE_PV_FEATURE_CPUID: 5225 vcpu->arch.pv_cpuid.enforce = cap->args[0]; 5226 if (vcpu->arch.pv_cpuid.enforce) 5227 kvm_update_pv_runtime(vcpu); 5228 5229 return 0; 5230 default: 5231 return -EINVAL; 5232 } 5233 } 5234 5235 long kvm_arch_vcpu_ioctl(struct file *filp, 5236 unsigned int ioctl, unsigned long arg) 5237 { 5238 struct kvm_vcpu *vcpu = filp->private_data; 5239 void __user *argp = (void __user *)arg; 5240 int r; 5241 union { 5242 struct kvm_sregs2 *sregs2; 5243 struct kvm_lapic_state *lapic; 5244 struct kvm_xsave *xsave; 5245 struct kvm_xcrs *xcrs; 5246 void *buffer; 5247 } u; 5248 5249 vcpu_load(vcpu); 5250 5251 u.buffer = NULL; 5252 switch (ioctl) { 5253 case KVM_GET_LAPIC: { 5254 r = -EINVAL; 5255 if (!lapic_in_kernel(vcpu)) 5256 goto out; 5257 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), 5258 GFP_KERNEL_ACCOUNT); 5259 5260 r = -ENOMEM; 5261 if (!u.lapic) 5262 goto out; 5263 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic); 5264 if (r) 5265 goto out; 5266 r = -EFAULT; 5267 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state))) 5268 goto out; 5269 r = 0; 5270 break; 5271 } 5272 case KVM_SET_LAPIC: { 5273 r = -EINVAL; 5274 if (!lapic_in_kernel(vcpu)) 5275 goto out; 5276 u.lapic = memdup_user(argp, sizeof(*u.lapic)); 5277 if (IS_ERR(u.lapic)) { 5278 r = PTR_ERR(u.lapic); 5279 goto out_nofree; 5280 } 5281 5282 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic); 5283 break; 5284 } 5285 case KVM_INTERRUPT: { 5286 struct kvm_interrupt irq; 5287 5288 r = -EFAULT; 5289 if (copy_from_user(&irq, argp, sizeof(irq))) 5290 goto out; 5291 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq); 5292 break; 5293 } 5294 case KVM_NMI: { 5295 r = kvm_vcpu_ioctl_nmi(vcpu); 5296 break; 5297 } 5298 case KVM_SMI: { 5299 r = kvm_vcpu_ioctl_smi(vcpu); 5300 break; 5301 } 5302 case KVM_SET_CPUID: { 5303 struct kvm_cpuid __user *cpuid_arg = argp; 5304 struct kvm_cpuid cpuid; 5305 5306 r = -EFAULT; 5307 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 5308 goto out; 5309 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries); 5310 break; 5311 } 5312 case KVM_SET_CPUID2: { 5313 struct kvm_cpuid2 __user *cpuid_arg = argp; 5314 struct kvm_cpuid2 cpuid; 5315 5316 r = -EFAULT; 5317 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 5318 goto out; 5319 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid, 5320 cpuid_arg->entries); 5321 break; 5322 } 5323 case KVM_GET_CPUID2: { 5324 struct kvm_cpuid2 __user *cpuid_arg = argp; 5325 struct kvm_cpuid2 cpuid; 5326 5327 r = -EFAULT; 5328 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 5329 goto out; 5330 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid, 5331 cpuid_arg->entries); 5332 if (r) 5333 goto out; 5334 r = -EFAULT; 5335 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) 5336 goto out; 5337 r = 0; 5338 break; 5339 } 5340 case KVM_GET_MSRS: { 5341 int idx = srcu_read_lock(&vcpu->kvm->srcu); 5342 r = msr_io(vcpu, argp, do_get_msr, 1); 5343 srcu_read_unlock(&vcpu->kvm->srcu, idx); 5344 break; 5345 } 5346 case KVM_SET_MSRS: { 5347 int idx = srcu_read_lock(&vcpu->kvm->srcu); 5348 r = msr_io(vcpu, argp, do_set_msr, 0); 5349 srcu_read_unlock(&vcpu->kvm->srcu, idx); 5350 break; 5351 } 5352 case KVM_TPR_ACCESS_REPORTING: { 5353 struct kvm_tpr_access_ctl tac; 5354 5355 r = -EFAULT; 5356 if (copy_from_user(&tac, argp, sizeof(tac))) 5357 goto out; 5358 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac); 5359 if (r) 5360 goto out; 5361 r = -EFAULT; 5362 if (copy_to_user(argp, &tac, sizeof(tac))) 5363 goto out; 5364 r = 0; 5365 break; 5366 }; 5367 case KVM_SET_VAPIC_ADDR: { 5368 struct kvm_vapic_addr va; 5369 int idx; 5370 5371 r = -EINVAL; 5372 if (!lapic_in_kernel(vcpu)) 5373 goto out; 5374 r = -EFAULT; 5375 if (copy_from_user(&va, argp, sizeof(va))) 5376 goto out; 5377 idx = srcu_read_lock(&vcpu->kvm->srcu); 5378 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr); 5379 srcu_read_unlock(&vcpu->kvm->srcu, idx); 5380 break; 5381 } 5382 case KVM_X86_SETUP_MCE: { 5383 u64 mcg_cap; 5384 5385 r = -EFAULT; 5386 if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap))) 5387 goto out; 5388 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap); 5389 break; 5390 } 5391 case KVM_X86_SET_MCE: { 5392 struct kvm_x86_mce mce; 5393 5394 r = -EFAULT; 5395 if (copy_from_user(&mce, argp, sizeof(mce))) 5396 goto out; 5397 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce); 5398 break; 5399 } 5400 case KVM_GET_VCPU_EVENTS: { 5401 struct kvm_vcpu_events events; 5402 5403 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events); 5404 5405 r = -EFAULT; 5406 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events))) 5407 break; 5408 r = 0; 5409 break; 5410 } 5411 case KVM_SET_VCPU_EVENTS: { 5412 struct kvm_vcpu_events events; 5413 5414 r = -EFAULT; 5415 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events))) 5416 break; 5417 5418 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events); 5419 break; 5420 } 5421 case KVM_GET_DEBUGREGS: { 5422 struct kvm_debugregs dbgregs; 5423 5424 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs); 5425 5426 r = -EFAULT; 5427 if (copy_to_user(argp, &dbgregs, 5428 sizeof(struct kvm_debugregs))) 5429 break; 5430 r = 0; 5431 break; 5432 } 5433 case KVM_SET_DEBUGREGS: { 5434 struct kvm_debugregs dbgregs; 5435 5436 r = -EFAULT; 5437 if (copy_from_user(&dbgregs, argp, 5438 sizeof(struct kvm_debugregs))) 5439 break; 5440 5441 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs); 5442 break; 5443 } 5444 case KVM_GET_XSAVE: { 5445 r = -EINVAL; 5446 if (vcpu->arch.guest_fpu.uabi_size > sizeof(struct kvm_xsave)) 5447 break; 5448 5449 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT); 5450 r = -ENOMEM; 5451 if (!u.xsave) 5452 break; 5453 5454 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave); 5455 5456 r = -EFAULT; 5457 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave))) 5458 break; 5459 r = 0; 5460 break; 5461 } 5462 case KVM_SET_XSAVE: { 5463 int size = vcpu->arch.guest_fpu.uabi_size; 5464 5465 u.xsave = memdup_user(argp, size); 5466 if (IS_ERR(u.xsave)) { 5467 r = PTR_ERR(u.xsave); 5468 goto out_nofree; 5469 } 5470 5471 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave); 5472 break; 5473 } 5474 5475 case KVM_GET_XSAVE2: { 5476 int size = vcpu->arch.guest_fpu.uabi_size; 5477 5478 u.xsave = kzalloc(size, GFP_KERNEL_ACCOUNT); 5479 r = -ENOMEM; 5480 if (!u.xsave) 5481 break; 5482 5483 kvm_vcpu_ioctl_x86_get_xsave2(vcpu, u.buffer, size); 5484 5485 r = -EFAULT; 5486 if (copy_to_user(argp, u.xsave, size)) 5487 break; 5488 5489 r = 0; 5490 break; 5491 } 5492 5493 case KVM_GET_XCRS: { 5494 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT); 5495 r = -ENOMEM; 5496 if (!u.xcrs) 5497 break; 5498 5499 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs); 5500 5501 r = -EFAULT; 5502 if (copy_to_user(argp, u.xcrs, 5503 sizeof(struct kvm_xcrs))) 5504 break; 5505 r = 0; 5506 break; 5507 } 5508 case KVM_SET_XCRS: { 5509 u.xcrs = memdup_user(argp, sizeof(*u.xcrs)); 5510 if (IS_ERR(u.xcrs)) { 5511 r = PTR_ERR(u.xcrs); 5512 goto out_nofree; 5513 } 5514 5515 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs); 5516 break; 5517 } 5518 case KVM_SET_TSC_KHZ: { 5519 u32 user_tsc_khz; 5520 5521 r = -EINVAL; 5522 user_tsc_khz = (u32)arg; 5523 5524 if (kvm_has_tsc_control && 5525 user_tsc_khz >= kvm_max_guest_tsc_khz) 5526 goto out; 5527 5528 if (user_tsc_khz == 0) 5529 user_tsc_khz = tsc_khz; 5530 5531 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz)) 5532 r = 0; 5533 5534 goto out; 5535 } 5536 case KVM_GET_TSC_KHZ: { 5537 r = vcpu->arch.virtual_tsc_khz; 5538 goto out; 5539 } 5540 case KVM_KVMCLOCK_CTRL: { 5541 r = kvm_set_guest_paused(vcpu); 5542 goto out; 5543 } 5544 case KVM_ENABLE_CAP: { 5545 struct kvm_enable_cap cap; 5546 5547 r = -EFAULT; 5548 if (copy_from_user(&cap, argp, sizeof(cap))) 5549 goto out; 5550 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap); 5551 break; 5552 } 5553 case KVM_GET_NESTED_STATE: { 5554 struct kvm_nested_state __user *user_kvm_nested_state = argp; 5555 u32 user_data_size; 5556 5557 r = -EINVAL; 5558 if (!kvm_x86_ops.nested_ops->get_state) 5559 break; 5560 5561 BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size)); 5562 r = -EFAULT; 5563 if (get_user(user_data_size, &user_kvm_nested_state->size)) 5564 break; 5565 5566 r = kvm_x86_ops.nested_ops->get_state(vcpu, user_kvm_nested_state, 5567 user_data_size); 5568 if (r < 0) 5569 break; 5570 5571 if (r > user_data_size) { 5572 if (put_user(r, &user_kvm_nested_state->size)) 5573 r = -EFAULT; 5574 else 5575 r = -E2BIG; 5576 break; 5577 } 5578 5579 r = 0; 5580 break; 5581 } 5582 case KVM_SET_NESTED_STATE: { 5583 struct kvm_nested_state __user *user_kvm_nested_state = argp; 5584 struct kvm_nested_state kvm_state; 5585 int idx; 5586 5587 r = -EINVAL; 5588 if (!kvm_x86_ops.nested_ops->set_state) 5589 break; 5590 5591 r = -EFAULT; 5592 if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state))) 5593 break; 5594 5595 r = -EINVAL; 5596 if (kvm_state.size < sizeof(kvm_state)) 5597 break; 5598 5599 if (kvm_state.flags & 5600 ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE 5601 | KVM_STATE_NESTED_EVMCS | KVM_STATE_NESTED_MTF_PENDING 5602 | KVM_STATE_NESTED_GIF_SET)) 5603 break; 5604 5605 /* nested_run_pending implies guest_mode. */ 5606 if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING) 5607 && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE)) 5608 break; 5609 5610 idx = srcu_read_lock(&vcpu->kvm->srcu); 5611 r = kvm_x86_ops.nested_ops->set_state(vcpu, user_kvm_nested_state, &kvm_state); 5612 srcu_read_unlock(&vcpu->kvm->srcu, idx); 5613 break; 5614 } 5615 case KVM_GET_SUPPORTED_HV_CPUID: 5616 r = kvm_ioctl_get_supported_hv_cpuid(vcpu, argp); 5617 break; 5618 #ifdef CONFIG_KVM_XEN 5619 case KVM_XEN_VCPU_GET_ATTR: { 5620 struct kvm_xen_vcpu_attr xva; 5621 5622 r = -EFAULT; 5623 if (copy_from_user(&xva, argp, sizeof(xva))) 5624 goto out; 5625 r = kvm_xen_vcpu_get_attr(vcpu, &xva); 5626 if (!r && copy_to_user(argp, &xva, sizeof(xva))) 5627 r = -EFAULT; 5628 break; 5629 } 5630 case KVM_XEN_VCPU_SET_ATTR: { 5631 struct kvm_xen_vcpu_attr xva; 5632 5633 r = -EFAULT; 5634 if (copy_from_user(&xva, argp, sizeof(xva))) 5635 goto out; 5636 r = kvm_xen_vcpu_set_attr(vcpu, &xva); 5637 break; 5638 } 5639 #endif 5640 case KVM_GET_SREGS2: { 5641 u.sregs2 = kzalloc(sizeof(struct kvm_sregs2), GFP_KERNEL); 5642 r = -ENOMEM; 5643 if (!u.sregs2) 5644 goto out; 5645 __get_sregs2(vcpu, u.sregs2); 5646 r = -EFAULT; 5647 if (copy_to_user(argp, u.sregs2, sizeof(struct kvm_sregs2))) 5648 goto out; 5649 r = 0; 5650 break; 5651 } 5652 case KVM_SET_SREGS2: { 5653 u.sregs2 = memdup_user(argp, sizeof(struct kvm_sregs2)); 5654 if (IS_ERR(u.sregs2)) { 5655 r = PTR_ERR(u.sregs2); 5656 u.sregs2 = NULL; 5657 goto out; 5658 } 5659 r = __set_sregs2(vcpu, u.sregs2); 5660 break; 5661 } 5662 case KVM_HAS_DEVICE_ATTR: 5663 case KVM_GET_DEVICE_ATTR: 5664 case KVM_SET_DEVICE_ATTR: 5665 r = kvm_vcpu_ioctl_device_attr(vcpu, ioctl, argp); 5666 break; 5667 default: 5668 r = -EINVAL; 5669 } 5670 out: 5671 kfree(u.buffer); 5672 out_nofree: 5673 vcpu_put(vcpu); 5674 return r; 5675 } 5676 5677 vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf) 5678 { 5679 return VM_FAULT_SIGBUS; 5680 } 5681 5682 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr) 5683 { 5684 int ret; 5685 5686 if (addr > (unsigned int)(-3 * PAGE_SIZE)) 5687 return -EINVAL; 5688 ret = static_call(kvm_x86_set_tss_addr)(kvm, addr); 5689 return ret; 5690 } 5691 5692 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm, 5693 u64 ident_addr) 5694 { 5695 return static_call(kvm_x86_set_identity_map_addr)(kvm, ident_addr); 5696 } 5697 5698 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm, 5699 unsigned long kvm_nr_mmu_pages) 5700 { 5701 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES) 5702 return -EINVAL; 5703 5704 mutex_lock(&kvm->slots_lock); 5705 5706 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages); 5707 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages; 5708 5709 mutex_unlock(&kvm->slots_lock); 5710 return 0; 5711 } 5712 5713 static unsigned long kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm) 5714 { 5715 return kvm->arch.n_max_mmu_pages; 5716 } 5717 5718 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) 5719 { 5720 struct kvm_pic *pic = kvm->arch.vpic; 5721 int r; 5722 5723 r = 0; 5724 switch (chip->chip_id) { 5725 case KVM_IRQCHIP_PIC_MASTER: 5726 memcpy(&chip->chip.pic, &pic->pics[0], 5727 sizeof(struct kvm_pic_state)); 5728 break; 5729 case KVM_IRQCHIP_PIC_SLAVE: 5730 memcpy(&chip->chip.pic, &pic->pics[1], 5731 sizeof(struct kvm_pic_state)); 5732 break; 5733 case KVM_IRQCHIP_IOAPIC: 5734 kvm_get_ioapic(kvm, &chip->chip.ioapic); 5735 break; 5736 default: 5737 r = -EINVAL; 5738 break; 5739 } 5740 return r; 5741 } 5742 5743 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) 5744 { 5745 struct kvm_pic *pic = kvm->arch.vpic; 5746 int r; 5747 5748 r = 0; 5749 switch (chip->chip_id) { 5750 case KVM_IRQCHIP_PIC_MASTER: 5751 spin_lock(&pic->lock); 5752 memcpy(&pic->pics[0], &chip->chip.pic, 5753 sizeof(struct kvm_pic_state)); 5754 spin_unlock(&pic->lock); 5755 break; 5756 case KVM_IRQCHIP_PIC_SLAVE: 5757 spin_lock(&pic->lock); 5758 memcpy(&pic->pics[1], &chip->chip.pic, 5759 sizeof(struct kvm_pic_state)); 5760 spin_unlock(&pic->lock); 5761 break; 5762 case KVM_IRQCHIP_IOAPIC: 5763 kvm_set_ioapic(kvm, &chip->chip.ioapic); 5764 break; 5765 default: 5766 r = -EINVAL; 5767 break; 5768 } 5769 kvm_pic_update_irq(pic); 5770 return r; 5771 } 5772 5773 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps) 5774 { 5775 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state; 5776 5777 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels)); 5778 5779 mutex_lock(&kps->lock); 5780 memcpy(ps, &kps->channels, sizeof(*ps)); 5781 mutex_unlock(&kps->lock); 5782 return 0; 5783 } 5784 5785 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps) 5786 { 5787 int i; 5788 struct kvm_pit *pit = kvm->arch.vpit; 5789 5790 mutex_lock(&pit->pit_state.lock); 5791 memcpy(&pit->pit_state.channels, ps, sizeof(*ps)); 5792 for (i = 0; i < 3; i++) 5793 kvm_pit_load_count(pit, i, ps->channels[i].count, 0); 5794 mutex_unlock(&pit->pit_state.lock); 5795 return 0; 5796 } 5797 5798 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) 5799 { 5800 mutex_lock(&kvm->arch.vpit->pit_state.lock); 5801 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels, 5802 sizeof(ps->channels)); 5803 ps->flags = kvm->arch.vpit->pit_state.flags; 5804 mutex_unlock(&kvm->arch.vpit->pit_state.lock); 5805 memset(&ps->reserved, 0, sizeof(ps->reserved)); 5806 return 0; 5807 } 5808 5809 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) 5810 { 5811 int start = 0; 5812 int i; 5813 u32 prev_legacy, cur_legacy; 5814 struct kvm_pit *pit = kvm->arch.vpit; 5815 5816 mutex_lock(&pit->pit_state.lock); 5817 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY; 5818 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY; 5819 if (!prev_legacy && cur_legacy) 5820 start = 1; 5821 memcpy(&pit->pit_state.channels, &ps->channels, 5822 sizeof(pit->pit_state.channels)); 5823 pit->pit_state.flags = ps->flags; 5824 for (i = 0; i < 3; i++) 5825 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count, 5826 start && i == 0); 5827 mutex_unlock(&pit->pit_state.lock); 5828 return 0; 5829 } 5830 5831 static int kvm_vm_ioctl_reinject(struct kvm *kvm, 5832 struct kvm_reinject_control *control) 5833 { 5834 struct kvm_pit *pit = kvm->arch.vpit; 5835 5836 /* pit->pit_state.lock was overloaded to prevent userspace from getting 5837 * an inconsistent state after running multiple KVM_REINJECT_CONTROL 5838 * ioctls in parallel. Use a separate lock if that ioctl isn't rare. 5839 */ 5840 mutex_lock(&pit->pit_state.lock); 5841 kvm_pit_set_reinject(pit, control->pit_reinject); 5842 mutex_unlock(&pit->pit_state.lock); 5843 5844 return 0; 5845 } 5846 5847 void kvm_arch_sync_dirty_log(struct kvm *kvm, struct kvm_memory_slot *memslot) 5848 { 5849 5850 /* 5851 * Flush all CPUs' dirty log buffers to the dirty_bitmap. Called 5852 * before reporting dirty_bitmap to userspace. KVM flushes the buffers 5853 * on all VM-Exits, thus we only need to kick running vCPUs to force a 5854 * VM-Exit. 5855 */ 5856 struct kvm_vcpu *vcpu; 5857 unsigned long i; 5858 5859 kvm_for_each_vcpu(i, vcpu, kvm) 5860 kvm_vcpu_kick(vcpu); 5861 } 5862 5863 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event, 5864 bool line_status) 5865 { 5866 if (!irqchip_in_kernel(kvm)) 5867 return -ENXIO; 5868 5869 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID, 5870 irq_event->irq, irq_event->level, 5871 line_status); 5872 return 0; 5873 } 5874 5875 int kvm_vm_ioctl_enable_cap(struct kvm *kvm, 5876 struct kvm_enable_cap *cap) 5877 { 5878 int r; 5879 5880 if (cap->flags) 5881 return -EINVAL; 5882 5883 switch (cap->cap) { 5884 case KVM_CAP_DISABLE_QUIRKS: 5885 kvm->arch.disabled_quirks = cap->args[0]; 5886 r = 0; 5887 break; 5888 case KVM_CAP_SPLIT_IRQCHIP: { 5889 mutex_lock(&kvm->lock); 5890 r = -EINVAL; 5891 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS) 5892 goto split_irqchip_unlock; 5893 r = -EEXIST; 5894 if (irqchip_in_kernel(kvm)) 5895 goto split_irqchip_unlock; 5896 if (kvm->created_vcpus) 5897 goto split_irqchip_unlock; 5898 r = kvm_setup_empty_irq_routing(kvm); 5899 if (r) 5900 goto split_irqchip_unlock; 5901 /* Pairs with irqchip_in_kernel. */ 5902 smp_wmb(); 5903 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT; 5904 kvm->arch.nr_reserved_ioapic_pins = cap->args[0]; 5905 kvm_request_apicv_update(kvm, true, APICV_INHIBIT_REASON_ABSENT); 5906 r = 0; 5907 split_irqchip_unlock: 5908 mutex_unlock(&kvm->lock); 5909 break; 5910 } 5911 case KVM_CAP_X2APIC_API: 5912 r = -EINVAL; 5913 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS) 5914 break; 5915 5916 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS) 5917 kvm->arch.x2apic_format = true; 5918 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK) 5919 kvm->arch.x2apic_broadcast_quirk_disabled = true; 5920 5921 r = 0; 5922 break; 5923 case KVM_CAP_X86_DISABLE_EXITS: 5924 r = -EINVAL; 5925 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS) 5926 break; 5927 5928 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) && 5929 kvm_can_mwait_in_guest()) 5930 kvm->arch.mwait_in_guest = true; 5931 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT) 5932 kvm->arch.hlt_in_guest = true; 5933 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE) 5934 kvm->arch.pause_in_guest = true; 5935 if (cap->args[0] & KVM_X86_DISABLE_EXITS_CSTATE) 5936 kvm->arch.cstate_in_guest = true; 5937 r = 0; 5938 break; 5939 case KVM_CAP_MSR_PLATFORM_INFO: 5940 kvm->arch.guest_can_read_msr_platform_info = cap->args[0]; 5941 r = 0; 5942 break; 5943 case KVM_CAP_EXCEPTION_PAYLOAD: 5944 kvm->arch.exception_payload_enabled = cap->args[0]; 5945 r = 0; 5946 break; 5947 case KVM_CAP_X86_USER_SPACE_MSR: 5948 kvm->arch.user_space_msr_mask = cap->args[0]; 5949 r = 0; 5950 break; 5951 case KVM_CAP_X86_BUS_LOCK_EXIT: 5952 r = -EINVAL; 5953 if (cap->args[0] & ~KVM_BUS_LOCK_DETECTION_VALID_MODE) 5954 break; 5955 5956 if ((cap->args[0] & KVM_BUS_LOCK_DETECTION_OFF) && 5957 (cap->args[0] & KVM_BUS_LOCK_DETECTION_EXIT)) 5958 break; 5959 5960 if (kvm_has_bus_lock_exit && 5961 cap->args[0] & KVM_BUS_LOCK_DETECTION_EXIT) 5962 kvm->arch.bus_lock_detection_enabled = true; 5963 r = 0; 5964 break; 5965 #ifdef CONFIG_X86_SGX_KVM 5966 case KVM_CAP_SGX_ATTRIBUTE: { 5967 unsigned long allowed_attributes = 0; 5968 5969 r = sgx_set_attribute(&allowed_attributes, cap->args[0]); 5970 if (r) 5971 break; 5972 5973 /* KVM only supports the PROVISIONKEY privileged attribute. */ 5974 if ((allowed_attributes & SGX_ATTR_PROVISIONKEY) && 5975 !(allowed_attributes & ~SGX_ATTR_PROVISIONKEY)) 5976 kvm->arch.sgx_provisioning_allowed = true; 5977 else 5978 r = -EINVAL; 5979 break; 5980 } 5981 #endif 5982 case KVM_CAP_VM_COPY_ENC_CONTEXT_FROM: 5983 r = -EINVAL; 5984 if (!kvm_x86_ops.vm_copy_enc_context_from) 5985 break; 5986 5987 r = static_call(kvm_x86_vm_copy_enc_context_from)(kvm, cap->args[0]); 5988 break; 5989 case KVM_CAP_VM_MOVE_ENC_CONTEXT_FROM: 5990 r = -EINVAL; 5991 if (!kvm_x86_ops.vm_move_enc_context_from) 5992 break; 5993 5994 r = static_call(kvm_x86_vm_move_enc_context_from)(kvm, cap->args[0]); 5995 break; 5996 case KVM_CAP_EXIT_HYPERCALL: 5997 if (cap->args[0] & ~KVM_EXIT_HYPERCALL_VALID_MASK) { 5998 r = -EINVAL; 5999 break; 6000 } 6001 kvm->arch.hypercall_exit_enabled = cap->args[0]; 6002 r = 0; 6003 break; 6004 case KVM_CAP_EXIT_ON_EMULATION_FAILURE: 6005 r = -EINVAL; 6006 if (cap->args[0] & ~1) 6007 break; 6008 kvm->arch.exit_on_emulation_error = cap->args[0]; 6009 r = 0; 6010 break; 6011 case KVM_CAP_PMU_CAPABILITY: 6012 r = -EINVAL; 6013 if (!enable_pmu || (cap->args[0] & ~KVM_CAP_PMU_VALID_MASK)) 6014 break; 6015 6016 mutex_lock(&kvm->lock); 6017 if (!kvm->created_vcpus) { 6018 kvm->arch.enable_pmu = !(cap->args[0] & KVM_PMU_CAP_DISABLE); 6019 r = 0; 6020 } 6021 mutex_unlock(&kvm->lock); 6022 break; 6023 default: 6024 r = -EINVAL; 6025 break; 6026 } 6027 return r; 6028 } 6029 6030 static struct kvm_x86_msr_filter *kvm_alloc_msr_filter(bool default_allow) 6031 { 6032 struct kvm_x86_msr_filter *msr_filter; 6033 6034 msr_filter = kzalloc(sizeof(*msr_filter), GFP_KERNEL_ACCOUNT); 6035 if (!msr_filter) 6036 return NULL; 6037 6038 msr_filter->default_allow = default_allow; 6039 return msr_filter; 6040 } 6041 6042 static void kvm_free_msr_filter(struct kvm_x86_msr_filter *msr_filter) 6043 { 6044 u32 i; 6045 6046 if (!msr_filter) 6047 return; 6048 6049 for (i = 0; i < msr_filter->count; i++) 6050 kfree(msr_filter->ranges[i].bitmap); 6051 6052 kfree(msr_filter); 6053 } 6054 6055 static int kvm_add_msr_filter(struct kvm_x86_msr_filter *msr_filter, 6056 struct kvm_msr_filter_range *user_range) 6057 { 6058 unsigned long *bitmap = NULL; 6059 size_t bitmap_size; 6060 6061 if (!user_range->nmsrs) 6062 return 0; 6063 6064 if (user_range->flags & ~(KVM_MSR_FILTER_READ | KVM_MSR_FILTER_WRITE)) 6065 return -EINVAL; 6066 6067 if (!user_range->flags) 6068 return -EINVAL; 6069 6070 bitmap_size = BITS_TO_LONGS(user_range->nmsrs) * sizeof(long); 6071 if (!bitmap_size || bitmap_size > KVM_MSR_FILTER_MAX_BITMAP_SIZE) 6072 return -EINVAL; 6073 6074 bitmap = memdup_user((__user u8*)user_range->bitmap, bitmap_size); 6075 if (IS_ERR(bitmap)) 6076 return PTR_ERR(bitmap); 6077 6078 msr_filter->ranges[msr_filter->count] = (struct msr_bitmap_range) { 6079 .flags = user_range->flags, 6080 .base = user_range->base, 6081 .nmsrs = user_range->nmsrs, 6082 .bitmap = bitmap, 6083 }; 6084 6085 msr_filter->count++; 6086 return 0; 6087 } 6088 6089 static int kvm_vm_ioctl_set_msr_filter(struct kvm *kvm, void __user *argp) 6090 { 6091 struct kvm_msr_filter __user *user_msr_filter = argp; 6092 struct kvm_x86_msr_filter *new_filter, *old_filter; 6093 struct kvm_msr_filter filter; 6094 bool default_allow; 6095 bool empty = true; 6096 int r = 0; 6097 u32 i; 6098 6099 if (copy_from_user(&filter, user_msr_filter, sizeof(filter))) 6100 return -EFAULT; 6101 6102 for (i = 0; i < ARRAY_SIZE(filter.ranges); i++) 6103 empty &= !filter.ranges[i].nmsrs; 6104 6105 default_allow = !(filter.flags & KVM_MSR_FILTER_DEFAULT_DENY); 6106 if (empty && !default_allow) 6107 return -EINVAL; 6108 6109 new_filter = kvm_alloc_msr_filter(default_allow); 6110 if (!new_filter) 6111 return -ENOMEM; 6112 6113 for (i = 0; i < ARRAY_SIZE(filter.ranges); i++) { 6114 r = kvm_add_msr_filter(new_filter, &filter.ranges[i]); 6115 if (r) { 6116 kvm_free_msr_filter(new_filter); 6117 return r; 6118 } 6119 } 6120 6121 mutex_lock(&kvm->lock); 6122 6123 /* The per-VM filter is protected by kvm->lock... */ 6124 old_filter = srcu_dereference_check(kvm->arch.msr_filter, &kvm->srcu, 1); 6125 6126 rcu_assign_pointer(kvm->arch.msr_filter, new_filter); 6127 synchronize_srcu(&kvm->srcu); 6128 6129 kvm_free_msr_filter(old_filter); 6130 6131 kvm_make_all_cpus_request(kvm, KVM_REQ_MSR_FILTER_CHANGED); 6132 mutex_unlock(&kvm->lock); 6133 6134 return 0; 6135 } 6136 6137 #ifdef CONFIG_HAVE_KVM_PM_NOTIFIER 6138 static int kvm_arch_suspend_notifier(struct kvm *kvm) 6139 { 6140 struct kvm_vcpu *vcpu; 6141 unsigned long i; 6142 int ret = 0; 6143 6144 mutex_lock(&kvm->lock); 6145 kvm_for_each_vcpu(i, vcpu, kvm) { 6146 if (!vcpu->arch.pv_time_enabled) 6147 continue; 6148 6149 ret = kvm_set_guest_paused(vcpu); 6150 if (ret) { 6151 kvm_err("Failed to pause guest VCPU%d: %d\n", 6152 vcpu->vcpu_id, ret); 6153 break; 6154 } 6155 } 6156 mutex_unlock(&kvm->lock); 6157 6158 return ret ? NOTIFY_BAD : NOTIFY_DONE; 6159 } 6160 6161 int kvm_arch_pm_notifier(struct kvm *kvm, unsigned long state) 6162 { 6163 switch (state) { 6164 case PM_HIBERNATION_PREPARE: 6165 case PM_SUSPEND_PREPARE: 6166 return kvm_arch_suspend_notifier(kvm); 6167 } 6168 6169 return NOTIFY_DONE; 6170 } 6171 #endif /* CONFIG_HAVE_KVM_PM_NOTIFIER */ 6172 6173 static int kvm_vm_ioctl_get_clock(struct kvm *kvm, void __user *argp) 6174 { 6175 struct kvm_clock_data data = { 0 }; 6176 6177 get_kvmclock(kvm, &data); 6178 if (copy_to_user(argp, &data, sizeof(data))) 6179 return -EFAULT; 6180 6181 return 0; 6182 } 6183 6184 static int kvm_vm_ioctl_set_clock(struct kvm *kvm, void __user *argp) 6185 { 6186 struct kvm_arch *ka = &kvm->arch; 6187 struct kvm_clock_data data; 6188 u64 now_raw_ns; 6189 6190 if (copy_from_user(&data, argp, sizeof(data))) 6191 return -EFAULT; 6192 6193 /* 6194 * Only KVM_CLOCK_REALTIME is used, but allow passing the 6195 * result of KVM_GET_CLOCK back to KVM_SET_CLOCK. 6196 */ 6197 if (data.flags & ~KVM_CLOCK_VALID_FLAGS) 6198 return -EINVAL; 6199 6200 kvm_hv_invalidate_tsc_page(kvm); 6201 kvm_start_pvclock_update(kvm); 6202 pvclock_update_vm_gtod_copy(kvm); 6203 6204 /* 6205 * This pairs with kvm_guest_time_update(): when masterclock is 6206 * in use, we use master_kernel_ns + kvmclock_offset to set 6207 * unsigned 'system_time' so if we use get_kvmclock_ns() (which 6208 * is slightly ahead) here we risk going negative on unsigned 6209 * 'system_time' when 'data.clock' is very small. 6210 */ 6211 if (data.flags & KVM_CLOCK_REALTIME) { 6212 u64 now_real_ns = ktime_get_real_ns(); 6213 6214 /* 6215 * Avoid stepping the kvmclock backwards. 6216 */ 6217 if (now_real_ns > data.realtime) 6218 data.clock += now_real_ns - data.realtime; 6219 } 6220 6221 if (ka->use_master_clock) 6222 now_raw_ns = ka->master_kernel_ns; 6223 else 6224 now_raw_ns = get_kvmclock_base_ns(); 6225 ka->kvmclock_offset = data.clock - now_raw_ns; 6226 kvm_end_pvclock_update(kvm); 6227 return 0; 6228 } 6229 6230 long kvm_arch_vm_ioctl(struct file *filp, 6231 unsigned int ioctl, unsigned long arg) 6232 { 6233 struct kvm *kvm = filp->private_data; 6234 void __user *argp = (void __user *)arg; 6235 int r = -ENOTTY; 6236 /* 6237 * This union makes it completely explicit to gcc-3.x 6238 * that these two variables' stack usage should be 6239 * combined, not added together. 6240 */ 6241 union { 6242 struct kvm_pit_state ps; 6243 struct kvm_pit_state2 ps2; 6244 struct kvm_pit_config pit_config; 6245 } u; 6246 6247 switch (ioctl) { 6248 case KVM_SET_TSS_ADDR: 6249 r = kvm_vm_ioctl_set_tss_addr(kvm, arg); 6250 break; 6251 case KVM_SET_IDENTITY_MAP_ADDR: { 6252 u64 ident_addr; 6253 6254 mutex_lock(&kvm->lock); 6255 r = -EINVAL; 6256 if (kvm->created_vcpus) 6257 goto set_identity_unlock; 6258 r = -EFAULT; 6259 if (copy_from_user(&ident_addr, argp, sizeof(ident_addr))) 6260 goto set_identity_unlock; 6261 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr); 6262 set_identity_unlock: 6263 mutex_unlock(&kvm->lock); 6264 break; 6265 } 6266 case KVM_SET_NR_MMU_PAGES: 6267 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg); 6268 break; 6269 case KVM_GET_NR_MMU_PAGES: 6270 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm); 6271 break; 6272 case KVM_CREATE_IRQCHIP: { 6273 mutex_lock(&kvm->lock); 6274 6275 r = -EEXIST; 6276 if (irqchip_in_kernel(kvm)) 6277 goto create_irqchip_unlock; 6278 6279 r = -EINVAL; 6280 if (kvm->created_vcpus) 6281 goto create_irqchip_unlock; 6282 6283 r = kvm_pic_init(kvm); 6284 if (r) 6285 goto create_irqchip_unlock; 6286 6287 r = kvm_ioapic_init(kvm); 6288 if (r) { 6289 kvm_pic_destroy(kvm); 6290 goto create_irqchip_unlock; 6291 } 6292 6293 r = kvm_setup_default_irq_routing(kvm); 6294 if (r) { 6295 kvm_ioapic_destroy(kvm); 6296 kvm_pic_destroy(kvm); 6297 goto create_irqchip_unlock; 6298 } 6299 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */ 6300 smp_wmb(); 6301 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL; 6302 kvm_request_apicv_update(kvm, true, APICV_INHIBIT_REASON_ABSENT); 6303 create_irqchip_unlock: 6304 mutex_unlock(&kvm->lock); 6305 break; 6306 } 6307 case KVM_CREATE_PIT: 6308 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY; 6309 goto create_pit; 6310 case KVM_CREATE_PIT2: 6311 r = -EFAULT; 6312 if (copy_from_user(&u.pit_config, argp, 6313 sizeof(struct kvm_pit_config))) 6314 goto out; 6315 create_pit: 6316 mutex_lock(&kvm->lock); 6317 r = -EEXIST; 6318 if (kvm->arch.vpit) 6319 goto create_pit_unlock; 6320 r = -ENOMEM; 6321 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags); 6322 if (kvm->arch.vpit) 6323 r = 0; 6324 create_pit_unlock: 6325 mutex_unlock(&kvm->lock); 6326 break; 6327 case KVM_GET_IRQCHIP: { 6328 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ 6329 struct kvm_irqchip *chip; 6330 6331 chip = memdup_user(argp, sizeof(*chip)); 6332 if (IS_ERR(chip)) { 6333 r = PTR_ERR(chip); 6334 goto out; 6335 } 6336 6337 r = -ENXIO; 6338 if (!irqchip_kernel(kvm)) 6339 goto get_irqchip_out; 6340 r = kvm_vm_ioctl_get_irqchip(kvm, chip); 6341 if (r) 6342 goto get_irqchip_out; 6343 r = -EFAULT; 6344 if (copy_to_user(argp, chip, sizeof(*chip))) 6345 goto get_irqchip_out; 6346 r = 0; 6347 get_irqchip_out: 6348 kfree(chip); 6349 break; 6350 } 6351 case KVM_SET_IRQCHIP: { 6352 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ 6353 struct kvm_irqchip *chip; 6354 6355 chip = memdup_user(argp, sizeof(*chip)); 6356 if (IS_ERR(chip)) { 6357 r = PTR_ERR(chip); 6358 goto out; 6359 } 6360 6361 r = -ENXIO; 6362 if (!irqchip_kernel(kvm)) 6363 goto set_irqchip_out; 6364 r = kvm_vm_ioctl_set_irqchip(kvm, chip); 6365 set_irqchip_out: 6366 kfree(chip); 6367 break; 6368 } 6369 case KVM_GET_PIT: { 6370 r = -EFAULT; 6371 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state))) 6372 goto out; 6373 r = -ENXIO; 6374 if (!kvm->arch.vpit) 6375 goto out; 6376 r = kvm_vm_ioctl_get_pit(kvm, &u.ps); 6377 if (r) 6378 goto out; 6379 r = -EFAULT; 6380 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state))) 6381 goto out; 6382 r = 0; 6383 break; 6384 } 6385 case KVM_SET_PIT: { 6386 r = -EFAULT; 6387 if (copy_from_user(&u.ps, argp, sizeof(u.ps))) 6388 goto out; 6389 mutex_lock(&kvm->lock); 6390 r = -ENXIO; 6391 if (!kvm->arch.vpit) 6392 goto set_pit_out; 6393 r = kvm_vm_ioctl_set_pit(kvm, &u.ps); 6394 set_pit_out: 6395 mutex_unlock(&kvm->lock); 6396 break; 6397 } 6398 case KVM_GET_PIT2: { 6399 r = -ENXIO; 6400 if (!kvm->arch.vpit) 6401 goto out; 6402 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2); 6403 if (r) 6404 goto out; 6405 r = -EFAULT; 6406 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2))) 6407 goto out; 6408 r = 0; 6409 break; 6410 } 6411 case KVM_SET_PIT2: { 6412 r = -EFAULT; 6413 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2))) 6414 goto out; 6415 mutex_lock(&kvm->lock); 6416 r = -ENXIO; 6417 if (!kvm->arch.vpit) 6418 goto set_pit2_out; 6419 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2); 6420 set_pit2_out: 6421 mutex_unlock(&kvm->lock); 6422 break; 6423 } 6424 case KVM_REINJECT_CONTROL: { 6425 struct kvm_reinject_control control; 6426 r = -EFAULT; 6427 if (copy_from_user(&control, argp, sizeof(control))) 6428 goto out; 6429 r = -ENXIO; 6430 if (!kvm->arch.vpit) 6431 goto out; 6432 r = kvm_vm_ioctl_reinject(kvm, &control); 6433 break; 6434 } 6435 case KVM_SET_BOOT_CPU_ID: 6436 r = 0; 6437 mutex_lock(&kvm->lock); 6438 if (kvm->created_vcpus) 6439 r = -EBUSY; 6440 else 6441 kvm->arch.bsp_vcpu_id = arg; 6442 mutex_unlock(&kvm->lock); 6443 break; 6444 #ifdef CONFIG_KVM_XEN 6445 case KVM_XEN_HVM_CONFIG: { 6446 struct kvm_xen_hvm_config xhc; 6447 r = -EFAULT; 6448 if (copy_from_user(&xhc, argp, sizeof(xhc))) 6449 goto out; 6450 r = kvm_xen_hvm_config(kvm, &xhc); 6451 break; 6452 } 6453 case KVM_XEN_HVM_GET_ATTR: { 6454 struct kvm_xen_hvm_attr xha; 6455 6456 r = -EFAULT; 6457 if (copy_from_user(&xha, argp, sizeof(xha))) 6458 goto out; 6459 r = kvm_xen_hvm_get_attr(kvm, &xha); 6460 if (!r && copy_to_user(argp, &xha, sizeof(xha))) 6461 r = -EFAULT; 6462 break; 6463 } 6464 case KVM_XEN_HVM_SET_ATTR: { 6465 struct kvm_xen_hvm_attr xha; 6466 6467 r = -EFAULT; 6468 if (copy_from_user(&xha, argp, sizeof(xha))) 6469 goto out; 6470 r = kvm_xen_hvm_set_attr(kvm, &xha); 6471 break; 6472 } 6473 #endif 6474 case KVM_SET_CLOCK: 6475 r = kvm_vm_ioctl_set_clock(kvm, argp); 6476 break; 6477 case KVM_GET_CLOCK: 6478 r = kvm_vm_ioctl_get_clock(kvm, argp); 6479 break; 6480 case KVM_MEMORY_ENCRYPT_OP: { 6481 r = -ENOTTY; 6482 if (!kvm_x86_ops.mem_enc_ioctl) 6483 goto out; 6484 6485 r = static_call(kvm_x86_mem_enc_ioctl)(kvm, argp); 6486 break; 6487 } 6488 case KVM_MEMORY_ENCRYPT_REG_REGION: { 6489 struct kvm_enc_region region; 6490 6491 r = -EFAULT; 6492 if (copy_from_user(®ion, argp, sizeof(region))) 6493 goto out; 6494 6495 r = -ENOTTY; 6496 if (!kvm_x86_ops.mem_enc_register_region) 6497 goto out; 6498 6499 r = static_call(kvm_x86_mem_enc_register_region)(kvm, ®ion); 6500 break; 6501 } 6502 case KVM_MEMORY_ENCRYPT_UNREG_REGION: { 6503 struct kvm_enc_region region; 6504 6505 r = -EFAULT; 6506 if (copy_from_user(®ion, argp, sizeof(region))) 6507 goto out; 6508 6509 r = -ENOTTY; 6510 if (!kvm_x86_ops.mem_enc_unregister_region) 6511 goto out; 6512 6513 r = static_call(kvm_x86_mem_enc_unregister_region)(kvm, ®ion); 6514 break; 6515 } 6516 case KVM_HYPERV_EVENTFD: { 6517 struct kvm_hyperv_eventfd hvevfd; 6518 6519 r = -EFAULT; 6520 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd))) 6521 goto out; 6522 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd); 6523 break; 6524 } 6525 case KVM_SET_PMU_EVENT_FILTER: 6526 r = kvm_vm_ioctl_set_pmu_event_filter(kvm, argp); 6527 break; 6528 case KVM_X86_SET_MSR_FILTER: 6529 r = kvm_vm_ioctl_set_msr_filter(kvm, argp); 6530 break; 6531 default: 6532 r = -ENOTTY; 6533 } 6534 out: 6535 return r; 6536 } 6537 6538 static void kvm_init_msr_list(void) 6539 { 6540 struct x86_pmu_capability x86_pmu; 6541 u32 dummy[2]; 6542 unsigned i; 6543 6544 BUILD_BUG_ON_MSG(INTEL_PMC_MAX_FIXED != 4, 6545 "Please update the fixed PMCs in msrs_to_saved_all[]"); 6546 6547 perf_get_x86_pmu_capability(&x86_pmu); 6548 6549 num_msrs_to_save = 0; 6550 num_emulated_msrs = 0; 6551 num_msr_based_features = 0; 6552 6553 for (i = 0; i < ARRAY_SIZE(msrs_to_save_all); i++) { 6554 if (rdmsr_safe(msrs_to_save_all[i], &dummy[0], &dummy[1]) < 0) 6555 continue; 6556 6557 /* 6558 * Even MSRs that are valid in the host may not be exposed 6559 * to the guests in some cases. 6560 */ 6561 switch (msrs_to_save_all[i]) { 6562 case MSR_IA32_BNDCFGS: 6563 if (!kvm_mpx_supported()) 6564 continue; 6565 break; 6566 case MSR_TSC_AUX: 6567 if (!kvm_cpu_cap_has(X86_FEATURE_RDTSCP) && 6568 !kvm_cpu_cap_has(X86_FEATURE_RDPID)) 6569 continue; 6570 break; 6571 case MSR_IA32_UMWAIT_CONTROL: 6572 if (!kvm_cpu_cap_has(X86_FEATURE_WAITPKG)) 6573 continue; 6574 break; 6575 case MSR_IA32_RTIT_CTL: 6576 case MSR_IA32_RTIT_STATUS: 6577 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT)) 6578 continue; 6579 break; 6580 case MSR_IA32_RTIT_CR3_MATCH: 6581 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) || 6582 !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering)) 6583 continue; 6584 break; 6585 case MSR_IA32_RTIT_OUTPUT_BASE: 6586 case MSR_IA32_RTIT_OUTPUT_MASK: 6587 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) || 6588 (!intel_pt_validate_hw_cap(PT_CAP_topa_output) && 6589 !intel_pt_validate_hw_cap(PT_CAP_single_range_output))) 6590 continue; 6591 break; 6592 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: 6593 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) || 6594 msrs_to_save_all[i] - MSR_IA32_RTIT_ADDR0_A >= 6595 intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2) 6596 continue; 6597 break; 6598 case MSR_ARCH_PERFMON_PERFCTR0 ... MSR_ARCH_PERFMON_PERFCTR0 + 17: 6599 if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_PERFCTR0 >= 6600 min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp)) 6601 continue; 6602 break; 6603 case MSR_ARCH_PERFMON_EVENTSEL0 ... MSR_ARCH_PERFMON_EVENTSEL0 + 17: 6604 if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_EVENTSEL0 >= 6605 min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp)) 6606 continue; 6607 break; 6608 case MSR_IA32_XFD: 6609 case MSR_IA32_XFD_ERR: 6610 if (!kvm_cpu_cap_has(X86_FEATURE_XFD)) 6611 continue; 6612 break; 6613 default: 6614 break; 6615 } 6616 6617 msrs_to_save[num_msrs_to_save++] = msrs_to_save_all[i]; 6618 } 6619 6620 for (i = 0; i < ARRAY_SIZE(emulated_msrs_all); i++) { 6621 if (!static_call(kvm_x86_has_emulated_msr)(NULL, emulated_msrs_all[i])) 6622 continue; 6623 6624 emulated_msrs[num_emulated_msrs++] = emulated_msrs_all[i]; 6625 } 6626 6627 for (i = 0; i < ARRAY_SIZE(msr_based_features_all); i++) { 6628 struct kvm_msr_entry msr; 6629 6630 msr.index = msr_based_features_all[i]; 6631 if (kvm_get_msr_feature(&msr)) 6632 continue; 6633 6634 msr_based_features[num_msr_based_features++] = msr_based_features_all[i]; 6635 } 6636 } 6637 6638 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len, 6639 const void *v) 6640 { 6641 int handled = 0; 6642 int n; 6643 6644 do { 6645 n = min(len, 8); 6646 if (!(lapic_in_kernel(vcpu) && 6647 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v)) 6648 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v)) 6649 break; 6650 handled += n; 6651 addr += n; 6652 len -= n; 6653 v += n; 6654 } while (len); 6655 6656 return handled; 6657 } 6658 6659 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v) 6660 { 6661 int handled = 0; 6662 int n; 6663 6664 do { 6665 n = min(len, 8); 6666 if (!(lapic_in_kernel(vcpu) && 6667 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev, 6668 addr, n, v)) 6669 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v)) 6670 break; 6671 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v); 6672 handled += n; 6673 addr += n; 6674 len -= n; 6675 v += n; 6676 } while (len); 6677 6678 return handled; 6679 } 6680 6681 static void kvm_set_segment(struct kvm_vcpu *vcpu, 6682 struct kvm_segment *var, int seg) 6683 { 6684 static_call(kvm_x86_set_segment)(vcpu, var, seg); 6685 } 6686 6687 void kvm_get_segment(struct kvm_vcpu *vcpu, 6688 struct kvm_segment *var, int seg) 6689 { 6690 static_call(kvm_x86_get_segment)(vcpu, var, seg); 6691 } 6692 6693 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, 6694 struct x86_exception *exception) 6695 { 6696 struct kvm_mmu *mmu = vcpu->arch.mmu; 6697 gpa_t t_gpa; 6698 6699 BUG_ON(!mmu_is_nested(vcpu)); 6700 6701 /* NPT walks are always user-walks */ 6702 access |= PFERR_USER_MASK; 6703 t_gpa = mmu->gva_to_gpa(vcpu, mmu, gpa, access, exception); 6704 6705 return t_gpa; 6706 } 6707 6708 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, 6709 struct x86_exception *exception) 6710 { 6711 struct kvm_mmu *mmu = vcpu->arch.walk_mmu; 6712 6713 u32 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; 6714 return mmu->gva_to_gpa(vcpu, mmu, gva, access, exception); 6715 } 6716 EXPORT_SYMBOL_GPL(kvm_mmu_gva_to_gpa_read); 6717 6718 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, 6719 struct x86_exception *exception) 6720 { 6721 struct kvm_mmu *mmu = vcpu->arch.walk_mmu; 6722 6723 u32 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; 6724 access |= PFERR_FETCH_MASK; 6725 return mmu->gva_to_gpa(vcpu, mmu, gva, access, exception); 6726 } 6727 6728 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, 6729 struct x86_exception *exception) 6730 { 6731 struct kvm_mmu *mmu = vcpu->arch.walk_mmu; 6732 6733 u32 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; 6734 access |= PFERR_WRITE_MASK; 6735 return mmu->gva_to_gpa(vcpu, mmu, gva, access, exception); 6736 } 6737 EXPORT_SYMBOL_GPL(kvm_mmu_gva_to_gpa_write); 6738 6739 /* uses this to access any guest's mapped memory without checking CPL */ 6740 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, 6741 struct x86_exception *exception) 6742 { 6743 struct kvm_mmu *mmu = vcpu->arch.walk_mmu; 6744 6745 return mmu->gva_to_gpa(vcpu, mmu, gva, 0, exception); 6746 } 6747 6748 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, 6749 struct kvm_vcpu *vcpu, u32 access, 6750 struct x86_exception *exception) 6751 { 6752 struct kvm_mmu *mmu = vcpu->arch.walk_mmu; 6753 void *data = val; 6754 int r = X86EMUL_CONTINUE; 6755 6756 while (bytes) { 6757 gpa_t gpa = mmu->gva_to_gpa(vcpu, mmu, addr, access, exception); 6758 unsigned offset = addr & (PAGE_SIZE-1); 6759 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset); 6760 int ret; 6761 6762 if (gpa == UNMAPPED_GVA) 6763 return X86EMUL_PROPAGATE_FAULT; 6764 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data, 6765 offset, toread); 6766 if (ret < 0) { 6767 r = X86EMUL_IO_NEEDED; 6768 goto out; 6769 } 6770 6771 bytes -= toread; 6772 data += toread; 6773 addr += toread; 6774 } 6775 out: 6776 return r; 6777 } 6778 6779 /* used for instruction fetching */ 6780 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt, 6781 gva_t addr, void *val, unsigned int bytes, 6782 struct x86_exception *exception) 6783 { 6784 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6785 struct kvm_mmu *mmu = vcpu->arch.walk_mmu; 6786 u32 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; 6787 unsigned offset; 6788 int ret; 6789 6790 /* Inline kvm_read_guest_virt_helper for speed. */ 6791 gpa_t gpa = mmu->gva_to_gpa(vcpu, mmu, addr, access|PFERR_FETCH_MASK, 6792 exception); 6793 if (unlikely(gpa == UNMAPPED_GVA)) 6794 return X86EMUL_PROPAGATE_FAULT; 6795 6796 offset = addr & (PAGE_SIZE-1); 6797 if (WARN_ON(offset + bytes > PAGE_SIZE)) 6798 bytes = (unsigned)PAGE_SIZE - offset; 6799 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val, 6800 offset, bytes); 6801 if (unlikely(ret < 0)) 6802 return X86EMUL_IO_NEEDED; 6803 6804 return X86EMUL_CONTINUE; 6805 } 6806 6807 int kvm_read_guest_virt(struct kvm_vcpu *vcpu, 6808 gva_t addr, void *val, unsigned int bytes, 6809 struct x86_exception *exception) 6810 { 6811 u32 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; 6812 6813 /* 6814 * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED 6815 * is returned, but our callers are not ready for that and they blindly 6816 * call kvm_inject_page_fault. Ensure that they at least do not leak 6817 * uninitialized kernel stack memory into cr2 and error code. 6818 */ 6819 memset(exception, 0, sizeof(*exception)); 6820 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, 6821 exception); 6822 } 6823 EXPORT_SYMBOL_GPL(kvm_read_guest_virt); 6824 6825 static int emulator_read_std(struct x86_emulate_ctxt *ctxt, 6826 gva_t addr, void *val, unsigned int bytes, 6827 struct x86_exception *exception, bool system) 6828 { 6829 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6830 u32 access = 0; 6831 6832 if (!system && static_call(kvm_x86_get_cpl)(vcpu) == 3) 6833 access |= PFERR_USER_MASK; 6834 6835 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception); 6836 } 6837 6838 static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt, 6839 unsigned long addr, void *val, unsigned int bytes) 6840 { 6841 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6842 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes); 6843 6844 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE; 6845 } 6846 6847 static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, 6848 struct kvm_vcpu *vcpu, u32 access, 6849 struct x86_exception *exception) 6850 { 6851 struct kvm_mmu *mmu = vcpu->arch.walk_mmu; 6852 void *data = val; 6853 int r = X86EMUL_CONTINUE; 6854 6855 while (bytes) { 6856 gpa_t gpa = mmu->gva_to_gpa(vcpu, mmu, addr, access, exception); 6857 unsigned offset = addr & (PAGE_SIZE-1); 6858 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset); 6859 int ret; 6860 6861 if (gpa == UNMAPPED_GVA) 6862 return X86EMUL_PROPAGATE_FAULT; 6863 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite); 6864 if (ret < 0) { 6865 r = X86EMUL_IO_NEEDED; 6866 goto out; 6867 } 6868 6869 bytes -= towrite; 6870 data += towrite; 6871 addr += towrite; 6872 } 6873 out: 6874 return r; 6875 } 6876 6877 static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val, 6878 unsigned int bytes, struct x86_exception *exception, 6879 bool system) 6880 { 6881 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6882 u32 access = PFERR_WRITE_MASK; 6883 6884 if (!system && static_call(kvm_x86_get_cpl)(vcpu) == 3) 6885 access |= PFERR_USER_MASK; 6886 6887 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu, 6888 access, exception); 6889 } 6890 6891 int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val, 6892 unsigned int bytes, struct x86_exception *exception) 6893 { 6894 /* kvm_write_guest_virt_system can pull in tons of pages. */ 6895 vcpu->arch.l1tf_flush_l1d = true; 6896 6897 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu, 6898 PFERR_WRITE_MASK, exception); 6899 } 6900 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system); 6901 6902 static int kvm_can_emulate_insn(struct kvm_vcpu *vcpu, int emul_type, 6903 void *insn, int insn_len) 6904 { 6905 return static_call(kvm_x86_can_emulate_instruction)(vcpu, emul_type, 6906 insn, insn_len); 6907 } 6908 6909 int handle_ud(struct kvm_vcpu *vcpu) 6910 { 6911 static const char kvm_emulate_prefix[] = { __KVM_EMULATE_PREFIX }; 6912 int emul_type = EMULTYPE_TRAP_UD; 6913 char sig[5]; /* ud2; .ascii "kvm" */ 6914 struct x86_exception e; 6915 6916 if (unlikely(!kvm_can_emulate_insn(vcpu, emul_type, NULL, 0))) 6917 return 1; 6918 6919 if (force_emulation_prefix && 6920 kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu), 6921 sig, sizeof(sig), &e) == 0 && 6922 memcmp(sig, kvm_emulate_prefix, sizeof(sig)) == 0) { 6923 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig)); 6924 emul_type = EMULTYPE_TRAP_UD_FORCED; 6925 } 6926 6927 return kvm_emulate_instruction(vcpu, emul_type); 6928 } 6929 EXPORT_SYMBOL_GPL(handle_ud); 6930 6931 static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva, 6932 gpa_t gpa, bool write) 6933 { 6934 /* For APIC access vmexit */ 6935 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) 6936 return 1; 6937 6938 if (vcpu_match_mmio_gpa(vcpu, gpa)) { 6939 trace_vcpu_match_mmio(gva, gpa, write, true); 6940 return 1; 6941 } 6942 6943 return 0; 6944 } 6945 6946 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva, 6947 gpa_t *gpa, struct x86_exception *exception, 6948 bool write) 6949 { 6950 struct kvm_mmu *mmu = vcpu->arch.walk_mmu; 6951 u32 access = ((static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0) 6952 | (write ? PFERR_WRITE_MASK : 0); 6953 6954 /* 6955 * currently PKRU is only applied to ept enabled guest so 6956 * there is no pkey in EPT page table for L1 guest or EPT 6957 * shadow page table for L2 guest. 6958 */ 6959 if (vcpu_match_mmio_gva(vcpu, gva) && (!is_paging(vcpu) || 6960 !permission_fault(vcpu, vcpu->arch.walk_mmu, 6961 vcpu->arch.mmio_access, 0, access))) { 6962 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT | 6963 (gva & (PAGE_SIZE - 1)); 6964 trace_vcpu_match_mmio(gva, *gpa, write, false); 6965 return 1; 6966 } 6967 6968 *gpa = mmu->gva_to_gpa(vcpu, mmu, gva, access, exception); 6969 6970 if (*gpa == UNMAPPED_GVA) 6971 return -1; 6972 6973 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write); 6974 } 6975 6976 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, 6977 const void *val, int bytes) 6978 { 6979 int ret; 6980 6981 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes); 6982 if (ret < 0) 6983 return 0; 6984 kvm_page_track_write(vcpu, gpa, val, bytes); 6985 return 1; 6986 } 6987 6988 struct read_write_emulator_ops { 6989 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val, 6990 int bytes); 6991 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa, 6992 void *val, int bytes); 6993 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, 6994 int bytes, void *val); 6995 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, 6996 void *val, int bytes); 6997 bool write; 6998 }; 6999 7000 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes) 7001 { 7002 if (vcpu->mmio_read_completed) { 7003 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, 7004 vcpu->mmio_fragments[0].gpa, val); 7005 vcpu->mmio_read_completed = 0; 7006 return 1; 7007 } 7008 7009 return 0; 7010 } 7011 7012 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, 7013 void *val, int bytes) 7014 { 7015 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes); 7016 } 7017 7018 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, 7019 void *val, int bytes) 7020 { 7021 return emulator_write_phys(vcpu, gpa, val, bytes); 7022 } 7023 7024 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val) 7025 { 7026 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val); 7027 return vcpu_mmio_write(vcpu, gpa, bytes, val); 7028 } 7029 7030 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, 7031 void *val, int bytes) 7032 { 7033 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL); 7034 return X86EMUL_IO_NEEDED; 7035 } 7036 7037 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, 7038 void *val, int bytes) 7039 { 7040 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0]; 7041 7042 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len)); 7043 return X86EMUL_CONTINUE; 7044 } 7045 7046 static const struct read_write_emulator_ops read_emultor = { 7047 .read_write_prepare = read_prepare, 7048 .read_write_emulate = read_emulate, 7049 .read_write_mmio = vcpu_mmio_read, 7050 .read_write_exit_mmio = read_exit_mmio, 7051 }; 7052 7053 static const struct read_write_emulator_ops write_emultor = { 7054 .read_write_emulate = write_emulate, 7055 .read_write_mmio = write_mmio, 7056 .read_write_exit_mmio = write_exit_mmio, 7057 .write = true, 7058 }; 7059 7060 static int emulator_read_write_onepage(unsigned long addr, void *val, 7061 unsigned int bytes, 7062 struct x86_exception *exception, 7063 struct kvm_vcpu *vcpu, 7064 const struct read_write_emulator_ops *ops) 7065 { 7066 gpa_t gpa; 7067 int handled, ret; 7068 bool write = ops->write; 7069 struct kvm_mmio_fragment *frag; 7070 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 7071 7072 /* 7073 * If the exit was due to a NPF we may already have a GPA. 7074 * If the GPA is present, use it to avoid the GVA to GPA table walk. 7075 * Note, this cannot be used on string operations since string 7076 * operation using rep will only have the initial GPA from the NPF 7077 * occurred. 7078 */ 7079 if (ctxt->gpa_available && emulator_can_use_gpa(ctxt) && 7080 (addr & ~PAGE_MASK) == (ctxt->gpa_val & ~PAGE_MASK)) { 7081 gpa = ctxt->gpa_val; 7082 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write); 7083 } else { 7084 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write); 7085 if (ret < 0) 7086 return X86EMUL_PROPAGATE_FAULT; 7087 } 7088 7089 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes)) 7090 return X86EMUL_CONTINUE; 7091 7092 /* 7093 * Is this MMIO handled locally? 7094 */ 7095 handled = ops->read_write_mmio(vcpu, gpa, bytes, val); 7096 if (handled == bytes) 7097 return X86EMUL_CONTINUE; 7098 7099 gpa += handled; 7100 bytes -= handled; 7101 val += handled; 7102 7103 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS); 7104 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++]; 7105 frag->gpa = gpa; 7106 frag->data = val; 7107 frag->len = bytes; 7108 return X86EMUL_CONTINUE; 7109 } 7110 7111 static int emulator_read_write(struct x86_emulate_ctxt *ctxt, 7112 unsigned long addr, 7113 void *val, unsigned int bytes, 7114 struct x86_exception *exception, 7115 const struct read_write_emulator_ops *ops) 7116 { 7117 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7118 gpa_t gpa; 7119 int rc; 7120 7121 if (ops->read_write_prepare && 7122 ops->read_write_prepare(vcpu, val, bytes)) 7123 return X86EMUL_CONTINUE; 7124 7125 vcpu->mmio_nr_fragments = 0; 7126 7127 /* Crossing a page boundary? */ 7128 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) { 7129 int now; 7130 7131 now = -addr & ~PAGE_MASK; 7132 rc = emulator_read_write_onepage(addr, val, now, exception, 7133 vcpu, ops); 7134 7135 if (rc != X86EMUL_CONTINUE) 7136 return rc; 7137 addr += now; 7138 if (ctxt->mode != X86EMUL_MODE_PROT64) 7139 addr = (u32)addr; 7140 val += now; 7141 bytes -= now; 7142 } 7143 7144 rc = emulator_read_write_onepage(addr, val, bytes, exception, 7145 vcpu, ops); 7146 if (rc != X86EMUL_CONTINUE) 7147 return rc; 7148 7149 if (!vcpu->mmio_nr_fragments) 7150 return rc; 7151 7152 gpa = vcpu->mmio_fragments[0].gpa; 7153 7154 vcpu->mmio_needed = 1; 7155 vcpu->mmio_cur_fragment = 0; 7156 7157 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len); 7158 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write; 7159 vcpu->run->exit_reason = KVM_EXIT_MMIO; 7160 vcpu->run->mmio.phys_addr = gpa; 7161 7162 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes); 7163 } 7164 7165 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt, 7166 unsigned long addr, 7167 void *val, 7168 unsigned int bytes, 7169 struct x86_exception *exception) 7170 { 7171 return emulator_read_write(ctxt, addr, val, bytes, 7172 exception, &read_emultor); 7173 } 7174 7175 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt, 7176 unsigned long addr, 7177 const void *val, 7178 unsigned int bytes, 7179 struct x86_exception *exception) 7180 { 7181 return emulator_read_write(ctxt, addr, (void *)val, bytes, 7182 exception, &write_emultor); 7183 } 7184 7185 #define CMPXCHG_TYPE(t, ptr, old, new) \ 7186 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old)) 7187 7188 #ifdef CONFIG_X86_64 7189 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new) 7190 #else 7191 # define CMPXCHG64(ptr, old, new) \ 7192 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old)) 7193 #endif 7194 7195 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt, 7196 unsigned long addr, 7197 const void *old, 7198 const void *new, 7199 unsigned int bytes, 7200 struct x86_exception *exception) 7201 { 7202 struct kvm_host_map map; 7203 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7204 u64 page_line_mask; 7205 gpa_t gpa; 7206 char *kaddr; 7207 bool exchanged; 7208 7209 /* guests cmpxchg8b have to be emulated atomically */ 7210 if (bytes > 8 || (bytes & (bytes - 1))) 7211 goto emul_write; 7212 7213 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL); 7214 7215 if (gpa == UNMAPPED_GVA || 7216 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) 7217 goto emul_write; 7218 7219 /* 7220 * Emulate the atomic as a straight write to avoid #AC if SLD is 7221 * enabled in the host and the access splits a cache line. 7222 */ 7223 if (boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT)) 7224 page_line_mask = ~(cache_line_size() - 1); 7225 else 7226 page_line_mask = PAGE_MASK; 7227 7228 if (((gpa + bytes - 1) & page_line_mask) != (gpa & page_line_mask)) 7229 goto emul_write; 7230 7231 if (kvm_vcpu_map(vcpu, gpa_to_gfn(gpa), &map)) 7232 goto emul_write; 7233 7234 kaddr = map.hva + offset_in_page(gpa); 7235 7236 switch (bytes) { 7237 case 1: 7238 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new); 7239 break; 7240 case 2: 7241 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new); 7242 break; 7243 case 4: 7244 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new); 7245 break; 7246 case 8: 7247 exchanged = CMPXCHG64(kaddr, old, new); 7248 break; 7249 default: 7250 BUG(); 7251 } 7252 7253 kvm_vcpu_unmap(vcpu, &map, true); 7254 7255 if (!exchanged) 7256 return X86EMUL_CMPXCHG_FAILED; 7257 7258 kvm_page_track_write(vcpu, gpa, new, bytes); 7259 7260 return X86EMUL_CONTINUE; 7261 7262 emul_write: 7263 printk_once(KERN_WARNING "kvm: emulating exchange as write\n"); 7264 7265 return emulator_write_emulated(ctxt, addr, new, bytes, exception); 7266 } 7267 7268 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd) 7269 { 7270 int r = 0, i; 7271 7272 for (i = 0; i < vcpu->arch.pio.count; i++) { 7273 if (vcpu->arch.pio.in) 7274 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port, 7275 vcpu->arch.pio.size, pd); 7276 else 7277 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS, 7278 vcpu->arch.pio.port, vcpu->arch.pio.size, 7279 pd); 7280 if (r) 7281 break; 7282 pd += vcpu->arch.pio.size; 7283 } 7284 return r; 7285 } 7286 7287 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size, 7288 unsigned short port, 7289 unsigned int count, bool in) 7290 { 7291 vcpu->arch.pio.port = port; 7292 vcpu->arch.pio.in = in; 7293 vcpu->arch.pio.count = count; 7294 vcpu->arch.pio.size = size; 7295 7296 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) 7297 return 1; 7298 7299 vcpu->run->exit_reason = KVM_EXIT_IO; 7300 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT; 7301 vcpu->run->io.size = size; 7302 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE; 7303 vcpu->run->io.count = count; 7304 vcpu->run->io.port = port; 7305 7306 return 0; 7307 } 7308 7309 static int __emulator_pio_in(struct kvm_vcpu *vcpu, int size, 7310 unsigned short port, unsigned int count) 7311 { 7312 WARN_ON(vcpu->arch.pio.count); 7313 memset(vcpu->arch.pio_data, 0, size * count); 7314 return emulator_pio_in_out(vcpu, size, port, count, true); 7315 } 7316 7317 static void complete_emulator_pio_in(struct kvm_vcpu *vcpu, void *val) 7318 { 7319 int size = vcpu->arch.pio.size; 7320 unsigned count = vcpu->arch.pio.count; 7321 memcpy(val, vcpu->arch.pio_data, size * count); 7322 trace_kvm_pio(KVM_PIO_IN, vcpu->arch.pio.port, size, count, vcpu->arch.pio_data); 7323 vcpu->arch.pio.count = 0; 7324 } 7325 7326 static int emulator_pio_in(struct kvm_vcpu *vcpu, int size, 7327 unsigned short port, void *val, unsigned int count) 7328 { 7329 if (vcpu->arch.pio.count) { 7330 /* 7331 * Complete a previous iteration that required userspace I/O. 7332 * Note, @count isn't guaranteed to match pio.count as userspace 7333 * can modify ECX before rerunning the vCPU. Ignore any such 7334 * shenanigans as KVM doesn't support modifying the rep count, 7335 * and the emulator ensures @count doesn't overflow the buffer. 7336 */ 7337 } else { 7338 int r = __emulator_pio_in(vcpu, size, port, count); 7339 if (!r) 7340 return r; 7341 7342 /* Results already available, fall through. */ 7343 } 7344 7345 complete_emulator_pio_in(vcpu, val); 7346 return 1; 7347 } 7348 7349 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt, 7350 int size, unsigned short port, void *val, 7351 unsigned int count) 7352 { 7353 return emulator_pio_in(emul_to_vcpu(ctxt), size, port, val, count); 7354 7355 } 7356 7357 static int emulator_pio_out(struct kvm_vcpu *vcpu, int size, 7358 unsigned short port, const void *val, 7359 unsigned int count) 7360 { 7361 int ret; 7362 7363 memcpy(vcpu->arch.pio_data, val, size * count); 7364 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data); 7365 ret = emulator_pio_in_out(vcpu, size, port, count, false); 7366 if (ret) 7367 vcpu->arch.pio.count = 0; 7368 7369 return ret; 7370 } 7371 7372 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt, 7373 int size, unsigned short port, 7374 const void *val, unsigned int count) 7375 { 7376 return emulator_pio_out(emul_to_vcpu(ctxt), size, port, val, count); 7377 } 7378 7379 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg) 7380 { 7381 return static_call(kvm_x86_get_segment_base)(vcpu, seg); 7382 } 7383 7384 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address) 7385 { 7386 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address); 7387 } 7388 7389 static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu) 7390 { 7391 if (!need_emulate_wbinvd(vcpu)) 7392 return X86EMUL_CONTINUE; 7393 7394 if (static_call(kvm_x86_has_wbinvd_exit)()) { 7395 int cpu = get_cpu(); 7396 7397 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); 7398 on_each_cpu_mask(vcpu->arch.wbinvd_dirty_mask, 7399 wbinvd_ipi, NULL, 1); 7400 put_cpu(); 7401 cpumask_clear(vcpu->arch.wbinvd_dirty_mask); 7402 } else 7403 wbinvd(); 7404 return X86EMUL_CONTINUE; 7405 } 7406 7407 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu) 7408 { 7409 kvm_emulate_wbinvd_noskip(vcpu); 7410 return kvm_skip_emulated_instruction(vcpu); 7411 } 7412 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd); 7413 7414 7415 7416 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt) 7417 { 7418 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt)); 7419 } 7420 7421 static void emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, 7422 unsigned long *dest) 7423 { 7424 kvm_get_dr(emul_to_vcpu(ctxt), dr, dest); 7425 } 7426 7427 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, 7428 unsigned long value) 7429 { 7430 7431 return kvm_set_dr(emul_to_vcpu(ctxt), dr, value); 7432 } 7433 7434 static u64 mk_cr_64(u64 curr_cr, u32 new_val) 7435 { 7436 return (curr_cr & ~((1ULL << 32) - 1)) | new_val; 7437 } 7438 7439 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr) 7440 { 7441 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7442 unsigned long value; 7443 7444 switch (cr) { 7445 case 0: 7446 value = kvm_read_cr0(vcpu); 7447 break; 7448 case 2: 7449 value = vcpu->arch.cr2; 7450 break; 7451 case 3: 7452 value = kvm_read_cr3(vcpu); 7453 break; 7454 case 4: 7455 value = kvm_read_cr4(vcpu); 7456 break; 7457 case 8: 7458 value = kvm_get_cr8(vcpu); 7459 break; 7460 default: 7461 kvm_err("%s: unexpected cr %u\n", __func__, cr); 7462 return 0; 7463 } 7464 7465 return value; 7466 } 7467 7468 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val) 7469 { 7470 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7471 int res = 0; 7472 7473 switch (cr) { 7474 case 0: 7475 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val)); 7476 break; 7477 case 2: 7478 vcpu->arch.cr2 = val; 7479 break; 7480 case 3: 7481 res = kvm_set_cr3(vcpu, val); 7482 break; 7483 case 4: 7484 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val)); 7485 break; 7486 case 8: 7487 res = kvm_set_cr8(vcpu, val); 7488 break; 7489 default: 7490 kvm_err("%s: unexpected cr %u\n", __func__, cr); 7491 res = -1; 7492 } 7493 7494 return res; 7495 } 7496 7497 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt) 7498 { 7499 return static_call(kvm_x86_get_cpl)(emul_to_vcpu(ctxt)); 7500 } 7501 7502 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 7503 { 7504 static_call(kvm_x86_get_gdt)(emul_to_vcpu(ctxt), dt); 7505 } 7506 7507 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 7508 { 7509 static_call(kvm_x86_get_idt)(emul_to_vcpu(ctxt), dt); 7510 } 7511 7512 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 7513 { 7514 static_call(kvm_x86_set_gdt)(emul_to_vcpu(ctxt), dt); 7515 } 7516 7517 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 7518 { 7519 static_call(kvm_x86_set_idt)(emul_to_vcpu(ctxt), dt); 7520 } 7521 7522 static unsigned long emulator_get_cached_segment_base( 7523 struct x86_emulate_ctxt *ctxt, int seg) 7524 { 7525 return get_segment_base(emul_to_vcpu(ctxt), seg); 7526 } 7527 7528 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector, 7529 struct desc_struct *desc, u32 *base3, 7530 int seg) 7531 { 7532 struct kvm_segment var; 7533 7534 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg); 7535 *selector = var.selector; 7536 7537 if (var.unusable) { 7538 memset(desc, 0, sizeof(*desc)); 7539 if (base3) 7540 *base3 = 0; 7541 return false; 7542 } 7543 7544 if (var.g) 7545 var.limit >>= 12; 7546 set_desc_limit(desc, var.limit); 7547 set_desc_base(desc, (unsigned long)var.base); 7548 #ifdef CONFIG_X86_64 7549 if (base3) 7550 *base3 = var.base >> 32; 7551 #endif 7552 desc->type = var.type; 7553 desc->s = var.s; 7554 desc->dpl = var.dpl; 7555 desc->p = var.present; 7556 desc->avl = var.avl; 7557 desc->l = var.l; 7558 desc->d = var.db; 7559 desc->g = var.g; 7560 7561 return true; 7562 } 7563 7564 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector, 7565 struct desc_struct *desc, u32 base3, 7566 int seg) 7567 { 7568 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7569 struct kvm_segment var; 7570 7571 var.selector = selector; 7572 var.base = get_desc_base(desc); 7573 #ifdef CONFIG_X86_64 7574 var.base |= ((u64)base3) << 32; 7575 #endif 7576 var.limit = get_desc_limit(desc); 7577 if (desc->g) 7578 var.limit = (var.limit << 12) | 0xfff; 7579 var.type = desc->type; 7580 var.dpl = desc->dpl; 7581 var.db = desc->d; 7582 var.s = desc->s; 7583 var.l = desc->l; 7584 var.g = desc->g; 7585 var.avl = desc->avl; 7586 var.present = desc->p; 7587 var.unusable = !var.present; 7588 var.padding = 0; 7589 7590 kvm_set_segment(vcpu, &var, seg); 7591 return; 7592 } 7593 7594 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt, 7595 u32 msr_index, u64 *pdata) 7596 { 7597 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7598 int r; 7599 7600 r = kvm_get_msr(vcpu, msr_index, pdata); 7601 7602 if (r && kvm_msr_user_space(vcpu, msr_index, KVM_EXIT_X86_RDMSR, 0, 7603 complete_emulated_rdmsr, r)) { 7604 /* Bounce to user space */ 7605 return X86EMUL_IO_NEEDED; 7606 } 7607 7608 return r; 7609 } 7610 7611 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt, 7612 u32 msr_index, u64 data) 7613 { 7614 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7615 int r; 7616 7617 r = kvm_set_msr(vcpu, msr_index, data); 7618 7619 if (r && kvm_msr_user_space(vcpu, msr_index, KVM_EXIT_X86_WRMSR, data, 7620 complete_emulated_msr_access, r)) { 7621 /* Bounce to user space */ 7622 return X86EMUL_IO_NEEDED; 7623 } 7624 7625 return r; 7626 } 7627 7628 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt) 7629 { 7630 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7631 7632 return vcpu->arch.smbase; 7633 } 7634 7635 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase) 7636 { 7637 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7638 7639 vcpu->arch.smbase = smbase; 7640 } 7641 7642 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt, 7643 u32 pmc) 7644 { 7645 if (kvm_pmu_is_valid_rdpmc_ecx(emul_to_vcpu(ctxt), pmc)) 7646 return 0; 7647 return -EINVAL; 7648 } 7649 7650 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt, 7651 u32 pmc, u64 *pdata) 7652 { 7653 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata); 7654 } 7655 7656 static void emulator_halt(struct x86_emulate_ctxt *ctxt) 7657 { 7658 emul_to_vcpu(ctxt)->arch.halt_request = 1; 7659 } 7660 7661 static int emulator_intercept(struct x86_emulate_ctxt *ctxt, 7662 struct x86_instruction_info *info, 7663 enum x86_intercept_stage stage) 7664 { 7665 return static_call(kvm_x86_check_intercept)(emul_to_vcpu(ctxt), info, stage, 7666 &ctxt->exception); 7667 } 7668 7669 static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt, 7670 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, 7671 bool exact_only) 7672 { 7673 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, exact_only); 7674 } 7675 7676 static bool emulator_guest_has_long_mode(struct x86_emulate_ctxt *ctxt) 7677 { 7678 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_LM); 7679 } 7680 7681 static bool emulator_guest_has_movbe(struct x86_emulate_ctxt *ctxt) 7682 { 7683 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_MOVBE); 7684 } 7685 7686 static bool emulator_guest_has_fxsr(struct x86_emulate_ctxt *ctxt) 7687 { 7688 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_FXSR); 7689 } 7690 7691 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg) 7692 { 7693 return kvm_register_read_raw(emul_to_vcpu(ctxt), reg); 7694 } 7695 7696 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val) 7697 { 7698 kvm_register_write_raw(emul_to_vcpu(ctxt), reg, val); 7699 } 7700 7701 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked) 7702 { 7703 static_call(kvm_x86_set_nmi_mask)(emul_to_vcpu(ctxt), masked); 7704 } 7705 7706 static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt) 7707 { 7708 return emul_to_vcpu(ctxt)->arch.hflags; 7709 } 7710 7711 static void emulator_exiting_smm(struct x86_emulate_ctxt *ctxt) 7712 { 7713 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7714 7715 kvm_smm_changed(vcpu, false); 7716 } 7717 7718 static int emulator_leave_smm(struct x86_emulate_ctxt *ctxt, 7719 const char *smstate) 7720 { 7721 return static_call(kvm_x86_leave_smm)(emul_to_vcpu(ctxt), smstate); 7722 } 7723 7724 static void emulator_triple_fault(struct x86_emulate_ctxt *ctxt) 7725 { 7726 kvm_make_request(KVM_REQ_TRIPLE_FAULT, emul_to_vcpu(ctxt)); 7727 } 7728 7729 static int emulator_set_xcr(struct x86_emulate_ctxt *ctxt, u32 index, u64 xcr) 7730 { 7731 return __kvm_set_xcr(emul_to_vcpu(ctxt), index, xcr); 7732 } 7733 7734 static const struct x86_emulate_ops emulate_ops = { 7735 .read_gpr = emulator_read_gpr, 7736 .write_gpr = emulator_write_gpr, 7737 .read_std = emulator_read_std, 7738 .write_std = emulator_write_std, 7739 .read_phys = kvm_read_guest_phys_system, 7740 .fetch = kvm_fetch_guest_virt, 7741 .read_emulated = emulator_read_emulated, 7742 .write_emulated = emulator_write_emulated, 7743 .cmpxchg_emulated = emulator_cmpxchg_emulated, 7744 .invlpg = emulator_invlpg, 7745 .pio_in_emulated = emulator_pio_in_emulated, 7746 .pio_out_emulated = emulator_pio_out_emulated, 7747 .get_segment = emulator_get_segment, 7748 .set_segment = emulator_set_segment, 7749 .get_cached_segment_base = emulator_get_cached_segment_base, 7750 .get_gdt = emulator_get_gdt, 7751 .get_idt = emulator_get_idt, 7752 .set_gdt = emulator_set_gdt, 7753 .set_idt = emulator_set_idt, 7754 .get_cr = emulator_get_cr, 7755 .set_cr = emulator_set_cr, 7756 .cpl = emulator_get_cpl, 7757 .get_dr = emulator_get_dr, 7758 .set_dr = emulator_set_dr, 7759 .get_smbase = emulator_get_smbase, 7760 .set_smbase = emulator_set_smbase, 7761 .set_msr = emulator_set_msr, 7762 .get_msr = emulator_get_msr, 7763 .check_pmc = emulator_check_pmc, 7764 .read_pmc = emulator_read_pmc, 7765 .halt = emulator_halt, 7766 .wbinvd = emulator_wbinvd, 7767 .fix_hypercall = emulator_fix_hypercall, 7768 .intercept = emulator_intercept, 7769 .get_cpuid = emulator_get_cpuid, 7770 .guest_has_long_mode = emulator_guest_has_long_mode, 7771 .guest_has_movbe = emulator_guest_has_movbe, 7772 .guest_has_fxsr = emulator_guest_has_fxsr, 7773 .set_nmi_mask = emulator_set_nmi_mask, 7774 .get_hflags = emulator_get_hflags, 7775 .exiting_smm = emulator_exiting_smm, 7776 .leave_smm = emulator_leave_smm, 7777 .triple_fault = emulator_triple_fault, 7778 .set_xcr = emulator_set_xcr, 7779 }; 7780 7781 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask) 7782 { 7783 u32 int_shadow = static_call(kvm_x86_get_interrupt_shadow)(vcpu); 7784 /* 7785 * an sti; sti; sequence only disable interrupts for the first 7786 * instruction. So, if the last instruction, be it emulated or 7787 * not, left the system with the INT_STI flag enabled, it 7788 * means that the last instruction is an sti. We should not 7789 * leave the flag on in this case. The same goes for mov ss 7790 */ 7791 if (int_shadow & mask) 7792 mask = 0; 7793 if (unlikely(int_shadow || mask)) { 7794 static_call(kvm_x86_set_interrupt_shadow)(vcpu, mask); 7795 if (!mask) 7796 kvm_make_request(KVM_REQ_EVENT, vcpu); 7797 } 7798 } 7799 7800 static bool inject_emulated_exception(struct kvm_vcpu *vcpu) 7801 { 7802 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 7803 if (ctxt->exception.vector == PF_VECTOR) 7804 return kvm_inject_emulated_page_fault(vcpu, &ctxt->exception); 7805 7806 if (ctxt->exception.error_code_valid) 7807 kvm_queue_exception_e(vcpu, ctxt->exception.vector, 7808 ctxt->exception.error_code); 7809 else 7810 kvm_queue_exception(vcpu, ctxt->exception.vector); 7811 return false; 7812 } 7813 7814 static struct x86_emulate_ctxt *alloc_emulate_ctxt(struct kvm_vcpu *vcpu) 7815 { 7816 struct x86_emulate_ctxt *ctxt; 7817 7818 ctxt = kmem_cache_zalloc(x86_emulator_cache, GFP_KERNEL_ACCOUNT); 7819 if (!ctxt) { 7820 pr_err("kvm: failed to allocate vcpu's emulator\n"); 7821 return NULL; 7822 } 7823 7824 ctxt->vcpu = vcpu; 7825 ctxt->ops = &emulate_ops; 7826 vcpu->arch.emulate_ctxt = ctxt; 7827 7828 return ctxt; 7829 } 7830 7831 static void init_emulate_ctxt(struct kvm_vcpu *vcpu) 7832 { 7833 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 7834 int cs_db, cs_l; 7835 7836 static_call(kvm_x86_get_cs_db_l_bits)(vcpu, &cs_db, &cs_l); 7837 7838 ctxt->gpa_available = false; 7839 ctxt->eflags = kvm_get_rflags(vcpu); 7840 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0; 7841 7842 ctxt->eip = kvm_rip_read(vcpu); 7843 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL : 7844 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 : 7845 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 : 7846 cs_db ? X86EMUL_MODE_PROT32 : 7847 X86EMUL_MODE_PROT16; 7848 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK); 7849 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK); 7850 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK); 7851 7852 ctxt->interruptibility = 0; 7853 ctxt->have_exception = false; 7854 ctxt->exception.vector = -1; 7855 ctxt->perm_ok = false; 7856 7857 init_decode_cache(ctxt); 7858 vcpu->arch.emulate_regs_need_sync_from_vcpu = false; 7859 } 7860 7861 void kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip) 7862 { 7863 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 7864 int ret; 7865 7866 init_emulate_ctxt(vcpu); 7867 7868 ctxt->op_bytes = 2; 7869 ctxt->ad_bytes = 2; 7870 ctxt->_eip = ctxt->eip + inc_eip; 7871 ret = emulate_int_real(ctxt, irq); 7872 7873 if (ret != X86EMUL_CONTINUE) { 7874 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 7875 } else { 7876 ctxt->eip = ctxt->_eip; 7877 kvm_rip_write(vcpu, ctxt->eip); 7878 kvm_set_rflags(vcpu, ctxt->eflags); 7879 } 7880 } 7881 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt); 7882 7883 static void prepare_emulation_failure_exit(struct kvm_vcpu *vcpu, u64 *data, 7884 u8 ndata, u8 *insn_bytes, u8 insn_size) 7885 { 7886 struct kvm_run *run = vcpu->run; 7887 u64 info[5]; 7888 u8 info_start; 7889 7890 /* 7891 * Zero the whole array used to retrieve the exit info, as casting to 7892 * u32 for select entries will leave some chunks uninitialized. 7893 */ 7894 memset(&info, 0, sizeof(info)); 7895 7896 static_call(kvm_x86_get_exit_info)(vcpu, (u32 *)&info[0], &info[1], 7897 &info[2], (u32 *)&info[3], 7898 (u32 *)&info[4]); 7899 7900 run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 7901 run->emulation_failure.suberror = KVM_INTERNAL_ERROR_EMULATION; 7902 7903 /* 7904 * There's currently space for 13 entries, but 5 are used for the exit 7905 * reason and info. Restrict to 4 to reduce the maintenance burden 7906 * when expanding kvm_run.emulation_failure in the future. 7907 */ 7908 if (WARN_ON_ONCE(ndata > 4)) 7909 ndata = 4; 7910 7911 /* Always include the flags as a 'data' entry. */ 7912 info_start = 1; 7913 run->emulation_failure.flags = 0; 7914 7915 if (insn_size) { 7916 BUILD_BUG_ON((sizeof(run->emulation_failure.insn_size) + 7917 sizeof(run->emulation_failure.insn_bytes) != 16)); 7918 info_start += 2; 7919 run->emulation_failure.flags |= 7920 KVM_INTERNAL_ERROR_EMULATION_FLAG_INSTRUCTION_BYTES; 7921 run->emulation_failure.insn_size = insn_size; 7922 memset(run->emulation_failure.insn_bytes, 0x90, 7923 sizeof(run->emulation_failure.insn_bytes)); 7924 memcpy(run->emulation_failure.insn_bytes, insn_bytes, insn_size); 7925 } 7926 7927 memcpy(&run->internal.data[info_start], info, sizeof(info)); 7928 memcpy(&run->internal.data[info_start + ARRAY_SIZE(info)], data, 7929 ndata * sizeof(data[0])); 7930 7931 run->emulation_failure.ndata = info_start + ARRAY_SIZE(info) + ndata; 7932 } 7933 7934 static void prepare_emulation_ctxt_failure_exit(struct kvm_vcpu *vcpu) 7935 { 7936 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 7937 7938 prepare_emulation_failure_exit(vcpu, NULL, 0, ctxt->fetch.data, 7939 ctxt->fetch.end - ctxt->fetch.data); 7940 } 7941 7942 void __kvm_prepare_emulation_failure_exit(struct kvm_vcpu *vcpu, u64 *data, 7943 u8 ndata) 7944 { 7945 prepare_emulation_failure_exit(vcpu, data, ndata, NULL, 0); 7946 } 7947 EXPORT_SYMBOL_GPL(__kvm_prepare_emulation_failure_exit); 7948 7949 void kvm_prepare_emulation_failure_exit(struct kvm_vcpu *vcpu) 7950 { 7951 __kvm_prepare_emulation_failure_exit(vcpu, NULL, 0); 7952 } 7953 EXPORT_SYMBOL_GPL(kvm_prepare_emulation_failure_exit); 7954 7955 static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type) 7956 { 7957 struct kvm *kvm = vcpu->kvm; 7958 7959 ++vcpu->stat.insn_emulation_fail; 7960 trace_kvm_emulate_insn_failed(vcpu); 7961 7962 if (emulation_type & EMULTYPE_VMWARE_GP) { 7963 kvm_queue_exception_e(vcpu, GP_VECTOR, 0); 7964 return 1; 7965 } 7966 7967 if (kvm->arch.exit_on_emulation_error || 7968 (emulation_type & EMULTYPE_SKIP)) { 7969 prepare_emulation_ctxt_failure_exit(vcpu); 7970 return 0; 7971 } 7972 7973 kvm_queue_exception(vcpu, UD_VECTOR); 7974 7975 if (!is_guest_mode(vcpu) && static_call(kvm_x86_get_cpl)(vcpu) == 0) { 7976 prepare_emulation_ctxt_failure_exit(vcpu); 7977 return 0; 7978 } 7979 7980 return 1; 7981 } 7982 7983 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, 7984 bool write_fault_to_shadow_pgtable, 7985 int emulation_type) 7986 { 7987 gpa_t gpa = cr2_or_gpa; 7988 kvm_pfn_t pfn; 7989 7990 if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF)) 7991 return false; 7992 7993 if (WARN_ON_ONCE(is_guest_mode(vcpu)) || 7994 WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF))) 7995 return false; 7996 7997 if (!vcpu->arch.mmu->direct_map) { 7998 /* 7999 * Write permission should be allowed since only 8000 * write access need to be emulated. 8001 */ 8002 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL); 8003 8004 /* 8005 * If the mapping is invalid in guest, let cpu retry 8006 * it to generate fault. 8007 */ 8008 if (gpa == UNMAPPED_GVA) 8009 return true; 8010 } 8011 8012 /* 8013 * Do not retry the unhandleable instruction if it faults on the 8014 * readonly host memory, otherwise it will goto a infinite loop: 8015 * retry instruction -> write #PF -> emulation fail -> retry 8016 * instruction -> ... 8017 */ 8018 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa)); 8019 8020 /* 8021 * If the instruction failed on the error pfn, it can not be fixed, 8022 * report the error to userspace. 8023 */ 8024 if (is_error_noslot_pfn(pfn)) 8025 return false; 8026 8027 kvm_release_pfn_clean(pfn); 8028 8029 /* The instructions are well-emulated on direct mmu. */ 8030 if (vcpu->arch.mmu->direct_map) { 8031 unsigned int indirect_shadow_pages; 8032 8033 write_lock(&vcpu->kvm->mmu_lock); 8034 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages; 8035 write_unlock(&vcpu->kvm->mmu_lock); 8036 8037 if (indirect_shadow_pages) 8038 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 8039 8040 return true; 8041 } 8042 8043 /* 8044 * if emulation was due to access to shadowed page table 8045 * and it failed try to unshadow page and re-enter the 8046 * guest to let CPU execute the instruction. 8047 */ 8048 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 8049 8050 /* 8051 * If the access faults on its page table, it can not 8052 * be fixed by unprotecting shadow page and it should 8053 * be reported to userspace. 8054 */ 8055 return !write_fault_to_shadow_pgtable; 8056 } 8057 8058 static bool retry_instruction(struct x86_emulate_ctxt *ctxt, 8059 gpa_t cr2_or_gpa, int emulation_type) 8060 { 8061 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 8062 unsigned long last_retry_eip, last_retry_addr, gpa = cr2_or_gpa; 8063 8064 last_retry_eip = vcpu->arch.last_retry_eip; 8065 last_retry_addr = vcpu->arch.last_retry_addr; 8066 8067 /* 8068 * If the emulation is caused by #PF and it is non-page_table 8069 * writing instruction, it means the VM-EXIT is caused by shadow 8070 * page protected, we can zap the shadow page and retry this 8071 * instruction directly. 8072 * 8073 * Note: if the guest uses a non-page-table modifying instruction 8074 * on the PDE that points to the instruction, then we will unmap 8075 * the instruction and go to an infinite loop. So, we cache the 8076 * last retried eip and the last fault address, if we meet the eip 8077 * and the address again, we can break out of the potential infinite 8078 * loop. 8079 */ 8080 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0; 8081 8082 if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF)) 8083 return false; 8084 8085 if (WARN_ON_ONCE(is_guest_mode(vcpu)) || 8086 WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF))) 8087 return false; 8088 8089 if (x86_page_table_writing_insn(ctxt)) 8090 return false; 8091 8092 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2_or_gpa) 8093 return false; 8094 8095 vcpu->arch.last_retry_eip = ctxt->eip; 8096 vcpu->arch.last_retry_addr = cr2_or_gpa; 8097 8098 if (!vcpu->arch.mmu->direct_map) 8099 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL); 8100 8101 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 8102 8103 return true; 8104 } 8105 8106 static int complete_emulated_mmio(struct kvm_vcpu *vcpu); 8107 static int complete_emulated_pio(struct kvm_vcpu *vcpu); 8108 8109 static void kvm_smm_changed(struct kvm_vcpu *vcpu, bool entering_smm) 8110 { 8111 trace_kvm_smm_transition(vcpu->vcpu_id, vcpu->arch.smbase, entering_smm); 8112 8113 if (entering_smm) { 8114 vcpu->arch.hflags |= HF_SMM_MASK; 8115 } else { 8116 vcpu->arch.hflags &= ~(HF_SMM_MASK | HF_SMM_INSIDE_NMI_MASK); 8117 8118 /* Process a latched INIT or SMI, if any. */ 8119 kvm_make_request(KVM_REQ_EVENT, vcpu); 8120 8121 /* 8122 * Even if KVM_SET_SREGS2 loaded PDPTRs out of band, 8123 * on SMM exit we still need to reload them from 8124 * guest memory 8125 */ 8126 vcpu->arch.pdptrs_from_userspace = false; 8127 } 8128 8129 kvm_mmu_reset_context(vcpu); 8130 } 8131 8132 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7, 8133 unsigned long *db) 8134 { 8135 u32 dr6 = 0; 8136 int i; 8137 u32 enable, rwlen; 8138 8139 enable = dr7; 8140 rwlen = dr7 >> 16; 8141 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4) 8142 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr) 8143 dr6 |= (1 << i); 8144 return dr6; 8145 } 8146 8147 static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu) 8148 { 8149 struct kvm_run *kvm_run = vcpu->run; 8150 8151 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) { 8152 kvm_run->debug.arch.dr6 = DR6_BS | DR6_ACTIVE_LOW; 8153 kvm_run->debug.arch.pc = kvm_get_linear_rip(vcpu); 8154 kvm_run->debug.arch.exception = DB_VECTOR; 8155 kvm_run->exit_reason = KVM_EXIT_DEBUG; 8156 return 0; 8157 } 8158 kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS); 8159 return 1; 8160 } 8161 8162 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu) 8163 { 8164 unsigned long rflags = static_call(kvm_x86_get_rflags)(vcpu); 8165 int r; 8166 8167 r = static_call(kvm_x86_skip_emulated_instruction)(vcpu); 8168 if (unlikely(!r)) 8169 return 0; 8170 8171 kvm_pmu_trigger_event(vcpu, PERF_COUNT_HW_INSTRUCTIONS); 8172 8173 /* 8174 * rflags is the old, "raw" value of the flags. The new value has 8175 * not been saved yet. 8176 * 8177 * This is correct even for TF set by the guest, because "the 8178 * processor will not generate this exception after the instruction 8179 * that sets the TF flag". 8180 */ 8181 if (unlikely(rflags & X86_EFLAGS_TF)) 8182 r = kvm_vcpu_do_singlestep(vcpu); 8183 return r; 8184 } 8185 EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction); 8186 8187 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r) 8188 { 8189 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) && 8190 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) { 8191 struct kvm_run *kvm_run = vcpu->run; 8192 unsigned long eip = kvm_get_linear_rip(vcpu); 8193 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, 8194 vcpu->arch.guest_debug_dr7, 8195 vcpu->arch.eff_db); 8196 8197 if (dr6 != 0) { 8198 kvm_run->debug.arch.dr6 = dr6 | DR6_ACTIVE_LOW; 8199 kvm_run->debug.arch.pc = eip; 8200 kvm_run->debug.arch.exception = DB_VECTOR; 8201 kvm_run->exit_reason = KVM_EXIT_DEBUG; 8202 *r = 0; 8203 return true; 8204 } 8205 } 8206 8207 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) && 8208 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) { 8209 unsigned long eip = kvm_get_linear_rip(vcpu); 8210 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, 8211 vcpu->arch.dr7, 8212 vcpu->arch.db); 8213 8214 if (dr6 != 0) { 8215 kvm_queue_exception_p(vcpu, DB_VECTOR, dr6); 8216 *r = 1; 8217 return true; 8218 } 8219 } 8220 8221 return false; 8222 } 8223 8224 static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt) 8225 { 8226 switch (ctxt->opcode_len) { 8227 case 1: 8228 switch (ctxt->b) { 8229 case 0xe4: /* IN */ 8230 case 0xe5: 8231 case 0xec: 8232 case 0xed: 8233 case 0xe6: /* OUT */ 8234 case 0xe7: 8235 case 0xee: 8236 case 0xef: 8237 case 0x6c: /* INS */ 8238 case 0x6d: 8239 case 0x6e: /* OUTS */ 8240 case 0x6f: 8241 return true; 8242 } 8243 break; 8244 case 2: 8245 switch (ctxt->b) { 8246 case 0x33: /* RDPMC */ 8247 return true; 8248 } 8249 break; 8250 } 8251 8252 return false; 8253 } 8254 8255 /* 8256 * Decode to be emulated instruction. Return EMULATION_OK if success. 8257 */ 8258 int x86_decode_emulated_instruction(struct kvm_vcpu *vcpu, int emulation_type, 8259 void *insn, int insn_len) 8260 { 8261 int r = EMULATION_OK; 8262 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 8263 8264 init_emulate_ctxt(vcpu); 8265 8266 /* 8267 * We will reenter on the same instruction since we do not set 8268 * complete_userspace_io. This does not handle watchpoints yet, 8269 * those would be handled in the emulate_ops. 8270 */ 8271 if (!(emulation_type & EMULTYPE_SKIP) && 8272 kvm_vcpu_check_breakpoint(vcpu, &r)) 8273 return r; 8274 8275 r = x86_decode_insn(ctxt, insn, insn_len, emulation_type); 8276 8277 trace_kvm_emulate_insn_start(vcpu); 8278 ++vcpu->stat.insn_emulation; 8279 8280 return r; 8281 } 8282 EXPORT_SYMBOL_GPL(x86_decode_emulated_instruction); 8283 8284 int x86_emulate_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, 8285 int emulation_type, void *insn, int insn_len) 8286 { 8287 int r; 8288 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 8289 bool writeback = true; 8290 bool write_fault_to_spt; 8291 8292 if (unlikely(!kvm_can_emulate_insn(vcpu, emulation_type, insn, insn_len))) 8293 return 1; 8294 8295 vcpu->arch.l1tf_flush_l1d = true; 8296 8297 /* 8298 * Clear write_fault_to_shadow_pgtable here to ensure it is 8299 * never reused. 8300 */ 8301 write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable; 8302 vcpu->arch.write_fault_to_shadow_pgtable = false; 8303 8304 if (!(emulation_type & EMULTYPE_NO_DECODE)) { 8305 kvm_clear_exception_queue(vcpu); 8306 8307 r = x86_decode_emulated_instruction(vcpu, emulation_type, 8308 insn, insn_len); 8309 if (r != EMULATION_OK) { 8310 if ((emulation_type & EMULTYPE_TRAP_UD) || 8311 (emulation_type & EMULTYPE_TRAP_UD_FORCED)) { 8312 kvm_queue_exception(vcpu, UD_VECTOR); 8313 return 1; 8314 } 8315 if (reexecute_instruction(vcpu, cr2_or_gpa, 8316 write_fault_to_spt, 8317 emulation_type)) 8318 return 1; 8319 if (ctxt->have_exception) { 8320 /* 8321 * #UD should result in just EMULATION_FAILED, and trap-like 8322 * exception should not be encountered during decode. 8323 */ 8324 WARN_ON_ONCE(ctxt->exception.vector == UD_VECTOR || 8325 exception_type(ctxt->exception.vector) == EXCPT_TRAP); 8326 inject_emulated_exception(vcpu); 8327 return 1; 8328 } 8329 return handle_emulation_failure(vcpu, emulation_type); 8330 } 8331 } 8332 8333 if ((emulation_type & EMULTYPE_VMWARE_GP) && 8334 !is_vmware_backdoor_opcode(ctxt)) { 8335 kvm_queue_exception_e(vcpu, GP_VECTOR, 0); 8336 return 1; 8337 } 8338 8339 /* 8340 * EMULTYPE_SKIP without EMULTYPE_COMPLETE_USER_EXIT is intended for 8341 * use *only* by vendor callbacks for kvm_skip_emulated_instruction(). 8342 * The caller is responsible for updating interruptibility state and 8343 * injecting single-step #DBs. 8344 */ 8345 if (emulation_type & EMULTYPE_SKIP) { 8346 if (ctxt->mode != X86EMUL_MODE_PROT64) 8347 ctxt->eip = (u32)ctxt->_eip; 8348 else 8349 ctxt->eip = ctxt->_eip; 8350 8351 if (emulation_type & EMULTYPE_COMPLETE_USER_EXIT) { 8352 r = 1; 8353 goto writeback; 8354 } 8355 8356 kvm_rip_write(vcpu, ctxt->eip); 8357 if (ctxt->eflags & X86_EFLAGS_RF) 8358 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF); 8359 return 1; 8360 } 8361 8362 if (retry_instruction(ctxt, cr2_or_gpa, emulation_type)) 8363 return 1; 8364 8365 /* this is needed for vmware backdoor interface to work since it 8366 changes registers values during IO operation */ 8367 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) { 8368 vcpu->arch.emulate_regs_need_sync_from_vcpu = false; 8369 emulator_invalidate_register_cache(ctxt); 8370 } 8371 8372 restart: 8373 if (emulation_type & EMULTYPE_PF) { 8374 /* Save the faulting GPA (cr2) in the address field */ 8375 ctxt->exception.address = cr2_or_gpa; 8376 8377 /* With shadow page tables, cr2 contains a GVA or nGPA. */ 8378 if (vcpu->arch.mmu->direct_map) { 8379 ctxt->gpa_available = true; 8380 ctxt->gpa_val = cr2_or_gpa; 8381 } 8382 } else { 8383 /* Sanitize the address out of an abundance of paranoia. */ 8384 ctxt->exception.address = 0; 8385 } 8386 8387 r = x86_emulate_insn(ctxt); 8388 8389 if (r == EMULATION_INTERCEPTED) 8390 return 1; 8391 8392 if (r == EMULATION_FAILED) { 8393 if (reexecute_instruction(vcpu, cr2_or_gpa, write_fault_to_spt, 8394 emulation_type)) 8395 return 1; 8396 8397 return handle_emulation_failure(vcpu, emulation_type); 8398 } 8399 8400 if (ctxt->have_exception) { 8401 r = 1; 8402 if (inject_emulated_exception(vcpu)) 8403 return r; 8404 } else if (vcpu->arch.pio.count) { 8405 if (!vcpu->arch.pio.in) { 8406 /* FIXME: return into emulator if single-stepping. */ 8407 vcpu->arch.pio.count = 0; 8408 } else { 8409 writeback = false; 8410 vcpu->arch.complete_userspace_io = complete_emulated_pio; 8411 } 8412 r = 0; 8413 } else if (vcpu->mmio_needed) { 8414 ++vcpu->stat.mmio_exits; 8415 8416 if (!vcpu->mmio_is_write) 8417 writeback = false; 8418 r = 0; 8419 vcpu->arch.complete_userspace_io = complete_emulated_mmio; 8420 } else if (vcpu->arch.complete_userspace_io) { 8421 writeback = false; 8422 r = 0; 8423 } else if (r == EMULATION_RESTART) 8424 goto restart; 8425 else 8426 r = 1; 8427 8428 writeback: 8429 if (writeback) { 8430 unsigned long rflags = static_call(kvm_x86_get_rflags)(vcpu); 8431 toggle_interruptibility(vcpu, ctxt->interruptibility); 8432 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 8433 if (!ctxt->have_exception || 8434 exception_type(ctxt->exception.vector) == EXCPT_TRAP) { 8435 kvm_pmu_trigger_event(vcpu, PERF_COUNT_HW_INSTRUCTIONS); 8436 if (ctxt->is_branch) 8437 kvm_pmu_trigger_event(vcpu, PERF_COUNT_HW_BRANCH_INSTRUCTIONS); 8438 kvm_rip_write(vcpu, ctxt->eip); 8439 if (r && (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP))) 8440 r = kvm_vcpu_do_singlestep(vcpu); 8441 static_call_cond(kvm_x86_update_emulated_instruction)(vcpu); 8442 __kvm_set_rflags(vcpu, ctxt->eflags); 8443 } 8444 8445 /* 8446 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will 8447 * do nothing, and it will be requested again as soon as 8448 * the shadow expires. But we still need to check here, 8449 * because POPF has no interrupt shadow. 8450 */ 8451 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF)) 8452 kvm_make_request(KVM_REQ_EVENT, vcpu); 8453 } else 8454 vcpu->arch.emulate_regs_need_sync_to_vcpu = true; 8455 8456 return r; 8457 } 8458 8459 int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type) 8460 { 8461 return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0); 8462 } 8463 EXPORT_SYMBOL_GPL(kvm_emulate_instruction); 8464 8465 int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu, 8466 void *insn, int insn_len) 8467 { 8468 return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len); 8469 } 8470 EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer); 8471 8472 static int complete_fast_pio_out_port_0x7e(struct kvm_vcpu *vcpu) 8473 { 8474 vcpu->arch.pio.count = 0; 8475 return 1; 8476 } 8477 8478 static int complete_fast_pio_out(struct kvm_vcpu *vcpu) 8479 { 8480 vcpu->arch.pio.count = 0; 8481 8482 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) 8483 return 1; 8484 8485 return kvm_skip_emulated_instruction(vcpu); 8486 } 8487 8488 static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, 8489 unsigned short port) 8490 { 8491 unsigned long val = kvm_rax_read(vcpu); 8492 int ret = emulator_pio_out(vcpu, size, port, &val, 1); 8493 8494 if (ret) 8495 return ret; 8496 8497 /* 8498 * Workaround userspace that relies on old KVM behavior of %rip being 8499 * incremented prior to exiting to userspace to handle "OUT 0x7e". 8500 */ 8501 if (port == 0x7e && 8502 kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_OUT_7E_INC_RIP)) { 8503 vcpu->arch.complete_userspace_io = 8504 complete_fast_pio_out_port_0x7e; 8505 kvm_skip_emulated_instruction(vcpu); 8506 } else { 8507 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu); 8508 vcpu->arch.complete_userspace_io = complete_fast_pio_out; 8509 } 8510 return 0; 8511 } 8512 8513 static int complete_fast_pio_in(struct kvm_vcpu *vcpu) 8514 { 8515 unsigned long val; 8516 8517 /* We should only ever be called with arch.pio.count equal to 1 */ 8518 BUG_ON(vcpu->arch.pio.count != 1); 8519 8520 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) { 8521 vcpu->arch.pio.count = 0; 8522 return 1; 8523 } 8524 8525 /* For size less than 4 we merge, else we zero extend */ 8526 val = (vcpu->arch.pio.size < 4) ? kvm_rax_read(vcpu) : 0; 8527 8528 /* 8529 * Since vcpu->arch.pio.count == 1 let emulator_pio_in perform 8530 * the copy and tracing 8531 */ 8532 emulator_pio_in(vcpu, vcpu->arch.pio.size, vcpu->arch.pio.port, &val, 1); 8533 kvm_rax_write(vcpu, val); 8534 8535 return kvm_skip_emulated_instruction(vcpu); 8536 } 8537 8538 static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size, 8539 unsigned short port) 8540 { 8541 unsigned long val; 8542 int ret; 8543 8544 /* For size less than 4 we merge, else we zero extend */ 8545 val = (size < 4) ? kvm_rax_read(vcpu) : 0; 8546 8547 ret = emulator_pio_in(vcpu, size, port, &val, 1); 8548 if (ret) { 8549 kvm_rax_write(vcpu, val); 8550 return ret; 8551 } 8552 8553 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu); 8554 vcpu->arch.complete_userspace_io = complete_fast_pio_in; 8555 8556 return 0; 8557 } 8558 8559 int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in) 8560 { 8561 int ret; 8562 8563 if (in) 8564 ret = kvm_fast_pio_in(vcpu, size, port); 8565 else 8566 ret = kvm_fast_pio_out(vcpu, size, port); 8567 return ret && kvm_skip_emulated_instruction(vcpu); 8568 } 8569 EXPORT_SYMBOL_GPL(kvm_fast_pio); 8570 8571 static int kvmclock_cpu_down_prep(unsigned int cpu) 8572 { 8573 __this_cpu_write(cpu_tsc_khz, 0); 8574 return 0; 8575 } 8576 8577 static void tsc_khz_changed(void *data) 8578 { 8579 struct cpufreq_freqs *freq = data; 8580 unsigned long khz = 0; 8581 8582 if (data) 8583 khz = freq->new; 8584 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) 8585 khz = cpufreq_quick_get(raw_smp_processor_id()); 8586 if (!khz) 8587 khz = tsc_khz; 8588 __this_cpu_write(cpu_tsc_khz, khz); 8589 } 8590 8591 #ifdef CONFIG_X86_64 8592 static void kvm_hyperv_tsc_notifier(void) 8593 { 8594 struct kvm *kvm; 8595 int cpu; 8596 8597 mutex_lock(&kvm_lock); 8598 list_for_each_entry(kvm, &vm_list, vm_list) 8599 kvm_make_mclock_inprogress_request(kvm); 8600 8601 /* no guest entries from this point */ 8602 hyperv_stop_tsc_emulation(); 8603 8604 /* TSC frequency always matches when on Hyper-V */ 8605 for_each_present_cpu(cpu) 8606 per_cpu(cpu_tsc_khz, cpu) = tsc_khz; 8607 kvm_max_guest_tsc_khz = tsc_khz; 8608 8609 list_for_each_entry(kvm, &vm_list, vm_list) { 8610 __kvm_start_pvclock_update(kvm); 8611 pvclock_update_vm_gtod_copy(kvm); 8612 kvm_end_pvclock_update(kvm); 8613 } 8614 8615 mutex_unlock(&kvm_lock); 8616 } 8617 #endif 8618 8619 static void __kvmclock_cpufreq_notifier(struct cpufreq_freqs *freq, int cpu) 8620 { 8621 struct kvm *kvm; 8622 struct kvm_vcpu *vcpu; 8623 int send_ipi = 0; 8624 unsigned long i; 8625 8626 /* 8627 * We allow guests to temporarily run on slowing clocks, 8628 * provided we notify them after, or to run on accelerating 8629 * clocks, provided we notify them before. Thus time never 8630 * goes backwards. 8631 * 8632 * However, we have a problem. We can't atomically update 8633 * the frequency of a given CPU from this function; it is 8634 * merely a notifier, which can be called from any CPU. 8635 * Changing the TSC frequency at arbitrary points in time 8636 * requires a recomputation of local variables related to 8637 * the TSC for each VCPU. We must flag these local variables 8638 * to be updated and be sure the update takes place with the 8639 * new frequency before any guests proceed. 8640 * 8641 * Unfortunately, the combination of hotplug CPU and frequency 8642 * change creates an intractable locking scenario; the order 8643 * of when these callouts happen is undefined with respect to 8644 * CPU hotplug, and they can race with each other. As such, 8645 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is 8646 * undefined; you can actually have a CPU frequency change take 8647 * place in between the computation of X and the setting of the 8648 * variable. To protect against this problem, all updates of 8649 * the per_cpu tsc_khz variable are done in an interrupt 8650 * protected IPI, and all callers wishing to update the value 8651 * must wait for a synchronous IPI to complete (which is trivial 8652 * if the caller is on the CPU already). This establishes the 8653 * necessary total order on variable updates. 8654 * 8655 * Note that because a guest time update may take place 8656 * anytime after the setting of the VCPU's request bit, the 8657 * correct TSC value must be set before the request. However, 8658 * to ensure the update actually makes it to any guest which 8659 * starts running in hardware virtualization between the set 8660 * and the acquisition of the spinlock, we must also ping the 8661 * CPU after setting the request bit. 8662 * 8663 */ 8664 8665 smp_call_function_single(cpu, tsc_khz_changed, freq, 1); 8666 8667 mutex_lock(&kvm_lock); 8668 list_for_each_entry(kvm, &vm_list, vm_list) { 8669 kvm_for_each_vcpu(i, vcpu, kvm) { 8670 if (vcpu->cpu != cpu) 8671 continue; 8672 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 8673 if (vcpu->cpu != raw_smp_processor_id()) 8674 send_ipi = 1; 8675 } 8676 } 8677 mutex_unlock(&kvm_lock); 8678 8679 if (freq->old < freq->new && send_ipi) { 8680 /* 8681 * We upscale the frequency. Must make the guest 8682 * doesn't see old kvmclock values while running with 8683 * the new frequency, otherwise we risk the guest sees 8684 * time go backwards. 8685 * 8686 * In case we update the frequency for another cpu 8687 * (which might be in guest context) send an interrupt 8688 * to kick the cpu out of guest context. Next time 8689 * guest context is entered kvmclock will be updated, 8690 * so the guest will not see stale values. 8691 */ 8692 smp_call_function_single(cpu, tsc_khz_changed, freq, 1); 8693 } 8694 } 8695 8696 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val, 8697 void *data) 8698 { 8699 struct cpufreq_freqs *freq = data; 8700 int cpu; 8701 8702 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new) 8703 return 0; 8704 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new) 8705 return 0; 8706 8707 for_each_cpu(cpu, freq->policy->cpus) 8708 __kvmclock_cpufreq_notifier(freq, cpu); 8709 8710 return 0; 8711 } 8712 8713 static struct notifier_block kvmclock_cpufreq_notifier_block = { 8714 .notifier_call = kvmclock_cpufreq_notifier 8715 }; 8716 8717 static int kvmclock_cpu_online(unsigned int cpu) 8718 { 8719 tsc_khz_changed(NULL); 8720 return 0; 8721 } 8722 8723 static void kvm_timer_init(void) 8724 { 8725 max_tsc_khz = tsc_khz; 8726 8727 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) { 8728 #ifdef CONFIG_CPU_FREQ 8729 struct cpufreq_policy *policy; 8730 int cpu; 8731 8732 cpu = get_cpu(); 8733 policy = cpufreq_cpu_get(cpu); 8734 if (policy) { 8735 if (policy->cpuinfo.max_freq) 8736 max_tsc_khz = policy->cpuinfo.max_freq; 8737 cpufreq_cpu_put(policy); 8738 } 8739 put_cpu(); 8740 #endif 8741 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block, 8742 CPUFREQ_TRANSITION_NOTIFIER); 8743 } 8744 8745 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online", 8746 kvmclock_cpu_online, kvmclock_cpu_down_prep); 8747 } 8748 8749 #ifdef CONFIG_X86_64 8750 static void pvclock_gtod_update_fn(struct work_struct *work) 8751 { 8752 struct kvm *kvm; 8753 struct kvm_vcpu *vcpu; 8754 unsigned long i; 8755 8756 mutex_lock(&kvm_lock); 8757 list_for_each_entry(kvm, &vm_list, vm_list) 8758 kvm_for_each_vcpu(i, vcpu, kvm) 8759 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 8760 atomic_set(&kvm_guest_has_master_clock, 0); 8761 mutex_unlock(&kvm_lock); 8762 } 8763 8764 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn); 8765 8766 /* 8767 * Indirection to move queue_work() out of the tk_core.seq write held 8768 * region to prevent possible deadlocks against time accessors which 8769 * are invoked with work related locks held. 8770 */ 8771 static void pvclock_irq_work_fn(struct irq_work *w) 8772 { 8773 queue_work(system_long_wq, &pvclock_gtod_work); 8774 } 8775 8776 static DEFINE_IRQ_WORK(pvclock_irq_work, pvclock_irq_work_fn); 8777 8778 /* 8779 * Notification about pvclock gtod data update. 8780 */ 8781 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused, 8782 void *priv) 8783 { 8784 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 8785 struct timekeeper *tk = priv; 8786 8787 update_pvclock_gtod(tk); 8788 8789 /* 8790 * Disable master clock if host does not trust, or does not use, 8791 * TSC based clocksource. Delegate queue_work() to irq_work as 8792 * this is invoked with tk_core.seq write held. 8793 */ 8794 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) && 8795 atomic_read(&kvm_guest_has_master_clock) != 0) 8796 irq_work_queue(&pvclock_irq_work); 8797 return 0; 8798 } 8799 8800 static struct notifier_block pvclock_gtod_notifier = { 8801 .notifier_call = pvclock_gtod_notify, 8802 }; 8803 #endif 8804 8805 int kvm_arch_init(void *opaque) 8806 { 8807 struct kvm_x86_init_ops *ops = opaque; 8808 int r; 8809 8810 if (kvm_x86_ops.hardware_enable) { 8811 pr_err("kvm: already loaded vendor module '%s'\n", kvm_x86_ops.name); 8812 r = -EEXIST; 8813 goto out; 8814 } 8815 8816 if (!ops->cpu_has_kvm_support()) { 8817 pr_err_ratelimited("kvm: no hardware support for '%s'\n", 8818 ops->runtime_ops->name); 8819 r = -EOPNOTSUPP; 8820 goto out; 8821 } 8822 if (ops->disabled_by_bios()) { 8823 pr_err_ratelimited("kvm: support for '%s' disabled by bios\n", 8824 ops->runtime_ops->name); 8825 r = -EOPNOTSUPP; 8826 goto out; 8827 } 8828 8829 /* 8830 * KVM explicitly assumes that the guest has an FPU and 8831 * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the 8832 * vCPU's FPU state as a fxregs_state struct. 8833 */ 8834 if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) { 8835 printk(KERN_ERR "kvm: inadequate fpu\n"); 8836 r = -EOPNOTSUPP; 8837 goto out; 8838 } 8839 8840 r = -ENOMEM; 8841 8842 x86_emulator_cache = kvm_alloc_emulator_cache(); 8843 if (!x86_emulator_cache) { 8844 pr_err("kvm: failed to allocate cache for x86 emulator\n"); 8845 goto out; 8846 } 8847 8848 user_return_msrs = alloc_percpu(struct kvm_user_return_msrs); 8849 if (!user_return_msrs) { 8850 printk(KERN_ERR "kvm: failed to allocate percpu kvm_user_return_msrs\n"); 8851 goto out_free_x86_emulator_cache; 8852 } 8853 kvm_nr_uret_msrs = 0; 8854 8855 r = kvm_mmu_module_init(); 8856 if (r) 8857 goto out_free_percpu; 8858 8859 kvm_timer_init(); 8860 8861 if (boot_cpu_has(X86_FEATURE_XSAVE)) { 8862 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK); 8863 supported_xcr0 = host_xcr0 & KVM_SUPPORTED_XCR0; 8864 } 8865 8866 if (pi_inject_timer == -1) 8867 pi_inject_timer = housekeeping_enabled(HK_FLAG_TIMER); 8868 #ifdef CONFIG_X86_64 8869 pvclock_gtod_register_notifier(&pvclock_gtod_notifier); 8870 8871 if (hypervisor_is_type(X86_HYPER_MS_HYPERV)) 8872 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier); 8873 #endif 8874 8875 return 0; 8876 8877 out_free_percpu: 8878 free_percpu(user_return_msrs); 8879 out_free_x86_emulator_cache: 8880 kmem_cache_destroy(x86_emulator_cache); 8881 out: 8882 return r; 8883 } 8884 8885 void kvm_arch_exit(void) 8886 { 8887 #ifdef CONFIG_X86_64 8888 if (hypervisor_is_type(X86_HYPER_MS_HYPERV)) 8889 clear_hv_tscchange_cb(); 8890 #endif 8891 kvm_lapic_exit(); 8892 8893 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) 8894 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block, 8895 CPUFREQ_TRANSITION_NOTIFIER); 8896 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE); 8897 #ifdef CONFIG_X86_64 8898 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier); 8899 irq_work_sync(&pvclock_irq_work); 8900 cancel_work_sync(&pvclock_gtod_work); 8901 #endif 8902 kvm_x86_ops.hardware_enable = NULL; 8903 kvm_mmu_module_exit(); 8904 free_percpu(user_return_msrs); 8905 kmem_cache_destroy(x86_emulator_cache); 8906 #ifdef CONFIG_KVM_XEN 8907 static_key_deferred_flush(&kvm_xen_enabled); 8908 WARN_ON(static_branch_unlikely(&kvm_xen_enabled.key)); 8909 #endif 8910 } 8911 8912 static int __kvm_emulate_halt(struct kvm_vcpu *vcpu, int state, int reason) 8913 { 8914 /* 8915 * The vCPU has halted, e.g. executed HLT. Update the run state if the 8916 * local APIC is in-kernel, the run loop will detect the non-runnable 8917 * state and halt the vCPU. Exit to userspace if the local APIC is 8918 * managed by userspace, in which case userspace is responsible for 8919 * handling wake events. 8920 */ 8921 ++vcpu->stat.halt_exits; 8922 if (lapic_in_kernel(vcpu)) { 8923 vcpu->arch.mp_state = state; 8924 return 1; 8925 } else { 8926 vcpu->run->exit_reason = reason; 8927 return 0; 8928 } 8929 } 8930 8931 int kvm_emulate_halt_noskip(struct kvm_vcpu *vcpu) 8932 { 8933 return __kvm_emulate_halt(vcpu, KVM_MP_STATE_HALTED, KVM_EXIT_HLT); 8934 } 8935 EXPORT_SYMBOL_GPL(kvm_emulate_halt_noskip); 8936 8937 int kvm_emulate_halt(struct kvm_vcpu *vcpu) 8938 { 8939 int ret = kvm_skip_emulated_instruction(vcpu); 8940 /* 8941 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered 8942 * KVM_EXIT_DEBUG here. 8943 */ 8944 return kvm_emulate_halt_noskip(vcpu) && ret; 8945 } 8946 EXPORT_SYMBOL_GPL(kvm_emulate_halt); 8947 8948 int kvm_emulate_ap_reset_hold(struct kvm_vcpu *vcpu) 8949 { 8950 int ret = kvm_skip_emulated_instruction(vcpu); 8951 8952 return __kvm_emulate_halt(vcpu, KVM_MP_STATE_AP_RESET_HOLD, 8953 KVM_EXIT_AP_RESET_HOLD) && ret; 8954 } 8955 EXPORT_SYMBOL_GPL(kvm_emulate_ap_reset_hold); 8956 8957 #ifdef CONFIG_X86_64 8958 static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr, 8959 unsigned long clock_type) 8960 { 8961 struct kvm_clock_pairing clock_pairing; 8962 struct timespec64 ts; 8963 u64 cycle; 8964 int ret; 8965 8966 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK) 8967 return -KVM_EOPNOTSUPP; 8968 8969 if (!kvm_get_walltime_and_clockread(&ts, &cycle)) 8970 return -KVM_EOPNOTSUPP; 8971 8972 clock_pairing.sec = ts.tv_sec; 8973 clock_pairing.nsec = ts.tv_nsec; 8974 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle); 8975 clock_pairing.flags = 0; 8976 memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad)); 8977 8978 ret = 0; 8979 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing, 8980 sizeof(struct kvm_clock_pairing))) 8981 ret = -KVM_EFAULT; 8982 8983 return ret; 8984 } 8985 #endif 8986 8987 /* 8988 * kvm_pv_kick_cpu_op: Kick a vcpu. 8989 * 8990 * @apicid - apicid of vcpu to be kicked. 8991 */ 8992 static void kvm_pv_kick_cpu_op(struct kvm *kvm, int apicid) 8993 { 8994 struct kvm_lapic_irq lapic_irq; 8995 8996 lapic_irq.shorthand = APIC_DEST_NOSHORT; 8997 lapic_irq.dest_mode = APIC_DEST_PHYSICAL; 8998 lapic_irq.level = 0; 8999 lapic_irq.dest_id = apicid; 9000 lapic_irq.msi_redir_hint = false; 9001 9002 lapic_irq.delivery_mode = APIC_DM_REMRD; 9003 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL); 9004 } 9005 9006 bool kvm_apicv_activated(struct kvm *kvm) 9007 { 9008 return (READ_ONCE(kvm->arch.apicv_inhibit_reasons) == 0); 9009 } 9010 EXPORT_SYMBOL_GPL(kvm_apicv_activated); 9011 9012 static void kvm_apicv_init(struct kvm *kvm) 9013 { 9014 init_rwsem(&kvm->arch.apicv_update_lock); 9015 9016 set_bit(APICV_INHIBIT_REASON_ABSENT, 9017 &kvm->arch.apicv_inhibit_reasons); 9018 if (!enable_apicv) 9019 set_bit(APICV_INHIBIT_REASON_DISABLE, 9020 &kvm->arch.apicv_inhibit_reasons); 9021 } 9022 9023 static void kvm_sched_yield(struct kvm_vcpu *vcpu, unsigned long dest_id) 9024 { 9025 struct kvm_vcpu *target = NULL; 9026 struct kvm_apic_map *map; 9027 9028 vcpu->stat.directed_yield_attempted++; 9029 9030 if (single_task_running()) 9031 goto no_yield; 9032 9033 rcu_read_lock(); 9034 map = rcu_dereference(vcpu->kvm->arch.apic_map); 9035 9036 if (likely(map) && dest_id <= map->max_apic_id && map->phys_map[dest_id]) 9037 target = map->phys_map[dest_id]->vcpu; 9038 9039 rcu_read_unlock(); 9040 9041 if (!target || !READ_ONCE(target->ready)) 9042 goto no_yield; 9043 9044 /* Ignore requests to yield to self */ 9045 if (vcpu == target) 9046 goto no_yield; 9047 9048 if (kvm_vcpu_yield_to(target) <= 0) 9049 goto no_yield; 9050 9051 vcpu->stat.directed_yield_successful++; 9052 9053 no_yield: 9054 return; 9055 } 9056 9057 static int complete_hypercall_exit(struct kvm_vcpu *vcpu) 9058 { 9059 u64 ret = vcpu->run->hypercall.ret; 9060 9061 if (!is_64_bit_mode(vcpu)) 9062 ret = (u32)ret; 9063 kvm_rax_write(vcpu, ret); 9064 ++vcpu->stat.hypercalls; 9065 return kvm_skip_emulated_instruction(vcpu); 9066 } 9067 9068 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu) 9069 { 9070 unsigned long nr, a0, a1, a2, a3, ret; 9071 int op_64_bit; 9072 9073 if (kvm_xen_hypercall_enabled(vcpu->kvm)) 9074 return kvm_xen_hypercall(vcpu); 9075 9076 if (kvm_hv_hypercall_enabled(vcpu)) 9077 return kvm_hv_hypercall(vcpu); 9078 9079 nr = kvm_rax_read(vcpu); 9080 a0 = kvm_rbx_read(vcpu); 9081 a1 = kvm_rcx_read(vcpu); 9082 a2 = kvm_rdx_read(vcpu); 9083 a3 = kvm_rsi_read(vcpu); 9084 9085 trace_kvm_hypercall(nr, a0, a1, a2, a3); 9086 9087 op_64_bit = is_64_bit_hypercall(vcpu); 9088 if (!op_64_bit) { 9089 nr &= 0xFFFFFFFF; 9090 a0 &= 0xFFFFFFFF; 9091 a1 &= 0xFFFFFFFF; 9092 a2 &= 0xFFFFFFFF; 9093 a3 &= 0xFFFFFFFF; 9094 } 9095 9096 if (static_call(kvm_x86_get_cpl)(vcpu) != 0) { 9097 ret = -KVM_EPERM; 9098 goto out; 9099 } 9100 9101 ret = -KVM_ENOSYS; 9102 9103 switch (nr) { 9104 case KVM_HC_VAPIC_POLL_IRQ: 9105 ret = 0; 9106 break; 9107 case KVM_HC_KICK_CPU: 9108 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_UNHALT)) 9109 break; 9110 9111 kvm_pv_kick_cpu_op(vcpu->kvm, a1); 9112 kvm_sched_yield(vcpu, a1); 9113 ret = 0; 9114 break; 9115 #ifdef CONFIG_X86_64 9116 case KVM_HC_CLOCK_PAIRING: 9117 ret = kvm_pv_clock_pairing(vcpu, a0, a1); 9118 break; 9119 #endif 9120 case KVM_HC_SEND_IPI: 9121 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SEND_IPI)) 9122 break; 9123 9124 ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit); 9125 break; 9126 case KVM_HC_SCHED_YIELD: 9127 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SCHED_YIELD)) 9128 break; 9129 9130 kvm_sched_yield(vcpu, a0); 9131 ret = 0; 9132 break; 9133 case KVM_HC_MAP_GPA_RANGE: { 9134 u64 gpa = a0, npages = a1, attrs = a2; 9135 9136 ret = -KVM_ENOSYS; 9137 if (!(vcpu->kvm->arch.hypercall_exit_enabled & (1 << KVM_HC_MAP_GPA_RANGE))) 9138 break; 9139 9140 if (!PAGE_ALIGNED(gpa) || !npages || 9141 gpa_to_gfn(gpa) + npages <= gpa_to_gfn(gpa)) { 9142 ret = -KVM_EINVAL; 9143 break; 9144 } 9145 9146 vcpu->run->exit_reason = KVM_EXIT_HYPERCALL; 9147 vcpu->run->hypercall.nr = KVM_HC_MAP_GPA_RANGE; 9148 vcpu->run->hypercall.args[0] = gpa; 9149 vcpu->run->hypercall.args[1] = npages; 9150 vcpu->run->hypercall.args[2] = attrs; 9151 vcpu->run->hypercall.longmode = op_64_bit; 9152 vcpu->arch.complete_userspace_io = complete_hypercall_exit; 9153 return 0; 9154 } 9155 default: 9156 ret = -KVM_ENOSYS; 9157 break; 9158 } 9159 out: 9160 if (!op_64_bit) 9161 ret = (u32)ret; 9162 kvm_rax_write(vcpu, ret); 9163 9164 ++vcpu->stat.hypercalls; 9165 return kvm_skip_emulated_instruction(vcpu); 9166 } 9167 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall); 9168 9169 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt) 9170 { 9171 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 9172 char instruction[3]; 9173 unsigned long rip = kvm_rip_read(vcpu); 9174 9175 static_call(kvm_x86_patch_hypercall)(vcpu, instruction); 9176 9177 return emulator_write_emulated(ctxt, rip, instruction, 3, 9178 &ctxt->exception); 9179 } 9180 9181 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu) 9182 { 9183 return vcpu->run->request_interrupt_window && 9184 likely(!pic_in_kernel(vcpu->kvm)); 9185 } 9186 9187 static void post_kvm_run_save(struct kvm_vcpu *vcpu) 9188 { 9189 struct kvm_run *kvm_run = vcpu->run; 9190 9191 kvm_run->if_flag = static_call(kvm_x86_get_if_flag)(vcpu); 9192 kvm_run->cr8 = kvm_get_cr8(vcpu); 9193 kvm_run->apic_base = kvm_get_apic_base(vcpu); 9194 9195 /* 9196 * The call to kvm_ready_for_interrupt_injection() may end up in 9197 * kvm_xen_has_interrupt() which may require the srcu lock to be 9198 * held, to protect against changes in the vcpu_info address. 9199 */ 9200 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 9201 kvm_run->ready_for_interrupt_injection = 9202 pic_in_kernel(vcpu->kvm) || 9203 kvm_vcpu_ready_for_interrupt_injection(vcpu); 9204 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); 9205 9206 if (is_smm(vcpu)) 9207 kvm_run->flags |= KVM_RUN_X86_SMM; 9208 } 9209 9210 static void update_cr8_intercept(struct kvm_vcpu *vcpu) 9211 { 9212 int max_irr, tpr; 9213 9214 if (!kvm_x86_ops.update_cr8_intercept) 9215 return; 9216 9217 if (!lapic_in_kernel(vcpu)) 9218 return; 9219 9220 if (vcpu->arch.apicv_active) 9221 return; 9222 9223 if (!vcpu->arch.apic->vapic_addr) 9224 max_irr = kvm_lapic_find_highest_irr(vcpu); 9225 else 9226 max_irr = -1; 9227 9228 if (max_irr != -1) 9229 max_irr >>= 4; 9230 9231 tpr = kvm_lapic_get_cr8(vcpu); 9232 9233 static_call(kvm_x86_update_cr8_intercept)(vcpu, tpr, max_irr); 9234 } 9235 9236 9237 int kvm_check_nested_events(struct kvm_vcpu *vcpu) 9238 { 9239 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) { 9240 kvm_x86_ops.nested_ops->triple_fault(vcpu); 9241 return 1; 9242 } 9243 9244 return kvm_x86_ops.nested_ops->check_events(vcpu); 9245 } 9246 9247 static void kvm_inject_exception(struct kvm_vcpu *vcpu) 9248 { 9249 if (vcpu->arch.exception.error_code && !is_protmode(vcpu)) 9250 vcpu->arch.exception.error_code = false; 9251 static_call(kvm_x86_queue_exception)(vcpu); 9252 } 9253 9254 static int inject_pending_event(struct kvm_vcpu *vcpu, bool *req_immediate_exit) 9255 { 9256 int r; 9257 bool can_inject = true; 9258 9259 /* try to reinject previous events if any */ 9260 9261 if (vcpu->arch.exception.injected) { 9262 kvm_inject_exception(vcpu); 9263 can_inject = false; 9264 } 9265 /* 9266 * Do not inject an NMI or interrupt if there is a pending 9267 * exception. Exceptions and interrupts are recognized at 9268 * instruction boundaries, i.e. the start of an instruction. 9269 * Trap-like exceptions, e.g. #DB, have higher priority than 9270 * NMIs and interrupts, i.e. traps are recognized before an 9271 * NMI/interrupt that's pending on the same instruction. 9272 * Fault-like exceptions, e.g. #GP and #PF, are the lowest 9273 * priority, but are only generated (pended) during instruction 9274 * execution, i.e. a pending fault-like exception means the 9275 * fault occurred on the *previous* instruction and must be 9276 * serviced prior to recognizing any new events in order to 9277 * fully complete the previous instruction. 9278 */ 9279 else if (!vcpu->arch.exception.pending) { 9280 if (vcpu->arch.nmi_injected) { 9281 static_call(kvm_x86_inject_nmi)(vcpu); 9282 can_inject = false; 9283 } else if (vcpu->arch.interrupt.injected) { 9284 static_call(kvm_x86_inject_irq)(vcpu); 9285 can_inject = false; 9286 } 9287 } 9288 9289 WARN_ON_ONCE(vcpu->arch.exception.injected && 9290 vcpu->arch.exception.pending); 9291 9292 /* 9293 * Call check_nested_events() even if we reinjected a previous event 9294 * in order for caller to determine if it should require immediate-exit 9295 * from L2 to L1 due to pending L1 events which require exit 9296 * from L2 to L1. 9297 */ 9298 if (is_guest_mode(vcpu)) { 9299 r = kvm_check_nested_events(vcpu); 9300 if (r < 0) 9301 goto out; 9302 } 9303 9304 /* try to inject new event if pending */ 9305 if (vcpu->arch.exception.pending) { 9306 trace_kvm_inj_exception(vcpu->arch.exception.nr, 9307 vcpu->arch.exception.has_error_code, 9308 vcpu->arch.exception.error_code); 9309 9310 vcpu->arch.exception.pending = false; 9311 vcpu->arch.exception.injected = true; 9312 9313 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT) 9314 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) | 9315 X86_EFLAGS_RF); 9316 9317 if (vcpu->arch.exception.nr == DB_VECTOR) { 9318 kvm_deliver_exception_payload(vcpu); 9319 if (vcpu->arch.dr7 & DR7_GD) { 9320 vcpu->arch.dr7 &= ~DR7_GD; 9321 kvm_update_dr7(vcpu); 9322 } 9323 } 9324 9325 kvm_inject_exception(vcpu); 9326 can_inject = false; 9327 } 9328 9329 /* Don't inject interrupts if the user asked to avoid doing so */ 9330 if (vcpu->guest_debug & KVM_GUESTDBG_BLOCKIRQ) 9331 return 0; 9332 9333 /* 9334 * Finally, inject interrupt events. If an event cannot be injected 9335 * due to architectural conditions (e.g. IF=0) a window-open exit 9336 * will re-request KVM_REQ_EVENT. Sometimes however an event is pending 9337 * and can architecturally be injected, but we cannot do it right now: 9338 * an interrupt could have arrived just now and we have to inject it 9339 * as a vmexit, or there could already an event in the queue, which is 9340 * indicated by can_inject. In that case we request an immediate exit 9341 * in order to make progress and get back here for another iteration. 9342 * The kvm_x86_ops hooks communicate this by returning -EBUSY. 9343 */ 9344 if (vcpu->arch.smi_pending) { 9345 r = can_inject ? static_call(kvm_x86_smi_allowed)(vcpu, true) : -EBUSY; 9346 if (r < 0) 9347 goto out; 9348 if (r) { 9349 vcpu->arch.smi_pending = false; 9350 ++vcpu->arch.smi_count; 9351 enter_smm(vcpu); 9352 can_inject = false; 9353 } else 9354 static_call(kvm_x86_enable_smi_window)(vcpu); 9355 } 9356 9357 if (vcpu->arch.nmi_pending) { 9358 r = can_inject ? static_call(kvm_x86_nmi_allowed)(vcpu, true) : -EBUSY; 9359 if (r < 0) 9360 goto out; 9361 if (r) { 9362 --vcpu->arch.nmi_pending; 9363 vcpu->arch.nmi_injected = true; 9364 static_call(kvm_x86_inject_nmi)(vcpu); 9365 can_inject = false; 9366 WARN_ON(static_call(kvm_x86_nmi_allowed)(vcpu, true) < 0); 9367 } 9368 if (vcpu->arch.nmi_pending) 9369 static_call(kvm_x86_enable_nmi_window)(vcpu); 9370 } 9371 9372 if (kvm_cpu_has_injectable_intr(vcpu)) { 9373 r = can_inject ? static_call(kvm_x86_interrupt_allowed)(vcpu, true) : -EBUSY; 9374 if (r < 0) 9375 goto out; 9376 if (r) { 9377 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu), false); 9378 static_call(kvm_x86_inject_irq)(vcpu); 9379 WARN_ON(static_call(kvm_x86_interrupt_allowed)(vcpu, true) < 0); 9380 } 9381 if (kvm_cpu_has_injectable_intr(vcpu)) 9382 static_call(kvm_x86_enable_irq_window)(vcpu); 9383 } 9384 9385 if (is_guest_mode(vcpu) && 9386 kvm_x86_ops.nested_ops->hv_timer_pending && 9387 kvm_x86_ops.nested_ops->hv_timer_pending(vcpu)) 9388 *req_immediate_exit = true; 9389 9390 WARN_ON(vcpu->arch.exception.pending); 9391 return 0; 9392 9393 out: 9394 if (r == -EBUSY) { 9395 *req_immediate_exit = true; 9396 r = 0; 9397 } 9398 return r; 9399 } 9400 9401 static void process_nmi(struct kvm_vcpu *vcpu) 9402 { 9403 unsigned limit = 2; 9404 9405 /* 9406 * x86 is limited to one NMI running, and one NMI pending after it. 9407 * If an NMI is already in progress, limit further NMIs to just one. 9408 * Otherwise, allow two (and we'll inject the first one immediately). 9409 */ 9410 if (static_call(kvm_x86_get_nmi_mask)(vcpu) || vcpu->arch.nmi_injected) 9411 limit = 1; 9412 9413 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0); 9414 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit); 9415 kvm_make_request(KVM_REQ_EVENT, vcpu); 9416 } 9417 9418 static u32 enter_smm_get_segment_flags(struct kvm_segment *seg) 9419 { 9420 u32 flags = 0; 9421 flags |= seg->g << 23; 9422 flags |= seg->db << 22; 9423 flags |= seg->l << 21; 9424 flags |= seg->avl << 20; 9425 flags |= seg->present << 15; 9426 flags |= seg->dpl << 13; 9427 flags |= seg->s << 12; 9428 flags |= seg->type << 8; 9429 return flags; 9430 } 9431 9432 static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n) 9433 { 9434 struct kvm_segment seg; 9435 int offset; 9436 9437 kvm_get_segment(vcpu, &seg, n); 9438 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector); 9439 9440 if (n < 3) 9441 offset = 0x7f84 + n * 12; 9442 else 9443 offset = 0x7f2c + (n - 3) * 12; 9444 9445 put_smstate(u32, buf, offset + 8, seg.base); 9446 put_smstate(u32, buf, offset + 4, seg.limit); 9447 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg)); 9448 } 9449 9450 #ifdef CONFIG_X86_64 9451 static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n) 9452 { 9453 struct kvm_segment seg; 9454 int offset; 9455 u16 flags; 9456 9457 kvm_get_segment(vcpu, &seg, n); 9458 offset = 0x7e00 + n * 16; 9459 9460 flags = enter_smm_get_segment_flags(&seg) >> 8; 9461 put_smstate(u16, buf, offset, seg.selector); 9462 put_smstate(u16, buf, offset + 2, flags); 9463 put_smstate(u32, buf, offset + 4, seg.limit); 9464 put_smstate(u64, buf, offset + 8, seg.base); 9465 } 9466 #endif 9467 9468 static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf) 9469 { 9470 struct desc_ptr dt; 9471 struct kvm_segment seg; 9472 unsigned long val; 9473 int i; 9474 9475 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu)); 9476 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu)); 9477 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu)); 9478 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu)); 9479 9480 for (i = 0; i < 8; i++) 9481 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read_raw(vcpu, i)); 9482 9483 kvm_get_dr(vcpu, 6, &val); 9484 put_smstate(u32, buf, 0x7fcc, (u32)val); 9485 kvm_get_dr(vcpu, 7, &val); 9486 put_smstate(u32, buf, 0x7fc8, (u32)val); 9487 9488 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); 9489 put_smstate(u32, buf, 0x7fc4, seg.selector); 9490 put_smstate(u32, buf, 0x7f64, seg.base); 9491 put_smstate(u32, buf, 0x7f60, seg.limit); 9492 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg)); 9493 9494 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); 9495 put_smstate(u32, buf, 0x7fc0, seg.selector); 9496 put_smstate(u32, buf, 0x7f80, seg.base); 9497 put_smstate(u32, buf, 0x7f7c, seg.limit); 9498 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg)); 9499 9500 static_call(kvm_x86_get_gdt)(vcpu, &dt); 9501 put_smstate(u32, buf, 0x7f74, dt.address); 9502 put_smstate(u32, buf, 0x7f70, dt.size); 9503 9504 static_call(kvm_x86_get_idt)(vcpu, &dt); 9505 put_smstate(u32, buf, 0x7f58, dt.address); 9506 put_smstate(u32, buf, 0x7f54, dt.size); 9507 9508 for (i = 0; i < 6; i++) 9509 enter_smm_save_seg_32(vcpu, buf, i); 9510 9511 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu)); 9512 9513 /* revision id */ 9514 put_smstate(u32, buf, 0x7efc, 0x00020000); 9515 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase); 9516 } 9517 9518 #ifdef CONFIG_X86_64 9519 static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf) 9520 { 9521 struct desc_ptr dt; 9522 struct kvm_segment seg; 9523 unsigned long val; 9524 int i; 9525 9526 for (i = 0; i < 16; i++) 9527 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read_raw(vcpu, i)); 9528 9529 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu)); 9530 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu)); 9531 9532 kvm_get_dr(vcpu, 6, &val); 9533 put_smstate(u64, buf, 0x7f68, val); 9534 kvm_get_dr(vcpu, 7, &val); 9535 put_smstate(u64, buf, 0x7f60, val); 9536 9537 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu)); 9538 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu)); 9539 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu)); 9540 9541 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase); 9542 9543 /* revision id */ 9544 put_smstate(u32, buf, 0x7efc, 0x00020064); 9545 9546 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer); 9547 9548 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); 9549 put_smstate(u16, buf, 0x7e90, seg.selector); 9550 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8); 9551 put_smstate(u32, buf, 0x7e94, seg.limit); 9552 put_smstate(u64, buf, 0x7e98, seg.base); 9553 9554 static_call(kvm_x86_get_idt)(vcpu, &dt); 9555 put_smstate(u32, buf, 0x7e84, dt.size); 9556 put_smstate(u64, buf, 0x7e88, dt.address); 9557 9558 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); 9559 put_smstate(u16, buf, 0x7e70, seg.selector); 9560 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8); 9561 put_smstate(u32, buf, 0x7e74, seg.limit); 9562 put_smstate(u64, buf, 0x7e78, seg.base); 9563 9564 static_call(kvm_x86_get_gdt)(vcpu, &dt); 9565 put_smstate(u32, buf, 0x7e64, dt.size); 9566 put_smstate(u64, buf, 0x7e68, dt.address); 9567 9568 for (i = 0; i < 6; i++) 9569 enter_smm_save_seg_64(vcpu, buf, i); 9570 } 9571 #endif 9572 9573 static void enter_smm(struct kvm_vcpu *vcpu) 9574 { 9575 struct kvm_segment cs, ds; 9576 struct desc_ptr dt; 9577 unsigned long cr0; 9578 char buf[512]; 9579 9580 memset(buf, 0, 512); 9581 #ifdef CONFIG_X86_64 9582 if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) 9583 enter_smm_save_state_64(vcpu, buf); 9584 else 9585 #endif 9586 enter_smm_save_state_32(vcpu, buf); 9587 9588 /* 9589 * Give enter_smm() a chance to make ISA-specific changes to the vCPU 9590 * state (e.g. leave guest mode) after we've saved the state into the 9591 * SMM state-save area. 9592 */ 9593 static_call(kvm_x86_enter_smm)(vcpu, buf); 9594 9595 kvm_smm_changed(vcpu, true); 9596 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf)); 9597 9598 if (static_call(kvm_x86_get_nmi_mask)(vcpu)) 9599 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; 9600 else 9601 static_call(kvm_x86_set_nmi_mask)(vcpu, true); 9602 9603 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED); 9604 kvm_rip_write(vcpu, 0x8000); 9605 9606 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG); 9607 static_call(kvm_x86_set_cr0)(vcpu, cr0); 9608 vcpu->arch.cr0 = cr0; 9609 9610 static_call(kvm_x86_set_cr4)(vcpu, 0); 9611 9612 /* Undocumented: IDT limit is set to zero on entry to SMM. */ 9613 dt.address = dt.size = 0; 9614 static_call(kvm_x86_set_idt)(vcpu, &dt); 9615 9616 kvm_set_dr(vcpu, 7, DR7_FIXED_1); 9617 9618 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff; 9619 cs.base = vcpu->arch.smbase; 9620 9621 ds.selector = 0; 9622 ds.base = 0; 9623 9624 cs.limit = ds.limit = 0xffffffff; 9625 cs.type = ds.type = 0x3; 9626 cs.dpl = ds.dpl = 0; 9627 cs.db = ds.db = 0; 9628 cs.s = ds.s = 1; 9629 cs.l = ds.l = 0; 9630 cs.g = ds.g = 1; 9631 cs.avl = ds.avl = 0; 9632 cs.present = ds.present = 1; 9633 cs.unusable = ds.unusable = 0; 9634 cs.padding = ds.padding = 0; 9635 9636 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); 9637 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS); 9638 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES); 9639 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS); 9640 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS); 9641 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS); 9642 9643 #ifdef CONFIG_X86_64 9644 if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) 9645 static_call(kvm_x86_set_efer)(vcpu, 0); 9646 #endif 9647 9648 kvm_update_cpuid_runtime(vcpu); 9649 kvm_mmu_reset_context(vcpu); 9650 } 9651 9652 static void process_smi(struct kvm_vcpu *vcpu) 9653 { 9654 vcpu->arch.smi_pending = true; 9655 kvm_make_request(KVM_REQ_EVENT, vcpu); 9656 } 9657 9658 void kvm_make_scan_ioapic_request_mask(struct kvm *kvm, 9659 unsigned long *vcpu_bitmap) 9660 { 9661 kvm_make_vcpus_request_mask(kvm, KVM_REQ_SCAN_IOAPIC, vcpu_bitmap); 9662 } 9663 9664 void kvm_make_scan_ioapic_request(struct kvm *kvm) 9665 { 9666 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC); 9667 } 9668 9669 void kvm_vcpu_update_apicv(struct kvm_vcpu *vcpu) 9670 { 9671 bool activate; 9672 9673 if (!lapic_in_kernel(vcpu)) 9674 return; 9675 9676 down_read(&vcpu->kvm->arch.apicv_update_lock); 9677 9678 activate = kvm_apicv_activated(vcpu->kvm); 9679 if (vcpu->arch.apicv_active == activate) 9680 goto out; 9681 9682 vcpu->arch.apicv_active = activate; 9683 kvm_apic_update_apicv(vcpu); 9684 static_call(kvm_x86_refresh_apicv_exec_ctrl)(vcpu); 9685 9686 /* 9687 * When APICv gets disabled, we may still have injected interrupts 9688 * pending. At the same time, KVM_REQ_EVENT may not be set as APICv was 9689 * still active when the interrupt got accepted. Make sure 9690 * inject_pending_event() is called to check for that. 9691 */ 9692 if (!vcpu->arch.apicv_active) 9693 kvm_make_request(KVM_REQ_EVENT, vcpu); 9694 9695 out: 9696 up_read(&vcpu->kvm->arch.apicv_update_lock); 9697 } 9698 EXPORT_SYMBOL_GPL(kvm_vcpu_update_apicv); 9699 9700 void __kvm_request_apicv_update(struct kvm *kvm, bool activate, ulong bit) 9701 { 9702 unsigned long old, new; 9703 9704 lockdep_assert_held_write(&kvm->arch.apicv_update_lock); 9705 9706 if (!static_call(kvm_x86_check_apicv_inhibit_reasons)(bit)) 9707 return; 9708 9709 old = new = kvm->arch.apicv_inhibit_reasons; 9710 9711 if (activate) 9712 __clear_bit(bit, &new); 9713 else 9714 __set_bit(bit, &new); 9715 9716 if (!!old != !!new) { 9717 trace_kvm_apicv_update_request(activate, bit); 9718 /* 9719 * Kick all vCPUs before setting apicv_inhibit_reasons to avoid 9720 * false positives in the sanity check WARN in svm_vcpu_run(). 9721 * This task will wait for all vCPUs to ack the kick IRQ before 9722 * updating apicv_inhibit_reasons, and all other vCPUs will 9723 * block on acquiring apicv_update_lock so that vCPUs can't 9724 * redo svm_vcpu_run() without seeing the new inhibit state. 9725 * 9726 * Note, holding apicv_update_lock and taking it in the read 9727 * side (handling the request) also prevents other vCPUs from 9728 * servicing the request with a stale apicv_inhibit_reasons. 9729 */ 9730 kvm_make_all_cpus_request(kvm, KVM_REQ_APICV_UPDATE); 9731 kvm->arch.apicv_inhibit_reasons = new; 9732 if (new) { 9733 unsigned long gfn = gpa_to_gfn(APIC_DEFAULT_PHYS_BASE); 9734 kvm_zap_gfn_range(kvm, gfn, gfn+1); 9735 } 9736 } else 9737 kvm->arch.apicv_inhibit_reasons = new; 9738 } 9739 9740 void kvm_request_apicv_update(struct kvm *kvm, bool activate, ulong bit) 9741 { 9742 if (!enable_apicv) 9743 return; 9744 9745 down_write(&kvm->arch.apicv_update_lock); 9746 __kvm_request_apicv_update(kvm, activate, bit); 9747 up_write(&kvm->arch.apicv_update_lock); 9748 } 9749 EXPORT_SYMBOL_GPL(kvm_request_apicv_update); 9750 9751 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu) 9752 { 9753 if (!kvm_apic_present(vcpu)) 9754 return; 9755 9756 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256); 9757 9758 if (irqchip_split(vcpu->kvm)) 9759 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors); 9760 else { 9761 static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu); 9762 if (ioapic_in_kernel(vcpu->kvm)) 9763 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors); 9764 } 9765 9766 if (is_guest_mode(vcpu)) 9767 vcpu->arch.load_eoi_exitmap_pending = true; 9768 else 9769 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu); 9770 } 9771 9772 static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu) 9773 { 9774 u64 eoi_exit_bitmap[4]; 9775 9776 if (!kvm_apic_hw_enabled(vcpu->arch.apic)) 9777 return; 9778 9779 if (to_hv_vcpu(vcpu)) { 9780 bitmap_or((ulong *)eoi_exit_bitmap, 9781 vcpu->arch.ioapic_handled_vectors, 9782 to_hv_synic(vcpu)->vec_bitmap, 256); 9783 static_call_cond(kvm_x86_load_eoi_exitmap)(vcpu, eoi_exit_bitmap); 9784 return; 9785 } 9786 9787 static_call_cond(kvm_x86_load_eoi_exitmap)( 9788 vcpu, (u64 *)vcpu->arch.ioapic_handled_vectors); 9789 } 9790 9791 void kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm, 9792 unsigned long start, unsigned long end) 9793 { 9794 unsigned long apic_address; 9795 9796 /* 9797 * The physical address of apic access page is stored in the VMCS. 9798 * Update it when it becomes invalid. 9799 */ 9800 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); 9801 if (start <= apic_address && apic_address < end) 9802 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD); 9803 } 9804 9805 static void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu) 9806 { 9807 if (!lapic_in_kernel(vcpu)) 9808 return; 9809 9810 static_call_cond(kvm_x86_set_apic_access_page_addr)(vcpu); 9811 } 9812 9813 void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu) 9814 { 9815 smp_send_reschedule(vcpu->cpu); 9816 } 9817 EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit); 9818 9819 /* 9820 * Returns 1 to let vcpu_run() continue the guest execution loop without 9821 * exiting to the userspace. Otherwise, the value will be returned to the 9822 * userspace. 9823 */ 9824 static int vcpu_enter_guest(struct kvm_vcpu *vcpu) 9825 { 9826 int r; 9827 bool req_int_win = 9828 dm_request_for_irq_injection(vcpu) && 9829 kvm_cpu_accept_dm_intr(vcpu); 9830 fastpath_t exit_fastpath; 9831 9832 bool req_immediate_exit = false; 9833 9834 /* Forbid vmenter if vcpu dirty ring is soft-full */ 9835 if (unlikely(vcpu->kvm->dirty_ring_size && 9836 kvm_dirty_ring_soft_full(&vcpu->dirty_ring))) { 9837 vcpu->run->exit_reason = KVM_EXIT_DIRTY_RING_FULL; 9838 trace_kvm_dirty_ring_exit(vcpu); 9839 r = 0; 9840 goto out; 9841 } 9842 9843 if (kvm_request_pending(vcpu)) { 9844 if (kvm_check_request(KVM_REQ_VM_DEAD, vcpu)) { 9845 r = -EIO; 9846 goto out; 9847 } 9848 if (kvm_check_request(KVM_REQ_GET_NESTED_STATE_PAGES, vcpu)) { 9849 if (unlikely(!kvm_x86_ops.nested_ops->get_nested_state_pages(vcpu))) { 9850 r = 0; 9851 goto out; 9852 } 9853 } 9854 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu)) 9855 kvm_mmu_unload(vcpu); 9856 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu)) 9857 __kvm_migrate_timers(vcpu); 9858 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu)) 9859 kvm_update_masterclock(vcpu->kvm); 9860 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu)) 9861 kvm_gen_kvmclock_update(vcpu); 9862 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) { 9863 r = kvm_guest_time_update(vcpu); 9864 if (unlikely(r)) 9865 goto out; 9866 } 9867 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu)) 9868 kvm_mmu_sync_roots(vcpu); 9869 if (kvm_check_request(KVM_REQ_LOAD_MMU_PGD, vcpu)) 9870 kvm_mmu_load_pgd(vcpu); 9871 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) { 9872 kvm_vcpu_flush_tlb_all(vcpu); 9873 9874 /* Flushing all ASIDs flushes the current ASID... */ 9875 kvm_clear_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); 9876 } 9877 kvm_service_local_tlb_flush_requests(vcpu); 9878 9879 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) { 9880 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS; 9881 r = 0; 9882 goto out; 9883 } 9884 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) { 9885 if (is_guest_mode(vcpu)) { 9886 kvm_x86_ops.nested_ops->triple_fault(vcpu); 9887 } else { 9888 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; 9889 vcpu->mmio_needed = 0; 9890 r = 0; 9891 goto out; 9892 } 9893 } 9894 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) { 9895 /* Page is swapped out. Do synthetic halt */ 9896 vcpu->arch.apf.halted = true; 9897 r = 1; 9898 goto out; 9899 } 9900 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu)) 9901 record_steal_time(vcpu); 9902 if (kvm_check_request(KVM_REQ_SMI, vcpu)) 9903 process_smi(vcpu); 9904 if (kvm_check_request(KVM_REQ_NMI, vcpu)) 9905 process_nmi(vcpu); 9906 if (kvm_check_request(KVM_REQ_PMU, vcpu)) 9907 kvm_pmu_handle_event(vcpu); 9908 if (kvm_check_request(KVM_REQ_PMI, vcpu)) 9909 kvm_pmu_deliver_pmi(vcpu); 9910 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) { 9911 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255); 9912 if (test_bit(vcpu->arch.pending_ioapic_eoi, 9913 vcpu->arch.ioapic_handled_vectors)) { 9914 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI; 9915 vcpu->run->eoi.vector = 9916 vcpu->arch.pending_ioapic_eoi; 9917 r = 0; 9918 goto out; 9919 } 9920 } 9921 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu)) 9922 vcpu_scan_ioapic(vcpu); 9923 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu)) 9924 vcpu_load_eoi_exitmap(vcpu); 9925 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu)) 9926 kvm_vcpu_reload_apic_access_page(vcpu); 9927 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) { 9928 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; 9929 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH; 9930 r = 0; 9931 goto out; 9932 } 9933 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) { 9934 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; 9935 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET; 9936 r = 0; 9937 goto out; 9938 } 9939 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) { 9940 struct kvm_vcpu_hv *hv_vcpu = to_hv_vcpu(vcpu); 9941 9942 vcpu->run->exit_reason = KVM_EXIT_HYPERV; 9943 vcpu->run->hyperv = hv_vcpu->exit; 9944 r = 0; 9945 goto out; 9946 } 9947 9948 /* 9949 * KVM_REQ_HV_STIMER has to be processed after 9950 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers 9951 * depend on the guest clock being up-to-date 9952 */ 9953 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu)) 9954 kvm_hv_process_stimers(vcpu); 9955 if (kvm_check_request(KVM_REQ_APICV_UPDATE, vcpu)) 9956 kvm_vcpu_update_apicv(vcpu); 9957 if (kvm_check_request(KVM_REQ_APF_READY, vcpu)) 9958 kvm_check_async_pf_completion(vcpu); 9959 if (kvm_check_request(KVM_REQ_MSR_FILTER_CHANGED, vcpu)) 9960 static_call(kvm_x86_msr_filter_changed)(vcpu); 9961 9962 if (kvm_check_request(KVM_REQ_UPDATE_CPU_DIRTY_LOGGING, vcpu)) 9963 static_call(kvm_x86_update_cpu_dirty_logging)(vcpu); 9964 } 9965 9966 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win || 9967 kvm_xen_has_interrupt(vcpu)) { 9968 ++vcpu->stat.req_event; 9969 r = kvm_apic_accept_events(vcpu); 9970 if (r < 0) { 9971 r = 0; 9972 goto out; 9973 } 9974 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) { 9975 r = 1; 9976 goto out; 9977 } 9978 9979 r = inject_pending_event(vcpu, &req_immediate_exit); 9980 if (r < 0) { 9981 r = 0; 9982 goto out; 9983 } 9984 if (req_int_win) 9985 static_call(kvm_x86_enable_irq_window)(vcpu); 9986 9987 if (kvm_lapic_enabled(vcpu)) { 9988 update_cr8_intercept(vcpu); 9989 kvm_lapic_sync_to_vapic(vcpu); 9990 } 9991 } 9992 9993 r = kvm_mmu_reload(vcpu); 9994 if (unlikely(r)) { 9995 goto cancel_injection; 9996 } 9997 9998 preempt_disable(); 9999 10000 static_call(kvm_x86_prepare_switch_to_guest)(vcpu); 10001 10002 /* 10003 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt 10004 * IPI are then delayed after guest entry, which ensures that they 10005 * result in virtual interrupt delivery. 10006 */ 10007 local_irq_disable(); 10008 10009 /* Store vcpu->apicv_active before vcpu->mode. */ 10010 smp_store_release(&vcpu->mode, IN_GUEST_MODE); 10011 10012 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); 10013 10014 /* 10015 * 1) We should set ->mode before checking ->requests. Please see 10016 * the comment in kvm_vcpu_exiting_guest_mode(). 10017 * 10018 * 2) For APICv, we should set ->mode before checking PID.ON. This 10019 * pairs with the memory barrier implicit in pi_test_and_set_on 10020 * (see vmx_deliver_posted_interrupt). 10021 * 10022 * 3) This also orders the write to mode from any reads to the page 10023 * tables done while the VCPU is running. Please see the comment 10024 * in kvm_flush_remote_tlbs. 10025 */ 10026 smp_mb__after_srcu_read_unlock(); 10027 10028 /* 10029 * Process pending posted interrupts to handle the case where the 10030 * notification IRQ arrived in the host, or was never sent (because the 10031 * target vCPU wasn't running). Do this regardless of the vCPU's APICv 10032 * status, KVM doesn't update assigned devices when APICv is inhibited, 10033 * i.e. they can post interrupts even if APICv is temporarily disabled. 10034 */ 10035 if (kvm_lapic_enabled(vcpu)) 10036 static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu); 10037 10038 if (kvm_vcpu_exit_request(vcpu)) { 10039 vcpu->mode = OUTSIDE_GUEST_MODE; 10040 smp_wmb(); 10041 local_irq_enable(); 10042 preempt_enable(); 10043 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 10044 r = 1; 10045 goto cancel_injection; 10046 } 10047 10048 if (req_immediate_exit) { 10049 kvm_make_request(KVM_REQ_EVENT, vcpu); 10050 static_call(kvm_x86_request_immediate_exit)(vcpu); 10051 } 10052 10053 fpregs_assert_state_consistent(); 10054 if (test_thread_flag(TIF_NEED_FPU_LOAD)) 10055 switch_fpu_return(); 10056 10057 if (vcpu->arch.guest_fpu.xfd_err) 10058 wrmsrl(MSR_IA32_XFD_ERR, vcpu->arch.guest_fpu.xfd_err); 10059 10060 if (unlikely(vcpu->arch.switch_db_regs)) { 10061 set_debugreg(0, 7); 10062 set_debugreg(vcpu->arch.eff_db[0], 0); 10063 set_debugreg(vcpu->arch.eff_db[1], 1); 10064 set_debugreg(vcpu->arch.eff_db[2], 2); 10065 set_debugreg(vcpu->arch.eff_db[3], 3); 10066 } else if (unlikely(hw_breakpoint_active())) { 10067 set_debugreg(0, 7); 10068 } 10069 10070 guest_timing_enter_irqoff(); 10071 10072 for (;;) { 10073 /* 10074 * Assert that vCPU vs. VM APICv state is consistent. An APICv 10075 * update must kick and wait for all vCPUs before toggling the 10076 * per-VM state, and responsing vCPUs must wait for the update 10077 * to complete before servicing KVM_REQ_APICV_UPDATE. 10078 */ 10079 WARN_ON_ONCE(kvm_apicv_activated(vcpu->kvm) != kvm_vcpu_apicv_active(vcpu)); 10080 10081 exit_fastpath = static_call(kvm_x86_vcpu_run)(vcpu); 10082 if (likely(exit_fastpath != EXIT_FASTPATH_REENTER_GUEST)) 10083 break; 10084 10085 if (kvm_lapic_enabled(vcpu)) 10086 static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu); 10087 10088 if (unlikely(kvm_vcpu_exit_request(vcpu))) { 10089 exit_fastpath = EXIT_FASTPATH_EXIT_HANDLED; 10090 break; 10091 } 10092 } 10093 10094 /* 10095 * Do this here before restoring debug registers on the host. And 10096 * since we do this before handling the vmexit, a DR access vmexit 10097 * can (a) read the correct value of the debug registers, (b) set 10098 * KVM_DEBUGREG_WONT_EXIT again. 10099 */ 10100 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) { 10101 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP); 10102 static_call(kvm_x86_sync_dirty_debug_regs)(vcpu); 10103 kvm_update_dr0123(vcpu); 10104 kvm_update_dr7(vcpu); 10105 } 10106 10107 /* 10108 * If the guest has used debug registers, at least dr7 10109 * will be disabled while returning to the host. 10110 * If we don't have active breakpoints in the host, we don't 10111 * care about the messed up debug address registers. But if 10112 * we have some of them active, restore the old state. 10113 */ 10114 if (hw_breakpoint_active()) 10115 hw_breakpoint_restore(); 10116 10117 vcpu->arch.last_vmentry_cpu = vcpu->cpu; 10118 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc()); 10119 10120 vcpu->mode = OUTSIDE_GUEST_MODE; 10121 smp_wmb(); 10122 10123 /* 10124 * Sync xfd before calling handle_exit_irqoff() which may 10125 * rely on the fact that guest_fpu::xfd is up-to-date (e.g. 10126 * in #NM irqoff handler). 10127 */ 10128 if (vcpu->arch.xfd_no_write_intercept) 10129 fpu_sync_guest_vmexit_xfd_state(); 10130 10131 static_call(kvm_x86_handle_exit_irqoff)(vcpu); 10132 10133 if (vcpu->arch.guest_fpu.xfd_err) 10134 wrmsrl(MSR_IA32_XFD_ERR, 0); 10135 10136 /* 10137 * Consume any pending interrupts, including the possible source of 10138 * VM-Exit on SVM and any ticks that occur between VM-Exit and now. 10139 * An instruction is required after local_irq_enable() to fully unblock 10140 * interrupts on processors that implement an interrupt shadow, the 10141 * stat.exits increment will do nicely. 10142 */ 10143 kvm_before_interrupt(vcpu, KVM_HANDLING_IRQ); 10144 local_irq_enable(); 10145 ++vcpu->stat.exits; 10146 local_irq_disable(); 10147 kvm_after_interrupt(vcpu); 10148 10149 /* 10150 * Wait until after servicing IRQs to account guest time so that any 10151 * ticks that occurred while running the guest are properly accounted 10152 * to the guest. Waiting until IRQs are enabled degrades the accuracy 10153 * of accounting via context tracking, but the loss of accuracy is 10154 * acceptable for all known use cases. 10155 */ 10156 guest_timing_exit_irqoff(); 10157 10158 if (lapic_in_kernel(vcpu)) { 10159 s64 delta = vcpu->arch.apic->lapic_timer.advance_expire_delta; 10160 if (delta != S64_MIN) { 10161 trace_kvm_wait_lapic_expire(vcpu->vcpu_id, delta); 10162 vcpu->arch.apic->lapic_timer.advance_expire_delta = S64_MIN; 10163 } 10164 } 10165 10166 local_irq_enable(); 10167 preempt_enable(); 10168 10169 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 10170 10171 /* 10172 * Profile KVM exit RIPs: 10173 */ 10174 if (unlikely(prof_on == KVM_PROFILING)) { 10175 unsigned long rip = kvm_rip_read(vcpu); 10176 profile_hit(KVM_PROFILING, (void *)rip); 10177 } 10178 10179 if (unlikely(vcpu->arch.tsc_always_catchup)) 10180 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 10181 10182 if (vcpu->arch.apic_attention) 10183 kvm_lapic_sync_from_vapic(vcpu); 10184 10185 r = static_call(kvm_x86_handle_exit)(vcpu, exit_fastpath); 10186 return r; 10187 10188 cancel_injection: 10189 if (req_immediate_exit) 10190 kvm_make_request(KVM_REQ_EVENT, vcpu); 10191 static_call(kvm_x86_cancel_injection)(vcpu); 10192 if (unlikely(vcpu->arch.apic_attention)) 10193 kvm_lapic_sync_from_vapic(vcpu); 10194 out: 10195 return r; 10196 } 10197 10198 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu) 10199 { 10200 bool hv_timer; 10201 10202 if (!kvm_arch_vcpu_runnable(vcpu)) { 10203 /* 10204 * Switch to the software timer before halt-polling/blocking as 10205 * the guest's timer may be a break event for the vCPU, and the 10206 * hypervisor timer runs only when the CPU is in guest mode. 10207 * Switch before halt-polling so that KVM recognizes an expired 10208 * timer before blocking. 10209 */ 10210 hv_timer = kvm_lapic_hv_timer_in_use(vcpu); 10211 if (hv_timer) 10212 kvm_lapic_switch_to_sw_timer(vcpu); 10213 10214 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 10215 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED) 10216 kvm_vcpu_halt(vcpu); 10217 else 10218 kvm_vcpu_block(vcpu); 10219 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 10220 10221 if (hv_timer) 10222 kvm_lapic_switch_to_hv_timer(vcpu); 10223 10224 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu)) 10225 return 1; 10226 } 10227 10228 if (kvm_apic_accept_events(vcpu) < 0) 10229 return 0; 10230 switch(vcpu->arch.mp_state) { 10231 case KVM_MP_STATE_HALTED: 10232 case KVM_MP_STATE_AP_RESET_HOLD: 10233 vcpu->arch.pv.pv_unhalted = false; 10234 vcpu->arch.mp_state = 10235 KVM_MP_STATE_RUNNABLE; 10236 fallthrough; 10237 case KVM_MP_STATE_RUNNABLE: 10238 vcpu->arch.apf.halted = false; 10239 break; 10240 case KVM_MP_STATE_INIT_RECEIVED: 10241 break; 10242 default: 10243 return -EINTR; 10244 } 10245 return 1; 10246 } 10247 10248 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu) 10249 { 10250 if (is_guest_mode(vcpu)) 10251 kvm_check_nested_events(vcpu); 10252 10253 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE && 10254 !vcpu->arch.apf.halted); 10255 } 10256 10257 static int vcpu_run(struct kvm_vcpu *vcpu) 10258 { 10259 int r; 10260 struct kvm *kvm = vcpu->kvm; 10261 10262 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 10263 vcpu->arch.l1tf_flush_l1d = true; 10264 10265 for (;;) { 10266 if (kvm_vcpu_running(vcpu)) { 10267 r = vcpu_enter_guest(vcpu); 10268 } else { 10269 r = vcpu_block(kvm, vcpu); 10270 } 10271 10272 if (r <= 0) 10273 break; 10274 10275 kvm_clear_request(KVM_REQ_UNBLOCK, vcpu); 10276 if (kvm_cpu_has_pending_timer(vcpu)) 10277 kvm_inject_pending_timer_irqs(vcpu); 10278 10279 if (dm_request_for_irq_injection(vcpu) && 10280 kvm_vcpu_ready_for_interrupt_injection(vcpu)) { 10281 r = 0; 10282 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; 10283 ++vcpu->stat.request_irq_exits; 10284 break; 10285 } 10286 10287 if (__xfer_to_guest_mode_work_pending()) { 10288 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 10289 r = xfer_to_guest_mode_handle_work(vcpu); 10290 if (r) 10291 return r; 10292 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 10293 } 10294 } 10295 10296 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 10297 10298 return r; 10299 } 10300 10301 static inline int complete_emulated_io(struct kvm_vcpu *vcpu) 10302 { 10303 int r; 10304 10305 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 10306 r = kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE); 10307 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); 10308 return r; 10309 } 10310 10311 static int complete_emulated_pio(struct kvm_vcpu *vcpu) 10312 { 10313 BUG_ON(!vcpu->arch.pio.count); 10314 10315 return complete_emulated_io(vcpu); 10316 } 10317 10318 /* 10319 * Implements the following, as a state machine: 10320 * 10321 * read: 10322 * for each fragment 10323 * for each mmio piece in the fragment 10324 * write gpa, len 10325 * exit 10326 * copy data 10327 * execute insn 10328 * 10329 * write: 10330 * for each fragment 10331 * for each mmio piece in the fragment 10332 * write gpa, len 10333 * copy data 10334 * exit 10335 */ 10336 static int complete_emulated_mmio(struct kvm_vcpu *vcpu) 10337 { 10338 struct kvm_run *run = vcpu->run; 10339 struct kvm_mmio_fragment *frag; 10340 unsigned len; 10341 10342 BUG_ON(!vcpu->mmio_needed); 10343 10344 /* Complete previous fragment */ 10345 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment]; 10346 len = min(8u, frag->len); 10347 if (!vcpu->mmio_is_write) 10348 memcpy(frag->data, run->mmio.data, len); 10349 10350 if (frag->len <= 8) { 10351 /* Switch to the next fragment. */ 10352 frag++; 10353 vcpu->mmio_cur_fragment++; 10354 } else { 10355 /* Go forward to the next mmio piece. */ 10356 frag->data += len; 10357 frag->gpa += len; 10358 frag->len -= len; 10359 } 10360 10361 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) { 10362 vcpu->mmio_needed = 0; 10363 10364 /* FIXME: return into emulator if single-stepping. */ 10365 if (vcpu->mmio_is_write) 10366 return 1; 10367 vcpu->mmio_read_completed = 1; 10368 return complete_emulated_io(vcpu); 10369 } 10370 10371 run->exit_reason = KVM_EXIT_MMIO; 10372 run->mmio.phys_addr = frag->gpa; 10373 if (vcpu->mmio_is_write) 10374 memcpy(run->mmio.data, frag->data, min(8u, frag->len)); 10375 run->mmio.len = min(8u, frag->len); 10376 run->mmio.is_write = vcpu->mmio_is_write; 10377 vcpu->arch.complete_userspace_io = complete_emulated_mmio; 10378 return 0; 10379 } 10380 10381 /* Swap (qemu) user FPU context for the guest FPU context. */ 10382 static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu) 10383 { 10384 /* Exclude PKRU, it's restored separately immediately after VM-Exit. */ 10385 fpu_swap_kvm_fpstate(&vcpu->arch.guest_fpu, true); 10386 trace_kvm_fpu(1); 10387 } 10388 10389 /* When vcpu_run ends, restore user space FPU context. */ 10390 static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu) 10391 { 10392 fpu_swap_kvm_fpstate(&vcpu->arch.guest_fpu, false); 10393 ++vcpu->stat.fpu_reload; 10394 trace_kvm_fpu(0); 10395 } 10396 10397 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu) 10398 { 10399 struct kvm_run *kvm_run = vcpu->run; 10400 int r; 10401 10402 vcpu_load(vcpu); 10403 kvm_sigset_activate(vcpu); 10404 kvm_run->flags = 0; 10405 kvm_load_guest_fpu(vcpu); 10406 10407 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) { 10408 if (kvm_run->immediate_exit) { 10409 r = -EINTR; 10410 goto out; 10411 } 10412 /* 10413 * It should be impossible for the hypervisor timer to be in 10414 * use before KVM has ever run the vCPU. 10415 */ 10416 WARN_ON_ONCE(kvm_lapic_hv_timer_in_use(vcpu)); 10417 kvm_vcpu_block(vcpu); 10418 if (kvm_apic_accept_events(vcpu) < 0) { 10419 r = 0; 10420 goto out; 10421 } 10422 kvm_clear_request(KVM_REQ_UNHALT, vcpu); 10423 r = -EAGAIN; 10424 if (signal_pending(current)) { 10425 r = -EINTR; 10426 kvm_run->exit_reason = KVM_EXIT_INTR; 10427 ++vcpu->stat.signal_exits; 10428 } 10429 goto out; 10430 } 10431 10432 if ((kvm_run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) || 10433 (kvm_run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)) { 10434 r = -EINVAL; 10435 goto out; 10436 } 10437 10438 if (kvm_run->kvm_dirty_regs) { 10439 r = sync_regs(vcpu); 10440 if (r != 0) 10441 goto out; 10442 } 10443 10444 /* re-sync apic's tpr */ 10445 if (!lapic_in_kernel(vcpu)) { 10446 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) { 10447 r = -EINVAL; 10448 goto out; 10449 } 10450 } 10451 10452 if (unlikely(vcpu->arch.complete_userspace_io)) { 10453 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io; 10454 vcpu->arch.complete_userspace_io = NULL; 10455 r = cui(vcpu); 10456 if (r <= 0) 10457 goto out; 10458 } else 10459 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed); 10460 10461 if (kvm_run->immediate_exit) { 10462 r = -EINTR; 10463 goto out; 10464 } 10465 10466 r = static_call(kvm_x86_vcpu_pre_run)(vcpu); 10467 if (r <= 0) 10468 goto out; 10469 10470 r = vcpu_run(vcpu); 10471 10472 out: 10473 kvm_put_guest_fpu(vcpu); 10474 if (kvm_run->kvm_valid_regs) 10475 store_regs(vcpu); 10476 post_kvm_run_save(vcpu); 10477 kvm_sigset_deactivate(vcpu); 10478 10479 vcpu_put(vcpu); 10480 return r; 10481 } 10482 10483 static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 10484 { 10485 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) { 10486 /* 10487 * We are here if userspace calls get_regs() in the middle of 10488 * instruction emulation. Registers state needs to be copied 10489 * back from emulation context to vcpu. Userspace shouldn't do 10490 * that usually, but some bad designed PV devices (vmware 10491 * backdoor interface) need this to work 10492 */ 10493 emulator_writeback_register_cache(vcpu->arch.emulate_ctxt); 10494 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 10495 } 10496 regs->rax = kvm_rax_read(vcpu); 10497 regs->rbx = kvm_rbx_read(vcpu); 10498 regs->rcx = kvm_rcx_read(vcpu); 10499 regs->rdx = kvm_rdx_read(vcpu); 10500 regs->rsi = kvm_rsi_read(vcpu); 10501 regs->rdi = kvm_rdi_read(vcpu); 10502 regs->rsp = kvm_rsp_read(vcpu); 10503 regs->rbp = kvm_rbp_read(vcpu); 10504 #ifdef CONFIG_X86_64 10505 regs->r8 = kvm_r8_read(vcpu); 10506 regs->r9 = kvm_r9_read(vcpu); 10507 regs->r10 = kvm_r10_read(vcpu); 10508 regs->r11 = kvm_r11_read(vcpu); 10509 regs->r12 = kvm_r12_read(vcpu); 10510 regs->r13 = kvm_r13_read(vcpu); 10511 regs->r14 = kvm_r14_read(vcpu); 10512 regs->r15 = kvm_r15_read(vcpu); 10513 #endif 10514 10515 regs->rip = kvm_rip_read(vcpu); 10516 regs->rflags = kvm_get_rflags(vcpu); 10517 } 10518 10519 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 10520 { 10521 vcpu_load(vcpu); 10522 __get_regs(vcpu, regs); 10523 vcpu_put(vcpu); 10524 return 0; 10525 } 10526 10527 static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 10528 { 10529 vcpu->arch.emulate_regs_need_sync_from_vcpu = true; 10530 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 10531 10532 kvm_rax_write(vcpu, regs->rax); 10533 kvm_rbx_write(vcpu, regs->rbx); 10534 kvm_rcx_write(vcpu, regs->rcx); 10535 kvm_rdx_write(vcpu, regs->rdx); 10536 kvm_rsi_write(vcpu, regs->rsi); 10537 kvm_rdi_write(vcpu, regs->rdi); 10538 kvm_rsp_write(vcpu, regs->rsp); 10539 kvm_rbp_write(vcpu, regs->rbp); 10540 #ifdef CONFIG_X86_64 10541 kvm_r8_write(vcpu, regs->r8); 10542 kvm_r9_write(vcpu, regs->r9); 10543 kvm_r10_write(vcpu, regs->r10); 10544 kvm_r11_write(vcpu, regs->r11); 10545 kvm_r12_write(vcpu, regs->r12); 10546 kvm_r13_write(vcpu, regs->r13); 10547 kvm_r14_write(vcpu, regs->r14); 10548 kvm_r15_write(vcpu, regs->r15); 10549 #endif 10550 10551 kvm_rip_write(vcpu, regs->rip); 10552 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED); 10553 10554 vcpu->arch.exception.pending = false; 10555 10556 kvm_make_request(KVM_REQ_EVENT, vcpu); 10557 } 10558 10559 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 10560 { 10561 vcpu_load(vcpu); 10562 __set_regs(vcpu, regs); 10563 vcpu_put(vcpu); 10564 return 0; 10565 } 10566 10567 static void __get_sregs_common(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) 10568 { 10569 struct desc_ptr dt; 10570 10571 if (vcpu->arch.guest_state_protected) 10572 goto skip_protected_regs; 10573 10574 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS); 10575 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS); 10576 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES); 10577 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS); 10578 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS); 10579 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS); 10580 10581 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR); 10582 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); 10583 10584 static_call(kvm_x86_get_idt)(vcpu, &dt); 10585 sregs->idt.limit = dt.size; 10586 sregs->idt.base = dt.address; 10587 static_call(kvm_x86_get_gdt)(vcpu, &dt); 10588 sregs->gdt.limit = dt.size; 10589 sregs->gdt.base = dt.address; 10590 10591 sregs->cr2 = vcpu->arch.cr2; 10592 sregs->cr3 = kvm_read_cr3(vcpu); 10593 10594 skip_protected_regs: 10595 sregs->cr0 = kvm_read_cr0(vcpu); 10596 sregs->cr4 = kvm_read_cr4(vcpu); 10597 sregs->cr8 = kvm_get_cr8(vcpu); 10598 sregs->efer = vcpu->arch.efer; 10599 sregs->apic_base = kvm_get_apic_base(vcpu); 10600 } 10601 10602 static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) 10603 { 10604 __get_sregs_common(vcpu, sregs); 10605 10606 if (vcpu->arch.guest_state_protected) 10607 return; 10608 10609 if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft) 10610 set_bit(vcpu->arch.interrupt.nr, 10611 (unsigned long *)sregs->interrupt_bitmap); 10612 } 10613 10614 static void __get_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2) 10615 { 10616 int i; 10617 10618 __get_sregs_common(vcpu, (struct kvm_sregs *)sregs2); 10619 10620 if (vcpu->arch.guest_state_protected) 10621 return; 10622 10623 if (is_pae_paging(vcpu)) { 10624 for (i = 0 ; i < 4 ; i++) 10625 sregs2->pdptrs[i] = kvm_pdptr_read(vcpu, i); 10626 sregs2->flags |= KVM_SREGS2_FLAGS_PDPTRS_VALID; 10627 } 10628 } 10629 10630 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, 10631 struct kvm_sregs *sregs) 10632 { 10633 vcpu_load(vcpu); 10634 __get_sregs(vcpu, sregs); 10635 vcpu_put(vcpu); 10636 return 0; 10637 } 10638 10639 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, 10640 struct kvm_mp_state *mp_state) 10641 { 10642 int r; 10643 10644 vcpu_load(vcpu); 10645 if (kvm_mpx_supported()) 10646 kvm_load_guest_fpu(vcpu); 10647 10648 r = kvm_apic_accept_events(vcpu); 10649 if (r < 0) 10650 goto out; 10651 r = 0; 10652 10653 if ((vcpu->arch.mp_state == KVM_MP_STATE_HALTED || 10654 vcpu->arch.mp_state == KVM_MP_STATE_AP_RESET_HOLD) && 10655 vcpu->arch.pv.pv_unhalted) 10656 mp_state->mp_state = KVM_MP_STATE_RUNNABLE; 10657 else 10658 mp_state->mp_state = vcpu->arch.mp_state; 10659 10660 out: 10661 if (kvm_mpx_supported()) 10662 kvm_put_guest_fpu(vcpu); 10663 vcpu_put(vcpu); 10664 return r; 10665 } 10666 10667 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, 10668 struct kvm_mp_state *mp_state) 10669 { 10670 int ret = -EINVAL; 10671 10672 vcpu_load(vcpu); 10673 10674 if (!lapic_in_kernel(vcpu) && 10675 mp_state->mp_state != KVM_MP_STATE_RUNNABLE) 10676 goto out; 10677 10678 /* 10679 * KVM_MP_STATE_INIT_RECEIVED means the processor is in 10680 * INIT state; latched init should be reported using 10681 * KVM_SET_VCPU_EVENTS, so reject it here. 10682 */ 10683 if ((kvm_vcpu_latch_init(vcpu) || vcpu->arch.smi_pending) && 10684 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED || 10685 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED)) 10686 goto out; 10687 10688 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) { 10689 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED; 10690 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events); 10691 } else 10692 vcpu->arch.mp_state = mp_state->mp_state; 10693 kvm_make_request(KVM_REQ_EVENT, vcpu); 10694 10695 ret = 0; 10696 out: 10697 vcpu_put(vcpu); 10698 return ret; 10699 } 10700 10701 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index, 10702 int reason, bool has_error_code, u32 error_code) 10703 { 10704 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 10705 int ret; 10706 10707 init_emulate_ctxt(vcpu); 10708 10709 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason, 10710 has_error_code, error_code); 10711 if (ret) { 10712 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 10713 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; 10714 vcpu->run->internal.ndata = 0; 10715 return 0; 10716 } 10717 10718 kvm_rip_write(vcpu, ctxt->eip); 10719 kvm_set_rflags(vcpu, ctxt->eflags); 10720 return 1; 10721 } 10722 EXPORT_SYMBOL_GPL(kvm_task_switch); 10723 10724 static bool kvm_is_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) 10725 { 10726 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) { 10727 /* 10728 * When EFER.LME and CR0.PG are set, the processor is in 10729 * 64-bit mode (though maybe in a 32-bit code segment). 10730 * CR4.PAE and EFER.LMA must be set. 10731 */ 10732 if (!(sregs->cr4 & X86_CR4_PAE) || !(sregs->efer & EFER_LMA)) 10733 return false; 10734 if (kvm_vcpu_is_illegal_gpa(vcpu, sregs->cr3)) 10735 return false; 10736 } else { 10737 /* 10738 * Not in 64-bit mode: EFER.LMA is clear and the code 10739 * segment cannot be 64-bit. 10740 */ 10741 if (sregs->efer & EFER_LMA || sregs->cs.l) 10742 return false; 10743 } 10744 10745 return kvm_is_valid_cr4(vcpu, sregs->cr4); 10746 } 10747 10748 static int __set_sregs_common(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs, 10749 int *mmu_reset_needed, bool update_pdptrs) 10750 { 10751 struct msr_data apic_base_msr; 10752 int idx; 10753 struct desc_ptr dt; 10754 10755 if (!kvm_is_valid_sregs(vcpu, sregs)) 10756 return -EINVAL; 10757 10758 apic_base_msr.data = sregs->apic_base; 10759 apic_base_msr.host_initiated = true; 10760 if (kvm_set_apic_base(vcpu, &apic_base_msr)) 10761 return -EINVAL; 10762 10763 if (vcpu->arch.guest_state_protected) 10764 return 0; 10765 10766 dt.size = sregs->idt.limit; 10767 dt.address = sregs->idt.base; 10768 static_call(kvm_x86_set_idt)(vcpu, &dt); 10769 dt.size = sregs->gdt.limit; 10770 dt.address = sregs->gdt.base; 10771 static_call(kvm_x86_set_gdt)(vcpu, &dt); 10772 10773 vcpu->arch.cr2 = sregs->cr2; 10774 *mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3; 10775 vcpu->arch.cr3 = sregs->cr3; 10776 kvm_register_mark_dirty(vcpu, VCPU_EXREG_CR3); 10777 static_call_cond(kvm_x86_post_set_cr3)(vcpu, sregs->cr3); 10778 10779 kvm_set_cr8(vcpu, sregs->cr8); 10780 10781 *mmu_reset_needed |= vcpu->arch.efer != sregs->efer; 10782 static_call(kvm_x86_set_efer)(vcpu, sregs->efer); 10783 10784 *mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0; 10785 static_call(kvm_x86_set_cr0)(vcpu, sregs->cr0); 10786 vcpu->arch.cr0 = sregs->cr0; 10787 10788 *mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4; 10789 static_call(kvm_x86_set_cr4)(vcpu, sregs->cr4); 10790 10791 if (update_pdptrs) { 10792 idx = srcu_read_lock(&vcpu->kvm->srcu); 10793 if (is_pae_paging(vcpu)) { 10794 load_pdptrs(vcpu, kvm_read_cr3(vcpu)); 10795 *mmu_reset_needed = 1; 10796 } 10797 srcu_read_unlock(&vcpu->kvm->srcu, idx); 10798 } 10799 10800 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS); 10801 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS); 10802 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES); 10803 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS); 10804 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS); 10805 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS); 10806 10807 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR); 10808 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); 10809 10810 update_cr8_intercept(vcpu); 10811 10812 /* Older userspace won't unhalt the vcpu on reset. */ 10813 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 && 10814 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 && 10815 !is_protmode(vcpu)) 10816 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 10817 10818 return 0; 10819 } 10820 10821 static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) 10822 { 10823 int pending_vec, max_bits; 10824 int mmu_reset_needed = 0; 10825 int ret = __set_sregs_common(vcpu, sregs, &mmu_reset_needed, true); 10826 10827 if (ret) 10828 return ret; 10829 10830 if (mmu_reset_needed) 10831 kvm_mmu_reset_context(vcpu); 10832 10833 max_bits = KVM_NR_INTERRUPTS; 10834 pending_vec = find_first_bit( 10835 (const unsigned long *)sregs->interrupt_bitmap, max_bits); 10836 10837 if (pending_vec < max_bits) { 10838 kvm_queue_interrupt(vcpu, pending_vec, false); 10839 pr_debug("Set back pending irq %d\n", pending_vec); 10840 kvm_make_request(KVM_REQ_EVENT, vcpu); 10841 } 10842 return 0; 10843 } 10844 10845 static int __set_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2) 10846 { 10847 int mmu_reset_needed = 0; 10848 bool valid_pdptrs = sregs2->flags & KVM_SREGS2_FLAGS_PDPTRS_VALID; 10849 bool pae = (sregs2->cr0 & X86_CR0_PG) && (sregs2->cr4 & X86_CR4_PAE) && 10850 !(sregs2->efer & EFER_LMA); 10851 int i, ret; 10852 10853 if (sregs2->flags & ~KVM_SREGS2_FLAGS_PDPTRS_VALID) 10854 return -EINVAL; 10855 10856 if (valid_pdptrs && (!pae || vcpu->arch.guest_state_protected)) 10857 return -EINVAL; 10858 10859 ret = __set_sregs_common(vcpu, (struct kvm_sregs *)sregs2, 10860 &mmu_reset_needed, !valid_pdptrs); 10861 if (ret) 10862 return ret; 10863 10864 if (valid_pdptrs) { 10865 for (i = 0; i < 4 ; i++) 10866 kvm_pdptr_write(vcpu, i, sregs2->pdptrs[i]); 10867 10868 kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR); 10869 mmu_reset_needed = 1; 10870 vcpu->arch.pdptrs_from_userspace = true; 10871 } 10872 if (mmu_reset_needed) 10873 kvm_mmu_reset_context(vcpu); 10874 return 0; 10875 } 10876 10877 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, 10878 struct kvm_sregs *sregs) 10879 { 10880 int ret; 10881 10882 vcpu_load(vcpu); 10883 ret = __set_sregs(vcpu, sregs); 10884 vcpu_put(vcpu); 10885 return ret; 10886 } 10887 10888 static void kvm_arch_vcpu_guestdbg_update_apicv_inhibit(struct kvm *kvm) 10889 { 10890 bool inhibit = false; 10891 struct kvm_vcpu *vcpu; 10892 unsigned long i; 10893 10894 down_write(&kvm->arch.apicv_update_lock); 10895 10896 kvm_for_each_vcpu(i, vcpu, kvm) { 10897 if (vcpu->guest_debug & KVM_GUESTDBG_BLOCKIRQ) { 10898 inhibit = true; 10899 break; 10900 } 10901 } 10902 __kvm_request_apicv_update(kvm, !inhibit, APICV_INHIBIT_REASON_BLOCKIRQ); 10903 up_write(&kvm->arch.apicv_update_lock); 10904 } 10905 10906 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, 10907 struct kvm_guest_debug *dbg) 10908 { 10909 unsigned long rflags; 10910 int i, r; 10911 10912 if (vcpu->arch.guest_state_protected) 10913 return -EINVAL; 10914 10915 vcpu_load(vcpu); 10916 10917 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) { 10918 r = -EBUSY; 10919 if (vcpu->arch.exception.pending) 10920 goto out; 10921 if (dbg->control & KVM_GUESTDBG_INJECT_DB) 10922 kvm_queue_exception(vcpu, DB_VECTOR); 10923 else 10924 kvm_queue_exception(vcpu, BP_VECTOR); 10925 } 10926 10927 /* 10928 * Read rflags as long as potentially injected trace flags are still 10929 * filtered out. 10930 */ 10931 rflags = kvm_get_rflags(vcpu); 10932 10933 vcpu->guest_debug = dbg->control; 10934 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE)) 10935 vcpu->guest_debug = 0; 10936 10937 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { 10938 for (i = 0; i < KVM_NR_DB_REGS; ++i) 10939 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i]; 10940 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7]; 10941 } else { 10942 for (i = 0; i < KVM_NR_DB_REGS; i++) 10943 vcpu->arch.eff_db[i] = vcpu->arch.db[i]; 10944 } 10945 kvm_update_dr7(vcpu); 10946 10947 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) 10948 vcpu->arch.singlestep_rip = kvm_get_linear_rip(vcpu); 10949 10950 /* 10951 * Trigger an rflags update that will inject or remove the trace 10952 * flags. 10953 */ 10954 kvm_set_rflags(vcpu, rflags); 10955 10956 static_call(kvm_x86_update_exception_bitmap)(vcpu); 10957 10958 kvm_arch_vcpu_guestdbg_update_apicv_inhibit(vcpu->kvm); 10959 10960 r = 0; 10961 10962 out: 10963 vcpu_put(vcpu); 10964 return r; 10965 } 10966 10967 /* 10968 * Translate a guest virtual address to a guest physical address. 10969 */ 10970 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, 10971 struct kvm_translation *tr) 10972 { 10973 unsigned long vaddr = tr->linear_address; 10974 gpa_t gpa; 10975 int idx; 10976 10977 vcpu_load(vcpu); 10978 10979 idx = srcu_read_lock(&vcpu->kvm->srcu); 10980 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL); 10981 srcu_read_unlock(&vcpu->kvm->srcu, idx); 10982 tr->physical_address = gpa; 10983 tr->valid = gpa != UNMAPPED_GVA; 10984 tr->writeable = 1; 10985 tr->usermode = 0; 10986 10987 vcpu_put(vcpu); 10988 return 0; 10989 } 10990 10991 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 10992 { 10993 struct fxregs_state *fxsave; 10994 10995 if (fpstate_is_confidential(&vcpu->arch.guest_fpu)) 10996 return 0; 10997 10998 vcpu_load(vcpu); 10999 11000 fxsave = &vcpu->arch.guest_fpu.fpstate->regs.fxsave; 11001 memcpy(fpu->fpr, fxsave->st_space, 128); 11002 fpu->fcw = fxsave->cwd; 11003 fpu->fsw = fxsave->swd; 11004 fpu->ftwx = fxsave->twd; 11005 fpu->last_opcode = fxsave->fop; 11006 fpu->last_ip = fxsave->rip; 11007 fpu->last_dp = fxsave->rdp; 11008 memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space)); 11009 11010 vcpu_put(vcpu); 11011 return 0; 11012 } 11013 11014 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 11015 { 11016 struct fxregs_state *fxsave; 11017 11018 if (fpstate_is_confidential(&vcpu->arch.guest_fpu)) 11019 return 0; 11020 11021 vcpu_load(vcpu); 11022 11023 fxsave = &vcpu->arch.guest_fpu.fpstate->regs.fxsave; 11024 11025 memcpy(fxsave->st_space, fpu->fpr, 128); 11026 fxsave->cwd = fpu->fcw; 11027 fxsave->swd = fpu->fsw; 11028 fxsave->twd = fpu->ftwx; 11029 fxsave->fop = fpu->last_opcode; 11030 fxsave->rip = fpu->last_ip; 11031 fxsave->rdp = fpu->last_dp; 11032 memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space)); 11033 11034 vcpu_put(vcpu); 11035 return 0; 11036 } 11037 11038 static void store_regs(struct kvm_vcpu *vcpu) 11039 { 11040 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES); 11041 11042 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS) 11043 __get_regs(vcpu, &vcpu->run->s.regs.regs); 11044 11045 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS) 11046 __get_sregs(vcpu, &vcpu->run->s.regs.sregs); 11047 11048 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS) 11049 kvm_vcpu_ioctl_x86_get_vcpu_events( 11050 vcpu, &vcpu->run->s.regs.events); 11051 } 11052 11053 static int sync_regs(struct kvm_vcpu *vcpu) 11054 { 11055 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) { 11056 __set_regs(vcpu, &vcpu->run->s.regs.regs); 11057 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS; 11058 } 11059 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) { 11060 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs)) 11061 return -EINVAL; 11062 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS; 11063 } 11064 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) { 11065 if (kvm_vcpu_ioctl_x86_set_vcpu_events( 11066 vcpu, &vcpu->run->s.regs.events)) 11067 return -EINVAL; 11068 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS; 11069 } 11070 11071 return 0; 11072 } 11073 11074 int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id) 11075 { 11076 if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0) 11077 pr_warn_once("kvm: SMP vm created on host with unstable TSC; " 11078 "guest TSC will not be reliable\n"); 11079 11080 return 0; 11081 } 11082 11083 int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu) 11084 { 11085 struct page *page; 11086 int r; 11087 11088 vcpu->arch.last_vmentry_cpu = -1; 11089 vcpu->arch.regs_avail = ~0; 11090 vcpu->arch.regs_dirty = ~0; 11091 11092 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu)) 11093 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 11094 else 11095 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED; 11096 11097 r = kvm_mmu_create(vcpu); 11098 if (r < 0) 11099 return r; 11100 11101 if (irqchip_in_kernel(vcpu->kvm)) { 11102 r = kvm_create_lapic(vcpu, lapic_timer_advance_ns); 11103 if (r < 0) 11104 goto fail_mmu_destroy; 11105 if (kvm_apicv_activated(vcpu->kvm)) 11106 vcpu->arch.apicv_active = true; 11107 } else 11108 static_branch_inc(&kvm_has_noapic_vcpu); 11109 11110 r = -ENOMEM; 11111 11112 page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO); 11113 if (!page) 11114 goto fail_free_lapic; 11115 vcpu->arch.pio_data = page_address(page); 11116 11117 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4, 11118 GFP_KERNEL_ACCOUNT); 11119 if (!vcpu->arch.mce_banks) 11120 goto fail_free_pio_data; 11121 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS; 11122 11123 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, 11124 GFP_KERNEL_ACCOUNT)) 11125 goto fail_free_mce_banks; 11126 11127 if (!alloc_emulate_ctxt(vcpu)) 11128 goto free_wbinvd_dirty_mask; 11129 11130 if (!fpu_alloc_guest_fpstate(&vcpu->arch.guest_fpu)) { 11131 pr_err("kvm: failed to allocate vcpu's fpu\n"); 11132 goto free_emulate_ctxt; 11133 } 11134 11135 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu); 11136 vcpu->arch.reserved_gpa_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu); 11137 11138 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT; 11139 11140 kvm_async_pf_hash_reset(vcpu); 11141 kvm_pmu_init(vcpu); 11142 11143 vcpu->arch.pending_external_vector = -1; 11144 vcpu->arch.preempted_in_kernel = false; 11145 11146 #if IS_ENABLED(CONFIG_HYPERV) 11147 vcpu->arch.hv_root_tdp = INVALID_PAGE; 11148 #endif 11149 11150 r = static_call(kvm_x86_vcpu_create)(vcpu); 11151 if (r) 11152 goto free_guest_fpu; 11153 11154 vcpu->arch.arch_capabilities = kvm_get_arch_capabilities(); 11155 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT; 11156 kvm_vcpu_mtrr_init(vcpu); 11157 vcpu_load(vcpu); 11158 kvm_set_tsc_khz(vcpu, max_tsc_khz); 11159 kvm_vcpu_reset(vcpu, false); 11160 kvm_init_mmu(vcpu); 11161 vcpu_put(vcpu); 11162 return 0; 11163 11164 free_guest_fpu: 11165 fpu_free_guest_fpstate(&vcpu->arch.guest_fpu); 11166 free_emulate_ctxt: 11167 kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt); 11168 free_wbinvd_dirty_mask: 11169 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); 11170 fail_free_mce_banks: 11171 kfree(vcpu->arch.mce_banks); 11172 fail_free_pio_data: 11173 free_page((unsigned long)vcpu->arch.pio_data); 11174 fail_free_lapic: 11175 kvm_free_lapic(vcpu); 11176 fail_mmu_destroy: 11177 kvm_mmu_destroy(vcpu); 11178 return r; 11179 } 11180 11181 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu) 11182 { 11183 struct kvm *kvm = vcpu->kvm; 11184 11185 if (mutex_lock_killable(&vcpu->mutex)) 11186 return; 11187 vcpu_load(vcpu); 11188 kvm_synchronize_tsc(vcpu, 0); 11189 vcpu_put(vcpu); 11190 11191 /* poll control enabled by default */ 11192 vcpu->arch.msr_kvm_poll_control = 1; 11193 11194 mutex_unlock(&vcpu->mutex); 11195 11196 if (kvmclock_periodic_sync && vcpu->vcpu_idx == 0) 11197 schedule_delayed_work(&kvm->arch.kvmclock_sync_work, 11198 KVMCLOCK_SYNC_PERIOD); 11199 } 11200 11201 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) 11202 { 11203 int idx; 11204 11205 kvmclock_reset(vcpu); 11206 11207 static_call(kvm_x86_vcpu_free)(vcpu); 11208 11209 kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt); 11210 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); 11211 fpu_free_guest_fpstate(&vcpu->arch.guest_fpu); 11212 11213 kvm_hv_vcpu_uninit(vcpu); 11214 kvm_pmu_destroy(vcpu); 11215 kfree(vcpu->arch.mce_banks); 11216 kvm_free_lapic(vcpu); 11217 idx = srcu_read_lock(&vcpu->kvm->srcu); 11218 kvm_mmu_destroy(vcpu); 11219 srcu_read_unlock(&vcpu->kvm->srcu, idx); 11220 free_page((unsigned long)vcpu->arch.pio_data); 11221 kvfree(vcpu->arch.cpuid_entries); 11222 if (!lapic_in_kernel(vcpu)) 11223 static_branch_dec(&kvm_has_noapic_vcpu); 11224 } 11225 11226 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) 11227 { 11228 struct kvm_cpuid_entry2 *cpuid_0x1; 11229 unsigned long old_cr0 = kvm_read_cr0(vcpu); 11230 unsigned long new_cr0; 11231 11232 /* 11233 * Several of the "set" flows, e.g. ->set_cr0(), read other registers 11234 * to handle side effects. RESET emulation hits those flows and relies 11235 * on emulated/virtualized registers, including those that are loaded 11236 * into hardware, to be zeroed at vCPU creation. Use CRs as a sentinel 11237 * to detect improper or missing initialization. 11238 */ 11239 WARN_ON_ONCE(!init_event && 11240 (old_cr0 || kvm_read_cr3(vcpu) || kvm_read_cr4(vcpu))); 11241 11242 kvm_lapic_reset(vcpu, init_event); 11243 11244 vcpu->arch.hflags = 0; 11245 11246 vcpu->arch.smi_pending = 0; 11247 vcpu->arch.smi_count = 0; 11248 atomic_set(&vcpu->arch.nmi_queued, 0); 11249 vcpu->arch.nmi_pending = 0; 11250 vcpu->arch.nmi_injected = false; 11251 kvm_clear_interrupt_queue(vcpu); 11252 kvm_clear_exception_queue(vcpu); 11253 11254 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db)); 11255 kvm_update_dr0123(vcpu); 11256 vcpu->arch.dr6 = DR6_ACTIVE_LOW; 11257 vcpu->arch.dr7 = DR7_FIXED_1; 11258 kvm_update_dr7(vcpu); 11259 11260 vcpu->arch.cr2 = 0; 11261 11262 kvm_make_request(KVM_REQ_EVENT, vcpu); 11263 vcpu->arch.apf.msr_en_val = 0; 11264 vcpu->arch.apf.msr_int_val = 0; 11265 vcpu->arch.st.msr_val = 0; 11266 11267 kvmclock_reset(vcpu); 11268 11269 kvm_clear_async_pf_completion_queue(vcpu); 11270 kvm_async_pf_hash_reset(vcpu); 11271 vcpu->arch.apf.halted = false; 11272 11273 if (vcpu->arch.guest_fpu.fpstate && kvm_mpx_supported()) { 11274 struct fpstate *fpstate = vcpu->arch.guest_fpu.fpstate; 11275 11276 /* 11277 * To avoid have the INIT path from kvm_apic_has_events() that be 11278 * called with loaded FPU and does not let userspace fix the state. 11279 */ 11280 if (init_event) 11281 kvm_put_guest_fpu(vcpu); 11282 11283 fpstate_clear_xstate_component(fpstate, XFEATURE_BNDREGS); 11284 fpstate_clear_xstate_component(fpstate, XFEATURE_BNDCSR); 11285 11286 if (init_event) 11287 kvm_load_guest_fpu(vcpu); 11288 } 11289 11290 if (!init_event) { 11291 kvm_pmu_reset(vcpu); 11292 vcpu->arch.smbase = 0x30000; 11293 11294 vcpu->arch.msr_misc_features_enables = 0; 11295 11296 __kvm_set_xcr(vcpu, 0, XFEATURE_MASK_FP); 11297 __kvm_set_msr(vcpu, MSR_IA32_XSS, 0, true); 11298 } 11299 11300 /* All GPRs except RDX (handled below) are zeroed on RESET/INIT. */ 11301 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs)); 11302 kvm_register_mark_dirty(vcpu, VCPU_REGS_RSP); 11303 11304 /* 11305 * Fall back to KVM's default Family/Model/Stepping of 0x600 (P6/Athlon) 11306 * if no CPUID match is found. Note, it's impossible to get a match at 11307 * RESET since KVM emulates RESET before exposing the vCPU to userspace, 11308 * i.e. it's impossible for kvm_find_cpuid_entry() to find a valid entry 11309 * on RESET. But, go through the motions in case that's ever remedied. 11310 */ 11311 cpuid_0x1 = kvm_find_cpuid_entry(vcpu, 1, 0); 11312 kvm_rdx_write(vcpu, cpuid_0x1 ? cpuid_0x1->eax : 0x600); 11313 11314 static_call(kvm_x86_vcpu_reset)(vcpu, init_event); 11315 11316 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED); 11317 kvm_rip_write(vcpu, 0xfff0); 11318 11319 vcpu->arch.cr3 = 0; 11320 kvm_register_mark_dirty(vcpu, VCPU_EXREG_CR3); 11321 11322 /* 11323 * CR0.CD/NW are set on RESET, preserved on INIT. Note, some versions 11324 * of Intel's SDM list CD/NW as being set on INIT, but they contradict 11325 * (or qualify) that with a footnote stating that CD/NW are preserved. 11326 */ 11327 new_cr0 = X86_CR0_ET; 11328 if (init_event) 11329 new_cr0 |= (old_cr0 & (X86_CR0_NW | X86_CR0_CD)); 11330 else 11331 new_cr0 |= X86_CR0_NW | X86_CR0_CD; 11332 11333 static_call(kvm_x86_set_cr0)(vcpu, new_cr0); 11334 static_call(kvm_x86_set_cr4)(vcpu, 0); 11335 static_call(kvm_x86_set_efer)(vcpu, 0); 11336 static_call(kvm_x86_update_exception_bitmap)(vcpu); 11337 11338 /* 11339 * Reset the MMU context if paging was enabled prior to INIT (which is 11340 * implied if CR0.PG=1 as CR0 will be '0' prior to RESET). Unlike the 11341 * standard CR0/CR4/EFER modification paths, only CR0.PG needs to be 11342 * checked because it is unconditionally cleared on INIT and all other 11343 * paging related bits are ignored if paging is disabled, i.e. CR0.WP, 11344 * CR4, and EFER changes are all irrelevant if CR0.PG was '0'. 11345 */ 11346 if (old_cr0 & X86_CR0_PG) 11347 kvm_mmu_reset_context(vcpu); 11348 11349 /* 11350 * Intel's SDM states that all TLB entries are flushed on INIT. AMD's 11351 * APM states the TLBs are untouched by INIT, but it also states that 11352 * the TLBs are flushed on "External initialization of the processor." 11353 * Flush the guest TLB regardless of vendor, there is no meaningful 11354 * benefit in relying on the guest to flush the TLB immediately after 11355 * INIT. A spurious TLB flush is benign and likely negligible from a 11356 * performance perspective. 11357 */ 11358 if (init_event) 11359 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu); 11360 } 11361 EXPORT_SYMBOL_GPL(kvm_vcpu_reset); 11362 11363 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector) 11364 { 11365 struct kvm_segment cs; 11366 11367 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); 11368 cs.selector = vector << 8; 11369 cs.base = vector << 12; 11370 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); 11371 kvm_rip_write(vcpu, 0); 11372 } 11373 EXPORT_SYMBOL_GPL(kvm_vcpu_deliver_sipi_vector); 11374 11375 int kvm_arch_hardware_enable(void) 11376 { 11377 struct kvm *kvm; 11378 struct kvm_vcpu *vcpu; 11379 unsigned long i; 11380 int ret; 11381 u64 local_tsc; 11382 u64 max_tsc = 0; 11383 bool stable, backwards_tsc = false; 11384 11385 kvm_user_return_msr_cpu_online(); 11386 ret = static_call(kvm_x86_hardware_enable)(); 11387 if (ret != 0) 11388 return ret; 11389 11390 local_tsc = rdtsc(); 11391 stable = !kvm_check_tsc_unstable(); 11392 list_for_each_entry(kvm, &vm_list, vm_list) { 11393 kvm_for_each_vcpu(i, vcpu, kvm) { 11394 if (!stable && vcpu->cpu == smp_processor_id()) 11395 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 11396 if (stable && vcpu->arch.last_host_tsc > local_tsc) { 11397 backwards_tsc = true; 11398 if (vcpu->arch.last_host_tsc > max_tsc) 11399 max_tsc = vcpu->arch.last_host_tsc; 11400 } 11401 } 11402 } 11403 11404 /* 11405 * Sometimes, even reliable TSCs go backwards. This happens on 11406 * platforms that reset TSC during suspend or hibernate actions, but 11407 * maintain synchronization. We must compensate. Fortunately, we can 11408 * detect that condition here, which happens early in CPU bringup, 11409 * before any KVM threads can be running. Unfortunately, we can't 11410 * bring the TSCs fully up to date with real time, as we aren't yet far 11411 * enough into CPU bringup that we know how much real time has actually 11412 * elapsed; our helper function, ktime_get_boottime_ns() will be using boot 11413 * variables that haven't been updated yet. 11414 * 11415 * So we simply find the maximum observed TSC above, then record the 11416 * adjustment to TSC in each VCPU. When the VCPU later gets loaded, 11417 * the adjustment will be applied. Note that we accumulate 11418 * adjustments, in case multiple suspend cycles happen before some VCPU 11419 * gets a chance to run again. In the event that no KVM threads get a 11420 * chance to run, we will miss the entire elapsed period, as we'll have 11421 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may 11422 * loose cycle time. This isn't too big a deal, since the loss will be 11423 * uniform across all VCPUs (not to mention the scenario is extremely 11424 * unlikely). It is possible that a second hibernate recovery happens 11425 * much faster than a first, causing the observed TSC here to be 11426 * smaller; this would require additional padding adjustment, which is 11427 * why we set last_host_tsc to the local tsc observed here. 11428 * 11429 * N.B. - this code below runs only on platforms with reliable TSC, 11430 * as that is the only way backwards_tsc is set above. Also note 11431 * that this runs for ALL vcpus, which is not a bug; all VCPUs should 11432 * have the same delta_cyc adjustment applied if backwards_tsc 11433 * is detected. Note further, this adjustment is only done once, 11434 * as we reset last_host_tsc on all VCPUs to stop this from being 11435 * called multiple times (one for each physical CPU bringup). 11436 * 11437 * Platforms with unreliable TSCs don't have to deal with this, they 11438 * will be compensated by the logic in vcpu_load, which sets the TSC to 11439 * catchup mode. This will catchup all VCPUs to real time, but cannot 11440 * guarantee that they stay in perfect synchronization. 11441 */ 11442 if (backwards_tsc) { 11443 u64 delta_cyc = max_tsc - local_tsc; 11444 list_for_each_entry(kvm, &vm_list, vm_list) { 11445 kvm->arch.backwards_tsc_observed = true; 11446 kvm_for_each_vcpu(i, vcpu, kvm) { 11447 vcpu->arch.tsc_offset_adjustment += delta_cyc; 11448 vcpu->arch.last_host_tsc = local_tsc; 11449 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 11450 } 11451 11452 /* 11453 * We have to disable TSC offset matching.. if you were 11454 * booting a VM while issuing an S4 host suspend.... 11455 * you may have some problem. Solving this issue is 11456 * left as an exercise to the reader. 11457 */ 11458 kvm->arch.last_tsc_nsec = 0; 11459 kvm->arch.last_tsc_write = 0; 11460 } 11461 11462 } 11463 return 0; 11464 } 11465 11466 void kvm_arch_hardware_disable(void) 11467 { 11468 static_call(kvm_x86_hardware_disable)(); 11469 drop_user_return_notifiers(); 11470 } 11471 11472 int kvm_arch_hardware_setup(void *opaque) 11473 { 11474 struct kvm_x86_init_ops *ops = opaque; 11475 int r; 11476 11477 rdmsrl_safe(MSR_EFER, &host_efer); 11478 11479 if (boot_cpu_has(X86_FEATURE_XSAVES)) 11480 rdmsrl(MSR_IA32_XSS, host_xss); 11481 11482 r = ops->hardware_setup(); 11483 if (r != 0) 11484 return r; 11485 11486 memcpy(&kvm_x86_ops, ops->runtime_ops, sizeof(kvm_x86_ops)); 11487 kvm_ops_static_call_update(); 11488 11489 kvm_register_perf_callbacks(ops->handle_intel_pt_intr); 11490 11491 if (!kvm_cpu_cap_has(X86_FEATURE_XSAVES)) 11492 supported_xss = 0; 11493 11494 #define __kvm_cpu_cap_has(UNUSED_, f) kvm_cpu_cap_has(f) 11495 cr4_reserved_bits = __cr4_reserved_bits(__kvm_cpu_cap_has, UNUSED_); 11496 #undef __kvm_cpu_cap_has 11497 11498 if (kvm_has_tsc_control) { 11499 /* 11500 * Make sure the user can only configure tsc_khz values that 11501 * fit into a signed integer. 11502 * A min value is not calculated because it will always 11503 * be 1 on all machines. 11504 */ 11505 u64 max = min(0x7fffffffULL, 11506 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz)); 11507 kvm_max_guest_tsc_khz = max; 11508 11509 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits; 11510 } 11511 11512 kvm_init_msr_list(); 11513 return 0; 11514 } 11515 11516 void kvm_arch_hardware_unsetup(void) 11517 { 11518 kvm_unregister_perf_callbacks(); 11519 11520 static_call(kvm_x86_hardware_unsetup)(); 11521 } 11522 11523 int kvm_arch_check_processor_compat(void *opaque) 11524 { 11525 struct cpuinfo_x86 *c = &cpu_data(smp_processor_id()); 11526 struct kvm_x86_init_ops *ops = opaque; 11527 11528 WARN_ON(!irqs_disabled()); 11529 11530 if (__cr4_reserved_bits(cpu_has, c) != 11531 __cr4_reserved_bits(cpu_has, &boot_cpu_data)) 11532 return -EIO; 11533 11534 return ops->check_processor_compatibility(); 11535 } 11536 11537 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu) 11538 { 11539 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id; 11540 } 11541 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp); 11542 11543 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu) 11544 { 11545 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0; 11546 } 11547 11548 __read_mostly DEFINE_STATIC_KEY_FALSE(kvm_has_noapic_vcpu); 11549 EXPORT_SYMBOL_GPL(kvm_has_noapic_vcpu); 11550 11551 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) 11552 { 11553 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); 11554 11555 vcpu->arch.l1tf_flush_l1d = true; 11556 if (pmu->version && unlikely(pmu->event_count)) { 11557 pmu->need_cleanup = true; 11558 kvm_make_request(KVM_REQ_PMU, vcpu); 11559 } 11560 static_call(kvm_x86_sched_in)(vcpu, cpu); 11561 } 11562 11563 void kvm_arch_free_vm(struct kvm *kvm) 11564 { 11565 kfree(to_kvm_hv(kvm)->hv_pa_pg); 11566 __kvm_arch_free_vm(kvm); 11567 } 11568 11569 11570 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) 11571 { 11572 int ret; 11573 unsigned long flags; 11574 11575 if (type) 11576 return -EINVAL; 11577 11578 ret = kvm_page_track_init(kvm); 11579 if (ret) 11580 return ret; 11581 11582 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list); 11583 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages); 11584 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages); 11585 INIT_LIST_HEAD(&kvm->arch.lpage_disallowed_mmu_pages); 11586 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head); 11587 atomic_set(&kvm->arch.noncoherent_dma_count, 0); 11588 11589 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */ 11590 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap); 11591 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */ 11592 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID, 11593 &kvm->arch.irq_sources_bitmap); 11594 11595 raw_spin_lock_init(&kvm->arch.tsc_write_lock); 11596 mutex_init(&kvm->arch.apic_map_lock); 11597 seqcount_raw_spinlock_init(&kvm->arch.pvclock_sc, &kvm->arch.tsc_write_lock); 11598 kvm->arch.kvmclock_offset = -get_kvmclock_base_ns(); 11599 11600 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags); 11601 pvclock_update_vm_gtod_copy(kvm); 11602 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags); 11603 11604 kvm->arch.guest_can_read_msr_platform_info = true; 11605 kvm->arch.enable_pmu = enable_pmu; 11606 11607 #if IS_ENABLED(CONFIG_HYPERV) 11608 spin_lock_init(&kvm->arch.hv_root_tdp_lock); 11609 kvm->arch.hv_root_tdp = INVALID_PAGE; 11610 #endif 11611 11612 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn); 11613 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn); 11614 11615 kvm_apicv_init(kvm); 11616 kvm_hv_init_vm(kvm); 11617 kvm_mmu_init_vm(kvm); 11618 kvm_xen_init_vm(kvm); 11619 11620 return static_call(kvm_x86_vm_init)(kvm); 11621 } 11622 11623 int kvm_arch_post_init_vm(struct kvm *kvm) 11624 { 11625 return kvm_mmu_post_init_vm(kvm); 11626 } 11627 11628 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu) 11629 { 11630 vcpu_load(vcpu); 11631 kvm_mmu_unload(vcpu); 11632 vcpu_put(vcpu); 11633 } 11634 11635 static void kvm_free_vcpus(struct kvm *kvm) 11636 { 11637 unsigned long i; 11638 struct kvm_vcpu *vcpu; 11639 11640 /* 11641 * Unpin any mmu pages first. 11642 */ 11643 kvm_for_each_vcpu(i, vcpu, kvm) { 11644 kvm_clear_async_pf_completion_queue(vcpu); 11645 kvm_unload_vcpu_mmu(vcpu); 11646 } 11647 11648 kvm_destroy_vcpus(kvm); 11649 } 11650 11651 void kvm_arch_sync_events(struct kvm *kvm) 11652 { 11653 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work); 11654 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work); 11655 kvm_free_pit(kvm); 11656 } 11657 11658 /** 11659 * __x86_set_memory_region: Setup KVM internal memory slot 11660 * 11661 * @kvm: the kvm pointer to the VM. 11662 * @id: the slot ID to setup. 11663 * @gpa: the GPA to install the slot (unused when @size == 0). 11664 * @size: the size of the slot. Set to zero to uninstall a slot. 11665 * 11666 * This function helps to setup a KVM internal memory slot. Specify 11667 * @size > 0 to install a new slot, while @size == 0 to uninstall a 11668 * slot. The return code can be one of the following: 11669 * 11670 * HVA: on success (uninstall will return a bogus HVA) 11671 * -errno: on error 11672 * 11673 * The caller should always use IS_ERR() to check the return value 11674 * before use. Note, the KVM internal memory slots are guaranteed to 11675 * remain valid and unchanged until the VM is destroyed, i.e., the 11676 * GPA->HVA translation will not change. However, the HVA is a user 11677 * address, i.e. its accessibility is not guaranteed, and must be 11678 * accessed via __copy_{to,from}_user(). 11679 */ 11680 void __user * __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, 11681 u32 size) 11682 { 11683 int i, r; 11684 unsigned long hva, old_npages; 11685 struct kvm_memslots *slots = kvm_memslots(kvm); 11686 struct kvm_memory_slot *slot; 11687 11688 /* Called with kvm->slots_lock held. */ 11689 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM)) 11690 return ERR_PTR_USR(-EINVAL); 11691 11692 slot = id_to_memslot(slots, id); 11693 if (size) { 11694 if (slot && slot->npages) 11695 return ERR_PTR_USR(-EEXIST); 11696 11697 /* 11698 * MAP_SHARED to prevent internal slot pages from being moved 11699 * by fork()/COW. 11700 */ 11701 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE, 11702 MAP_SHARED | MAP_ANONYMOUS, 0); 11703 if (IS_ERR((void *)hva)) 11704 return (void __user *)hva; 11705 } else { 11706 if (!slot || !slot->npages) 11707 return NULL; 11708 11709 old_npages = slot->npages; 11710 hva = slot->userspace_addr; 11711 } 11712 11713 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { 11714 struct kvm_userspace_memory_region m; 11715 11716 m.slot = id | (i << 16); 11717 m.flags = 0; 11718 m.guest_phys_addr = gpa; 11719 m.userspace_addr = hva; 11720 m.memory_size = size; 11721 r = __kvm_set_memory_region(kvm, &m); 11722 if (r < 0) 11723 return ERR_PTR_USR(r); 11724 } 11725 11726 if (!size) 11727 vm_munmap(hva, old_npages * PAGE_SIZE); 11728 11729 return (void __user *)hva; 11730 } 11731 EXPORT_SYMBOL_GPL(__x86_set_memory_region); 11732 11733 void kvm_arch_pre_destroy_vm(struct kvm *kvm) 11734 { 11735 kvm_mmu_pre_destroy_vm(kvm); 11736 } 11737 11738 void kvm_arch_destroy_vm(struct kvm *kvm) 11739 { 11740 if (current->mm == kvm->mm) { 11741 /* 11742 * Free memory regions allocated on behalf of userspace, 11743 * unless the the memory map has changed due to process exit 11744 * or fd copying. 11745 */ 11746 mutex_lock(&kvm->slots_lock); 11747 __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 11748 0, 0); 11749 __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 11750 0, 0); 11751 __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0); 11752 mutex_unlock(&kvm->slots_lock); 11753 } 11754 static_call_cond(kvm_x86_vm_destroy)(kvm); 11755 kvm_free_msr_filter(srcu_dereference_check(kvm->arch.msr_filter, &kvm->srcu, 1)); 11756 kvm_pic_destroy(kvm); 11757 kvm_ioapic_destroy(kvm); 11758 kvm_free_vcpus(kvm); 11759 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1)); 11760 kfree(srcu_dereference_check(kvm->arch.pmu_event_filter, &kvm->srcu, 1)); 11761 kvm_mmu_uninit_vm(kvm); 11762 kvm_page_track_cleanup(kvm); 11763 kvm_xen_destroy_vm(kvm); 11764 kvm_hv_destroy_vm(kvm); 11765 } 11766 11767 static void memslot_rmap_free(struct kvm_memory_slot *slot) 11768 { 11769 int i; 11770 11771 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 11772 kvfree(slot->arch.rmap[i]); 11773 slot->arch.rmap[i] = NULL; 11774 } 11775 } 11776 11777 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *slot) 11778 { 11779 int i; 11780 11781 memslot_rmap_free(slot); 11782 11783 for (i = 1; i < KVM_NR_PAGE_SIZES; ++i) { 11784 kvfree(slot->arch.lpage_info[i - 1]); 11785 slot->arch.lpage_info[i - 1] = NULL; 11786 } 11787 11788 kvm_page_track_free_memslot(slot); 11789 } 11790 11791 int memslot_rmap_alloc(struct kvm_memory_slot *slot, unsigned long npages) 11792 { 11793 const int sz = sizeof(*slot->arch.rmap[0]); 11794 int i; 11795 11796 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 11797 int level = i + 1; 11798 int lpages = __kvm_mmu_slot_lpages(slot, npages, level); 11799 11800 if (slot->arch.rmap[i]) 11801 continue; 11802 11803 slot->arch.rmap[i] = kvcalloc(lpages, sz, GFP_KERNEL_ACCOUNT); 11804 if (!slot->arch.rmap[i]) { 11805 memslot_rmap_free(slot); 11806 return -ENOMEM; 11807 } 11808 } 11809 11810 return 0; 11811 } 11812 11813 static int kvm_alloc_memslot_metadata(struct kvm *kvm, 11814 struct kvm_memory_slot *slot) 11815 { 11816 unsigned long npages = slot->npages; 11817 int i, r; 11818 11819 /* 11820 * Clear out the previous array pointers for the KVM_MR_MOVE case. The 11821 * old arrays will be freed by __kvm_set_memory_region() if installing 11822 * the new memslot is successful. 11823 */ 11824 memset(&slot->arch, 0, sizeof(slot->arch)); 11825 11826 if (kvm_memslots_have_rmaps(kvm)) { 11827 r = memslot_rmap_alloc(slot, npages); 11828 if (r) 11829 return r; 11830 } 11831 11832 for (i = 1; i < KVM_NR_PAGE_SIZES; ++i) { 11833 struct kvm_lpage_info *linfo; 11834 unsigned long ugfn; 11835 int lpages; 11836 int level = i + 1; 11837 11838 lpages = __kvm_mmu_slot_lpages(slot, npages, level); 11839 11840 linfo = kvcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT); 11841 if (!linfo) 11842 goto out_free; 11843 11844 slot->arch.lpage_info[i - 1] = linfo; 11845 11846 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1)) 11847 linfo[0].disallow_lpage = 1; 11848 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1)) 11849 linfo[lpages - 1].disallow_lpage = 1; 11850 ugfn = slot->userspace_addr >> PAGE_SHIFT; 11851 /* 11852 * If the gfn and userspace address are not aligned wrt each 11853 * other, disable large page support for this slot. 11854 */ 11855 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1)) { 11856 unsigned long j; 11857 11858 for (j = 0; j < lpages; ++j) 11859 linfo[j].disallow_lpage = 1; 11860 } 11861 } 11862 11863 if (kvm_page_track_create_memslot(kvm, slot, npages)) 11864 goto out_free; 11865 11866 return 0; 11867 11868 out_free: 11869 memslot_rmap_free(slot); 11870 11871 for (i = 1; i < KVM_NR_PAGE_SIZES; ++i) { 11872 kvfree(slot->arch.lpage_info[i - 1]); 11873 slot->arch.lpage_info[i - 1] = NULL; 11874 } 11875 return -ENOMEM; 11876 } 11877 11878 void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen) 11879 { 11880 struct kvm_vcpu *vcpu; 11881 unsigned long i; 11882 11883 /* 11884 * memslots->generation has been incremented. 11885 * mmio generation may have reached its maximum value. 11886 */ 11887 kvm_mmu_invalidate_mmio_sptes(kvm, gen); 11888 11889 /* Force re-initialization of steal_time cache */ 11890 kvm_for_each_vcpu(i, vcpu, kvm) 11891 kvm_vcpu_kick(vcpu); 11892 } 11893 11894 int kvm_arch_prepare_memory_region(struct kvm *kvm, 11895 const struct kvm_memory_slot *old, 11896 struct kvm_memory_slot *new, 11897 enum kvm_mr_change change) 11898 { 11899 if (change == KVM_MR_CREATE || change == KVM_MR_MOVE) 11900 return kvm_alloc_memslot_metadata(kvm, new); 11901 11902 if (change == KVM_MR_FLAGS_ONLY) 11903 memcpy(&new->arch, &old->arch, sizeof(old->arch)); 11904 else if (WARN_ON_ONCE(change != KVM_MR_DELETE)) 11905 return -EIO; 11906 11907 return 0; 11908 } 11909 11910 11911 static void kvm_mmu_update_cpu_dirty_logging(struct kvm *kvm, bool enable) 11912 { 11913 struct kvm_arch *ka = &kvm->arch; 11914 11915 if (!kvm_x86_ops.cpu_dirty_log_size) 11916 return; 11917 11918 if ((enable && ++ka->cpu_dirty_logging_count == 1) || 11919 (!enable && --ka->cpu_dirty_logging_count == 0)) 11920 kvm_make_all_cpus_request(kvm, KVM_REQ_UPDATE_CPU_DIRTY_LOGGING); 11921 11922 WARN_ON_ONCE(ka->cpu_dirty_logging_count < 0); 11923 } 11924 11925 static void kvm_mmu_slot_apply_flags(struct kvm *kvm, 11926 struct kvm_memory_slot *old, 11927 const struct kvm_memory_slot *new, 11928 enum kvm_mr_change change) 11929 { 11930 u32 old_flags = old ? old->flags : 0; 11931 u32 new_flags = new ? new->flags : 0; 11932 bool log_dirty_pages = new_flags & KVM_MEM_LOG_DIRTY_PAGES; 11933 11934 /* 11935 * Update CPU dirty logging if dirty logging is being toggled. This 11936 * applies to all operations. 11937 */ 11938 if ((old_flags ^ new_flags) & KVM_MEM_LOG_DIRTY_PAGES) 11939 kvm_mmu_update_cpu_dirty_logging(kvm, log_dirty_pages); 11940 11941 /* 11942 * Nothing more to do for RO slots (which can't be dirtied and can't be 11943 * made writable) or CREATE/MOVE/DELETE of a slot. 11944 * 11945 * For a memslot with dirty logging disabled: 11946 * CREATE: No dirty mappings will already exist. 11947 * MOVE/DELETE: The old mappings will already have been cleaned up by 11948 * kvm_arch_flush_shadow_memslot() 11949 * 11950 * For a memslot with dirty logging enabled: 11951 * CREATE: No shadow pages exist, thus nothing to write-protect 11952 * and no dirty bits to clear. 11953 * MOVE/DELETE: The old mappings will already have been cleaned up by 11954 * kvm_arch_flush_shadow_memslot(). 11955 */ 11956 if ((change != KVM_MR_FLAGS_ONLY) || (new_flags & KVM_MEM_READONLY)) 11957 return; 11958 11959 /* 11960 * READONLY and non-flags changes were filtered out above, and the only 11961 * other flag is LOG_DIRTY_PAGES, i.e. something is wrong if dirty 11962 * logging isn't being toggled on or off. 11963 */ 11964 if (WARN_ON_ONCE(!((old_flags ^ new_flags) & KVM_MEM_LOG_DIRTY_PAGES))) 11965 return; 11966 11967 if (!log_dirty_pages) { 11968 /* 11969 * Dirty logging tracks sptes in 4k granularity, meaning that 11970 * large sptes have to be split. If live migration succeeds, 11971 * the guest in the source machine will be destroyed and large 11972 * sptes will be created in the destination. However, if the 11973 * guest continues to run in the source machine (for example if 11974 * live migration fails), small sptes will remain around and 11975 * cause bad performance. 11976 * 11977 * Scan sptes if dirty logging has been stopped, dropping those 11978 * which can be collapsed into a single large-page spte. Later 11979 * page faults will create the large-page sptes. 11980 */ 11981 kvm_mmu_zap_collapsible_sptes(kvm, new); 11982 } else { 11983 /* 11984 * Initially-all-set does not require write protecting any page, 11985 * because they're all assumed to be dirty. 11986 */ 11987 if (kvm_dirty_log_manual_protect_and_init_set(kvm)) 11988 return; 11989 11990 if (READ_ONCE(eager_page_split)) 11991 kvm_mmu_slot_try_split_huge_pages(kvm, new, PG_LEVEL_4K); 11992 11993 if (kvm_x86_ops.cpu_dirty_log_size) { 11994 kvm_mmu_slot_leaf_clear_dirty(kvm, new); 11995 kvm_mmu_slot_remove_write_access(kvm, new, PG_LEVEL_2M); 11996 } else { 11997 kvm_mmu_slot_remove_write_access(kvm, new, PG_LEVEL_4K); 11998 } 11999 } 12000 } 12001 12002 void kvm_arch_commit_memory_region(struct kvm *kvm, 12003 struct kvm_memory_slot *old, 12004 const struct kvm_memory_slot *new, 12005 enum kvm_mr_change change) 12006 { 12007 if (!kvm->arch.n_requested_mmu_pages && 12008 (change == KVM_MR_CREATE || change == KVM_MR_DELETE)) { 12009 unsigned long nr_mmu_pages; 12010 12011 nr_mmu_pages = kvm->nr_memslot_pages / KVM_MEMSLOT_PAGES_TO_MMU_PAGES_RATIO; 12012 nr_mmu_pages = max(nr_mmu_pages, KVM_MIN_ALLOC_MMU_PAGES); 12013 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages); 12014 } 12015 12016 kvm_mmu_slot_apply_flags(kvm, old, new, change); 12017 12018 /* Free the arrays associated with the old memslot. */ 12019 if (change == KVM_MR_MOVE) 12020 kvm_arch_free_memslot(kvm, old); 12021 } 12022 12023 void kvm_arch_flush_shadow_all(struct kvm *kvm) 12024 { 12025 kvm_mmu_zap_all(kvm); 12026 } 12027 12028 void kvm_arch_flush_shadow_memslot(struct kvm *kvm, 12029 struct kvm_memory_slot *slot) 12030 { 12031 kvm_page_track_flush_slot(kvm, slot); 12032 } 12033 12034 static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu) 12035 { 12036 return (is_guest_mode(vcpu) && 12037 static_call(kvm_x86_guest_apic_has_interrupt)(vcpu)); 12038 } 12039 12040 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu) 12041 { 12042 if (!list_empty_careful(&vcpu->async_pf.done)) 12043 return true; 12044 12045 if (kvm_apic_has_events(vcpu)) 12046 return true; 12047 12048 if (vcpu->arch.pv.pv_unhalted) 12049 return true; 12050 12051 if (vcpu->arch.exception.pending) 12052 return true; 12053 12054 if (kvm_test_request(KVM_REQ_NMI, vcpu) || 12055 (vcpu->arch.nmi_pending && 12056 static_call(kvm_x86_nmi_allowed)(vcpu, false))) 12057 return true; 12058 12059 if (kvm_test_request(KVM_REQ_SMI, vcpu) || 12060 (vcpu->arch.smi_pending && 12061 static_call(kvm_x86_smi_allowed)(vcpu, false))) 12062 return true; 12063 12064 if (kvm_arch_interrupt_allowed(vcpu) && 12065 (kvm_cpu_has_interrupt(vcpu) || 12066 kvm_guest_apic_has_interrupt(vcpu))) 12067 return true; 12068 12069 if (kvm_hv_has_stimer_pending(vcpu)) 12070 return true; 12071 12072 if (is_guest_mode(vcpu) && 12073 kvm_x86_ops.nested_ops->hv_timer_pending && 12074 kvm_x86_ops.nested_ops->hv_timer_pending(vcpu)) 12075 return true; 12076 12077 return false; 12078 } 12079 12080 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) 12081 { 12082 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu); 12083 } 12084 12085 bool kvm_arch_dy_has_pending_interrupt(struct kvm_vcpu *vcpu) 12086 { 12087 if (vcpu->arch.apicv_active && static_call(kvm_x86_dy_apicv_has_pending_interrupt)(vcpu)) 12088 return true; 12089 12090 return false; 12091 } 12092 12093 bool kvm_arch_dy_runnable(struct kvm_vcpu *vcpu) 12094 { 12095 if (READ_ONCE(vcpu->arch.pv.pv_unhalted)) 12096 return true; 12097 12098 if (kvm_test_request(KVM_REQ_NMI, vcpu) || 12099 kvm_test_request(KVM_REQ_SMI, vcpu) || 12100 kvm_test_request(KVM_REQ_EVENT, vcpu)) 12101 return true; 12102 12103 return kvm_arch_dy_has_pending_interrupt(vcpu); 12104 } 12105 12106 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu) 12107 { 12108 if (vcpu->arch.guest_state_protected) 12109 return true; 12110 12111 return vcpu->arch.preempted_in_kernel; 12112 } 12113 12114 unsigned long kvm_arch_vcpu_get_ip(struct kvm_vcpu *vcpu) 12115 { 12116 return kvm_rip_read(vcpu); 12117 } 12118 12119 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu) 12120 { 12121 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE; 12122 } 12123 12124 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu) 12125 { 12126 return static_call(kvm_x86_interrupt_allowed)(vcpu, false); 12127 } 12128 12129 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu) 12130 { 12131 /* Can't read the RIP when guest state is protected, just return 0 */ 12132 if (vcpu->arch.guest_state_protected) 12133 return 0; 12134 12135 if (is_64_bit_mode(vcpu)) 12136 return kvm_rip_read(vcpu); 12137 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) + 12138 kvm_rip_read(vcpu)); 12139 } 12140 EXPORT_SYMBOL_GPL(kvm_get_linear_rip); 12141 12142 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip) 12143 { 12144 return kvm_get_linear_rip(vcpu) == linear_rip; 12145 } 12146 EXPORT_SYMBOL_GPL(kvm_is_linear_rip); 12147 12148 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu) 12149 { 12150 unsigned long rflags; 12151 12152 rflags = static_call(kvm_x86_get_rflags)(vcpu); 12153 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) 12154 rflags &= ~X86_EFLAGS_TF; 12155 return rflags; 12156 } 12157 EXPORT_SYMBOL_GPL(kvm_get_rflags); 12158 12159 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) 12160 { 12161 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP && 12162 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip)) 12163 rflags |= X86_EFLAGS_TF; 12164 static_call(kvm_x86_set_rflags)(vcpu, rflags); 12165 } 12166 12167 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) 12168 { 12169 __kvm_set_rflags(vcpu, rflags); 12170 kvm_make_request(KVM_REQ_EVENT, vcpu); 12171 } 12172 EXPORT_SYMBOL_GPL(kvm_set_rflags); 12173 12174 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work) 12175 { 12176 int r; 12177 12178 if ((vcpu->arch.mmu->direct_map != work->arch.direct_map) || 12179 work->wakeup_all) 12180 return; 12181 12182 r = kvm_mmu_reload(vcpu); 12183 if (unlikely(r)) 12184 return; 12185 12186 if (!vcpu->arch.mmu->direct_map && 12187 work->arch.cr3 != vcpu->arch.mmu->get_guest_pgd(vcpu)) 12188 return; 12189 12190 kvm_mmu_do_page_fault(vcpu, work->cr2_or_gpa, 0, true); 12191 } 12192 12193 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn) 12194 { 12195 BUILD_BUG_ON(!is_power_of_2(ASYNC_PF_PER_VCPU)); 12196 12197 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU)); 12198 } 12199 12200 static inline u32 kvm_async_pf_next_probe(u32 key) 12201 { 12202 return (key + 1) & (ASYNC_PF_PER_VCPU - 1); 12203 } 12204 12205 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 12206 { 12207 u32 key = kvm_async_pf_hash_fn(gfn); 12208 12209 while (vcpu->arch.apf.gfns[key] != ~0) 12210 key = kvm_async_pf_next_probe(key); 12211 12212 vcpu->arch.apf.gfns[key] = gfn; 12213 } 12214 12215 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn) 12216 { 12217 int i; 12218 u32 key = kvm_async_pf_hash_fn(gfn); 12219 12220 for (i = 0; i < ASYNC_PF_PER_VCPU && 12221 (vcpu->arch.apf.gfns[key] != gfn && 12222 vcpu->arch.apf.gfns[key] != ~0); i++) 12223 key = kvm_async_pf_next_probe(key); 12224 12225 return key; 12226 } 12227 12228 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 12229 { 12230 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn; 12231 } 12232 12233 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 12234 { 12235 u32 i, j, k; 12236 12237 i = j = kvm_async_pf_gfn_slot(vcpu, gfn); 12238 12239 if (WARN_ON_ONCE(vcpu->arch.apf.gfns[i] != gfn)) 12240 return; 12241 12242 while (true) { 12243 vcpu->arch.apf.gfns[i] = ~0; 12244 do { 12245 j = kvm_async_pf_next_probe(j); 12246 if (vcpu->arch.apf.gfns[j] == ~0) 12247 return; 12248 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]); 12249 /* 12250 * k lies cyclically in ]i,j] 12251 * | i.k.j | 12252 * |....j i.k.| or |.k..j i...| 12253 */ 12254 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j)); 12255 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j]; 12256 i = j; 12257 } 12258 } 12259 12260 static inline int apf_put_user_notpresent(struct kvm_vcpu *vcpu) 12261 { 12262 u32 reason = KVM_PV_REASON_PAGE_NOT_PRESENT; 12263 12264 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &reason, 12265 sizeof(reason)); 12266 } 12267 12268 static inline int apf_put_user_ready(struct kvm_vcpu *vcpu, u32 token) 12269 { 12270 unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token); 12271 12272 return kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data, 12273 &token, offset, sizeof(token)); 12274 } 12275 12276 static inline bool apf_pageready_slot_free(struct kvm_vcpu *vcpu) 12277 { 12278 unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token); 12279 u32 val; 12280 12281 if (kvm_read_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data, 12282 &val, offset, sizeof(val))) 12283 return false; 12284 12285 return !val; 12286 } 12287 12288 static bool kvm_can_deliver_async_pf(struct kvm_vcpu *vcpu) 12289 { 12290 if (!vcpu->arch.apf.delivery_as_pf_vmexit && is_guest_mode(vcpu)) 12291 return false; 12292 12293 if (!kvm_pv_async_pf_enabled(vcpu) || 12294 (vcpu->arch.apf.send_user_only && static_call(kvm_x86_get_cpl)(vcpu) == 0)) 12295 return false; 12296 12297 return true; 12298 } 12299 12300 bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu) 12301 { 12302 if (unlikely(!lapic_in_kernel(vcpu) || 12303 kvm_event_needs_reinjection(vcpu) || 12304 vcpu->arch.exception.pending)) 12305 return false; 12306 12307 if (kvm_hlt_in_guest(vcpu->kvm) && !kvm_can_deliver_async_pf(vcpu)) 12308 return false; 12309 12310 /* 12311 * If interrupts are off we cannot even use an artificial 12312 * halt state. 12313 */ 12314 return kvm_arch_interrupt_allowed(vcpu); 12315 } 12316 12317 bool kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu, 12318 struct kvm_async_pf *work) 12319 { 12320 struct x86_exception fault; 12321 12322 trace_kvm_async_pf_not_present(work->arch.token, work->cr2_or_gpa); 12323 kvm_add_async_pf_gfn(vcpu, work->arch.gfn); 12324 12325 if (kvm_can_deliver_async_pf(vcpu) && 12326 !apf_put_user_notpresent(vcpu)) { 12327 fault.vector = PF_VECTOR; 12328 fault.error_code_valid = true; 12329 fault.error_code = 0; 12330 fault.nested_page_fault = false; 12331 fault.address = work->arch.token; 12332 fault.async_page_fault = true; 12333 kvm_inject_page_fault(vcpu, &fault); 12334 return true; 12335 } else { 12336 /* 12337 * It is not possible to deliver a paravirtualized asynchronous 12338 * page fault, but putting the guest in an artificial halt state 12339 * can be beneficial nevertheless: if an interrupt arrives, we 12340 * can deliver it timely and perhaps the guest will schedule 12341 * another process. When the instruction that triggered a page 12342 * fault is retried, hopefully the page will be ready in the host. 12343 */ 12344 kvm_make_request(KVM_REQ_APF_HALT, vcpu); 12345 return false; 12346 } 12347 } 12348 12349 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu, 12350 struct kvm_async_pf *work) 12351 { 12352 struct kvm_lapic_irq irq = { 12353 .delivery_mode = APIC_DM_FIXED, 12354 .vector = vcpu->arch.apf.vec 12355 }; 12356 12357 if (work->wakeup_all) 12358 work->arch.token = ~0; /* broadcast wakeup */ 12359 else 12360 kvm_del_async_pf_gfn(vcpu, work->arch.gfn); 12361 trace_kvm_async_pf_ready(work->arch.token, work->cr2_or_gpa); 12362 12363 if ((work->wakeup_all || work->notpresent_injected) && 12364 kvm_pv_async_pf_enabled(vcpu) && 12365 !apf_put_user_ready(vcpu, work->arch.token)) { 12366 vcpu->arch.apf.pageready_pending = true; 12367 kvm_apic_set_irq(vcpu, &irq, NULL); 12368 } 12369 12370 vcpu->arch.apf.halted = false; 12371 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 12372 } 12373 12374 void kvm_arch_async_page_present_queued(struct kvm_vcpu *vcpu) 12375 { 12376 kvm_make_request(KVM_REQ_APF_READY, vcpu); 12377 if (!vcpu->arch.apf.pageready_pending) 12378 kvm_vcpu_kick(vcpu); 12379 } 12380 12381 bool kvm_arch_can_dequeue_async_page_present(struct kvm_vcpu *vcpu) 12382 { 12383 if (!kvm_pv_async_pf_enabled(vcpu)) 12384 return true; 12385 else 12386 return kvm_lapic_enabled(vcpu) && apf_pageready_slot_free(vcpu); 12387 } 12388 12389 void kvm_arch_start_assignment(struct kvm *kvm) 12390 { 12391 if (atomic_inc_return(&kvm->arch.assigned_device_count) == 1) 12392 static_call_cond(kvm_x86_pi_start_assignment)(kvm); 12393 } 12394 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment); 12395 12396 void kvm_arch_end_assignment(struct kvm *kvm) 12397 { 12398 atomic_dec(&kvm->arch.assigned_device_count); 12399 } 12400 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment); 12401 12402 bool kvm_arch_has_assigned_device(struct kvm *kvm) 12403 { 12404 return atomic_read(&kvm->arch.assigned_device_count); 12405 } 12406 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device); 12407 12408 void kvm_arch_register_noncoherent_dma(struct kvm *kvm) 12409 { 12410 atomic_inc(&kvm->arch.noncoherent_dma_count); 12411 } 12412 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma); 12413 12414 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm) 12415 { 12416 atomic_dec(&kvm->arch.noncoherent_dma_count); 12417 } 12418 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma); 12419 12420 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm) 12421 { 12422 return atomic_read(&kvm->arch.noncoherent_dma_count); 12423 } 12424 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma); 12425 12426 bool kvm_arch_has_irq_bypass(void) 12427 { 12428 return true; 12429 } 12430 12431 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons, 12432 struct irq_bypass_producer *prod) 12433 { 12434 struct kvm_kernel_irqfd *irqfd = 12435 container_of(cons, struct kvm_kernel_irqfd, consumer); 12436 int ret; 12437 12438 irqfd->producer = prod; 12439 kvm_arch_start_assignment(irqfd->kvm); 12440 ret = static_call(kvm_x86_pi_update_irte)(irqfd->kvm, 12441 prod->irq, irqfd->gsi, 1); 12442 12443 if (ret) 12444 kvm_arch_end_assignment(irqfd->kvm); 12445 12446 return ret; 12447 } 12448 12449 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons, 12450 struct irq_bypass_producer *prod) 12451 { 12452 int ret; 12453 struct kvm_kernel_irqfd *irqfd = 12454 container_of(cons, struct kvm_kernel_irqfd, consumer); 12455 12456 WARN_ON(irqfd->producer != prod); 12457 irqfd->producer = NULL; 12458 12459 /* 12460 * When producer of consumer is unregistered, we change back to 12461 * remapped mode, so we can re-use the current implementation 12462 * when the irq is masked/disabled or the consumer side (KVM 12463 * int this case doesn't want to receive the interrupts. 12464 */ 12465 ret = static_call(kvm_x86_pi_update_irte)(irqfd->kvm, prod->irq, irqfd->gsi, 0); 12466 if (ret) 12467 printk(KERN_INFO "irq bypass consumer (token %p) unregistration" 12468 " fails: %d\n", irqfd->consumer.token, ret); 12469 12470 kvm_arch_end_assignment(irqfd->kvm); 12471 } 12472 12473 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq, 12474 uint32_t guest_irq, bool set) 12475 { 12476 return static_call(kvm_x86_pi_update_irte)(kvm, host_irq, guest_irq, set); 12477 } 12478 12479 bool kvm_arch_irqfd_route_changed(struct kvm_kernel_irq_routing_entry *old, 12480 struct kvm_kernel_irq_routing_entry *new) 12481 { 12482 if (new->type != KVM_IRQ_ROUTING_MSI) 12483 return true; 12484 12485 return !!memcmp(&old->msi, &new->msi, sizeof(new->msi)); 12486 } 12487 12488 bool kvm_vector_hashing_enabled(void) 12489 { 12490 return vector_hashing; 12491 } 12492 12493 bool kvm_arch_no_poll(struct kvm_vcpu *vcpu) 12494 { 12495 return (vcpu->arch.msr_kvm_poll_control & 1) == 0; 12496 } 12497 EXPORT_SYMBOL_GPL(kvm_arch_no_poll); 12498 12499 12500 int kvm_spec_ctrl_test_value(u64 value) 12501 { 12502 /* 12503 * test that setting IA32_SPEC_CTRL to given value 12504 * is allowed by the host processor 12505 */ 12506 12507 u64 saved_value; 12508 unsigned long flags; 12509 int ret = 0; 12510 12511 local_irq_save(flags); 12512 12513 if (rdmsrl_safe(MSR_IA32_SPEC_CTRL, &saved_value)) 12514 ret = 1; 12515 else if (wrmsrl_safe(MSR_IA32_SPEC_CTRL, value)) 12516 ret = 1; 12517 else 12518 wrmsrl(MSR_IA32_SPEC_CTRL, saved_value); 12519 12520 local_irq_restore(flags); 12521 12522 return ret; 12523 } 12524 EXPORT_SYMBOL_GPL(kvm_spec_ctrl_test_value); 12525 12526 void kvm_fixup_and_inject_pf_error(struct kvm_vcpu *vcpu, gva_t gva, u16 error_code) 12527 { 12528 struct kvm_mmu *mmu = vcpu->arch.walk_mmu; 12529 struct x86_exception fault; 12530 u32 access = error_code & 12531 (PFERR_WRITE_MASK | PFERR_FETCH_MASK | PFERR_USER_MASK); 12532 12533 if (!(error_code & PFERR_PRESENT_MASK) || 12534 mmu->gva_to_gpa(vcpu, mmu, gva, access, &fault) != UNMAPPED_GVA) { 12535 /* 12536 * If vcpu->arch.walk_mmu->gva_to_gpa succeeded, the page 12537 * tables probably do not match the TLB. Just proceed 12538 * with the error code that the processor gave. 12539 */ 12540 fault.vector = PF_VECTOR; 12541 fault.error_code_valid = true; 12542 fault.error_code = error_code; 12543 fault.nested_page_fault = false; 12544 fault.address = gva; 12545 } 12546 vcpu->arch.walk_mmu->inject_page_fault(vcpu, &fault); 12547 } 12548 EXPORT_SYMBOL_GPL(kvm_fixup_and_inject_pf_error); 12549 12550 /* 12551 * Handles kvm_read/write_guest_virt*() result and either injects #PF or returns 12552 * KVM_EXIT_INTERNAL_ERROR for cases not currently handled by KVM. Return value 12553 * indicates whether exit to userspace is needed. 12554 */ 12555 int kvm_handle_memory_failure(struct kvm_vcpu *vcpu, int r, 12556 struct x86_exception *e) 12557 { 12558 if (r == X86EMUL_PROPAGATE_FAULT) { 12559 kvm_inject_emulated_page_fault(vcpu, e); 12560 return 1; 12561 } 12562 12563 /* 12564 * In case kvm_read/write_guest_virt*() failed with X86EMUL_IO_NEEDED 12565 * while handling a VMX instruction KVM could've handled the request 12566 * correctly by exiting to userspace and performing I/O but there 12567 * doesn't seem to be a real use-case behind such requests, just return 12568 * KVM_EXIT_INTERNAL_ERROR for now. 12569 */ 12570 kvm_prepare_emulation_failure_exit(vcpu); 12571 12572 return 0; 12573 } 12574 EXPORT_SYMBOL_GPL(kvm_handle_memory_failure); 12575 12576 int kvm_handle_invpcid(struct kvm_vcpu *vcpu, unsigned long type, gva_t gva) 12577 { 12578 bool pcid_enabled; 12579 struct x86_exception e; 12580 struct { 12581 u64 pcid; 12582 u64 gla; 12583 } operand; 12584 int r; 12585 12586 r = kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e); 12587 if (r != X86EMUL_CONTINUE) 12588 return kvm_handle_memory_failure(vcpu, r, &e); 12589 12590 if (operand.pcid >> 12 != 0) { 12591 kvm_inject_gp(vcpu, 0); 12592 return 1; 12593 } 12594 12595 pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE); 12596 12597 switch (type) { 12598 case INVPCID_TYPE_INDIV_ADDR: 12599 if ((!pcid_enabled && (operand.pcid != 0)) || 12600 is_noncanonical_address(operand.gla, vcpu)) { 12601 kvm_inject_gp(vcpu, 0); 12602 return 1; 12603 } 12604 kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid); 12605 return kvm_skip_emulated_instruction(vcpu); 12606 12607 case INVPCID_TYPE_SINGLE_CTXT: 12608 if (!pcid_enabled && (operand.pcid != 0)) { 12609 kvm_inject_gp(vcpu, 0); 12610 return 1; 12611 } 12612 12613 kvm_invalidate_pcid(vcpu, operand.pcid); 12614 return kvm_skip_emulated_instruction(vcpu); 12615 12616 case INVPCID_TYPE_ALL_NON_GLOBAL: 12617 /* 12618 * Currently, KVM doesn't mark global entries in the shadow 12619 * page tables, so a non-global flush just degenerates to a 12620 * global flush. If needed, we could optimize this later by 12621 * keeping track of global entries in shadow page tables. 12622 */ 12623 12624 fallthrough; 12625 case INVPCID_TYPE_ALL_INCL_GLOBAL: 12626 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu); 12627 return kvm_skip_emulated_instruction(vcpu); 12628 12629 default: 12630 kvm_inject_gp(vcpu, 0); 12631 return 1; 12632 } 12633 } 12634 EXPORT_SYMBOL_GPL(kvm_handle_invpcid); 12635 12636 static int complete_sev_es_emulated_mmio(struct kvm_vcpu *vcpu) 12637 { 12638 struct kvm_run *run = vcpu->run; 12639 struct kvm_mmio_fragment *frag; 12640 unsigned int len; 12641 12642 BUG_ON(!vcpu->mmio_needed); 12643 12644 /* Complete previous fragment */ 12645 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment]; 12646 len = min(8u, frag->len); 12647 if (!vcpu->mmio_is_write) 12648 memcpy(frag->data, run->mmio.data, len); 12649 12650 if (frag->len <= 8) { 12651 /* Switch to the next fragment. */ 12652 frag++; 12653 vcpu->mmio_cur_fragment++; 12654 } else { 12655 /* Go forward to the next mmio piece. */ 12656 frag->data += len; 12657 frag->gpa += len; 12658 frag->len -= len; 12659 } 12660 12661 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) { 12662 vcpu->mmio_needed = 0; 12663 12664 // VMG change, at this point, we're always done 12665 // RIP has already been advanced 12666 return 1; 12667 } 12668 12669 // More MMIO is needed 12670 run->mmio.phys_addr = frag->gpa; 12671 run->mmio.len = min(8u, frag->len); 12672 run->mmio.is_write = vcpu->mmio_is_write; 12673 if (run->mmio.is_write) 12674 memcpy(run->mmio.data, frag->data, min(8u, frag->len)); 12675 run->exit_reason = KVM_EXIT_MMIO; 12676 12677 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio; 12678 12679 return 0; 12680 } 12681 12682 int kvm_sev_es_mmio_write(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned int bytes, 12683 void *data) 12684 { 12685 int handled; 12686 struct kvm_mmio_fragment *frag; 12687 12688 if (!data) 12689 return -EINVAL; 12690 12691 handled = write_emultor.read_write_mmio(vcpu, gpa, bytes, data); 12692 if (handled == bytes) 12693 return 1; 12694 12695 bytes -= handled; 12696 gpa += handled; 12697 data += handled; 12698 12699 /*TODO: Check if need to increment number of frags */ 12700 frag = vcpu->mmio_fragments; 12701 vcpu->mmio_nr_fragments = 1; 12702 frag->len = bytes; 12703 frag->gpa = gpa; 12704 frag->data = data; 12705 12706 vcpu->mmio_needed = 1; 12707 vcpu->mmio_cur_fragment = 0; 12708 12709 vcpu->run->mmio.phys_addr = gpa; 12710 vcpu->run->mmio.len = min(8u, frag->len); 12711 vcpu->run->mmio.is_write = 1; 12712 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len)); 12713 vcpu->run->exit_reason = KVM_EXIT_MMIO; 12714 12715 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio; 12716 12717 return 0; 12718 } 12719 EXPORT_SYMBOL_GPL(kvm_sev_es_mmio_write); 12720 12721 int kvm_sev_es_mmio_read(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned int bytes, 12722 void *data) 12723 { 12724 int handled; 12725 struct kvm_mmio_fragment *frag; 12726 12727 if (!data) 12728 return -EINVAL; 12729 12730 handled = read_emultor.read_write_mmio(vcpu, gpa, bytes, data); 12731 if (handled == bytes) 12732 return 1; 12733 12734 bytes -= handled; 12735 gpa += handled; 12736 data += handled; 12737 12738 /*TODO: Check if need to increment number of frags */ 12739 frag = vcpu->mmio_fragments; 12740 vcpu->mmio_nr_fragments = 1; 12741 frag->len = bytes; 12742 frag->gpa = gpa; 12743 frag->data = data; 12744 12745 vcpu->mmio_needed = 1; 12746 vcpu->mmio_cur_fragment = 0; 12747 12748 vcpu->run->mmio.phys_addr = gpa; 12749 vcpu->run->mmio.len = min(8u, frag->len); 12750 vcpu->run->mmio.is_write = 0; 12751 vcpu->run->exit_reason = KVM_EXIT_MMIO; 12752 12753 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio; 12754 12755 return 0; 12756 } 12757 EXPORT_SYMBOL_GPL(kvm_sev_es_mmio_read); 12758 12759 static int kvm_sev_es_outs(struct kvm_vcpu *vcpu, unsigned int size, 12760 unsigned int port); 12761 12762 static int complete_sev_es_emulated_outs(struct kvm_vcpu *vcpu) 12763 { 12764 int size = vcpu->arch.pio.size; 12765 int port = vcpu->arch.pio.port; 12766 12767 vcpu->arch.pio.count = 0; 12768 if (vcpu->arch.sev_pio_count) 12769 return kvm_sev_es_outs(vcpu, size, port); 12770 return 1; 12771 } 12772 12773 static int kvm_sev_es_outs(struct kvm_vcpu *vcpu, unsigned int size, 12774 unsigned int port) 12775 { 12776 for (;;) { 12777 unsigned int count = 12778 min_t(unsigned int, PAGE_SIZE / size, vcpu->arch.sev_pio_count); 12779 int ret = emulator_pio_out(vcpu, size, port, vcpu->arch.sev_pio_data, count); 12780 12781 /* memcpy done already by emulator_pio_out. */ 12782 vcpu->arch.sev_pio_count -= count; 12783 vcpu->arch.sev_pio_data += count * vcpu->arch.pio.size; 12784 if (!ret) 12785 break; 12786 12787 /* Emulation done by the kernel. */ 12788 if (!vcpu->arch.sev_pio_count) 12789 return 1; 12790 } 12791 12792 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_outs; 12793 return 0; 12794 } 12795 12796 static int kvm_sev_es_ins(struct kvm_vcpu *vcpu, unsigned int size, 12797 unsigned int port); 12798 12799 static void advance_sev_es_emulated_ins(struct kvm_vcpu *vcpu) 12800 { 12801 unsigned count = vcpu->arch.pio.count; 12802 complete_emulator_pio_in(vcpu, vcpu->arch.sev_pio_data); 12803 vcpu->arch.sev_pio_count -= count; 12804 vcpu->arch.sev_pio_data += count * vcpu->arch.pio.size; 12805 } 12806 12807 static int complete_sev_es_emulated_ins(struct kvm_vcpu *vcpu) 12808 { 12809 int size = vcpu->arch.pio.size; 12810 int port = vcpu->arch.pio.port; 12811 12812 advance_sev_es_emulated_ins(vcpu); 12813 if (vcpu->arch.sev_pio_count) 12814 return kvm_sev_es_ins(vcpu, size, port); 12815 return 1; 12816 } 12817 12818 static int kvm_sev_es_ins(struct kvm_vcpu *vcpu, unsigned int size, 12819 unsigned int port) 12820 { 12821 for (;;) { 12822 unsigned int count = 12823 min_t(unsigned int, PAGE_SIZE / size, vcpu->arch.sev_pio_count); 12824 if (!__emulator_pio_in(vcpu, size, port, count)) 12825 break; 12826 12827 /* Emulation done by the kernel. */ 12828 advance_sev_es_emulated_ins(vcpu); 12829 if (!vcpu->arch.sev_pio_count) 12830 return 1; 12831 } 12832 12833 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_ins; 12834 return 0; 12835 } 12836 12837 int kvm_sev_es_string_io(struct kvm_vcpu *vcpu, unsigned int size, 12838 unsigned int port, void *data, unsigned int count, 12839 int in) 12840 { 12841 vcpu->arch.sev_pio_data = data; 12842 vcpu->arch.sev_pio_count = count; 12843 return in ? kvm_sev_es_ins(vcpu, size, port) 12844 : kvm_sev_es_outs(vcpu, size, port); 12845 } 12846 EXPORT_SYMBOL_GPL(kvm_sev_es_string_io); 12847 12848 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_entry); 12849 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit); 12850 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio); 12851 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq); 12852 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault); 12853 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr); 12854 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr); 12855 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun); 12856 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit); 12857 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject); 12858 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit); 12859 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmenter_failed); 12860 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga); 12861 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit); 12862 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts); 12863 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset); 12864 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window_update); 12865 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full); 12866 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update); 12867 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access); 12868 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi); 12869 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_ga_log); 12870 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_apicv_update_request); 12871 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_apicv_accept_irq); 12872 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_enter); 12873 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_exit); 12874 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_enter); 12875 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_exit); 12876