xref: /openbmc/linux/arch/x86/kvm/x86.c (revision b51012deb390528d89d426f328d84618683f5d73)
1 /*
2  * Kernel-based Virtual Machine driver for Linux
3  *
4  * derived from drivers/kvm/kvm_main.c
5  *
6  * Copyright (C) 2006 Qumranet, Inc.
7  * Copyright (C) 2008 Qumranet, Inc.
8  * Copyright IBM Corporation, 2008
9  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
10  *
11  * Authors:
12  *   Avi Kivity   <avi@qumranet.com>
13  *   Yaniv Kamay  <yaniv@qumranet.com>
14  *   Amit Shah    <amit.shah@qumranet.com>
15  *   Ben-Ami Yassour <benami@il.ibm.com>
16  *
17  * This work is licensed under the terms of the GNU GPL, version 2.  See
18  * the COPYING file in the top-level directory.
19  *
20  */
21 
22 #include <linux/kvm_host.h>
23 #include "irq.h"
24 #include "mmu.h"
25 #include "i8254.h"
26 #include "tss.h"
27 #include "kvm_cache_regs.h"
28 #include "x86.h"
29 #include "cpuid.h"
30 #include "assigned-dev.h"
31 #include "pmu.h"
32 #include "hyperv.h"
33 
34 #include <linux/clocksource.h>
35 #include <linux/interrupt.h>
36 #include <linux/kvm.h>
37 #include <linux/fs.h>
38 #include <linux/vmalloc.h>
39 #include <linux/module.h>
40 #include <linux/mman.h>
41 #include <linux/highmem.h>
42 #include <linux/iommu.h>
43 #include <linux/intel-iommu.h>
44 #include <linux/cpufreq.h>
45 #include <linux/user-return-notifier.h>
46 #include <linux/srcu.h>
47 #include <linux/slab.h>
48 #include <linux/perf_event.h>
49 #include <linux/uaccess.h>
50 #include <linux/hash.h>
51 #include <linux/pci.h>
52 #include <linux/timekeeper_internal.h>
53 #include <linux/pvclock_gtod.h>
54 #include <linux/kvm_irqfd.h>
55 #include <linux/irqbypass.h>
56 #include <trace/events/kvm.h>
57 
58 #define CREATE_TRACE_POINTS
59 #include "trace.h"
60 
61 #include <asm/debugreg.h>
62 #include <asm/msr.h>
63 #include <asm/desc.h>
64 #include <asm/mce.h>
65 #include <linux/kernel_stat.h>
66 #include <asm/fpu/internal.h> /* Ugh! */
67 #include <asm/pvclock.h>
68 #include <asm/div64.h>
69 #include <asm/irq_remapping.h>
70 
71 #define MAX_IO_MSRS 256
72 #define KVM_MAX_MCE_BANKS 32
73 #define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
74 
75 #define emul_to_vcpu(ctxt) \
76 	container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
77 
78 /* EFER defaults:
79  * - enable syscall per default because its emulated by KVM
80  * - enable LME and LMA per default on 64 bit KVM
81  */
82 #ifdef CONFIG_X86_64
83 static
84 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
85 #else
86 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
87 #endif
88 
89 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
90 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
91 
92 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
93 static void process_nmi(struct kvm_vcpu *vcpu);
94 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
95 
96 struct kvm_x86_ops *kvm_x86_ops __read_mostly;
97 EXPORT_SYMBOL_GPL(kvm_x86_ops);
98 
99 static bool __read_mostly ignore_msrs = 0;
100 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
101 
102 unsigned int min_timer_period_us = 500;
103 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
104 
105 static bool __read_mostly kvmclock_periodic_sync = true;
106 module_param(kvmclock_periodic_sync, bool, S_IRUGO);
107 
108 bool __read_mostly kvm_has_tsc_control;
109 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
110 u32  __read_mostly kvm_max_guest_tsc_khz;
111 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
112 u8   __read_mostly kvm_tsc_scaling_ratio_frac_bits;
113 EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
114 u64  __read_mostly kvm_max_tsc_scaling_ratio;
115 EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
116 static u64 __read_mostly kvm_default_tsc_scaling_ratio;
117 
118 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
119 static u32 __read_mostly tsc_tolerance_ppm = 250;
120 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
121 
122 /* lapic timer advance (tscdeadline mode only) in nanoseconds */
123 unsigned int __read_mostly lapic_timer_advance_ns = 0;
124 module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
125 
126 static bool __read_mostly backwards_tsc_observed = false;
127 
128 #define KVM_NR_SHARED_MSRS 16
129 
130 struct kvm_shared_msrs_global {
131 	int nr;
132 	u32 msrs[KVM_NR_SHARED_MSRS];
133 };
134 
135 struct kvm_shared_msrs {
136 	struct user_return_notifier urn;
137 	bool registered;
138 	struct kvm_shared_msr_values {
139 		u64 host;
140 		u64 curr;
141 	} values[KVM_NR_SHARED_MSRS];
142 };
143 
144 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
145 static struct kvm_shared_msrs __percpu *shared_msrs;
146 
147 struct kvm_stats_debugfs_item debugfs_entries[] = {
148 	{ "pf_fixed", VCPU_STAT(pf_fixed) },
149 	{ "pf_guest", VCPU_STAT(pf_guest) },
150 	{ "tlb_flush", VCPU_STAT(tlb_flush) },
151 	{ "invlpg", VCPU_STAT(invlpg) },
152 	{ "exits", VCPU_STAT(exits) },
153 	{ "io_exits", VCPU_STAT(io_exits) },
154 	{ "mmio_exits", VCPU_STAT(mmio_exits) },
155 	{ "signal_exits", VCPU_STAT(signal_exits) },
156 	{ "irq_window", VCPU_STAT(irq_window_exits) },
157 	{ "nmi_window", VCPU_STAT(nmi_window_exits) },
158 	{ "halt_exits", VCPU_STAT(halt_exits) },
159 	{ "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
160 	{ "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
161 	{ "halt_wakeup", VCPU_STAT(halt_wakeup) },
162 	{ "hypercalls", VCPU_STAT(hypercalls) },
163 	{ "request_irq", VCPU_STAT(request_irq_exits) },
164 	{ "irq_exits", VCPU_STAT(irq_exits) },
165 	{ "host_state_reload", VCPU_STAT(host_state_reload) },
166 	{ "efer_reload", VCPU_STAT(efer_reload) },
167 	{ "fpu_reload", VCPU_STAT(fpu_reload) },
168 	{ "insn_emulation", VCPU_STAT(insn_emulation) },
169 	{ "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
170 	{ "irq_injections", VCPU_STAT(irq_injections) },
171 	{ "nmi_injections", VCPU_STAT(nmi_injections) },
172 	{ "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
173 	{ "mmu_pte_write", VM_STAT(mmu_pte_write) },
174 	{ "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
175 	{ "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
176 	{ "mmu_flooded", VM_STAT(mmu_flooded) },
177 	{ "mmu_recycled", VM_STAT(mmu_recycled) },
178 	{ "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
179 	{ "mmu_unsync", VM_STAT(mmu_unsync) },
180 	{ "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
181 	{ "largepages", VM_STAT(lpages) },
182 	{ NULL }
183 };
184 
185 u64 __read_mostly host_xcr0;
186 
187 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
188 
189 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
190 {
191 	int i;
192 	for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
193 		vcpu->arch.apf.gfns[i] = ~0;
194 }
195 
196 static void kvm_on_user_return(struct user_return_notifier *urn)
197 {
198 	unsigned slot;
199 	struct kvm_shared_msrs *locals
200 		= container_of(urn, struct kvm_shared_msrs, urn);
201 	struct kvm_shared_msr_values *values;
202 
203 	for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
204 		values = &locals->values[slot];
205 		if (values->host != values->curr) {
206 			wrmsrl(shared_msrs_global.msrs[slot], values->host);
207 			values->curr = values->host;
208 		}
209 	}
210 	locals->registered = false;
211 	user_return_notifier_unregister(urn);
212 }
213 
214 static void shared_msr_update(unsigned slot, u32 msr)
215 {
216 	u64 value;
217 	unsigned int cpu = smp_processor_id();
218 	struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
219 
220 	/* only read, and nobody should modify it at this time,
221 	 * so don't need lock */
222 	if (slot >= shared_msrs_global.nr) {
223 		printk(KERN_ERR "kvm: invalid MSR slot!");
224 		return;
225 	}
226 	rdmsrl_safe(msr, &value);
227 	smsr->values[slot].host = value;
228 	smsr->values[slot].curr = value;
229 }
230 
231 void kvm_define_shared_msr(unsigned slot, u32 msr)
232 {
233 	BUG_ON(slot >= KVM_NR_SHARED_MSRS);
234 	shared_msrs_global.msrs[slot] = msr;
235 	if (slot >= shared_msrs_global.nr)
236 		shared_msrs_global.nr = slot + 1;
237 }
238 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
239 
240 static void kvm_shared_msr_cpu_online(void)
241 {
242 	unsigned i;
243 
244 	for (i = 0; i < shared_msrs_global.nr; ++i)
245 		shared_msr_update(i, shared_msrs_global.msrs[i]);
246 }
247 
248 int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
249 {
250 	unsigned int cpu = smp_processor_id();
251 	struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
252 	int err;
253 
254 	if (((value ^ smsr->values[slot].curr) & mask) == 0)
255 		return 0;
256 	smsr->values[slot].curr = value;
257 	err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
258 	if (err)
259 		return 1;
260 
261 	if (!smsr->registered) {
262 		smsr->urn.on_user_return = kvm_on_user_return;
263 		user_return_notifier_register(&smsr->urn);
264 		smsr->registered = true;
265 	}
266 	return 0;
267 }
268 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
269 
270 static void drop_user_return_notifiers(void)
271 {
272 	unsigned int cpu = smp_processor_id();
273 	struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
274 
275 	if (smsr->registered)
276 		kvm_on_user_return(&smsr->urn);
277 }
278 
279 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
280 {
281 	return vcpu->arch.apic_base;
282 }
283 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
284 
285 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
286 {
287 	u64 old_state = vcpu->arch.apic_base &
288 		(MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
289 	u64 new_state = msr_info->data &
290 		(MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
291 	u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
292 		0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
293 
294 	if (!msr_info->host_initiated &&
295 	    ((msr_info->data & reserved_bits) != 0 ||
296 	     new_state == X2APIC_ENABLE ||
297 	     (new_state == MSR_IA32_APICBASE_ENABLE &&
298 	      old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
299 	     (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
300 	      old_state == 0)))
301 		return 1;
302 
303 	kvm_lapic_set_base(vcpu, msr_info->data);
304 	return 0;
305 }
306 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
307 
308 asmlinkage __visible void kvm_spurious_fault(void)
309 {
310 	/* Fault while not rebooting.  We want the trace. */
311 	BUG();
312 }
313 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
314 
315 #define EXCPT_BENIGN		0
316 #define EXCPT_CONTRIBUTORY	1
317 #define EXCPT_PF		2
318 
319 static int exception_class(int vector)
320 {
321 	switch (vector) {
322 	case PF_VECTOR:
323 		return EXCPT_PF;
324 	case DE_VECTOR:
325 	case TS_VECTOR:
326 	case NP_VECTOR:
327 	case SS_VECTOR:
328 	case GP_VECTOR:
329 		return EXCPT_CONTRIBUTORY;
330 	default:
331 		break;
332 	}
333 	return EXCPT_BENIGN;
334 }
335 
336 #define EXCPT_FAULT		0
337 #define EXCPT_TRAP		1
338 #define EXCPT_ABORT		2
339 #define EXCPT_INTERRUPT		3
340 
341 static int exception_type(int vector)
342 {
343 	unsigned int mask;
344 
345 	if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
346 		return EXCPT_INTERRUPT;
347 
348 	mask = 1 << vector;
349 
350 	/* #DB is trap, as instruction watchpoints are handled elsewhere */
351 	if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
352 		return EXCPT_TRAP;
353 
354 	if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
355 		return EXCPT_ABORT;
356 
357 	/* Reserved exceptions will result in fault */
358 	return EXCPT_FAULT;
359 }
360 
361 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
362 		unsigned nr, bool has_error, u32 error_code,
363 		bool reinject)
364 {
365 	u32 prev_nr;
366 	int class1, class2;
367 
368 	kvm_make_request(KVM_REQ_EVENT, vcpu);
369 
370 	if (!vcpu->arch.exception.pending) {
371 	queue:
372 		if (has_error && !is_protmode(vcpu))
373 			has_error = false;
374 		vcpu->arch.exception.pending = true;
375 		vcpu->arch.exception.has_error_code = has_error;
376 		vcpu->arch.exception.nr = nr;
377 		vcpu->arch.exception.error_code = error_code;
378 		vcpu->arch.exception.reinject = reinject;
379 		return;
380 	}
381 
382 	/* to check exception */
383 	prev_nr = vcpu->arch.exception.nr;
384 	if (prev_nr == DF_VECTOR) {
385 		/* triple fault -> shutdown */
386 		kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
387 		return;
388 	}
389 	class1 = exception_class(prev_nr);
390 	class2 = exception_class(nr);
391 	if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
392 		|| (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
393 		/* generate double fault per SDM Table 5-5 */
394 		vcpu->arch.exception.pending = true;
395 		vcpu->arch.exception.has_error_code = true;
396 		vcpu->arch.exception.nr = DF_VECTOR;
397 		vcpu->arch.exception.error_code = 0;
398 	} else
399 		/* replace previous exception with a new one in a hope
400 		   that instruction re-execution will regenerate lost
401 		   exception */
402 		goto queue;
403 }
404 
405 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
406 {
407 	kvm_multiple_exception(vcpu, nr, false, 0, false);
408 }
409 EXPORT_SYMBOL_GPL(kvm_queue_exception);
410 
411 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
412 {
413 	kvm_multiple_exception(vcpu, nr, false, 0, true);
414 }
415 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
416 
417 void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
418 {
419 	if (err)
420 		kvm_inject_gp(vcpu, 0);
421 	else
422 		kvm_x86_ops->skip_emulated_instruction(vcpu);
423 }
424 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
425 
426 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
427 {
428 	++vcpu->stat.pf_guest;
429 	vcpu->arch.cr2 = fault->address;
430 	kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
431 }
432 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
433 
434 static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
435 {
436 	if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
437 		vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
438 	else
439 		vcpu->arch.mmu.inject_page_fault(vcpu, fault);
440 
441 	return fault->nested_page_fault;
442 }
443 
444 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
445 {
446 	atomic_inc(&vcpu->arch.nmi_queued);
447 	kvm_make_request(KVM_REQ_NMI, vcpu);
448 }
449 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
450 
451 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
452 {
453 	kvm_multiple_exception(vcpu, nr, true, error_code, false);
454 }
455 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
456 
457 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
458 {
459 	kvm_multiple_exception(vcpu, nr, true, error_code, true);
460 }
461 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
462 
463 /*
464  * Checks if cpl <= required_cpl; if true, return true.  Otherwise queue
465  * a #GP and return false.
466  */
467 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
468 {
469 	if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
470 		return true;
471 	kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
472 	return false;
473 }
474 EXPORT_SYMBOL_GPL(kvm_require_cpl);
475 
476 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
477 {
478 	if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
479 		return true;
480 
481 	kvm_queue_exception(vcpu, UD_VECTOR);
482 	return false;
483 }
484 EXPORT_SYMBOL_GPL(kvm_require_dr);
485 
486 /*
487  * This function will be used to read from the physical memory of the currently
488  * running guest. The difference to kvm_vcpu_read_guest_page is that this function
489  * can read from guest physical or from the guest's guest physical memory.
490  */
491 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
492 			    gfn_t ngfn, void *data, int offset, int len,
493 			    u32 access)
494 {
495 	struct x86_exception exception;
496 	gfn_t real_gfn;
497 	gpa_t ngpa;
498 
499 	ngpa     = gfn_to_gpa(ngfn);
500 	real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
501 	if (real_gfn == UNMAPPED_GVA)
502 		return -EFAULT;
503 
504 	real_gfn = gpa_to_gfn(real_gfn);
505 
506 	return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
507 }
508 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
509 
510 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
511 			       void *data, int offset, int len, u32 access)
512 {
513 	return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
514 				       data, offset, len, access);
515 }
516 
517 /*
518  * Load the pae pdptrs.  Return true is they are all valid.
519  */
520 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
521 {
522 	gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
523 	unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
524 	int i;
525 	int ret;
526 	u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
527 
528 	ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
529 				      offset * sizeof(u64), sizeof(pdpte),
530 				      PFERR_USER_MASK|PFERR_WRITE_MASK);
531 	if (ret < 0) {
532 		ret = 0;
533 		goto out;
534 	}
535 	for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
536 		if (is_present_gpte(pdpte[i]) &&
537 		    (pdpte[i] &
538 		     vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
539 			ret = 0;
540 			goto out;
541 		}
542 	}
543 	ret = 1;
544 
545 	memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
546 	__set_bit(VCPU_EXREG_PDPTR,
547 		  (unsigned long *)&vcpu->arch.regs_avail);
548 	__set_bit(VCPU_EXREG_PDPTR,
549 		  (unsigned long *)&vcpu->arch.regs_dirty);
550 out:
551 
552 	return ret;
553 }
554 EXPORT_SYMBOL_GPL(load_pdptrs);
555 
556 static bool pdptrs_changed(struct kvm_vcpu *vcpu)
557 {
558 	u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
559 	bool changed = true;
560 	int offset;
561 	gfn_t gfn;
562 	int r;
563 
564 	if (is_long_mode(vcpu) || !is_pae(vcpu))
565 		return false;
566 
567 	if (!test_bit(VCPU_EXREG_PDPTR,
568 		      (unsigned long *)&vcpu->arch.regs_avail))
569 		return true;
570 
571 	gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
572 	offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
573 	r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
574 				       PFERR_USER_MASK | PFERR_WRITE_MASK);
575 	if (r < 0)
576 		goto out;
577 	changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
578 out:
579 
580 	return changed;
581 }
582 
583 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
584 {
585 	unsigned long old_cr0 = kvm_read_cr0(vcpu);
586 	unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
587 
588 	cr0 |= X86_CR0_ET;
589 
590 #ifdef CONFIG_X86_64
591 	if (cr0 & 0xffffffff00000000UL)
592 		return 1;
593 #endif
594 
595 	cr0 &= ~CR0_RESERVED_BITS;
596 
597 	if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
598 		return 1;
599 
600 	if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
601 		return 1;
602 
603 	if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
604 #ifdef CONFIG_X86_64
605 		if ((vcpu->arch.efer & EFER_LME)) {
606 			int cs_db, cs_l;
607 
608 			if (!is_pae(vcpu))
609 				return 1;
610 			kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
611 			if (cs_l)
612 				return 1;
613 		} else
614 #endif
615 		if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
616 						 kvm_read_cr3(vcpu)))
617 			return 1;
618 	}
619 
620 	if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
621 		return 1;
622 
623 	kvm_x86_ops->set_cr0(vcpu, cr0);
624 
625 	if ((cr0 ^ old_cr0) & X86_CR0_PG) {
626 		kvm_clear_async_pf_completion_queue(vcpu);
627 		kvm_async_pf_hash_reset(vcpu);
628 	}
629 
630 	if ((cr0 ^ old_cr0) & update_bits)
631 		kvm_mmu_reset_context(vcpu);
632 
633 	if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
634 	    kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
635 	    !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
636 		kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
637 
638 	return 0;
639 }
640 EXPORT_SYMBOL_GPL(kvm_set_cr0);
641 
642 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
643 {
644 	(void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
645 }
646 EXPORT_SYMBOL_GPL(kvm_lmsw);
647 
648 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
649 {
650 	if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
651 			!vcpu->guest_xcr0_loaded) {
652 		/* kvm_set_xcr() also depends on this */
653 		xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
654 		vcpu->guest_xcr0_loaded = 1;
655 	}
656 }
657 
658 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
659 {
660 	if (vcpu->guest_xcr0_loaded) {
661 		if (vcpu->arch.xcr0 != host_xcr0)
662 			xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
663 		vcpu->guest_xcr0_loaded = 0;
664 	}
665 }
666 
667 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
668 {
669 	u64 xcr0 = xcr;
670 	u64 old_xcr0 = vcpu->arch.xcr0;
671 	u64 valid_bits;
672 
673 	/* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now  */
674 	if (index != XCR_XFEATURE_ENABLED_MASK)
675 		return 1;
676 	if (!(xcr0 & XFEATURE_MASK_FP))
677 		return 1;
678 	if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
679 		return 1;
680 
681 	/*
682 	 * Do not allow the guest to set bits that we do not support
683 	 * saving.  However, xcr0 bit 0 is always set, even if the
684 	 * emulated CPU does not support XSAVE (see fx_init).
685 	 */
686 	valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
687 	if (xcr0 & ~valid_bits)
688 		return 1;
689 
690 	if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
691 	    (!(xcr0 & XFEATURE_MASK_BNDCSR)))
692 		return 1;
693 
694 	if (xcr0 & XFEATURE_MASK_AVX512) {
695 		if (!(xcr0 & XFEATURE_MASK_YMM))
696 			return 1;
697 		if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
698 			return 1;
699 	}
700 	kvm_put_guest_xcr0(vcpu);
701 	vcpu->arch.xcr0 = xcr0;
702 
703 	if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
704 		kvm_update_cpuid(vcpu);
705 	return 0;
706 }
707 
708 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
709 {
710 	if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
711 	    __kvm_set_xcr(vcpu, index, xcr)) {
712 		kvm_inject_gp(vcpu, 0);
713 		return 1;
714 	}
715 	return 0;
716 }
717 EXPORT_SYMBOL_GPL(kvm_set_xcr);
718 
719 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
720 {
721 	unsigned long old_cr4 = kvm_read_cr4(vcpu);
722 	unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
723 				   X86_CR4_SMEP | X86_CR4_SMAP;
724 
725 	if (cr4 & CR4_RESERVED_BITS)
726 		return 1;
727 
728 	if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
729 		return 1;
730 
731 	if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
732 		return 1;
733 
734 	if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
735 		return 1;
736 
737 	if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
738 		return 1;
739 
740 	if (is_long_mode(vcpu)) {
741 		if (!(cr4 & X86_CR4_PAE))
742 			return 1;
743 	} else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
744 		   && ((cr4 ^ old_cr4) & pdptr_bits)
745 		   && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
746 				   kvm_read_cr3(vcpu)))
747 		return 1;
748 
749 	if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
750 		if (!guest_cpuid_has_pcid(vcpu))
751 			return 1;
752 
753 		/* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
754 		if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
755 			return 1;
756 	}
757 
758 	if (kvm_x86_ops->set_cr4(vcpu, cr4))
759 		return 1;
760 
761 	if (((cr4 ^ old_cr4) & pdptr_bits) ||
762 	    (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
763 		kvm_mmu_reset_context(vcpu);
764 
765 	if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
766 		kvm_update_cpuid(vcpu);
767 
768 	return 0;
769 }
770 EXPORT_SYMBOL_GPL(kvm_set_cr4);
771 
772 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
773 {
774 #ifdef CONFIG_X86_64
775 	cr3 &= ~CR3_PCID_INVD;
776 #endif
777 
778 	if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
779 		kvm_mmu_sync_roots(vcpu);
780 		kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
781 		return 0;
782 	}
783 
784 	if (is_long_mode(vcpu)) {
785 		if (cr3 & CR3_L_MODE_RESERVED_BITS)
786 			return 1;
787 	} else if (is_pae(vcpu) && is_paging(vcpu) &&
788 		   !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
789 		return 1;
790 
791 	vcpu->arch.cr3 = cr3;
792 	__set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
793 	kvm_mmu_new_cr3(vcpu);
794 	return 0;
795 }
796 EXPORT_SYMBOL_GPL(kvm_set_cr3);
797 
798 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
799 {
800 	if (cr8 & CR8_RESERVED_BITS)
801 		return 1;
802 	if (lapic_in_kernel(vcpu))
803 		kvm_lapic_set_tpr(vcpu, cr8);
804 	else
805 		vcpu->arch.cr8 = cr8;
806 	return 0;
807 }
808 EXPORT_SYMBOL_GPL(kvm_set_cr8);
809 
810 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
811 {
812 	if (lapic_in_kernel(vcpu))
813 		return kvm_lapic_get_cr8(vcpu);
814 	else
815 		return vcpu->arch.cr8;
816 }
817 EXPORT_SYMBOL_GPL(kvm_get_cr8);
818 
819 static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
820 {
821 	int i;
822 
823 	if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
824 		for (i = 0; i < KVM_NR_DB_REGS; i++)
825 			vcpu->arch.eff_db[i] = vcpu->arch.db[i];
826 		vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
827 	}
828 }
829 
830 static void kvm_update_dr6(struct kvm_vcpu *vcpu)
831 {
832 	if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
833 		kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
834 }
835 
836 static void kvm_update_dr7(struct kvm_vcpu *vcpu)
837 {
838 	unsigned long dr7;
839 
840 	if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
841 		dr7 = vcpu->arch.guest_debug_dr7;
842 	else
843 		dr7 = vcpu->arch.dr7;
844 	kvm_x86_ops->set_dr7(vcpu, dr7);
845 	vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
846 	if (dr7 & DR7_BP_EN_MASK)
847 		vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
848 }
849 
850 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
851 {
852 	u64 fixed = DR6_FIXED_1;
853 
854 	if (!guest_cpuid_has_rtm(vcpu))
855 		fixed |= DR6_RTM;
856 	return fixed;
857 }
858 
859 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
860 {
861 	switch (dr) {
862 	case 0 ... 3:
863 		vcpu->arch.db[dr] = val;
864 		if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
865 			vcpu->arch.eff_db[dr] = val;
866 		break;
867 	case 4:
868 		/* fall through */
869 	case 6:
870 		if (val & 0xffffffff00000000ULL)
871 			return -1; /* #GP */
872 		vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
873 		kvm_update_dr6(vcpu);
874 		break;
875 	case 5:
876 		/* fall through */
877 	default: /* 7 */
878 		if (val & 0xffffffff00000000ULL)
879 			return -1; /* #GP */
880 		vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
881 		kvm_update_dr7(vcpu);
882 		break;
883 	}
884 
885 	return 0;
886 }
887 
888 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
889 {
890 	if (__kvm_set_dr(vcpu, dr, val)) {
891 		kvm_inject_gp(vcpu, 0);
892 		return 1;
893 	}
894 	return 0;
895 }
896 EXPORT_SYMBOL_GPL(kvm_set_dr);
897 
898 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
899 {
900 	switch (dr) {
901 	case 0 ... 3:
902 		*val = vcpu->arch.db[dr];
903 		break;
904 	case 4:
905 		/* fall through */
906 	case 6:
907 		if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
908 			*val = vcpu->arch.dr6;
909 		else
910 			*val = kvm_x86_ops->get_dr6(vcpu);
911 		break;
912 	case 5:
913 		/* fall through */
914 	default: /* 7 */
915 		*val = vcpu->arch.dr7;
916 		break;
917 	}
918 	return 0;
919 }
920 EXPORT_SYMBOL_GPL(kvm_get_dr);
921 
922 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
923 {
924 	u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
925 	u64 data;
926 	int err;
927 
928 	err = kvm_pmu_rdpmc(vcpu, ecx, &data);
929 	if (err)
930 		return err;
931 	kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
932 	kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
933 	return err;
934 }
935 EXPORT_SYMBOL_GPL(kvm_rdpmc);
936 
937 /*
938  * List of msr numbers which we expose to userspace through KVM_GET_MSRS
939  * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
940  *
941  * This list is modified at module load time to reflect the
942  * capabilities of the host cpu. This capabilities test skips MSRs that are
943  * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
944  * may depend on host virtualization features rather than host cpu features.
945  */
946 
947 static u32 msrs_to_save[] = {
948 	MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
949 	MSR_STAR,
950 #ifdef CONFIG_X86_64
951 	MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
952 #endif
953 	MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
954 	MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
955 };
956 
957 static unsigned num_msrs_to_save;
958 
959 static u32 emulated_msrs[] = {
960 	MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
961 	MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
962 	HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
963 	HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
964 	HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
965 	HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
966 	HV_X64_MSR_RESET,
967 	HV_X64_MSR_VP_INDEX,
968 	HV_X64_MSR_VP_RUNTIME,
969 	HV_X64_MSR_SCONTROL,
970 	HV_X64_MSR_STIMER0_CONFIG,
971 	HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
972 	MSR_KVM_PV_EOI_EN,
973 
974 	MSR_IA32_TSC_ADJUST,
975 	MSR_IA32_TSCDEADLINE,
976 	MSR_IA32_MISC_ENABLE,
977 	MSR_IA32_MCG_STATUS,
978 	MSR_IA32_MCG_CTL,
979 	MSR_IA32_SMBASE,
980 };
981 
982 static unsigned num_emulated_msrs;
983 
984 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
985 {
986 	if (efer & efer_reserved_bits)
987 		return false;
988 
989 	if (efer & EFER_FFXSR) {
990 		struct kvm_cpuid_entry2 *feat;
991 
992 		feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
993 		if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
994 			return false;
995 	}
996 
997 	if (efer & EFER_SVME) {
998 		struct kvm_cpuid_entry2 *feat;
999 
1000 		feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
1001 		if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
1002 			return false;
1003 	}
1004 
1005 	return true;
1006 }
1007 EXPORT_SYMBOL_GPL(kvm_valid_efer);
1008 
1009 static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1010 {
1011 	u64 old_efer = vcpu->arch.efer;
1012 
1013 	if (!kvm_valid_efer(vcpu, efer))
1014 		return 1;
1015 
1016 	if (is_paging(vcpu)
1017 	    && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1018 		return 1;
1019 
1020 	efer &= ~EFER_LMA;
1021 	efer |= vcpu->arch.efer & EFER_LMA;
1022 
1023 	kvm_x86_ops->set_efer(vcpu, efer);
1024 
1025 	/* Update reserved bits */
1026 	if ((efer ^ old_efer) & EFER_NX)
1027 		kvm_mmu_reset_context(vcpu);
1028 
1029 	return 0;
1030 }
1031 
1032 void kvm_enable_efer_bits(u64 mask)
1033 {
1034        efer_reserved_bits &= ~mask;
1035 }
1036 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1037 
1038 /*
1039  * Writes msr value into into the appropriate "register".
1040  * Returns 0 on success, non-0 otherwise.
1041  * Assumes vcpu_load() was already called.
1042  */
1043 int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
1044 {
1045 	switch (msr->index) {
1046 	case MSR_FS_BASE:
1047 	case MSR_GS_BASE:
1048 	case MSR_KERNEL_GS_BASE:
1049 	case MSR_CSTAR:
1050 	case MSR_LSTAR:
1051 		if (is_noncanonical_address(msr->data))
1052 			return 1;
1053 		break;
1054 	case MSR_IA32_SYSENTER_EIP:
1055 	case MSR_IA32_SYSENTER_ESP:
1056 		/*
1057 		 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1058 		 * non-canonical address is written on Intel but not on
1059 		 * AMD (which ignores the top 32-bits, because it does
1060 		 * not implement 64-bit SYSENTER).
1061 		 *
1062 		 * 64-bit code should hence be able to write a non-canonical
1063 		 * value on AMD.  Making the address canonical ensures that
1064 		 * vmentry does not fail on Intel after writing a non-canonical
1065 		 * value, and that something deterministic happens if the guest
1066 		 * invokes 64-bit SYSENTER.
1067 		 */
1068 		msr->data = get_canonical(msr->data);
1069 	}
1070 	return kvm_x86_ops->set_msr(vcpu, msr);
1071 }
1072 EXPORT_SYMBOL_GPL(kvm_set_msr);
1073 
1074 /*
1075  * Adapt set_msr() to msr_io()'s calling convention
1076  */
1077 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1078 {
1079 	struct msr_data msr;
1080 	int r;
1081 
1082 	msr.index = index;
1083 	msr.host_initiated = true;
1084 	r = kvm_get_msr(vcpu, &msr);
1085 	if (r)
1086 		return r;
1087 
1088 	*data = msr.data;
1089 	return 0;
1090 }
1091 
1092 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1093 {
1094 	struct msr_data msr;
1095 
1096 	msr.data = *data;
1097 	msr.index = index;
1098 	msr.host_initiated = true;
1099 	return kvm_set_msr(vcpu, &msr);
1100 }
1101 
1102 #ifdef CONFIG_X86_64
1103 struct pvclock_gtod_data {
1104 	seqcount_t	seq;
1105 
1106 	struct { /* extract of a clocksource struct */
1107 		int vclock_mode;
1108 		cycle_t	cycle_last;
1109 		cycle_t	mask;
1110 		u32	mult;
1111 		u32	shift;
1112 	} clock;
1113 
1114 	u64		boot_ns;
1115 	u64		nsec_base;
1116 };
1117 
1118 static struct pvclock_gtod_data pvclock_gtod_data;
1119 
1120 static void update_pvclock_gtod(struct timekeeper *tk)
1121 {
1122 	struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
1123 	u64 boot_ns;
1124 
1125 	boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
1126 
1127 	write_seqcount_begin(&vdata->seq);
1128 
1129 	/* copy pvclock gtod data */
1130 	vdata->clock.vclock_mode	= tk->tkr_mono.clock->archdata.vclock_mode;
1131 	vdata->clock.cycle_last		= tk->tkr_mono.cycle_last;
1132 	vdata->clock.mask		= tk->tkr_mono.mask;
1133 	vdata->clock.mult		= tk->tkr_mono.mult;
1134 	vdata->clock.shift		= tk->tkr_mono.shift;
1135 
1136 	vdata->boot_ns			= boot_ns;
1137 	vdata->nsec_base		= tk->tkr_mono.xtime_nsec;
1138 
1139 	write_seqcount_end(&vdata->seq);
1140 }
1141 #endif
1142 
1143 void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1144 {
1145 	/*
1146 	 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1147 	 * vcpu_enter_guest.  This function is only called from
1148 	 * the physical CPU that is running vcpu.
1149 	 */
1150 	kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1151 }
1152 
1153 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1154 {
1155 	int version;
1156 	int r;
1157 	struct pvclock_wall_clock wc;
1158 	struct timespec boot;
1159 
1160 	if (!wall_clock)
1161 		return;
1162 
1163 	r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1164 	if (r)
1165 		return;
1166 
1167 	if (version & 1)
1168 		++version;  /* first time write, random junk */
1169 
1170 	++version;
1171 
1172 	if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1173 		return;
1174 
1175 	/*
1176 	 * The guest calculates current wall clock time by adding
1177 	 * system time (updated by kvm_guest_time_update below) to the
1178 	 * wall clock specified here.  guest system time equals host
1179 	 * system time for us, thus we must fill in host boot time here.
1180 	 */
1181 	getboottime(&boot);
1182 
1183 	if (kvm->arch.kvmclock_offset) {
1184 		struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1185 		boot = timespec_sub(boot, ts);
1186 	}
1187 	wc.sec = boot.tv_sec;
1188 	wc.nsec = boot.tv_nsec;
1189 	wc.version = version;
1190 
1191 	kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1192 
1193 	version++;
1194 	kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1195 }
1196 
1197 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1198 {
1199 	do_shl32_div32(dividend, divisor);
1200 	return dividend;
1201 }
1202 
1203 static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1204 			       s8 *pshift, u32 *pmultiplier)
1205 {
1206 	uint64_t scaled64;
1207 	int32_t  shift = 0;
1208 	uint64_t tps64;
1209 	uint32_t tps32;
1210 
1211 	tps64 = base_khz * 1000LL;
1212 	scaled64 = scaled_khz * 1000LL;
1213 	while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
1214 		tps64 >>= 1;
1215 		shift--;
1216 	}
1217 
1218 	tps32 = (uint32_t)tps64;
1219 	while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1220 		if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
1221 			scaled64 >>= 1;
1222 		else
1223 			tps32 <<= 1;
1224 		shift++;
1225 	}
1226 
1227 	*pshift = shift;
1228 	*pmultiplier = div_frac(scaled64, tps32);
1229 
1230 	pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1231 		 __func__, base_khz, scaled_khz, shift, *pmultiplier);
1232 }
1233 
1234 #ifdef CONFIG_X86_64
1235 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
1236 #endif
1237 
1238 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
1239 static unsigned long max_tsc_khz;
1240 
1241 static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
1242 {
1243 	return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1244 				   vcpu->arch.virtual_tsc_shift);
1245 }
1246 
1247 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1248 {
1249 	u64 v = (u64)khz * (1000000 + ppm);
1250 	do_div(v, 1000000);
1251 	return v;
1252 }
1253 
1254 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1255 {
1256 	u64 ratio;
1257 
1258 	/* Guest TSC same frequency as host TSC? */
1259 	if (!scale) {
1260 		vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1261 		return 0;
1262 	}
1263 
1264 	/* TSC scaling supported? */
1265 	if (!kvm_has_tsc_control) {
1266 		if (user_tsc_khz > tsc_khz) {
1267 			vcpu->arch.tsc_catchup = 1;
1268 			vcpu->arch.tsc_always_catchup = 1;
1269 			return 0;
1270 		} else {
1271 			WARN(1, "user requested TSC rate below hardware speed\n");
1272 			return -1;
1273 		}
1274 	}
1275 
1276 	/* TSC scaling required  - calculate ratio */
1277 	ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1278 				user_tsc_khz, tsc_khz);
1279 
1280 	if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1281 		WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1282 			  user_tsc_khz);
1283 		return -1;
1284 	}
1285 
1286 	vcpu->arch.tsc_scaling_ratio = ratio;
1287 	return 0;
1288 }
1289 
1290 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
1291 {
1292 	u32 thresh_lo, thresh_hi;
1293 	int use_scaling = 0;
1294 
1295 	/* tsc_khz can be zero if TSC calibration fails */
1296 	if (this_tsc_khz == 0) {
1297 		/* set tsc_scaling_ratio to a safe value */
1298 		vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1299 		return -1;
1300 	}
1301 
1302 	/* Compute a scale to convert nanoseconds in TSC cycles */
1303 	kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
1304 			   &vcpu->arch.virtual_tsc_shift,
1305 			   &vcpu->arch.virtual_tsc_mult);
1306 	vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1307 
1308 	/*
1309 	 * Compute the variation in TSC rate which is acceptable
1310 	 * within the range of tolerance and decide if the
1311 	 * rate being applied is within that bounds of the hardware
1312 	 * rate.  If so, no scaling or compensation need be done.
1313 	 */
1314 	thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1315 	thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1316 	if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1317 		pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1318 		use_scaling = 1;
1319 	}
1320 	return set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
1321 }
1322 
1323 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1324 {
1325 	u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1326 				      vcpu->arch.virtual_tsc_mult,
1327 				      vcpu->arch.virtual_tsc_shift);
1328 	tsc += vcpu->arch.this_tsc_write;
1329 	return tsc;
1330 }
1331 
1332 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1333 {
1334 #ifdef CONFIG_X86_64
1335 	bool vcpus_matched;
1336 	struct kvm_arch *ka = &vcpu->kvm->arch;
1337 	struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1338 
1339 	vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1340 			 atomic_read(&vcpu->kvm->online_vcpus));
1341 
1342 	/*
1343 	 * Once the masterclock is enabled, always perform request in
1344 	 * order to update it.
1345 	 *
1346 	 * In order to enable masterclock, the host clocksource must be TSC
1347 	 * and the vcpus need to have matched TSCs.  When that happens,
1348 	 * perform request to enable masterclock.
1349 	 */
1350 	if (ka->use_master_clock ||
1351 	    (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
1352 		kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1353 
1354 	trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1355 			    atomic_read(&vcpu->kvm->online_vcpus),
1356 		            ka->use_master_clock, gtod->clock.vclock_mode);
1357 #endif
1358 }
1359 
1360 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1361 {
1362 	u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1363 	vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1364 }
1365 
1366 /*
1367  * Multiply tsc by a fixed point number represented by ratio.
1368  *
1369  * The most significant 64-N bits (mult) of ratio represent the
1370  * integral part of the fixed point number; the remaining N bits
1371  * (frac) represent the fractional part, ie. ratio represents a fixed
1372  * point number (mult + frac * 2^(-N)).
1373  *
1374  * N equals to kvm_tsc_scaling_ratio_frac_bits.
1375  */
1376 static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1377 {
1378 	return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1379 }
1380 
1381 u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1382 {
1383 	u64 _tsc = tsc;
1384 	u64 ratio = vcpu->arch.tsc_scaling_ratio;
1385 
1386 	if (ratio != kvm_default_tsc_scaling_ratio)
1387 		_tsc = __scale_tsc(ratio, tsc);
1388 
1389 	return _tsc;
1390 }
1391 EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1392 
1393 static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1394 {
1395 	u64 tsc;
1396 
1397 	tsc = kvm_scale_tsc(vcpu, rdtsc());
1398 
1399 	return target_tsc - tsc;
1400 }
1401 
1402 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1403 {
1404 	return kvm_x86_ops->read_l1_tsc(vcpu, kvm_scale_tsc(vcpu, host_tsc));
1405 }
1406 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1407 
1408 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
1409 {
1410 	struct kvm *kvm = vcpu->kvm;
1411 	u64 offset, ns, elapsed;
1412 	unsigned long flags;
1413 	s64 usdiff;
1414 	bool matched;
1415 	bool already_matched;
1416 	u64 data = msr->data;
1417 
1418 	raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1419 	offset = kvm_compute_tsc_offset(vcpu, data);
1420 	ns = get_kernel_ns();
1421 	elapsed = ns - kvm->arch.last_tsc_nsec;
1422 
1423 	if (vcpu->arch.virtual_tsc_khz) {
1424 		int faulted = 0;
1425 
1426 		/* n.b - signed multiplication and division required */
1427 		usdiff = data - kvm->arch.last_tsc_write;
1428 #ifdef CONFIG_X86_64
1429 		usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
1430 #else
1431 		/* do_div() only does unsigned */
1432 		asm("1: idivl %[divisor]\n"
1433 		    "2: xor %%edx, %%edx\n"
1434 		    "   movl $0, %[faulted]\n"
1435 		    "3:\n"
1436 		    ".section .fixup,\"ax\"\n"
1437 		    "4: movl $1, %[faulted]\n"
1438 		    "   jmp  3b\n"
1439 		    ".previous\n"
1440 
1441 		_ASM_EXTABLE(1b, 4b)
1442 
1443 		: "=A"(usdiff), [faulted] "=r" (faulted)
1444 		: "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1445 
1446 #endif
1447 		do_div(elapsed, 1000);
1448 		usdiff -= elapsed;
1449 		if (usdiff < 0)
1450 			usdiff = -usdiff;
1451 
1452 		/* idivl overflow => difference is larger than USEC_PER_SEC */
1453 		if (faulted)
1454 			usdiff = USEC_PER_SEC;
1455 	} else
1456 		usdiff = USEC_PER_SEC; /* disable TSC match window below */
1457 
1458 	/*
1459 	 * Special case: TSC write with a small delta (1 second) of virtual
1460 	 * cycle time against real time is interpreted as an attempt to
1461 	 * synchronize the CPU.
1462          *
1463 	 * For a reliable TSC, we can match TSC offsets, and for an unstable
1464 	 * TSC, we add elapsed time in this computation.  We could let the
1465 	 * compensation code attempt to catch up if we fall behind, but
1466 	 * it's better to try to match offsets from the beginning.
1467          */
1468 	if (usdiff < USEC_PER_SEC &&
1469 	    vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
1470 		if (!check_tsc_unstable()) {
1471 			offset = kvm->arch.cur_tsc_offset;
1472 			pr_debug("kvm: matched tsc offset for %llu\n", data);
1473 		} else {
1474 			u64 delta = nsec_to_cycles(vcpu, elapsed);
1475 			data += delta;
1476 			offset = kvm_compute_tsc_offset(vcpu, data);
1477 			pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
1478 		}
1479 		matched = true;
1480 		already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
1481 	} else {
1482 		/*
1483 		 * We split periods of matched TSC writes into generations.
1484 		 * For each generation, we track the original measured
1485 		 * nanosecond time, offset, and write, so if TSCs are in
1486 		 * sync, we can match exact offset, and if not, we can match
1487 		 * exact software computation in compute_guest_tsc()
1488 		 *
1489 		 * These values are tracked in kvm->arch.cur_xxx variables.
1490 		 */
1491 		kvm->arch.cur_tsc_generation++;
1492 		kvm->arch.cur_tsc_nsec = ns;
1493 		kvm->arch.cur_tsc_write = data;
1494 		kvm->arch.cur_tsc_offset = offset;
1495 		matched = false;
1496 		pr_debug("kvm: new tsc generation %llu, clock %llu\n",
1497 			 kvm->arch.cur_tsc_generation, data);
1498 	}
1499 
1500 	/*
1501 	 * We also track th most recent recorded KHZ, write and time to
1502 	 * allow the matching interval to be extended at each write.
1503 	 */
1504 	kvm->arch.last_tsc_nsec = ns;
1505 	kvm->arch.last_tsc_write = data;
1506 	kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
1507 
1508 	vcpu->arch.last_guest_tsc = data;
1509 
1510 	/* Keep track of which generation this VCPU has synchronized to */
1511 	vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1512 	vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1513 	vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1514 
1515 	if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1516 		update_ia32_tsc_adjust_msr(vcpu, offset);
1517 	kvm_x86_ops->write_tsc_offset(vcpu, offset);
1518 	raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1519 
1520 	spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1521 	if (!matched) {
1522 		kvm->arch.nr_vcpus_matched_tsc = 0;
1523 	} else if (!already_matched) {
1524 		kvm->arch.nr_vcpus_matched_tsc++;
1525 	}
1526 
1527 	kvm_track_tsc_matching(vcpu);
1528 	spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
1529 }
1530 
1531 EXPORT_SYMBOL_GPL(kvm_write_tsc);
1532 
1533 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1534 					   s64 adjustment)
1535 {
1536 	kvm_x86_ops->adjust_tsc_offset_guest(vcpu, adjustment);
1537 }
1538 
1539 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1540 {
1541 	if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1542 		WARN_ON(adjustment < 0);
1543 	adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
1544 	kvm_x86_ops->adjust_tsc_offset_guest(vcpu, adjustment);
1545 }
1546 
1547 #ifdef CONFIG_X86_64
1548 
1549 static cycle_t read_tsc(void)
1550 {
1551 	cycle_t ret = (cycle_t)rdtsc_ordered();
1552 	u64 last = pvclock_gtod_data.clock.cycle_last;
1553 
1554 	if (likely(ret >= last))
1555 		return ret;
1556 
1557 	/*
1558 	 * GCC likes to generate cmov here, but this branch is extremely
1559 	 * predictable (it's just a funciton of time and the likely is
1560 	 * very likely) and there's a data dependence, so force GCC
1561 	 * to generate a branch instead.  I don't barrier() because
1562 	 * we don't actually need a barrier, and if this function
1563 	 * ever gets inlined it will generate worse code.
1564 	 */
1565 	asm volatile ("");
1566 	return last;
1567 }
1568 
1569 static inline u64 vgettsc(cycle_t *cycle_now)
1570 {
1571 	long v;
1572 	struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1573 
1574 	*cycle_now = read_tsc();
1575 
1576 	v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1577 	return v * gtod->clock.mult;
1578 }
1579 
1580 static int do_monotonic_boot(s64 *t, cycle_t *cycle_now)
1581 {
1582 	struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1583 	unsigned long seq;
1584 	int mode;
1585 	u64 ns;
1586 
1587 	do {
1588 		seq = read_seqcount_begin(&gtod->seq);
1589 		mode = gtod->clock.vclock_mode;
1590 		ns = gtod->nsec_base;
1591 		ns += vgettsc(cycle_now);
1592 		ns >>= gtod->clock.shift;
1593 		ns += gtod->boot_ns;
1594 	} while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1595 	*t = ns;
1596 
1597 	return mode;
1598 }
1599 
1600 /* returns true if host is using tsc clocksource */
1601 static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1602 {
1603 	/* checked again under seqlock below */
1604 	if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1605 		return false;
1606 
1607 	return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
1608 }
1609 #endif
1610 
1611 /*
1612  *
1613  * Assuming a stable TSC across physical CPUS, and a stable TSC
1614  * across virtual CPUs, the following condition is possible.
1615  * Each numbered line represents an event visible to both
1616  * CPUs at the next numbered event.
1617  *
1618  * "timespecX" represents host monotonic time. "tscX" represents
1619  * RDTSC value.
1620  *
1621  * 		VCPU0 on CPU0		|	VCPU1 on CPU1
1622  *
1623  * 1.  read timespec0,tsc0
1624  * 2.					| timespec1 = timespec0 + N
1625  * 					| tsc1 = tsc0 + M
1626  * 3. transition to guest		| transition to guest
1627  * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1628  * 5.				        | ret1 = timespec1 + (rdtsc - tsc1)
1629  * 				        | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1630  *
1631  * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1632  *
1633  * 	- ret0 < ret1
1634  *	- timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1635  *		...
1636  *	- 0 < N - M => M < N
1637  *
1638  * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1639  * always the case (the difference between two distinct xtime instances
1640  * might be smaller then the difference between corresponding TSC reads,
1641  * when updating guest vcpus pvclock areas).
1642  *
1643  * To avoid that problem, do not allow visibility of distinct
1644  * system_timestamp/tsc_timestamp values simultaneously: use a master
1645  * copy of host monotonic time values. Update that master copy
1646  * in lockstep.
1647  *
1648  * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
1649  *
1650  */
1651 
1652 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1653 {
1654 #ifdef CONFIG_X86_64
1655 	struct kvm_arch *ka = &kvm->arch;
1656 	int vclock_mode;
1657 	bool host_tsc_clocksource, vcpus_matched;
1658 
1659 	vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1660 			atomic_read(&kvm->online_vcpus));
1661 
1662 	/*
1663 	 * If the host uses TSC clock, then passthrough TSC as stable
1664 	 * to the guest.
1665 	 */
1666 	host_tsc_clocksource = kvm_get_time_and_clockread(
1667 					&ka->master_kernel_ns,
1668 					&ka->master_cycle_now);
1669 
1670 	ka->use_master_clock = host_tsc_clocksource && vcpus_matched
1671 				&& !backwards_tsc_observed
1672 				&& !ka->boot_vcpu_runs_old_kvmclock;
1673 
1674 	if (ka->use_master_clock)
1675 		atomic_set(&kvm_guest_has_master_clock, 1);
1676 
1677 	vclock_mode = pvclock_gtod_data.clock.vclock_mode;
1678 	trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1679 					vcpus_matched);
1680 #endif
1681 }
1682 
1683 void kvm_make_mclock_inprogress_request(struct kvm *kvm)
1684 {
1685 	kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
1686 }
1687 
1688 static void kvm_gen_update_masterclock(struct kvm *kvm)
1689 {
1690 #ifdef CONFIG_X86_64
1691 	int i;
1692 	struct kvm_vcpu *vcpu;
1693 	struct kvm_arch *ka = &kvm->arch;
1694 
1695 	spin_lock(&ka->pvclock_gtod_sync_lock);
1696 	kvm_make_mclock_inprogress_request(kvm);
1697 	/* no guest entries from this point */
1698 	pvclock_update_vm_gtod_copy(kvm);
1699 
1700 	kvm_for_each_vcpu(i, vcpu, kvm)
1701 		kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
1702 
1703 	/* guest entries allowed */
1704 	kvm_for_each_vcpu(i, vcpu, kvm)
1705 		clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1706 
1707 	spin_unlock(&ka->pvclock_gtod_sync_lock);
1708 #endif
1709 }
1710 
1711 static int kvm_guest_time_update(struct kvm_vcpu *v)
1712 {
1713 	unsigned long flags, this_tsc_khz, tgt_tsc_khz;
1714 	struct kvm_vcpu_arch *vcpu = &v->arch;
1715 	struct kvm_arch *ka = &v->kvm->arch;
1716 	s64 kernel_ns;
1717 	u64 tsc_timestamp, host_tsc;
1718 	struct pvclock_vcpu_time_info guest_hv_clock;
1719 	u8 pvclock_flags;
1720 	bool use_master_clock;
1721 
1722 	kernel_ns = 0;
1723 	host_tsc = 0;
1724 
1725 	/*
1726 	 * If the host uses TSC clock, then passthrough TSC as stable
1727 	 * to the guest.
1728 	 */
1729 	spin_lock(&ka->pvclock_gtod_sync_lock);
1730 	use_master_clock = ka->use_master_clock;
1731 	if (use_master_clock) {
1732 		host_tsc = ka->master_cycle_now;
1733 		kernel_ns = ka->master_kernel_ns;
1734 	}
1735 	spin_unlock(&ka->pvclock_gtod_sync_lock);
1736 
1737 	/* Keep irq disabled to prevent changes to the clock */
1738 	local_irq_save(flags);
1739 	this_tsc_khz = __this_cpu_read(cpu_tsc_khz);
1740 	if (unlikely(this_tsc_khz == 0)) {
1741 		local_irq_restore(flags);
1742 		kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1743 		return 1;
1744 	}
1745 	if (!use_master_clock) {
1746 		host_tsc = rdtsc();
1747 		kernel_ns = get_kernel_ns();
1748 	}
1749 
1750 	tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
1751 
1752 	/*
1753 	 * We may have to catch up the TSC to match elapsed wall clock
1754 	 * time for two reasons, even if kvmclock is used.
1755 	 *   1) CPU could have been running below the maximum TSC rate
1756 	 *   2) Broken TSC compensation resets the base at each VCPU
1757 	 *      entry to avoid unknown leaps of TSC even when running
1758 	 *      again on the same CPU.  This may cause apparent elapsed
1759 	 *      time to disappear, and the guest to stand still or run
1760 	 *	very slowly.
1761 	 */
1762 	if (vcpu->tsc_catchup) {
1763 		u64 tsc = compute_guest_tsc(v, kernel_ns);
1764 		if (tsc > tsc_timestamp) {
1765 			adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
1766 			tsc_timestamp = tsc;
1767 		}
1768 	}
1769 
1770 	local_irq_restore(flags);
1771 
1772 	if (!vcpu->pv_time_enabled)
1773 		return 0;
1774 
1775 	if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
1776 		tgt_tsc_khz = kvm_has_tsc_control ?
1777 			vcpu->virtual_tsc_khz : this_tsc_khz;
1778 		kvm_get_time_scale(NSEC_PER_SEC / 1000, tgt_tsc_khz,
1779 				   &vcpu->hv_clock.tsc_shift,
1780 				   &vcpu->hv_clock.tsc_to_system_mul);
1781 		vcpu->hw_tsc_khz = this_tsc_khz;
1782 	}
1783 
1784 	/* With all the info we got, fill in the values */
1785 	vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
1786 	vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1787 	vcpu->last_guest_tsc = tsc_timestamp;
1788 
1789 	if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1790 		&guest_hv_clock, sizeof(guest_hv_clock))))
1791 		return 0;
1792 
1793 	/* This VCPU is paused, but it's legal for a guest to read another
1794 	 * VCPU's kvmclock, so we really have to follow the specification where
1795 	 * it says that version is odd if data is being modified, and even after
1796 	 * it is consistent.
1797 	 *
1798 	 * Version field updates must be kept separate.  This is because
1799 	 * kvm_write_guest_cached might use a "rep movs" instruction, and
1800 	 * writes within a string instruction are weakly ordered.  So there
1801 	 * are three writes overall.
1802 	 *
1803 	 * As a small optimization, only write the version field in the first
1804 	 * and third write.  The vcpu->pv_time cache is still valid, because the
1805 	 * version field is the first in the struct.
1806 	 */
1807 	BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1808 
1809 	vcpu->hv_clock.version = guest_hv_clock.version + 1;
1810 	kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1811 				&vcpu->hv_clock,
1812 				sizeof(vcpu->hv_clock.version));
1813 
1814 	smp_wmb();
1815 
1816 	/* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1817 	pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1818 
1819 	if (vcpu->pvclock_set_guest_stopped_request) {
1820 		pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1821 		vcpu->pvclock_set_guest_stopped_request = false;
1822 	}
1823 
1824 	/* If the host uses TSC clocksource, then it is stable */
1825 	if (use_master_clock)
1826 		pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1827 
1828 	vcpu->hv_clock.flags = pvclock_flags;
1829 
1830 	trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1831 
1832 	kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1833 				&vcpu->hv_clock,
1834 				sizeof(vcpu->hv_clock));
1835 
1836 	smp_wmb();
1837 
1838 	vcpu->hv_clock.version++;
1839 	kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1840 				&vcpu->hv_clock,
1841 				sizeof(vcpu->hv_clock.version));
1842 	return 0;
1843 }
1844 
1845 /*
1846  * kvmclock updates which are isolated to a given vcpu, such as
1847  * vcpu->cpu migration, should not allow system_timestamp from
1848  * the rest of the vcpus to remain static. Otherwise ntp frequency
1849  * correction applies to one vcpu's system_timestamp but not
1850  * the others.
1851  *
1852  * So in those cases, request a kvmclock update for all vcpus.
1853  * We need to rate-limit these requests though, as they can
1854  * considerably slow guests that have a large number of vcpus.
1855  * The time for a remote vcpu to update its kvmclock is bound
1856  * by the delay we use to rate-limit the updates.
1857  */
1858 
1859 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1860 
1861 static void kvmclock_update_fn(struct work_struct *work)
1862 {
1863 	int i;
1864 	struct delayed_work *dwork = to_delayed_work(work);
1865 	struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1866 					   kvmclock_update_work);
1867 	struct kvm *kvm = container_of(ka, struct kvm, arch);
1868 	struct kvm_vcpu *vcpu;
1869 
1870 	kvm_for_each_vcpu(i, vcpu, kvm) {
1871 		kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
1872 		kvm_vcpu_kick(vcpu);
1873 	}
1874 }
1875 
1876 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1877 {
1878 	struct kvm *kvm = v->kvm;
1879 
1880 	kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1881 	schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1882 					KVMCLOCK_UPDATE_DELAY);
1883 }
1884 
1885 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1886 
1887 static void kvmclock_sync_fn(struct work_struct *work)
1888 {
1889 	struct delayed_work *dwork = to_delayed_work(work);
1890 	struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1891 					   kvmclock_sync_work);
1892 	struct kvm *kvm = container_of(ka, struct kvm, arch);
1893 
1894 	if (!kvmclock_periodic_sync)
1895 		return;
1896 
1897 	schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1898 	schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1899 					KVMCLOCK_SYNC_PERIOD);
1900 }
1901 
1902 static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1903 {
1904 	u64 mcg_cap = vcpu->arch.mcg_cap;
1905 	unsigned bank_num = mcg_cap & 0xff;
1906 
1907 	switch (msr) {
1908 	case MSR_IA32_MCG_STATUS:
1909 		vcpu->arch.mcg_status = data;
1910 		break;
1911 	case MSR_IA32_MCG_CTL:
1912 		if (!(mcg_cap & MCG_CTL_P))
1913 			return 1;
1914 		if (data != 0 && data != ~(u64)0)
1915 			return -1;
1916 		vcpu->arch.mcg_ctl = data;
1917 		break;
1918 	default:
1919 		if (msr >= MSR_IA32_MC0_CTL &&
1920 		    msr < MSR_IA32_MCx_CTL(bank_num)) {
1921 			u32 offset = msr - MSR_IA32_MC0_CTL;
1922 			/* only 0 or all 1s can be written to IA32_MCi_CTL
1923 			 * some Linux kernels though clear bit 10 in bank 4 to
1924 			 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1925 			 * this to avoid an uncatched #GP in the guest
1926 			 */
1927 			if ((offset & 0x3) == 0 &&
1928 			    data != 0 && (data | (1 << 10)) != ~(u64)0)
1929 				return -1;
1930 			vcpu->arch.mce_banks[offset] = data;
1931 			break;
1932 		}
1933 		return 1;
1934 	}
1935 	return 0;
1936 }
1937 
1938 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1939 {
1940 	struct kvm *kvm = vcpu->kvm;
1941 	int lm = is_long_mode(vcpu);
1942 	u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1943 		: (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1944 	u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1945 		: kvm->arch.xen_hvm_config.blob_size_32;
1946 	u32 page_num = data & ~PAGE_MASK;
1947 	u64 page_addr = data & PAGE_MASK;
1948 	u8 *page;
1949 	int r;
1950 
1951 	r = -E2BIG;
1952 	if (page_num >= blob_size)
1953 		goto out;
1954 	r = -ENOMEM;
1955 	page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1956 	if (IS_ERR(page)) {
1957 		r = PTR_ERR(page);
1958 		goto out;
1959 	}
1960 	if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
1961 		goto out_free;
1962 	r = 0;
1963 out_free:
1964 	kfree(page);
1965 out:
1966 	return r;
1967 }
1968 
1969 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1970 {
1971 	gpa_t gpa = data & ~0x3f;
1972 
1973 	/* Bits 2:5 are reserved, Should be zero */
1974 	if (data & 0x3c)
1975 		return 1;
1976 
1977 	vcpu->arch.apf.msr_val = data;
1978 
1979 	if (!(data & KVM_ASYNC_PF_ENABLED)) {
1980 		kvm_clear_async_pf_completion_queue(vcpu);
1981 		kvm_async_pf_hash_reset(vcpu);
1982 		return 0;
1983 	}
1984 
1985 	if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
1986 					sizeof(u32)))
1987 		return 1;
1988 
1989 	vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
1990 	kvm_async_pf_wakeup_all(vcpu);
1991 	return 0;
1992 }
1993 
1994 static void kvmclock_reset(struct kvm_vcpu *vcpu)
1995 {
1996 	vcpu->arch.pv_time_enabled = false;
1997 }
1998 
1999 static void accumulate_steal_time(struct kvm_vcpu *vcpu)
2000 {
2001 	u64 delta;
2002 
2003 	if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2004 		return;
2005 
2006 	delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
2007 	vcpu->arch.st.last_steal = current->sched_info.run_delay;
2008 	vcpu->arch.st.accum_steal = delta;
2009 }
2010 
2011 static void record_steal_time(struct kvm_vcpu *vcpu)
2012 {
2013 	accumulate_steal_time(vcpu);
2014 
2015 	if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2016 		return;
2017 
2018 	if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2019 		&vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2020 		return;
2021 
2022 	vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
2023 	vcpu->arch.st.steal.version += 2;
2024 	vcpu->arch.st.accum_steal = 0;
2025 
2026 	kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2027 		&vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2028 }
2029 
2030 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2031 {
2032 	bool pr = false;
2033 	u32 msr = msr_info->index;
2034 	u64 data = msr_info->data;
2035 
2036 	switch (msr) {
2037 	case MSR_AMD64_NB_CFG:
2038 	case MSR_IA32_UCODE_REV:
2039 	case MSR_IA32_UCODE_WRITE:
2040 	case MSR_VM_HSAVE_PA:
2041 	case MSR_AMD64_PATCH_LOADER:
2042 	case MSR_AMD64_BU_CFG2:
2043 		break;
2044 
2045 	case MSR_EFER:
2046 		return set_efer(vcpu, data);
2047 	case MSR_K7_HWCR:
2048 		data &= ~(u64)0x40;	/* ignore flush filter disable */
2049 		data &= ~(u64)0x100;	/* ignore ignne emulation enable */
2050 		data &= ~(u64)0x8;	/* ignore TLB cache disable */
2051 		data &= ~(u64)0x40000;  /* ignore Mc status write enable */
2052 		if (data != 0) {
2053 			vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2054 				    data);
2055 			return 1;
2056 		}
2057 		break;
2058 	case MSR_FAM10H_MMIO_CONF_BASE:
2059 		if (data != 0) {
2060 			vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2061 				    "0x%llx\n", data);
2062 			return 1;
2063 		}
2064 		break;
2065 	case MSR_IA32_DEBUGCTLMSR:
2066 		if (!data) {
2067 			/* We support the non-activated case already */
2068 			break;
2069 		} else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2070 			/* Values other than LBR and BTF are vendor-specific,
2071 			   thus reserved and should throw a #GP */
2072 			return 1;
2073 		}
2074 		vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2075 			    __func__, data);
2076 		break;
2077 	case 0x200 ... 0x2ff:
2078 		return kvm_mtrr_set_msr(vcpu, msr, data);
2079 	case MSR_IA32_APICBASE:
2080 		return kvm_set_apic_base(vcpu, msr_info);
2081 	case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2082 		return kvm_x2apic_msr_write(vcpu, msr, data);
2083 	case MSR_IA32_TSCDEADLINE:
2084 		kvm_set_lapic_tscdeadline_msr(vcpu, data);
2085 		break;
2086 	case MSR_IA32_TSC_ADJUST:
2087 		if (guest_cpuid_has_tsc_adjust(vcpu)) {
2088 			if (!msr_info->host_initiated) {
2089 				s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2090 				adjust_tsc_offset_guest(vcpu, adj);
2091 			}
2092 			vcpu->arch.ia32_tsc_adjust_msr = data;
2093 		}
2094 		break;
2095 	case MSR_IA32_MISC_ENABLE:
2096 		vcpu->arch.ia32_misc_enable_msr = data;
2097 		break;
2098 	case MSR_IA32_SMBASE:
2099 		if (!msr_info->host_initiated)
2100 			return 1;
2101 		vcpu->arch.smbase = data;
2102 		break;
2103 	case MSR_KVM_WALL_CLOCK_NEW:
2104 	case MSR_KVM_WALL_CLOCK:
2105 		vcpu->kvm->arch.wall_clock = data;
2106 		kvm_write_wall_clock(vcpu->kvm, data);
2107 		break;
2108 	case MSR_KVM_SYSTEM_TIME_NEW:
2109 	case MSR_KVM_SYSTEM_TIME: {
2110 		u64 gpa_offset;
2111 		struct kvm_arch *ka = &vcpu->kvm->arch;
2112 
2113 		kvmclock_reset(vcpu);
2114 
2115 		if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2116 			bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2117 
2118 			if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2119 				set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
2120 					&vcpu->requests);
2121 
2122 			ka->boot_vcpu_runs_old_kvmclock = tmp;
2123 		}
2124 
2125 		vcpu->arch.time = data;
2126 		kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2127 
2128 		/* we verify if the enable bit is set... */
2129 		if (!(data & 1))
2130 			break;
2131 
2132 		gpa_offset = data & ~(PAGE_MASK | 1);
2133 
2134 		if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
2135 		     &vcpu->arch.pv_time, data & ~1ULL,
2136 		     sizeof(struct pvclock_vcpu_time_info)))
2137 			vcpu->arch.pv_time_enabled = false;
2138 		else
2139 			vcpu->arch.pv_time_enabled = true;
2140 
2141 		break;
2142 	}
2143 	case MSR_KVM_ASYNC_PF_EN:
2144 		if (kvm_pv_enable_async_pf(vcpu, data))
2145 			return 1;
2146 		break;
2147 	case MSR_KVM_STEAL_TIME:
2148 
2149 		if (unlikely(!sched_info_on()))
2150 			return 1;
2151 
2152 		if (data & KVM_STEAL_RESERVED_MASK)
2153 			return 1;
2154 
2155 		if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
2156 						data & KVM_STEAL_VALID_BITS,
2157 						sizeof(struct kvm_steal_time)))
2158 			return 1;
2159 
2160 		vcpu->arch.st.msr_val = data;
2161 
2162 		if (!(data & KVM_MSR_ENABLED))
2163 			break;
2164 
2165 		kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2166 
2167 		break;
2168 	case MSR_KVM_PV_EOI_EN:
2169 		if (kvm_lapic_enable_pv_eoi(vcpu, data))
2170 			return 1;
2171 		break;
2172 
2173 	case MSR_IA32_MCG_CTL:
2174 	case MSR_IA32_MCG_STATUS:
2175 	case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2176 		return set_msr_mce(vcpu, msr, data);
2177 
2178 	case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2179 	case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2180 		pr = true; /* fall through */
2181 	case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2182 	case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2183 		if (kvm_pmu_is_valid_msr(vcpu, msr))
2184 			return kvm_pmu_set_msr(vcpu, msr_info);
2185 
2186 		if (pr || data != 0)
2187 			vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2188 				    "0x%x data 0x%llx\n", msr, data);
2189 		break;
2190 	case MSR_K7_CLK_CTL:
2191 		/*
2192 		 * Ignore all writes to this no longer documented MSR.
2193 		 * Writes are only relevant for old K7 processors,
2194 		 * all pre-dating SVM, but a recommended workaround from
2195 		 * AMD for these chips. It is possible to specify the
2196 		 * affected processor models on the command line, hence
2197 		 * the need to ignore the workaround.
2198 		 */
2199 		break;
2200 	case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2201 	case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2202 	case HV_X64_MSR_CRASH_CTL:
2203 	case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
2204 		return kvm_hv_set_msr_common(vcpu, msr, data,
2205 					     msr_info->host_initiated);
2206 	case MSR_IA32_BBL_CR_CTL3:
2207 		/* Drop writes to this legacy MSR -- see rdmsr
2208 		 * counterpart for further detail.
2209 		 */
2210 		vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
2211 		break;
2212 	case MSR_AMD64_OSVW_ID_LENGTH:
2213 		if (!guest_cpuid_has_osvw(vcpu))
2214 			return 1;
2215 		vcpu->arch.osvw.length = data;
2216 		break;
2217 	case MSR_AMD64_OSVW_STATUS:
2218 		if (!guest_cpuid_has_osvw(vcpu))
2219 			return 1;
2220 		vcpu->arch.osvw.status = data;
2221 		break;
2222 	default:
2223 		if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2224 			return xen_hvm_config(vcpu, data);
2225 		if (kvm_pmu_is_valid_msr(vcpu, msr))
2226 			return kvm_pmu_set_msr(vcpu, msr_info);
2227 		if (!ignore_msrs) {
2228 			vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2229 				    msr, data);
2230 			return 1;
2231 		} else {
2232 			vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2233 				    msr, data);
2234 			break;
2235 		}
2236 	}
2237 	return 0;
2238 }
2239 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2240 
2241 
2242 /*
2243  * Reads an msr value (of 'msr_index') into 'pdata'.
2244  * Returns 0 on success, non-0 otherwise.
2245  * Assumes vcpu_load() was already called.
2246  */
2247 int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
2248 {
2249 	return kvm_x86_ops->get_msr(vcpu, msr);
2250 }
2251 EXPORT_SYMBOL_GPL(kvm_get_msr);
2252 
2253 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2254 {
2255 	u64 data;
2256 	u64 mcg_cap = vcpu->arch.mcg_cap;
2257 	unsigned bank_num = mcg_cap & 0xff;
2258 
2259 	switch (msr) {
2260 	case MSR_IA32_P5_MC_ADDR:
2261 	case MSR_IA32_P5_MC_TYPE:
2262 		data = 0;
2263 		break;
2264 	case MSR_IA32_MCG_CAP:
2265 		data = vcpu->arch.mcg_cap;
2266 		break;
2267 	case MSR_IA32_MCG_CTL:
2268 		if (!(mcg_cap & MCG_CTL_P))
2269 			return 1;
2270 		data = vcpu->arch.mcg_ctl;
2271 		break;
2272 	case MSR_IA32_MCG_STATUS:
2273 		data = vcpu->arch.mcg_status;
2274 		break;
2275 	default:
2276 		if (msr >= MSR_IA32_MC0_CTL &&
2277 		    msr < MSR_IA32_MCx_CTL(bank_num)) {
2278 			u32 offset = msr - MSR_IA32_MC0_CTL;
2279 			data = vcpu->arch.mce_banks[offset];
2280 			break;
2281 		}
2282 		return 1;
2283 	}
2284 	*pdata = data;
2285 	return 0;
2286 }
2287 
2288 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2289 {
2290 	switch (msr_info->index) {
2291 	case MSR_IA32_PLATFORM_ID:
2292 	case MSR_IA32_EBL_CR_POWERON:
2293 	case MSR_IA32_DEBUGCTLMSR:
2294 	case MSR_IA32_LASTBRANCHFROMIP:
2295 	case MSR_IA32_LASTBRANCHTOIP:
2296 	case MSR_IA32_LASTINTFROMIP:
2297 	case MSR_IA32_LASTINTTOIP:
2298 	case MSR_K8_SYSCFG:
2299 	case MSR_K8_TSEG_ADDR:
2300 	case MSR_K8_TSEG_MASK:
2301 	case MSR_K7_HWCR:
2302 	case MSR_VM_HSAVE_PA:
2303 	case MSR_K8_INT_PENDING_MSG:
2304 	case MSR_AMD64_NB_CFG:
2305 	case MSR_FAM10H_MMIO_CONF_BASE:
2306 	case MSR_AMD64_BU_CFG2:
2307 		msr_info->data = 0;
2308 		break;
2309 	case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2310 	case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2311 	case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2312 	case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2313 		if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
2314 			return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2315 		msr_info->data = 0;
2316 		break;
2317 	case MSR_IA32_UCODE_REV:
2318 		msr_info->data = 0x100000000ULL;
2319 		break;
2320 	case MSR_MTRRcap:
2321 	case 0x200 ... 0x2ff:
2322 		return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
2323 	case 0xcd: /* fsb frequency */
2324 		msr_info->data = 3;
2325 		break;
2326 		/*
2327 		 * MSR_EBC_FREQUENCY_ID
2328 		 * Conservative value valid for even the basic CPU models.
2329 		 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2330 		 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2331 		 * and 266MHz for model 3, or 4. Set Core Clock
2332 		 * Frequency to System Bus Frequency Ratio to 1 (bits
2333 		 * 31:24) even though these are only valid for CPU
2334 		 * models > 2, however guests may end up dividing or
2335 		 * multiplying by zero otherwise.
2336 		 */
2337 	case MSR_EBC_FREQUENCY_ID:
2338 		msr_info->data = 1 << 24;
2339 		break;
2340 	case MSR_IA32_APICBASE:
2341 		msr_info->data = kvm_get_apic_base(vcpu);
2342 		break;
2343 	case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2344 		return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
2345 		break;
2346 	case MSR_IA32_TSCDEADLINE:
2347 		msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
2348 		break;
2349 	case MSR_IA32_TSC_ADJUST:
2350 		msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2351 		break;
2352 	case MSR_IA32_MISC_ENABLE:
2353 		msr_info->data = vcpu->arch.ia32_misc_enable_msr;
2354 		break;
2355 	case MSR_IA32_SMBASE:
2356 		if (!msr_info->host_initiated)
2357 			return 1;
2358 		msr_info->data = vcpu->arch.smbase;
2359 		break;
2360 	case MSR_IA32_PERF_STATUS:
2361 		/* TSC increment by tick */
2362 		msr_info->data = 1000ULL;
2363 		/* CPU multiplier */
2364 		msr_info->data |= (((uint64_t)4ULL) << 40);
2365 		break;
2366 	case MSR_EFER:
2367 		msr_info->data = vcpu->arch.efer;
2368 		break;
2369 	case MSR_KVM_WALL_CLOCK:
2370 	case MSR_KVM_WALL_CLOCK_NEW:
2371 		msr_info->data = vcpu->kvm->arch.wall_clock;
2372 		break;
2373 	case MSR_KVM_SYSTEM_TIME:
2374 	case MSR_KVM_SYSTEM_TIME_NEW:
2375 		msr_info->data = vcpu->arch.time;
2376 		break;
2377 	case MSR_KVM_ASYNC_PF_EN:
2378 		msr_info->data = vcpu->arch.apf.msr_val;
2379 		break;
2380 	case MSR_KVM_STEAL_TIME:
2381 		msr_info->data = vcpu->arch.st.msr_val;
2382 		break;
2383 	case MSR_KVM_PV_EOI_EN:
2384 		msr_info->data = vcpu->arch.pv_eoi.msr_val;
2385 		break;
2386 	case MSR_IA32_P5_MC_ADDR:
2387 	case MSR_IA32_P5_MC_TYPE:
2388 	case MSR_IA32_MCG_CAP:
2389 	case MSR_IA32_MCG_CTL:
2390 	case MSR_IA32_MCG_STATUS:
2391 	case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2392 		return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
2393 	case MSR_K7_CLK_CTL:
2394 		/*
2395 		 * Provide expected ramp-up count for K7. All other
2396 		 * are set to zero, indicating minimum divisors for
2397 		 * every field.
2398 		 *
2399 		 * This prevents guest kernels on AMD host with CPU
2400 		 * type 6, model 8 and higher from exploding due to
2401 		 * the rdmsr failing.
2402 		 */
2403 		msr_info->data = 0x20000000;
2404 		break;
2405 	case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2406 	case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2407 	case HV_X64_MSR_CRASH_CTL:
2408 	case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
2409 		return kvm_hv_get_msr_common(vcpu,
2410 					     msr_info->index, &msr_info->data);
2411 		break;
2412 	case MSR_IA32_BBL_CR_CTL3:
2413 		/* This legacy MSR exists but isn't fully documented in current
2414 		 * silicon.  It is however accessed by winxp in very narrow
2415 		 * scenarios where it sets bit #19, itself documented as
2416 		 * a "reserved" bit.  Best effort attempt to source coherent
2417 		 * read data here should the balance of the register be
2418 		 * interpreted by the guest:
2419 		 *
2420 		 * L2 cache control register 3: 64GB range, 256KB size,
2421 		 * enabled, latency 0x1, configured
2422 		 */
2423 		msr_info->data = 0xbe702111;
2424 		break;
2425 	case MSR_AMD64_OSVW_ID_LENGTH:
2426 		if (!guest_cpuid_has_osvw(vcpu))
2427 			return 1;
2428 		msr_info->data = vcpu->arch.osvw.length;
2429 		break;
2430 	case MSR_AMD64_OSVW_STATUS:
2431 		if (!guest_cpuid_has_osvw(vcpu))
2432 			return 1;
2433 		msr_info->data = vcpu->arch.osvw.status;
2434 		break;
2435 	default:
2436 		if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
2437 			return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2438 		if (!ignore_msrs) {
2439 			vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr_info->index);
2440 			return 1;
2441 		} else {
2442 			vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr_info->index);
2443 			msr_info->data = 0;
2444 		}
2445 		break;
2446 	}
2447 	return 0;
2448 }
2449 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2450 
2451 /*
2452  * Read or write a bunch of msrs. All parameters are kernel addresses.
2453  *
2454  * @return number of msrs set successfully.
2455  */
2456 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2457 		    struct kvm_msr_entry *entries,
2458 		    int (*do_msr)(struct kvm_vcpu *vcpu,
2459 				  unsigned index, u64 *data))
2460 {
2461 	int i, idx;
2462 
2463 	idx = srcu_read_lock(&vcpu->kvm->srcu);
2464 	for (i = 0; i < msrs->nmsrs; ++i)
2465 		if (do_msr(vcpu, entries[i].index, &entries[i].data))
2466 			break;
2467 	srcu_read_unlock(&vcpu->kvm->srcu, idx);
2468 
2469 	return i;
2470 }
2471 
2472 /*
2473  * Read or write a bunch of msrs. Parameters are user addresses.
2474  *
2475  * @return number of msrs set successfully.
2476  */
2477 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2478 		  int (*do_msr)(struct kvm_vcpu *vcpu,
2479 				unsigned index, u64 *data),
2480 		  int writeback)
2481 {
2482 	struct kvm_msrs msrs;
2483 	struct kvm_msr_entry *entries;
2484 	int r, n;
2485 	unsigned size;
2486 
2487 	r = -EFAULT;
2488 	if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2489 		goto out;
2490 
2491 	r = -E2BIG;
2492 	if (msrs.nmsrs >= MAX_IO_MSRS)
2493 		goto out;
2494 
2495 	size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
2496 	entries = memdup_user(user_msrs->entries, size);
2497 	if (IS_ERR(entries)) {
2498 		r = PTR_ERR(entries);
2499 		goto out;
2500 	}
2501 
2502 	r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2503 	if (r < 0)
2504 		goto out_free;
2505 
2506 	r = -EFAULT;
2507 	if (writeback && copy_to_user(user_msrs->entries, entries, size))
2508 		goto out_free;
2509 
2510 	r = n;
2511 
2512 out_free:
2513 	kfree(entries);
2514 out:
2515 	return r;
2516 }
2517 
2518 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
2519 {
2520 	int r;
2521 
2522 	switch (ext) {
2523 	case KVM_CAP_IRQCHIP:
2524 	case KVM_CAP_HLT:
2525 	case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
2526 	case KVM_CAP_SET_TSS_ADDR:
2527 	case KVM_CAP_EXT_CPUID:
2528 	case KVM_CAP_EXT_EMUL_CPUID:
2529 	case KVM_CAP_CLOCKSOURCE:
2530 	case KVM_CAP_PIT:
2531 	case KVM_CAP_NOP_IO_DELAY:
2532 	case KVM_CAP_MP_STATE:
2533 	case KVM_CAP_SYNC_MMU:
2534 	case KVM_CAP_USER_NMI:
2535 	case KVM_CAP_REINJECT_CONTROL:
2536 	case KVM_CAP_IRQ_INJECT_STATUS:
2537 	case KVM_CAP_IOEVENTFD:
2538 	case KVM_CAP_IOEVENTFD_NO_LENGTH:
2539 	case KVM_CAP_PIT2:
2540 	case KVM_CAP_PIT_STATE2:
2541 	case KVM_CAP_SET_IDENTITY_MAP_ADDR:
2542 	case KVM_CAP_XEN_HVM:
2543 	case KVM_CAP_ADJUST_CLOCK:
2544 	case KVM_CAP_VCPU_EVENTS:
2545 	case KVM_CAP_HYPERV:
2546 	case KVM_CAP_HYPERV_VAPIC:
2547 	case KVM_CAP_HYPERV_SPIN:
2548 	case KVM_CAP_HYPERV_SYNIC:
2549 	case KVM_CAP_PCI_SEGMENT:
2550 	case KVM_CAP_DEBUGREGS:
2551 	case KVM_CAP_X86_ROBUST_SINGLESTEP:
2552 	case KVM_CAP_XSAVE:
2553 	case KVM_CAP_ASYNC_PF:
2554 	case KVM_CAP_GET_TSC_KHZ:
2555 	case KVM_CAP_KVMCLOCK_CTRL:
2556 	case KVM_CAP_READONLY_MEM:
2557 	case KVM_CAP_HYPERV_TIME:
2558 	case KVM_CAP_IOAPIC_POLARITY_IGNORED:
2559 	case KVM_CAP_TSC_DEADLINE_TIMER:
2560 	case KVM_CAP_ENABLE_CAP_VM:
2561 	case KVM_CAP_DISABLE_QUIRKS:
2562 	case KVM_CAP_SET_BOOT_CPU_ID:
2563  	case KVM_CAP_SPLIT_IRQCHIP:
2564 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2565 	case KVM_CAP_ASSIGN_DEV_IRQ:
2566 	case KVM_CAP_PCI_2_3:
2567 #endif
2568 		r = 1;
2569 		break;
2570 	case KVM_CAP_X86_SMM:
2571 		/* SMBASE is usually relocated above 1M on modern chipsets,
2572 		 * and SMM handlers might indeed rely on 4G segment limits,
2573 		 * so do not report SMM to be available if real mode is
2574 		 * emulated via vm86 mode.  Still, do not go to great lengths
2575 		 * to avoid userspace's usage of the feature, because it is a
2576 		 * fringe case that is not enabled except via specific settings
2577 		 * of the module parameters.
2578 		 */
2579 		r = kvm_x86_ops->cpu_has_high_real_mode_segbase();
2580 		break;
2581 	case KVM_CAP_COALESCED_MMIO:
2582 		r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2583 		break;
2584 	case KVM_CAP_VAPIC:
2585 		r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2586 		break;
2587 	case KVM_CAP_NR_VCPUS:
2588 		r = KVM_SOFT_MAX_VCPUS;
2589 		break;
2590 	case KVM_CAP_MAX_VCPUS:
2591 		r = KVM_MAX_VCPUS;
2592 		break;
2593 	case KVM_CAP_NR_MEMSLOTS:
2594 		r = KVM_USER_MEM_SLOTS;
2595 		break;
2596 	case KVM_CAP_PV_MMU:	/* obsolete */
2597 		r = 0;
2598 		break;
2599 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2600 	case KVM_CAP_IOMMU:
2601 		r = iommu_present(&pci_bus_type);
2602 		break;
2603 #endif
2604 	case KVM_CAP_MCE:
2605 		r = KVM_MAX_MCE_BANKS;
2606 		break;
2607 	case KVM_CAP_XCRS:
2608 		r = cpu_has_xsave;
2609 		break;
2610 	case KVM_CAP_TSC_CONTROL:
2611 		r = kvm_has_tsc_control;
2612 		break;
2613 	default:
2614 		r = 0;
2615 		break;
2616 	}
2617 	return r;
2618 
2619 }
2620 
2621 long kvm_arch_dev_ioctl(struct file *filp,
2622 			unsigned int ioctl, unsigned long arg)
2623 {
2624 	void __user *argp = (void __user *)arg;
2625 	long r;
2626 
2627 	switch (ioctl) {
2628 	case KVM_GET_MSR_INDEX_LIST: {
2629 		struct kvm_msr_list __user *user_msr_list = argp;
2630 		struct kvm_msr_list msr_list;
2631 		unsigned n;
2632 
2633 		r = -EFAULT;
2634 		if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2635 			goto out;
2636 		n = msr_list.nmsrs;
2637 		msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
2638 		if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2639 			goto out;
2640 		r = -E2BIG;
2641 		if (n < msr_list.nmsrs)
2642 			goto out;
2643 		r = -EFAULT;
2644 		if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2645 				 num_msrs_to_save * sizeof(u32)))
2646 			goto out;
2647 		if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
2648 				 &emulated_msrs,
2649 				 num_emulated_msrs * sizeof(u32)))
2650 			goto out;
2651 		r = 0;
2652 		break;
2653 	}
2654 	case KVM_GET_SUPPORTED_CPUID:
2655 	case KVM_GET_EMULATED_CPUID: {
2656 		struct kvm_cpuid2 __user *cpuid_arg = argp;
2657 		struct kvm_cpuid2 cpuid;
2658 
2659 		r = -EFAULT;
2660 		if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2661 			goto out;
2662 
2663 		r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2664 					    ioctl);
2665 		if (r)
2666 			goto out;
2667 
2668 		r = -EFAULT;
2669 		if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2670 			goto out;
2671 		r = 0;
2672 		break;
2673 	}
2674 	case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2675 		u64 mce_cap;
2676 
2677 		mce_cap = KVM_MCE_CAP_SUPPORTED;
2678 		r = -EFAULT;
2679 		if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2680 			goto out;
2681 		r = 0;
2682 		break;
2683 	}
2684 	default:
2685 		r = -EINVAL;
2686 	}
2687 out:
2688 	return r;
2689 }
2690 
2691 static void wbinvd_ipi(void *garbage)
2692 {
2693 	wbinvd();
2694 }
2695 
2696 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2697 {
2698 	return kvm_arch_has_noncoherent_dma(vcpu->kvm);
2699 }
2700 
2701 static inline void kvm_migrate_timers(struct kvm_vcpu *vcpu)
2702 {
2703 	set_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests);
2704 }
2705 
2706 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2707 {
2708 	/* Address WBINVD may be executed by guest */
2709 	if (need_emulate_wbinvd(vcpu)) {
2710 		if (kvm_x86_ops->has_wbinvd_exit())
2711 			cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2712 		else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2713 			smp_call_function_single(vcpu->cpu,
2714 					wbinvd_ipi, NULL, 1);
2715 	}
2716 
2717 	kvm_x86_ops->vcpu_load(vcpu, cpu);
2718 
2719 	/* Apply any externally detected TSC adjustments (due to suspend) */
2720 	if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2721 		adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2722 		vcpu->arch.tsc_offset_adjustment = 0;
2723 		kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2724 	}
2725 
2726 	if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
2727 		s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2728 				rdtsc() - vcpu->arch.last_host_tsc;
2729 		if (tsc_delta < 0)
2730 			mark_tsc_unstable("KVM discovered backwards TSC");
2731 		if (check_tsc_unstable()) {
2732 			u64 offset = kvm_compute_tsc_offset(vcpu,
2733 						vcpu->arch.last_guest_tsc);
2734 			kvm_x86_ops->write_tsc_offset(vcpu, offset);
2735 			vcpu->arch.tsc_catchup = 1;
2736 		}
2737 		/*
2738 		 * On a host with synchronized TSC, there is no need to update
2739 		 * kvmclock on vcpu->cpu migration
2740 		 */
2741 		if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
2742 			kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2743 		if (vcpu->cpu != cpu)
2744 			kvm_migrate_timers(vcpu);
2745 		vcpu->cpu = cpu;
2746 	}
2747 
2748 	kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2749 }
2750 
2751 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2752 {
2753 	kvm_x86_ops->vcpu_put(vcpu);
2754 	kvm_put_guest_fpu(vcpu);
2755 	vcpu->arch.last_host_tsc = rdtsc();
2756 }
2757 
2758 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2759 				    struct kvm_lapic_state *s)
2760 {
2761 	if (vcpu->arch.apicv_active)
2762 		kvm_x86_ops->sync_pir_to_irr(vcpu);
2763 
2764 	memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
2765 
2766 	return 0;
2767 }
2768 
2769 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2770 				    struct kvm_lapic_state *s)
2771 {
2772 	kvm_apic_post_state_restore(vcpu, s);
2773 	update_cr8_intercept(vcpu);
2774 
2775 	return 0;
2776 }
2777 
2778 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
2779 {
2780 	return (!lapic_in_kernel(vcpu) ||
2781 		kvm_apic_accept_pic_intr(vcpu));
2782 }
2783 
2784 /*
2785  * if userspace requested an interrupt window, check that the
2786  * interrupt window is open.
2787  *
2788  * No need to exit to userspace if we already have an interrupt queued.
2789  */
2790 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
2791 {
2792 	return kvm_arch_interrupt_allowed(vcpu) &&
2793 		!kvm_cpu_has_interrupt(vcpu) &&
2794 		!kvm_event_needs_reinjection(vcpu) &&
2795 		kvm_cpu_accept_dm_intr(vcpu);
2796 }
2797 
2798 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2799 				    struct kvm_interrupt *irq)
2800 {
2801 	if (irq->irq >= KVM_NR_INTERRUPTS)
2802 		return -EINVAL;
2803 
2804 	if (!irqchip_in_kernel(vcpu->kvm)) {
2805 		kvm_queue_interrupt(vcpu, irq->irq, false);
2806 		kvm_make_request(KVM_REQ_EVENT, vcpu);
2807 		return 0;
2808 	}
2809 
2810 	/*
2811 	 * With in-kernel LAPIC, we only use this to inject EXTINT, so
2812 	 * fail for in-kernel 8259.
2813 	 */
2814 	if (pic_in_kernel(vcpu->kvm))
2815 		return -ENXIO;
2816 
2817 	if (vcpu->arch.pending_external_vector != -1)
2818 		return -EEXIST;
2819 
2820 	vcpu->arch.pending_external_vector = irq->irq;
2821 	kvm_make_request(KVM_REQ_EVENT, vcpu);
2822 	return 0;
2823 }
2824 
2825 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2826 {
2827 	kvm_inject_nmi(vcpu);
2828 
2829 	return 0;
2830 }
2831 
2832 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
2833 {
2834 	kvm_make_request(KVM_REQ_SMI, vcpu);
2835 
2836 	return 0;
2837 }
2838 
2839 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2840 					   struct kvm_tpr_access_ctl *tac)
2841 {
2842 	if (tac->flags)
2843 		return -EINVAL;
2844 	vcpu->arch.tpr_access_reporting = !!tac->enabled;
2845 	return 0;
2846 }
2847 
2848 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2849 					u64 mcg_cap)
2850 {
2851 	int r;
2852 	unsigned bank_num = mcg_cap & 0xff, bank;
2853 
2854 	r = -EINVAL;
2855 	if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
2856 		goto out;
2857 	if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2858 		goto out;
2859 	r = 0;
2860 	vcpu->arch.mcg_cap = mcg_cap;
2861 	/* Init IA32_MCG_CTL to all 1s */
2862 	if (mcg_cap & MCG_CTL_P)
2863 		vcpu->arch.mcg_ctl = ~(u64)0;
2864 	/* Init IA32_MCi_CTL to all 1s */
2865 	for (bank = 0; bank < bank_num; bank++)
2866 		vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2867 out:
2868 	return r;
2869 }
2870 
2871 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2872 				      struct kvm_x86_mce *mce)
2873 {
2874 	u64 mcg_cap = vcpu->arch.mcg_cap;
2875 	unsigned bank_num = mcg_cap & 0xff;
2876 	u64 *banks = vcpu->arch.mce_banks;
2877 
2878 	if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2879 		return -EINVAL;
2880 	/*
2881 	 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2882 	 * reporting is disabled
2883 	 */
2884 	if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2885 	    vcpu->arch.mcg_ctl != ~(u64)0)
2886 		return 0;
2887 	banks += 4 * mce->bank;
2888 	/*
2889 	 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2890 	 * reporting is disabled for the bank
2891 	 */
2892 	if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2893 		return 0;
2894 	if (mce->status & MCI_STATUS_UC) {
2895 		if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
2896 		    !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
2897 			kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2898 			return 0;
2899 		}
2900 		if (banks[1] & MCI_STATUS_VAL)
2901 			mce->status |= MCI_STATUS_OVER;
2902 		banks[2] = mce->addr;
2903 		banks[3] = mce->misc;
2904 		vcpu->arch.mcg_status = mce->mcg_status;
2905 		banks[1] = mce->status;
2906 		kvm_queue_exception(vcpu, MC_VECTOR);
2907 	} else if (!(banks[1] & MCI_STATUS_VAL)
2908 		   || !(banks[1] & MCI_STATUS_UC)) {
2909 		if (banks[1] & MCI_STATUS_VAL)
2910 			mce->status |= MCI_STATUS_OVER;
2911 		banks[2] = mce->addr;
2912 		banks[3] = mce->misc;
2913 		banks[1] = mce->status;
2914 	} else
2915 		banks[1] |= MCI_STATUS_OVER;
2916 	return 0;
2917 }
2918 
2919 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2920 					       struct kvm_vcpu_events *events)
2921 {
2922 	process_nmi(vcpu);
2923 	events->exception.injected =
2924 		vcpu->arch.exception.pending &&
2925 		!kvm_exception_is_soft(vcpu->arch.exception.nr);
2926 	events->exception.nr = vcpu->arch.exception.nr;
2927 	events->exception.has_error_code = vcpu->arch.exception.has_error_code;
2928 	events->exception.pad = 0;
2929 	events->exception.error_code = vcpu->arch.exception.error_code;
2930 
2931 	events->interrupt.injected =
2932 		vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
2933 	events->interrupt.nr = vcpu->arch.interrupt.nr;
2934 	events->interrupt.soft = 0;
2935 	events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
2936 
2937 	events->nmi.injected = vcpu->arch.nmi_injected;
2938 	events->nmi.pending = vcpu->arch.nmi_pending != 0;
2939 	events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
2940 	events->nmi.pad = 0;
2941 
2942 	events->sipi_vector = 0; /* never valid when reporting to user space */
2943 
2944 	events->smi.smm = is_smm(vcpu);
2945 	events->smi.pending = vcpu->arch.smi_pending;
2946 	events->smi.smm_inside_nmi =
2947 		!!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
2948 	events->smi.latched_init = kvm_lapic_latched_init(vcpu);
2949 
2950 	events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
2951 			 | KVM_VCPUEVENT_VALID_SHADOW
2952 			 | KVM_VCPUEVENT_VALID_SMM);
2953 	memset(&events->reserved, 0, sizeof(events->reserved));
2954 }
2955 
2956 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2957 					      struct kvm_vcpu_events *events)
2958 {
2959 	if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
2960 			      | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2961 			      | KVM_VCPUEVENT_VALID_SHADOW
2962 			      | KVM_VCPUEVENT_VALID_SMM))
2963 		return -EINVAL;
2964 
2965 	process_nmi(vcpu);
2966 	vcpu->arch.exception.pending = events->exception.injected;
2967 	vcpu->arch.exception.nr = events->exception.nr;
2968 	vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2969 	vcpu->arch.exception.error_code = events->exception.error_code;
2970 
2971 	vcpu->arch.interrupt.pending = events->interrupt.injected;
2972 	vcpu->arch.interrupt.nr = events->interrupt.nr;
2973 	vcpu->arch.interrupt.soft = events->interrupt.soft;
2974 	if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2975 		kvm_x86_ops->set_interrupt_shadow(vcpu,
2976 						  events->interrupt.shadow);
2977 
2978 	vcpu->arch.nmi_injected = events->nmi.injected;
2979 	if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2980 		vcpu->arch.nmi_pending = events->nmi.pending;
2981 	kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2982 
2983 	if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
2984 	    kvm_vcpu_has_lapic(vcpu))
2985 		vcpu->arch.apic->sipi_vector = events->sipi_vector;
2986 
2987 	if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
2988 		if (events->smi.smm)
2989 			vcpu->arch.hflags |= HF_SMM_MASK;
2990 		else
2991 			vcpu->arch.hflags &= ~HF_SMM_MASK;
2992 		vcpu->arch.smi_pending = events->smi.pending;
2993 		if (events->smi.smm_inside_nmi)
2994 			vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
2995 		else
2996 			vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
2997 		if (kvm_vcpu_has_lapic(vcpu)) {
2998 			if (events->smi.latched_init)
2999 				set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3000 			else
3001 				clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3002 		}
3003 	}
3004 
3005 	kvm_make_request(KVM_REQ_EVENT, vcpu);
3006 
3007 	return 0;
3008 }
3009 
3010 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3011 					     struct kvm_debugregs *dbgregs)
3012 {
3013 	unsigned long val;
3014 
3015 	memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
3016 	kvm_get_dr(vcpu, 6, &val);
3017 	dbgregs->dr6 = val;
3018 	dbgregs->dr7 = vcpu->arch.dr7;
3019 	dbgregs->flags = 0;
3020 	memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
3021 }
3022 
3023 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3024 					    struct kvm_debugregs *dbgregs)
3025 {
3026 	if (dbgregs->flags)
3027 		return -EINVAL;
3028 
3029 	memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
3030 	kvm_update_dr0123(vcpu);
3031 	vcpu->arch.dr6 = dbgregs->dr6;
3032 	kvm_update_dr6(vcpu);
3033 	vcpu->arch.dr7 = dbgregs->dr7;
3034 	kvm_update_dr7(vcpu);
3035 
3036 	return 0;
3037 }
3038 
3039 #define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3040 
3041 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3042 {
3043 	struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
3044 	u64 xstate_bv = xsave->header.xfeatures;
3045 	u64 valid;
3046 
3047 	/*
3048 	 * Copy legacy XSAVE area, to avoid complications with CPUID
3049 	 * leaves 0 and 1 in the loop below.
3050 	 */
3051 	memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3052 
3053 	/* Set XSTATE_BV */
3054 	*(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3055 
3056 	/*
3057 	 * Copy each region from the possibly compacted offset to the
3058 	 * non-compacted offset.
3059 	 */
3060 	valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
3061 	while (valid) {
3062 		u64 feature = valid & -valid;
3063 		int index = fls64(feature) - 1;
3064 		void *src = get_xsave_addr(xsave, feature);
3065 
3066 		if (src) {
3067 			u32 size, offset, ecx, edx;
3068 			cpuid_count(XSTATE_CPUID, index,
3069 				    &size, &offset, &ecx, &edx);
3070 			memcpy(dest + offset, src, size);
3071 		}
3072 
3073 		valid -= feature;
3074 	}
3075 }
3076 
3077 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3078 {
3079 	struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
3080 	u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3081 	u64 valid;
3082 
3083 	/*
3084 	 * Copy legacy XSAVE area, to avoid complications with CPUID
3085 	 * leaves 0 and 1 in the loop below.
3086 	 */
3087 	memcpy(xsave, src, XSAVE_HDR_OFFSET);
3088 
3089 	/* Set XSTATE_BV and possibly XCOMP_BV.  */
3090 	xsave->header.xfeatures = xstate_bv;
3091 	if (cpu_has_xsaves)
3092 		xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
3093 
3094 	/*
3095 	 * Copy each region from the non-compacted offset to the
3096 	 * possibly compacted offset.
3097 	 */
3098 	valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
3099 	while (valid) {
3100 		u64 feature = valid & -valid;
3101 		int index = fls64(feature) - 1;
3102 		void *dest = get_xsave_addr(xsave, feature);
3103 
3104 		if (dest) {
3105 			u32 size, offset, ecx, edx;
3106 			cpuid_count(XSTATE_CPUID, index,
3107 				    &size, &offset, &ecx, &edx);
3108 			memcpy(dest, src + offset, size);
3109 		}
3110 
3111 		valid -= feature;
3112 	}
3113 }
3114 
3115 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3116 					 struct kvm_xsave *guest_xsave)
3117 {
3118 	if (cpu_has_xsave) {
3119 		memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3120 		fill_xsave((u8 *) guest_xsave->region, vcpu);
3121 	} else {
3122 		memcpy(guest_xsave->region,
3123 			&vcpu->arch.guest_fpu.state.fxsave,
3124 			sizeof(struct fxregs_state));
3125 		*(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3126 			XFEATURE_MASK_FPSSE;
3127 	}
3128 }
3129 
3130 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3131 					struct kvm_xsave *guest_xsave)
3132 {
3133 	u64 xstate_bv =
3134 		*(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3135 
3136 	if (cpu_has_xsave) {
3137 		/*
3138 		 * Here we allow setting states that are not present in
3139 		 * CPUID leaf 0xD, index 0, EDX:EAX.  This is for compatibility
3140 		 * with old userspace.
3141 		 */
3142 		if (xstate_bv & ~kvm_supported_xcr0())
3143 			return -EINVAL;
3144 		load_xsave(vcpu, (u8 *)guest_xsave->region);
3145 	} else {
3146 		if (xstate_bv & ~XFEATURE_MASK_FPSSE)
3147 			return -EINVAL;
3148 		memcpy(&vcpu->arch.guest_fpu.state.fxsave,
3149 			guest_xsave->region, sizeof(struct fxregs_state));
3150 	}
3151 	return 0;
3152 }
3153 
3154 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3155 					struct kvm_xcrs *guest_xcrs)
3156 {
3157 	if (!cpu_has_xsave) {
3158 		guest_xcrs->nr_xcrs = 0;
3159 		return;
3160 	}
3161 
3162 	guest_xcrs->nr_xcrs = 1;
3163 	guest_xcrs->flags = 0;
3164 	guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3165 	guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3166 }
3167 
3168 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3169 				       struct kvm_xcrs *guest_xcrs)
3170 {
3171 	int i, r = 0;
3172 
3173 	if (!cpu_has_xsave)
3174 		return -EINVAL;
3175 
3176 	if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3177 		return -EINVAL;
3178 
3179 	for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3180 		/* Only support XCR0 currently */
3181 		if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
3182 			r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
3183 				guest_xcrs->xcrs[i].value);
3184 			break;
3185 		}
3186 	if (r)
3187 		r = -EINVAL;
3188 	return r;
3189 }
3190 
3191 /*
3192  * kvm_set_guest_paused() indicates to the guest kernel that it has been
3193  * stopped by the hypervisor.  This function will be called from the host only.
3194  * EINVAL is returned when the host attempts to set the flag for a guest that
3195  * does not support pv clocks.
3196  */
3197 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3198 {
3199 	if (!vcpu->arch.pv_time_enabled)
3200 		return -EINVAL;
3201 	vcpu->arch.pvclock_set_guest_stopped_request = true;
3202 	kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3203 	return 0;
3204 }
3205 
3206 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3207 				     struct kvm_enable_cap *cap)
3208 {
3209 	if (cap->flags)
3210 		return -EINVAL;
3211 
3212 	switch (cap->cap) {
3213 	case KVM_CAP_HYPERV_SYNIC:
3214 		return kvm_hv_activate_synic(vcpu);
3215 	default:
3216 		return -EINVAL;
3217 	}
3218 }
3219 
3220 long kvm_arch_vcpu_ioctl(struct file *filp,
3221 			 unsigned int ioctl, unsigned long arg)
3222 {
3223 	struct kvm_vcpu *vcpu = filp->private_data;
3224 	void __user *argp = (void __user *)arg;
3225 	int r;
3226 	union {
3227 		struct kvm_lapic_state *lapic;
3228 		struct kvm_xsave *xsave;
3229 		struct kvm_xcrs *xcrs;
3230 		void *buffer;
3231 	} u;
3232 
3233 	u.buffer = NULL;
3234 	switch (ioctl) {
3235 	case KVM_GET_LAPIC: {
3236 		r = -EINVAL;
3237 		if (!vcpu->arch.apic)
3238 			goto out;
3239 		u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
3240 
3241 		r = -ENOMEM;
3242 		if (!u.lapic)
3243 			goto out;
3244 		r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
3245 		if (r)
3246 			goto out;
3247 		r = -EFAULT;
3248 		if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
3249 			goto out;
3250 		r = 0;
3251 		break;
3252 	}
3253 	case KVM_SET_LAPIC: {
3254 		r = -EINVAL;
3255 		if (!vcpu->arch.apic)
3256 			goto out;
3257 		u.lapic = memdup_user(argp, sizeof(*u.lapic));
3258 		if (IS_ERR(u.lapic))
3259 			return PTR_ERR(u.lapic);
3260 
3261 		r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
3262 		break;
3263 	}
3264 	case KVM_INTERRUPT: {
3265 		struct kvm_interrupt irq;
3266 
3267 		r = -EFAULT;
3268 		if (copy_from_user(&irq, argp, sizeof irq))
3269 			goto out;
3270 		r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
3271 		break;
3272 	}
3273 	case KVM_NMI: {
3274 		r = kvm_vcpu_ioctl_nmi(vcpu);
3275 		break;
3276 	}
3277 	case KVM_SMI: {
3278 		r = kvm_vcpu_ioctl_smi(vcpu);
3279 		break;
3280 	}
3281 	case KVM_SET_CPUID: {
3282 		struct kvm_cpuid __user *cpuid_arg = argp;
3283 		struct kvm_cpuid cpuid;
3284 
3285 		r = -EFAULT;
3286 		if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3287 			goto out;
3288 		r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
3289 		break;
3290 	}
3291 	case KVM_SET_CPUID2: {
3292 		struct kvm_cpuid2 __user *cpuid_arg = argp;
3293 		struct kvm_cpuid2 cpuid;
3294 
3295 		r = -EFAULT;
3296 		if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3297 			goto out;
3298 		r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
3299 					      cpuid_arg->entries);
3300 		break;
3301 	}
3302 	case KVM_GET_CPUID2: {
3303 		struct kvm_cpuid2 __user *cpuid_arg = argp;
3304 		struct kvm_cpuid2 cpuid;
3305 
3306 		r = -EFAULT;
3307 		if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3308 			goto out;
3309 		r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
3310 					      cpuid_arg->entries);
3311 		if (r)
3312 			goto out;
3313 		r = -EFAULT;
3314 		if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3315 			goto out;
3316 		r = 0;
3317 		break;
3318 	}
3319 	case KVM_GET_MSRS:
3320 		r = msr_io(vcpu, argp, do_get_msr, 1);
3321 		break;
3322 	case KVM_SET_MSRS:
3323 		r = msr_io(vcpu, argp, do_set_msr, 0);
3324 		break;
3325 	case KVM_TPR_ACCESS_REPORTING: {
3326 		struct kvm_tpr_access_ctl tac;
3327 
3328 		r = -EFAULT;
3329 		if (copy_from_user(&tac, argp, sizeof tac))
3330 			goto out;
3331 		r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3332 		if (r)
3333 			goto out;
3334 		r = -EFAULT;
3335 		if (copy_to_user(argp, &tac, sizeof tac))
3336 			goto out;
3337 		r = 0;
3338 		break;
3339 	};
3340 	case KVM_SET_VAPIC_ADDR: {
3341 		struct kvm_vapic_addr va;
3342 
3343 		r = -EINVAL;
3344 		if (!lapic_in_kernel(vcpu))
3345 			goto out;
3346 		r = -EFAULT;
3347 		if (copy_from_user(&va, argp, sizeof va))
3348 			goto out;
3349 		r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
3350 		break;
3351 	}
3352 	case KVM_X86_SETUP_MCE: {
3353 		u64 mcg_cap;
3354 
3355 		r = -EFAULT;
3356 		if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3357 			goto out;
3358 		r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3359 		break;
3360 	}
3361 	case KVM_X86_SET_MCE: {
3362 		struct kvm_x86_mce mce;
3363 
3364 		r = -EFAULT;
3365 		if (copy_from_user(&mce, argp, sizeof mce))
3366 			goto out;
3367 		r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3368 		break;
3369 	}
3370 	case KVM_GET_VCPU_EVENTS: {
3371 		struct kvm_vcpu_events events;
3372 
3373 		kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3374 
3375 		r = -EFAULT;
3376 		if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3377 			break;
3378 		r = 0;
3379 		break;
3380 	}
3381 	case KVM_SET_VCPU_EVENTS: {
3382 		struct kvm_vcpu_events events;
3383 
3384 		r = -EFAULT;
3385 		if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3386 			break;
3387 
3388 		r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3389 		break;
3390 	}
3391 	case KVM_GET_DEBUGREGS: {
3392 		struct kvm_debugregs dbgregs;
3393 
3394 		kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3395 
3396 		r = -EFAULT;
3397 		if (copy_to_user(argp, &dbgregs,
3398 				 sizeof(struct kvm_debugregs)))
3399 			break;
3400 		r = 0;
3401 		break;
3402 	}
3403 	case KVM_SET_DEBUGREGS: {
3404 		struct kvm_debugregs dbgregs;
3405 
3406 		r = -EFAULT;
3407 		if (copy_from_user(&dbgregs, argp,
3408 				   sizeof(struct kvm_debugregs)))
3409 			break;
3410 
3411 		r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3412 		break;
3413 	}
3414 	case KVM_GET_XSAVE: {
3415 		u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
3416 		r = -ENOMEM;
3417 		if (!u.xsave)
3418 			break;
3419 
3420 		kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
3421 
3422 		r = -EFAULT;
3423 		if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
3424 			break;
3425 		r = 0;
3426 		break;
3427 	}
3428 	case KVM_SET_XSAVE: {
3429 		u.xsave = memdup_user(argp, sizeof(*u.xsave));
3430 		if (IS_ERR(u.xsave))
3431 			return PTR_ERR(u.xsave);
3432 
3433 		r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
3434 		break;
3435 	}
3436 	case KVM_GET_XCRS: {
3437 		u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
3438 		r = -ENOMEM;
3439 		if (!u.xcrs)
3440 			break;
3441 
3442 		kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
3443 
3444 		r = -EFAULT;
3445 		if (copy_to_user(argp, u.xcrs,
3446 				 sizeof(struct kvm_xcrs)))
3447 			break;
3448 		r = 0;
3449 		break;
3450 	}
3451 	case KVM_SET_XCRS: {
3452 		u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
3453 		if (IS_ERR(u.xcrs))
3454 			return PTR_ERR(u.xcrs);
3455 
3456 		r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
3457 		break;
3458 	}
3459 	case KVM_SET_TSC_KHZ: {
3460 		u32 user_tsc_khz;
3461 
3462 		r = -EINVAL;
3463 		user_tsc_khz = (u32)arg;
3464 
3465 		if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3466 			goto out;
3467 
3468 		if (user_tsc_khz == 0)
3469 			user_tsc_khz = tsc_khz;
3470 
3471 		if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
3472 			r = 0;
3473 
3474 		goto out;
3475 	}
3476 	case KVM_GET_TSC_KHZ: {
3477 		r = vcpu->arch.virtual_tsc_khz;
3478 		goto out;
3479 	}
3480 	case KVM_KVMCLOCK_CTRL: {
3481 		r = kvm_set_guest_paused(vcpu);
3482 		goto out;
3483 	}
3484 	case KVM_ENABLE_CAP: {
3485 		struct kvm_enable_cap cap;
3486 
3487 		r = -EFAULT;
3488 		if (copy_from_user(&cap, argp, sizeof(cap)))
3489 			goto out;
3490 		r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
3491 		break;
3492 	}
3493 	default:
3494 		r = -EINVAL;
3495 	}
3496 out:
3497 	kfree(u.buffer);
3498 	return r;
3499 }
3500 
3501 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3502 {
3503 	return VM_FAULT_SIGBUS;
3504 }
3505 
3506 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3507 {
3508 	int ret;
3509 
3510 	if (addr > (unsigned int)(-3 * PAGE_SIZE))
3511 		return -EINVAL;
3512 	ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3513 	return ret;
3514 }
3515 
3516 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3517 					      u64 ident_addr)
3518 {
3519 	kvm->arch.ept_identity_map_addr = ident_addr;
3520 	return 0;
3521 }
3522 
3523 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3524 					  u32 kvm_nr_mmu_pages)
3525 {
3526 	if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3527 		return -EINVAL;
3528 
3529 	mutex_lock(&kvm->slots_lock);
3530 
3531 	kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
3532 	kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
3533 
3534 	mutex_unlock(&kvm->slots_lock);
3535 	return 0;
3536 }
3537 
3538 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3539 {
3540 	return kvm->arch.n_max_mmu_pages;
3541 }
3542 
3543 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3544 {
3545 	int r;
3546 
3547 	r = 0;
3548 	switch (chip->chip_id) {
3549 	case KVM_IRQCHIP_PIC_MASTER:
3550 		memcpy(&chip->chip.pic,
3551 			&pic_irqchip(kvm)->pics[0],
3552 			sizeof(struct kvm_pic_state));
3553 		break;
3554 	case KVM_IRQCHIP_PIC_SLAVE:
3555 		memcpy(&chip->chip.pic,
3556 			&pic_irqchip(kvm)->pics[1],
3557 			sizeof(struct kvm_pic_state));
3558 		break;
3559 	case KVM_IRQCHIP_IOAPIC:
3560 		r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
3561 		break;
3562 	default:
3563 		r = -EINVAL;
3564 		break;
3565 	}
3566 	return r;
3567 }
3568 
3569 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3570 {
3571 	int r;
3572 
3573 	r = 0;
3574 	switch (chip->chip_id) {
3575 	case KVM_IRQCHIP_PIC_MASTER:
3576 		spin_lock(&pic_irqchip(kvm)->lock);
3577 		memcpy(&pic_irqchip(kvm)->pics[0],
3578 			&chip->chip.pic,
3579 			sizeof(struct kvm_pic_state));
3580 		spin_unlock(&pic_irqchip(kvm)->lock);
3581 		break;
3582 	case KVM_IRQCHIP_PIC_SLAVE:
3583 		spin_lock(&pic_irqchip(kvm)->lock);
3584 		memcpy(&pic_irqchip(kvm)->pics[1],
3585 			&chip->chip.pic,
3586 			sizeof(struct kvm_pic_state));
3587 		spin_unlock(&pic_irqchip(kvm)->lock);
3588 		break;
3589 	case KVM_IRQCHIP_IOAPIC:
3590 		r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
3591 		break;
3592 	default:
3593 		r = -EINVAL;
3594 		break;
3595 	}
3596 	kvm_pic_update_irq(pic_irqchip(kvm));
3597 	return r;
3598 }
3599 
3600 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3601 {
3602 	mutex_lock(&kvm->arch.vpit->pit_state.lock);
3603 	memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
3604 	mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3605 	return 0;
3606 }
3607 
3608 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3609 {
3610 	int i;
3611 	mutex_lock(&kvm->arch.vpit->pit_state.lock);
3612 	memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
3613 	for (i = 0; i < 3; i++)
3614 		kvm_pit_load_count(kvm, i, ps->channels[i].count, 0);
3615 	mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3616 	return 0;
3617 }
3618 
3619 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3620 {
3621 	mutex_lock(&kvm->arch.vpit->pit_state.lock);
3622 	memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3623 		sizeof(ps->channels));
3624 	ps->flags = kvm->arch.vpit->pit_state.flags;
3625 	mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3626 	memset(&ps->reserved, 0, sizeof(ps->reserved));
3627 	return 0;
3628 }
3629 
3630 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3631 {
3632 	int start = 0;
3633 	int i;
3634 	u32 prev_legacy, cur_legacy;
3635 	mutex_lock(&kvm->arch.vpit->pit_state.lock);
3636 	prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3637 	cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3638 	if (!prev_legacy && cur_legacy)
3639 		start = 1;
3640 	memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3641 	       sizeof(kvm->arch.vpit->pit_state.channels));
3642 	kvm->arch.vpit->pit_state.flags = ps->flags;
3643 	for (i = 0; i < 3; i++)
3644 		kvm_pit_load_count(kvm, i, kvm->arch.vpit->pit_state.channels[i].count,
3645 				   start && i == 0);
3646 	mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3647 	return 0;
3648 }
3649 
3650 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3651 				 struct kvm_reinject_control *control)
3652 {
3653 	if (!kvm->arch.vpit)
3654 		return -ENXIO;
3655 	mutex_lock(&kvm->arch.vpit->pit_state.lock);
3656 	kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
3657 	mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3658 	return 0;
3659 }
3660 
3661 /**
3662  * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3663  * @kvm: kvm instance
3664  * @log: slot id and address to which we copy the log
3665  *
3666  * Steps 1-4 below provide general overview of dirty page logging. See
3667  * kvm_get_dirty_log_protect() function description for additional details.
3668  *
3669  * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3670  * always flush the TLB (step 4) even if previous step failed  and the dirty
3671  * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3672  * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3673  * writes will be marked dirty for next log read.
3674  *
3675  *   1. Take a snapshot of the bit and clear it if needed.
3676  *   2. Write protect the corresponding page.
3677  *   3. Copy the snapshot to the userspace.
3678  *   4. Flush TLB's if needed.
3679  */
3680 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
3681 {
3682 	bool is_dirty = false;
3683 	int r;
3684 
3685 	mutex_lock(&kvm->slots_lock);
3686 
3687 	/*
3688 	 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3689 	 */
3690 	if (kvm_x86_ops->flush_log_dirty)
3691 		kvm_x86_ops->flush_log_dirty(kvm);
3692 
3693 	r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
3694 
3695 	/*
3696 	 * All the TLBs can be flushed out of mmu lock, see the comments in
3697 	 * kvm_mmu_slot_remove_write_access().
3698 	 */
3699 	lockdep_assert_held(&kvm->slots_lock);
3700 	if (is_dirty)
3701 		kvm_flush_remote_tlbs(kvm);
3702 
3703 	mutex_unlock(&kvm->slots_lock);
3704 	return r;
3705 }
3706 
3707 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3708 			bool line_status)
3709 {
3710 	if (!irqchip_in_kernel(kvm))
3711 		return -ENXIO;
3712 
3713 	irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3714 					irq_event->irq, irq_event->level,
3715 					line_status);
3716 	return 0;
3717 }
3718 
3719 static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
3720 				   struct kvm_enable_cap *cap)
3721 {
3722 	int r;
3723 
3724 	if (cap->flags)
3725 		return -EINVAL;
3726 
3727 	switch (cap->cap) {
3728 	case KVM_CAP_DISABLE_QUIRKS:
3729 		kvm->arch.disabled_quirks = cap->args[0];
3730 		r = 0;
3731 		break;
3732 	case KVM_CAP_SPLIT_IRQCHIP: {
3733 		mutex_lock(&kvm->lock);
3734 		r = -EINVAL;
3735 		if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
3736 			goto split_irqchip_unlock;
3737 		r = -EEXIST;
3738 		if (irqchip_in_kernel(kvm))
3739 			goto split_irqchip_unlock;
3740 		if (atomic_read(&kvm->online_vcpus))
3741 			goto split_irqchip_unlock;
3742 		r = kvm_setup_empty_irq_routing(kvm);
3743 		if (r)
3744 			goto split_irqchip_unlock;
3745 		/* Pairs with irqchip_in_kernel. */
3746 		smp_wmb();
3747 		kvm->arch.irqchip_split = true;
3748 		kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
3749 		r = 0;
3750 split_irqchip_unlock:
3751 		mutex_unlock(&kvm->lock);
3752 		break;
3753 	}
3754 	default:
3755 		r = -EINVAL;
3756 		break;
3757 	}
3758 	return r;
3759 }
3760 
3761 long kvm_arch_vm_ioctl(struct file *filp,
3762 		       unsigned int ioctl, unsigned long arg)
3763 {
3764 	struct kvm *kvm = filp->private_data;
3765 	void __user *argp = (void __user *)arg;
3766 	int r = -ENOTTY;
3767 	/*
3768 	 * This union makes it completely explicit to gcc-3.x
3769 	 * that these two variables' stack usage should be
3770 	 * combined, not added together.
3771 	 */
3772 	union {
3773 		struct kvm_pit_state ps;
3774 		struct kvm_pit_state2 ps2;
3775 		struct kvm_pit_config pit_config;
3776 	} u;
3777 
3778 	switch (ioctl) {
3779 	case KVM_SET_TSS_ADDR:
3780 		r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3781 		break;
3782 	case KVM_SET_IDENTITY_MAP_ADDR: {
3783 		u64 ident_addr;
3784 
3785 		r = -EFAULT;
3786 		if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3787 			goto out;
3788 		r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3789 		break;
3790 	}
3791 	case KVM_SET_NR_MMU_PAGES:
3792 		r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3793 		break;
3794 	case KVM_GET_NR_MMU_PAGES:
3795 		r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3796 		break;
3797 	case KVM_CREATE_IRQCHIP: {
3798 		struct kvm_pic *vpic;
3799 
3800 		mutex_lock(&kvm->lock);
3801 		r = -EEXIST;
3802 		if (kvm->arch.vpic)
3803 			goto create_irqchip_unlock;
3804 		r = -EINVAL;
3805 		if (atomic_read(&kvm->online_vcpus))
3806 			goto create_irqchip_unlock;
3807 		r = -ENOMEM;
3808 		vpic = kvm_create_pic(kvm);
3809 		if (vpic) {
3810 			r = kvm_ioapic_init(kvm);
3811 			if (r) {
3812 				mutex_lock(&kvm->slots_lock);
3813 				kvm_destroy_pic(vpic);
3814 				mutex_unlock(&kvm->slots_lock);
3815 				goto create_irqchip_unlock;
3816 			}
3817 		} else
3818 			goto create_irqchip_unlock;
3819 		r = kvm_setup_default_irq_routing(kvm);
3820 		if (r) {
3821 			mutex_lock(&kvm->slots_lock);
3822 			mutex_lock(&kvm->irq_lock);
3823 			kvm_ioapic_destroy(kvm);
3824 			kvm_destroy_pic(vpic);
3825 			mutex_unlock(&kvm->irq_lock);
3826 			mutex_unlock(&kvm->slots_lock);
3827 			goto create_irqchip_unlock;
3828 		}
3829 		/* Write kvm->irq_routing before kvm->arch.vpic.  */
3830 		smp_wmb();
3831 		kvm->arch.vpic = vpic;
3832 	create_irqchip_unlock:
3833 		mutex_unlock(&kvm->lock);
3834 		break;
3835 	}
3836 	case KVM_CREATE_PIT:
3837 		u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3838 		goto create_pit;
3839 	case KVM_CREATE_PIT2:
3840 		r = -EFAULT;
3841 		if (copy_from_user(&u.pit_config, argp,
3842 				   sizeof(struct kvm_pit_config)))
3843 			goto out;
3844 	create_pit:
3845 		mutex_lock(&kvm->slots_lock);
3846 		r = -EEXIST;
3847 		if (kvm->arch.vpit)
3848 			goto create_pit_unlock;
3849 		r = -ENOMEM;
3850 		kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
3851 		if (kvm->arch.vpit)
3852 			r = 0;
3853 	create_pit_unlock:
3854 		mutex_unlock(&kvm->slots_lock);
3855 		break;
3856 	case KVM_GET_IRQCHIP: {
3857 		/* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3858 		struct kvm_irqchip *chip;
3859 
3860 		chip = memdup_user(argp, sizeof(*chip));
3861 		if (IS_ERR(chip)) {
3862 			r = PTR_ERR(chip);
3863 			goto out;
3864 		}
3865 
3866 		r = -ENXIO;
3867 		if (!irqchip_in_kernel(kvm) || irqchip_split(kvm))
3868 			goto get_irqchip_out;
3869 		r = kvm_vm_ioctl_get_irqchip(kvm, chip);
3870 		if (r)
3871 			goto get_irqchip_out;
3872 		r = -EFAULT;
3873 		if (copy_to_user(argp, chip, sizeof *chip))
3874 			goto get_irqchip_out;
3875 		r = 0;
3876 	get_irqchip_out:
3877 		kfree(chip);
3878 		break;
3879 	}
3880 	case KVM_SET_IRQCHIP: {
3881 		/* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3882 		struct kvm_irqchip *chip;
3883 
3884 		chip = memdup_user(argp, sizeof(*chip));
3885 		if (IS_ERR(chip)) {
3886 			r = PTR_ERR(chip);
3887 			goto out;
3888 		}
3889 
3890 		r = -ENXIO;
3891 		if (!irqchip_in_kernel(kvm) || irqchip_split(kvm))
3892 			goto set_irqchip_out;
3893 		r = kvm_vm_ioctl_set_irqchip(kvm, chip);
3894 		if (r)
3895 			goto set_irqchip_out;
3896 		r = 0;
3897 	set_irqchip_out:
3898 		kfree(chip);
3899 		break;
3900 	}
3901 	case KVM_GET_PIT: {
3902 		r = -EFAULT;
3903 		if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
3904 			goto out;
3905 		r = -ENXIO;
3906 		if (!kvm->arch.vpit)
3907 			goto out;
3908 		r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
3909 		if (r)
3910 			goto out;
3911 		r = -EFAULT;
3912 		if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
3913 			goto out;
3914 		r = 0;
3915 		break;
3916 	}
3917 	case KVM_SET_PIT: {
3918 		r = -EFAULT;
3919 		if (copy_from_user(&u.ps, argp, sizeof u.ps))
3920 			goto out;
3921 		r = -ENXIO;
3922 		if (!kvm->arch.vpit)
3923 			goto out;
3924 		r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
3925 		break;
3926 	}
3927 	case KVM_GET_PIT2: {
3928 		r = -ENXIO;
3929 		if (!kvm->arch.vpit)
3930 			goto out;
3931 		r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3932 		if (r)
3933 			goto out;
3934 		r = -EFAULT;
3935 		if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3936 			goto out;
3937 		r = 0;
3938 		break;
3939 	}
3940 	case KVM_SET_PIT2: {
3941 		r = -EFAULT;
3942 		if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3943 			goto out;
3944 		r = -ENXIO;
3945 		if (!kvm->arch.vpit)
3946 			goto out;
3947 		r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3948 		break;
3949 	}
3950 	case KVM_REINJECT_CONTROL: {
3951 		struct kvm_reinject_control control;
3952 		r =  -EFAULT;
3953 		if (copy_from_user(&control, argp, sizeof(control)))
3954 			goto out;
3955 		r = kvm_vm_ioctl_reinject(kvm, &control);
3956 		break;
3957 	}
3958 	case KVM_SET_BOOT_CPU_ID:
3959 		r = 0;
3960 		mutex_lock(&kvm->lock);
3961 		if (atomic_read(&kvm->online_vcpus) != 0)
3962 			r = -EBUSY;
3963 		else
3964 			kvm->arch.bsp_vcpu_id = arg;
3965 		mutex_unlock(&kvm->lock);
3966 		break;
3967 	case KVM_XEN_HVM_CONFIG: {
3968 		r = -EFAULT;
3969 		if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3970 				   sizeof(struct kvm_xen_hvm_config)))
3971 			goto out;
3972 		r = -EINVAL;
3973 		if (kvm->arch.xen_hvm_config.flags)
3974 			goto out;
3975 		r = 0;
3976 		break;
3977 	}
3978 	case KVM_SET_CLOCK: {
3979 		struct kvm_clock_data user_ns;
3980 		u64 now_ns;
3981 		s64 delta;
3982 
3983 		r = -EFAULT;
3984 		if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3985 			goto out;
3986 
3987 		r = -EINVAL;
3988 		if (user_ns.flags)
3989 			goto out;
3990 
3991 		r = 0;
3992 		local_irq_disable();
3993 		now_ns = get_kernel_ns();
3994 		delta = user_ns.clock - now_ns;
3995 		local_irq_enable();
3996 		kvm->arch.kvmclock_offset = delta;
3997 		kvm_gen_update_masterclock(kvm);
3998 		break;
3999 	}
4000 	case KVM_GET_CLOCK: {
4001 		struct kvm_clock_data user_ns;
4002 		u64 now_ns;
4003 
4004 		local_irq_disable();
4005 		now_ns = get_kernel_ns();
4006 		user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
4007 		local_irq_enable();
4008 		user_ns.flags = 0;
4009 		memset(&user_ns.pad, 0, sizeof(user_ns.pad));
4010 
4011 		r = -EFAULT;
4012 		if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4013 			goto out;
4014 		r = 0;
4015 		break;
4016 	}
4017 	case KVM_ENABLE_CAP: {
4018 		struct kvm_enable_cap cap;
4019 
4020 		r = -EFAULT;
4021 		if (copy_from_user(&cap, argp, sizeof(cap)))
4022 			goto out;
4023 		r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4024 		break;
4025 	}
4026 	default:
4027 		r = kvm_vm_ioctl_assigned_device(kvm, ioctl, arg);
4028 	}
4029 out:
4030 	return r;
4031 }
4032 
4033 static void kvm_init_msr_list(void)
4034 {
4035 	u32 dummy[2];
4036 	unsigned i, j;
4037 
4038 	for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
4039 		if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4040 			continue;
4041 
4042 		/*
4043 		 * Even MSRs that are valid in the host may not be exposed
4044 		 * to the guests in some cases.
4045 		 */
4046 		switch (msrs_to_save[i]) {
4047 		case MSR_IA32_BNDCFGS:
4048 			if (!kvm_x86_ops->mpx_supported())
4049 				continue;
4050 			break;
4051 		case MSR_TSC_AUX:
4052 			if (!kvm_x86_ops->rdtscp_supported())
4053 				continue;
4054 			break;
4055 		default:
4056 			break;
4057 		}
4058 
4059 		if (j < i)
4060 			msrs_to_save[j] = msrs_to_save[i];
4061 		j++;
4062 	}
4063 	num_msrs_to_save = j;
4064 
4065 	for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
4066 		switch (emulated_msrs[i]) {
4067 		case MSR_IA32_SMBASE:
4068 			if (!kvm_x86_ops->cpu_has_high_real_mode_segbase())
4069 				continue;
4070 			break;
4071 		default:
4072 			break;
4073 		}
4074 
4075 		if (j < i)
4076 			emulated_msrs[j] = emulated_msrs[i];
4077 		j++;
4078 	}
4079 	num_emulated_msrs = j;
4080 }
4081 
4082 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4083 			   const void *v)
4084 {
4085 	int handled = 0;
4086 	int n;
4087 
4088 	do {
4089 		n = min(len, 8);
4090 		if (!(vcpu->arch.apic &&
4091 		      !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4092 		    && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
4093 			break;
4094 		handled += n;
4095 		addr += n;
4096 		len -= n;
4097 		v += n;
4098 	} while (len);
4099 
4100 	return handled;
4101 }
4102 
4103 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
4104 {
4105 	int handled = 0;
4106 	int n;
4107 
4108 	do {
4109 		n = min(len, 8);
4110 		if (!(vcpu->arch.apic &&
4111 		      !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4112 					 addr, n, v))
4113 		    && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
4114 			break;
4115 		trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4116 		handled += n;
4117 		addr += n;
4118 		len -= n;
4119 		v += n;
4120 	} while (len);
4121 
4122 	return handled;
4123 }
4124 
4125 static void kvm_set_segment(struct kvm_vcpu *vcpu,
4126 			struct kvm_segment *var, int seg)
4127 {
4128 	kvm_x86_ops->set_segment(vcpu, var, seg);
4129 }
4130 
4131 void kvm_get_segment(struct kvm_vcpu *vcpu,
4132 		     struct kvm_segment *var, int seg)
4133 {
4134 	kvm_x86_ops->get_segment(vcpu, var, seg);
4135 }
4136 
4137 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4138 			   struct x86_exception *exception)
4139 {
4140 	gpa_t t_gpa;
4141 
4142 	BUG_ON(!mmu_is_nested(vcpu));
4143 
4144 	/* NPT walks are always user-walks */
4145 	access |= PFERR_USER_MASK;
4146 	t_gpa  = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
4147 
4148 	return t_gpa;
4149 }
4150 
4151 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4152 			      struct x86_exception *exception)
4153 {
4154 	u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4155 	return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4156 }
4157 
4158  gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4159 				struct x86_exception *exception)
4160 {
4161 	u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4162 	access |= PFERR_FETCH_MASK;
4163 	return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4164 }
4165 
4166 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4167 			       struct x86_exception *exception)
4168 {
4169 	u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4170 	access |= PFERR_WRITE_MASK;
4171 	return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4172 }
4173 
4174 /* uses this to access any guest's mapped memory without checking CPL */
4175 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4176 				struct x86_exception *exception)
4177 {
4178 	return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
4179 }
4180 
4181 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4182 				      struct kvm_vcpu *vcpu, u32 access,
4183 				      struct x86_exception *exception)
4184 {
4185 	void *data = val;
4186 	int r = X86EMUL_CONTINUE;
4187 
4188 	while (bytes) {
4189 		gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
4190 							    exception);
4191 		unsigned offset = addr & (PAGE_SIZE-1);
4192 		unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
4193 		int ret;
4194 
4195 		if (gpa == UNMAPPED_GVA)
4196 			return X86EMUL_PROPAGATE_FAULT;
4197 		ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4198 					       offset, toread);
4199 		if (ret < 0) {
4200 			r = X86EMUL_IO_NEEDED;
4201 			goto out;
4202 		}
4203 
4204 		bytes -= toread;
4205 		data += toread;
4206 		addr += toread;
4207 	}
4208 out:
4209 	return r;
4210 }
4211 
4212 /* used for instruction fetching */
4213 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4214 				gva_t addr, void *val, unsigned int bytes,
4215 				struct x86_exception *exception)
4216 {
4217 	struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4218 	u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4219 	unsigned offset;
4220 	int ret;
4221 
4222 	/* Inline kvm_read_guest_virt_helper for speed.  */
4223 	gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4224 						    exception);
4225 	if (unlikely(gpa == UNMAPPED_GVA))
4226 		return X86EMUL_PROPAGATE_FAULT;
4227 
4228 	offset = addr & (PAGE_SIZE-1);
4229 	if (WARN_ON(offset + bytes > PAGE_SIZE))
4230 		bytes = (unsigned)PAGE_SIZE - offset;
4231 	ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4232 				       offset, bytes);
4233 	if (unlikely(ret < 0))
4234 		return X86EMUL_IO_NEEDED;
4235 
4236 	return X86EMUL_CONTINUE;
4237 }
4238 
4239 int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
4240 			       gva_t addr, void *val, unsigned int bytes,
4241 			       struct x86_exception *exception)
4242 {
4243 	struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4244 	u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4245 
4246 	return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
4247 					  exception);
4248 }
4249 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
4250 
4251 static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4252 				      gva_t addr, void *val, unsigned int bytes,
4253 				      struct x86_exception *exception)
4254 {
4255 	struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4256 	return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
4257 }
4258 
4259 static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4260 		unsigned long addr, void *val, unsigned int bytes)
4261 {
4262 	struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4263 	int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4264 
4265 	return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4266 }
4267 
4268 int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4269 				       gva_t addr, void *val,
4270 				       unsigned int bytes,
4271 				       struct x86_exception *exception)
4272 {
4273 	struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4274 	void *data = val;
4275 	int r = X86EMUL_CONTINUE;
4276 
4277 	while (bytes) {
4278 		gpa_t gpa =  vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4279 							     PFERR_WRITE_MASK,
4280 							     exception);
4281 		unsigned offset = addr & (PAGE_SIZE-1);
4282 		unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4283 		int ret;
4284 
4285 		if (gpa == UNMAPPED_GVA)
4286 			return X86EMUL_PROPAGATE_FAULT;
4287 		ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
4288 		if (ret < 0) {
4289 			r = X86EMUL_IO_NEEDED;
4290 			goto out;
4291 		}
4292 
4293 		bytes -= towrite;
4294 		data += towrite;
4295 		addr += towrite;
4296 	}
4297 out:
4298 	return r;
4299 }
4300 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
4301 
4302 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4303 				gpa_t *gpa, struct x86_exception *exception,
4304 				bool write)
4305 {
4306 	u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4307 		| (write ? PFERR_WRITE_MASK : 0);
4308 
4309 	if (vcpu_match_mmio_gva(vcpu, gva)
4310 	    && !permission_fault(vcpu, vcpu->arch.walk_mmu,
4311 				 vcpu->arch.access, access)) {
4312 		*gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4313 					(gva & (PAGE_SIZE - 1));
4314 		trace_vcpu_match_mmio(gva, *gpa, write, false);
4315 		return 1;
4316 	}
4317 
4318 	*gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4319 
4320 	if (*gpa == UNMAPPED_GVA)
4321 		return -1;
4322 
4323 	/* For APIC access vmexit */
4324 	if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4325 		return 1;
4326 
4327 	if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4328 		trace_vcpu_match_mmio(gva, *gpa, write, true);
4329 		return 1;
4330 	}
4331 
4332 	return 0;
4333 }
4334 
4335 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
4336 			const void *val, int bytes)
4337 {
4338 	int ret;
4339 
4340 	ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
4341 	if (ret < 0)
4342 		return 0;
4343 	kvm_mmu_pte_write(vcpu, gpa, val, bytes);
4344 	return 1;
4345 }
4346 
4347 struct read_write_emulator_ops {
4348 	int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4349 				  int bytes);
4350 	int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4351 				  void *val, int bytes);
4352 	int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4353 			       int bytes, void *val);
4354 	int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4355 				    void *val, int bytes);
4356 	bool write;
4357 };
4358 
4359 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4360 {
4361 	if (vcpu->mmio_read_completed) {
4362 		trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
4363 			       vcpu->mmio_fragments[0].gpa, *(u64 *)val);
4364 		vcpu->mmio_read_completed = 0;
4365 		return 1;
4366 	}
4367 
4368 	return 0;
4369 }
4370 
4371 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4372 			void *val, int bytes)
4373 {
4374 	return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
4375 }
4376 
4377 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4378 			 void *val, int bytes)
4379 {
4380 	return emulator_write_phys(vcpu, gpa, val, bytes);
4381 }
4382 
4383 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4384 {
4385 	trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4386 	return vcpu_mmio_write(vcpu, gpa, bytes, val);
4387 }
4388 
4389 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4390 			  void *val, int bytes)
4391 {
4392 	trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4393 	return X86EMUL_IO_NEEDED;
4394 }
4395 
4396 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4397 			   void *val, int bytes)
4398 {
4399 	struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4400 
4401 	memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
4402 	return X86EMUL_CONTINUE;
4403 }
4404 
4405 static const struct read_write_emulator_ops read_emultor = {
4406 	.read_write_prepare = read_prepare,
4407 	.read_write_emulate = read_emulate,
4408 	.read_write_mmio = vcpu_mmio_read,
4409 	.read_write_exit_mmio = read_exit_mmio,
4410 };
4411 
4412 static const struct read_write_emulator_ops write_emultor = {
4413 	.read_write_emulate = write_emulate,
4414 	.read_write_mmio = write_mmio,
4415 	.read_write_exit_mmio = write_exit_mmio,
4416 	.write = true,
4417 };
4418 
4419 static int emulator_read_write_onepage(unsigned long addr, void *val,
4420 				       unsigned int bytes,
4421 				       struct x86_exception *exception,
4422 				       struct kvm_vcpu *vcpu,
4423 				       const struct read_write_emulator_ops *ops)
4424 {
4425 	gpa_t gpa;
4426 	int handled, ret;
4427 	bool write = ops->write;
4428 	struct kvm_mmio_fragment *frag;
4429 
4430 	ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
4431 
4432 	if (ret < 0)
4433 		return X86EMUL_PROPAGATE_FAULT;
4434 
4435 	/* For APIC access vmexit */
4436 	if (ret)
4437 		goto mmio;
4438 
4439 	if (ops->read_write_emulate(vcpu, gpa, val, bytes))
4440 		return X86EMUL_CONTINUE;
4441 
4442 mmio:
4443 	/*
4444 	 * Is this MMIO handled locally?
4445 	 */
4446 	handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
4447 	if (handled == bytes)
4448 		return X86EMUL_CONTINUE;
4449 
4450 	gpa += handled;
4451 	bytes -= handled;
4452 	val += handled;
4453 
4454 	WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4455 	frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4456 	frag->gpa = gpa;
4457 	frag->data = val;
4458 	frag->len = bytes;
4459 	return X86EMUL_CONTINUE;
4460 }
4461 
4462 static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4463 			unsigned long addr,
4464 			void *val, unsigned int bytes,
4465 			struct x86_exception *exception,
4466 			const struct read_write_emulator_ops *ops)
4467 {
4468 	struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4469 	gpa_t gpa;
4470 	int rc;
4471 
4472 	if (ops->read_write_prepare &&
4473 		  ops->read_write_prepare(vcpu, val, bytes))
4474 		return X86EMUL_CONTINUE;
4475 
4476 	vcpu->mmio_nr_fragments = 0;
4477 
4478 	/* Crossing a page boundary? */
4479 	if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
4480 		int now;
4481 
4482 		now = -addr & ~PAGE_MASK;
4483 		rc = emulator_read_write_onepage(addr, val, now, exception,
4484 						 vcpu, ops);
4485 
4486 		if (rc != X86EMUL_CONTINUE)
4487 			return rc;
4488 		addr += now;
4489 		if (ctxt->mode != X86EMUL_MODE_PROT64)
4490 			addr = (u32)addr;
4491 		val += now;
4492 		bytes -= now;
4493 	}
4494 
4495 	rc = emulator_read_write_onepage(addr, val, bytes, exception,
4496 					 vcpu, ops);
4497 	if (rc != X86EMUL_CONTINUE)
4498 		return rc;
4499 
4500 	if (!vcpu->mmio_nr_fragments)
4501 		return rc;
4502 
4503 	gpa = vcpu->mmio_fragments[0].gpa;
4504 
4505 	vcpu->mmio_needed = 1;
4506 	vcpu->mmio_cur_fragment = 0;
4507 
4508 	vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
4509 	vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4510 	vcpu->run->exit_reason = KVM_EXIT_MMIO;
4511 	vcpu->run->mmio.phys_addr = gpa;
4512 
4513 	return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
4514 }
4515 
4516 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4517 				  unsigned long addr,
4518 				  void *val,
4519 				  unsigned int bytes,
4520 				  struct x86_exception *exception)
4521 {
4522 	return emulator_read_write(ctxt, addr, val, bytes,
4523 				   exception, &read_emultor);
4524 }
4525 
4526 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4527 			    unsigned long addr,
4528 			    const void *val,
4529 			    unsigned int bytes,
4530 			    struct x86_exception *exception)
4531 {
4532 	return emulator_read_write(ctxt, addr, (void *)val, bytes,
4533 				   exception, &write_emultor);
4534 }
4535 
4536 #define CMPXCHG_TYPE(t, ptr, old, new) \
4537 	(cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4538 
4539 #ifdef CONFIG_X86_64
4540 #  define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4541 #else
4542 #  define CMPXCHG64(ptr, old, new) \
4543 	(cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
4544 #endif
4545 
4546 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4547 				     unsigned long addr,
4548 				     const void *old,
4549 				     const void *new,
4550 				     unsigned int bytes,
4551 				     struct x86_exception *exception)
4552 {
4553 	struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4554 	gpa_t gpa;
4555 	struct page *page;
4556 	char *kaddr;
4557 	bool exchanged;
4558 
4559 	/* guests cmpxchg8b have to be emulated atomically */
4560 	if (bytes > 8 || (bytes & (bytes - 1)))
4561 		goto emul_write;
4562 
4563 	gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
4564 
4565 	if (gpa == UNMAPPED_GVA ||
4566 	    (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4567 		goto emul_write;
4568 
4569 	if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4570 		goto emul_write;
4571 
4572 	page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
4573 	if (is_error_page(page))
4574 		goto emul_write;
4575 
4576 	kaddr = kmap_atomic(page);
4577 	kaddr += offset_in_page(gpa);
4578 	switch (bytes) {
4579 	case 1:
4580 		exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4581 		break;
4582 	case 2:
4583 		exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4584 		break;
4585 	case 4:
4586 		exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4587 		break;
4588 	case 8:
4589 		exchanged = CMPXCHG64(kaddr, old, new);
4590 		break;
4591 	default:
4592 		BUG();
4593 	}
4594 	kunmap_atomic(kaddr);
4595 	kvm_release_page_dirty(page);
4596 
4597 	if (!exchanged)
4598 		return X86EMUL_CMPXCHG_FAILED;
4599 
4600 	kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
4601 	kvm_mmu_pte_write(vcpu, gpa, new, bytes);
4602 
4603 	return X86EMUL_CONTINUE;
4604 
4605 emul_write:
4606 	printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
4607 
4608 	return emulator_write_emulated(ctxt, addr, new, bytes, exception);
4609 }
4610 
4611 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4612 {
4613 	/* TODO: String I/O for in kernel device */
4614 	int r;
4615 
4616 	if (vcpu->arch.pio.in)
4617 		r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
4618 				    vcpu->arch.pio.size, pd);
4619 	else
4620 		r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
4621 				     vcpu->arch.pio.port, vcpu->arch.pio.size,
4622 				     pd);
4623 	return r;
4624 }
4625 
4626 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4627 			       unsigned short port, void *val,
4628 			       unsigned int count, bool in)
4629 {
4630 	vcpu->arch.pio.port = port;
4631 	vcpu->arch.pio.in = in;
4632 	vcpu->arch.pio.count  = count;
4633 	vcpu->arch.pio.size = size;
4634 
4635 	if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
4636 		vcpu->arch.pio.count = 0;
4637 		return 1;
4638 	}
4639 
4640 	vcpu->run->exit_reason = KVM_EXIT_IO;
4641 	vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
4642 	vcpu->run->io.size = size;
4643 	vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4644 	vcpu->run->io.count = count;
4645 	vcpu->run->io.port = port;
4646 
4647 	return 0;
4648 }
4649 
4650 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4651 				    int size, unsigned short port, void *val,
4652 				    unsigned int count)
4653 {
4654 	struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4655 	int ret;
4656 
4657 	if (vcpu->arch.pio.count)
4658 		goto data_avail;
4659 
4660 	ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4661 	if (ret) {
4662 data_avail:
4663 		memcpy(val, vcpu->arch.pio_data, size * count);
4664 		trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
4665 		vcpu->arch.pio.count = 0;
4666 		return 1;
4667 	}
4668 
4669 	return 0;
4670 }
4671 
4672 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4673 				     int size, unsigned short port,
4674 				     const void *val, unsigned int count)
4675 {
4676 	struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4677 
4678 	memcpy(vcpu->arch.pio_data, val, size * count);
4679 	trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
4680 	return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4681 }
4682 
4683 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4684 {
4685 	return kvm_x86_ops->get_segment_base(vcpu, seg);
4686 }
4687 
4688 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
4689 {
4690 	kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
4691 }
4692 
4693 int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
4694 {
4695 	if (!need_emulate_wbinvd(vcpu))
4696 		return X86EMUL_CONTINUE;
4697 
4698 	if (kvm_x86_ops->has_wbinvd_exit()) {
4699 		int cpu = get_cpu();
4700 
4701 		cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
4702 		smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4703 				wbinvd_ipi, NULL, 1);
4704 		put_cpu();
4705 		cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
4706 	} else
4707 		wbinvd();
4708 	return X86EMUL_CONTINUE;
4709 }
4710 
4711 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4712 {
4713 	kvm_x86_ops->skip_emulated_instruction(vcpu);
4714 	return kvm_emulate_wbinvd_noskip(vcpu);
4715 }
4716 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4717 
4718 
4719 
4720 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4721 {
4722 	kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
4723 }
4724 
4725 static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
4726 			   unsigned long *dest)
4727 {
4728 	return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
4729 }
4730 
4731 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
4732 			   unsigned long value)
4733 {
4734 
4735 	return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
4736 }
4737 
4738 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
4739 {
4740 	return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
4741 }
4742 
4743 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
4744 {
4745 	struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4746 	unsigned long value;
4747 
4748 	switch (cr) {
4749 	case 0:
4750 		value = kvm_read_cr0(vcpu);
4751 		break;
4752 	case 2:
4753 		value = vcpu->arch.cr2;
4754 		break;
4755 	case 3:
4756 		value = kvm_read_cr3(vcpu);
4757 		break;
4758 	case 4:
4759 		value = kvm_read_cr4(vcpu);
4760 		break;
4761 	case 8:
4762 		value = kvm_get_cr8(vcpu);
4763 		break;
4764 	default:
4765 		kvm_err("%s: unexpected cr %u\n", __func__, cr);
4766 		return 0;
4767 	}
4768 
4769 	return value;
4770 }
4771 
4772 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
4773 {
4774 	struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4775 	int res = 0;
4776 
4777 	switch (cr) {
4778 	case 0:
4779 		res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
4780 		break;
4781 	case 2:
4782 		vcpu->arch.cr2 = val;
4783 		break;
4784 	case 3:
4785 		res = kvm_set_cr3(vcpu, val);
4786 		break;
4787 	case 4:
4788 		res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
4789 		break;
4790 	case 8:
4791 		res = kvm_set_cr8(vcpu, val);
4792 		break;
4793 	default:
4794 		kvm_err("%s: unexpected cr %u\n", __func__, cr);
4795 		res = -1;
4796 	}
4797 
4798 	return res;
4799 }
4800 
4801 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
4802 {
4803 	return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
4804 }
4805 
4806 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4807 {
4808 	kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
4809 }
4810 
4811 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4812 {
4813 	kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
4814 }
4815 
4816 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4817 {
4818 	kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4819 }
4820 
4821 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4822 {
4823 	kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4824 }
4825 
4826 static unsigned long emulator_get_cached_segment_base(
4827 	struct x86_emulate_ctxt *ctxt, int seg)
4828 {
4829 	return get_segment_base(emul_to_vcpu(ctxt), seg);
4830 }
4831 
4832 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4833 				 struct desc_struct *desc, u32 *base3,
4834 				 int seg)
4835 {
4836 	struct kvm_segment var;
4837 
4838 	kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
4839 	*selector = var.selector;
4840 
4841 	if (var.unusable) {
4842 		memset(desc, 0, sizeof(*desc));
4843 		return false;
4844 	}
4845 
4846 	if (var.g)
4847 		var.limit >>= 12;
4848 	set_desc_limit(desc, var.limit);
4849 	set_desc_base(desc, (unsigned long)var.base);
4850 #ifdef CONFIG_X86_64
4851 	if (base3)
4852 		*base3 = var.base >> 32;
4853 #endif
4854 	desc->type = var.type;
4855 	desc->s = var.s;
4856 	desc->dpl = var.dpl;
4857 	desc->p = var.present;
4858 	desc->avl = var.avl;
4859 	desc->l = var.l;
4860 	desc->d = var.db;
4861 	desc->g = var.g;
4862 
4863 	return true;
4864 }
4865 
4866 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4867 				 struct desc_struct *desc, u32 base3,
4868 				 int seg)
4869 {
4870 	struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4871 	struct kvm_segment var;
4872 
4873 	var.selector = selector;
4874 	var.base = get_desc_base(desc);
4875 #ifdef CONFIG_X86_64
4876 	var.base |= ((u64)base3) << 32;
4877 #endif
4878 	var.limit = get_desc_limit(desc);
4879 	if (desc->g)
4880 		var.limit = (var.limit << 12) | 0xfff;
4881 	var.type = desc->type;
4882 	var.dpl = desc->dpl;
4883 	var.db = desc->d;
4884 	var.s = desc->s;
4885 	var.l = desc->l;
4886 	var.g = desc->g;
4887 	var.avl = desc->avl;
4888 	var.present = desc->p;
4889 	var.unusable = !var.present;
4890 	var.padding = 0;
4891 
4892 	kvm_set_segment(vcpu, &var, seg);
4893 	return;
4894 }
4895 
4896 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4897 			    u32 msr_index, u64 *pdata)
4898 {
4899 	struct msr_data msr;
4900 	int r;
4901 
4902 	msr.index = msr_index;
4903 	msr.host_initiated = false;
4904 	r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
4905 	if (r)
4906 		return r;
4907 
4908 	*pdata = msr.data;
4909 	return 0;
4910 }
4911 
4912 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4913 			    u32 msr_index, u64 data)
4914 {
4915 	struct msr_data msr;
4916 
4917 	msr.data = data;
4918 	msr.index = msr_index;
4919 	msr.host_initiated = false;
4920 	return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
4921 }
4922 
4923 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
4924 {
4925 	struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4926 
4927 	return vcpu->arch.smbase;
4928 }
4929 
4930 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
4931 {
4932 	struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4933 
4934 	vcpu->arch.smbase = smbase;
4935 }
4936 
4937 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
4938 			      u32 pmc)
4939 {
4940 	return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
4941 }
4942 
4943 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4944 			     u32 pmc, u64 *pdata)
4945 {
4946 	return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
4947 }
4948 
4949 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4950 {
4951 	emul_to_vcpu(ctxt)->arch.halt_request = 1;
4952 }
4953 
4954 static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4955 {
4956 	preempt_disable();
4957 	kvm_load_guest_fpu(emul_to_vcpu(ctxt));
4958 	/*
4959 	 * CR0.TS may reference the host fpu state, not the guest fpu state,
4960 	 * so it may be clear at this point.
4961 	 */
4962 	clts();
4963 }
4964 
4965 static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4966 {
4967 	preempt_enable();
4968 }
4969 
4970 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
4971 			      struct x86_instruction_info *info,
4972 			      enum x86_intercept_stage stage)
4973 {
4974 	return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
4975 }
4976 
4977 static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
4978 			       u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4979 {
4980 	kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
4981 }
4982 
4983 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4984 {
4985 	return kvm_register_read(emul_to_vcpu(ctxt), reg);
4986 }
4987 
4988 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4989 {
4990 	kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4991 }
4992 
4993 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
4994 {
4995 	kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
4996 }
4997 
4998 static const struct x86_emulate_ops emulate_ops = {
4999 	.read_gpr            = emulator_read_gpr,
5000 	.write_gpr           = emulator_write_gpr,
5001 	.read_std            = kvm_read_guest_virt_system,
5002 	.write_std           = kvm_write_guest_virt_system,
5003 	.read_phys           = kvm_read_guest_phys_system,
5004 	.fetch               = kvm_fetch_guest_virt,
5005 	.read_emulated       = emulator_read_emulated,
5006 	.write_emulated      = emulator_write_emulated,
5007 	.cmpxchg_emulated    = emulator_cmpxchg_emulated,
5008 	.invlpg              = emulator_invlpg,
5009 	.pio_in_emulated     = emulator_pio_in_emulated,
5010 	.pio_out_emulated    = emulator_pio_out_emulated,
5011 	.get_segment         = emulator_get_segment,
5012 	.set_segment         = emulator_set_segment,
5013 	.get_cached_segment_base = emulator_get_cached_segment_base,
5014 	.get_gdt             = emulator_get_gdt,
5015 	.get_idt	     = emulator_get_idt,
5016 	.set_gdt             = emulator_set_gdt,
5017 	.set_idt	     = emulator_set_idt,
5018 	.get_cr              = emulator_get_cr,
5019 	.set_cr              = emulator_set_cr,
5020 	.cpl                 = emulator_get_cpl,
5021 	.get_dr              = emulator_get_dr,
5022 	.set_dr              = emulator_set_dr,
5023 	.get_smbase          = emulator_get_smbase,
5024 	.set_smbase          = emulator_set_smbase,
5025 	.set_msr             = emulator_set_msr,
5026 	.get_msr             = emulator_get_msr,
5027 	.check_pmc	     = emulator_check_pmc,
5028 	.read_pmc            = emulator_read_pmc,
5029 	.halt                = emulator_halt,
5030 	.wbinvd              = emulator_wbinvd,
5031 	.fix_hypercall       = emulator_fix_hypercall,
5032 	.get_fpu             = emulator_get_fpu,
5033 	.put_fpu             = emulator_put_fpu,
5034 	.intercept           = emulator_intercept,
5035 	.get_cpuid           = emulator_get_cpuid,
5036 	.set_nmi_mask        = emulator_set_nmi_mask,
5037 };
5038 
5039 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5040 {
5041 	u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
5042 	/*
5043 	 * an sti; sti; sequence only disable interrupts for the first
5044 	 * instruction. So, if the last instruction, be it emulated or
5045 	 * not, left the system with the INT_STI flag enabled, it
5046 	 * means that the last instruction is an sti. We should not
5047 	 * leave the flag on in this case. The same goes for mov ss
5048 	 */
5049 	if (int_shadow & mask)
5050 		mask = 0;
5051 	if (unlikely(int_shadow || mask)) {
5052 		kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
5053 		if (!mask)
5054 			kvm_make_request(KVM_REQ_EVENT, vcpu);
5055 	}
5056 }
5057 
5058 static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
5059 {
5060 	struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5061 	if (ctxt->exception.vector == PF_VECTOR)
5062 		return kvm_propagate_fault(vcpu, &ctxt->exception);
5063 
5064 	if (ctxt->exception.error_code_valid)
5065 		kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5066 				      ctxt->exception.error_code);
5067 	else
5068 		kvm_queue_exception(vcpu, ctxt->exception.vector);
5069 	return false;
5070 }
5071 
5072 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5073 {
5074 	struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5075 	int cs_db, cs_l;
5076 
5077 	kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5078 
5079 	ctxt->eflags = kvm_get_rflags(vcpu);
5080 	ctxt->eip = kvm_rip_read(vcpu);
5081 	ctxt->mode = (!is_protmode(vcpu))		? X86EMUL_MODE_REAL :
5082 		     (ctxt->eflags & X86_EFLAGS_VM)	? X86EMUL_MODE_VM86 :
5083 		     (cs_l && is_long_mode(vcpu))	? X86EMUL_MODE_PROT64 :
5084 		     cs_db				? X86EMUL_MODE_PROT32 :
5085 							  X86EMUL_MODE_PROT16;
5086 	BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
5087 	BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5088 	BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
5089 	ctxt->emul_flags = vcpu->arch.hflags;
5090 
5091 	init_decode_cache(ctxt);
5092 	vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
5093 }
5094 
5095 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
5096 {
5097 	struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5098 	int ret;
5099 
5100 	init_emulate_ctxt(vcpu);
5101 
5102 	ctxt->op_bytes = 2;
5103 	ctxt->ad_bytes = 2;
5104 	ctxt->_eip = ctxt->eip + inc_eip;
5105 	ret = emulate_int_real(ctxt, irq);
5106 
5107 	if (ret != X86EMUL_CONTINUE)
5108 		return EMULATE_FAIL;
5109 
5110 	ctxt->eip = ctxt->_eip;
5111 	kvm_rip_write(vcpu, ctxt->eip);
5112 	kvm_set_rflags(vcpu, ctxt->eflags);
5113 
5114 	if (irq == NMI_VECTOR)
5115 		vcpu->arch.nmi_pending = 0;
5116 	else
5117 		vcpu->arch.interrupt.pending = false;
5118 
5119 	return EMULATE_DONE;
5120 }
5121 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5122 
5123 static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5124 {
5125 	int r = EMULATE_DONE;
5126 
5127 	++vcpu->stat.insn_emulation_fail;
5128 	trace_kvm_emulate_insn_failed(vcpu);
5129 	if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
5130 		vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5131 		vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5132 		vcpu->run->internal.ndata = 0;
5133 		r = EMULATE_FAIL;
5134 	}
5135 	kvm_queue_exception(vcpu, UD_VECTOR);
5136 
5137 	return r;
5138 }
5139 
5140 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
5141 				  bool write_fault_to_shadow_pgtable,
5142 				  int emulation_type)
5143 {
5144 	gpa_t gpa = cr2;
5145 	kvm_pfn_t pfn;
5146 
5147 	if (emulation_type & EMULTYPE_NO_REEXECUTE)
5148 		return false;
5149 
5150 	if (!vcpu->arch.mmu.direct_map) {
5151 		/*
5152 		 * Write permission should be allowed since only
5153 		 * write access need to be emulated.
5154 		 */
5155 		gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5156 
5157 		/*
5158 		 * If the mapping is invalid in guest, let cpu retry
5159 		 * it to generate fault.
5160 		 */
5161 		if (gpa == UNMAPPED_GVA)
5162 			return true;
5163 	}
5164 
5165 	/*
5166 	 * Do not retry the unhandleable instruction if it faults on the
5167 	 * readonly host memory, otherwise it will goto a infinite loop:
5168 	 * retry instruction -> write #PF -> emulation fail -> retry
5169 	 * instruction -> ...
5170 	 */
5171 	pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
5172 
5173 	/*
5174 	 * If the instruction failed on the error pfn, it can not be fixed,
5175 	 * report the error to userspace.
5176 	 */
5177 	if (is_error_noslot_pfn(pfn))
5178 		return false;
5179 
5180 	kvm_release_pfn_clean(pfn);
5181 
5182 	/* The instructions are well-emulated on direct mmu. */
5183 	if (vcpu->arch.mmu.direct_map) {
5184 		unsigned int indirect_shadow_pages;
5185 
5186 		spin_lock(&vcpu->kvm->mmu_lock);
5187 		indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5188 		spin_unlock(&vcpu->kvm->mmu_lock);
5189 
5190 		if (indirect_shadow_pages)
5191 			kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5192 
5193 		return true;
5194 	}
5195 
5196 	/*
5197 	 * if emulation was due to access to shadowed page table
5198 	 * and it failed try to unshadow page and re-enter the
5199 	 * guest to let CPU execute the instruction.
5200 	 */
5201 	kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5202 
5203 	/*
5204 	 * If the access faults on its page table, it can not
5205 	 * be fixed by unprotecting shadow page and it should
5206 	 * be reported to userspace.
5207 	 */
5208 	return !write_fault_to_shadow_pgtable;
5209 }
5210 
5211 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5212 			      unsigned long cr2,  int emulation_type)
5213 {
5214 	struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5215 	unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5216 
5217 	last_retry_eip = vcpu->arch.last_retry_eip;
5218 	last_retry_addr = vcpu->arch.last_retry_addr;
5219 
5220 	/*
5221 	 * If the emulation is caused by #PF and it is non-page_table
5222 	 * writing instruction, it means the VM-EXIT is caused by shadow
5223 	 * page protected, we can zap the shadow page and retry this
5224 	 * instruction directly.
5225 	 *
5226 	 * Note: if the guest uses a non-page-table modifying instruction
5227 	 * on the PDE that points to the instruction, then we will unmap
5228 	 * the instruction and go to an infinite loop. So, we cache the
5229 	 * last retried eip and the last fault address, if we meet the eip
5230 	 * and the address again, we can break out of the potential infinite
5231 	 * loop.
5232 	 */
5233 	vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5234 
5235 	if (!(emulation_type & EMULTYPE_RETRY))
5236 		return false;
5237 
5238 	if (x86_page_table_writing_insn(ctxt))
5239 		return false;
5240 
5241 	if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5242 		return false;
5243 
5244 	vcpu->arch.last_retry_eip = ctxt->eip;
5245 	vcpu->arch.last_retry_addr = cr2;
5246 
5247 	if (!vcpu->arch.mmu.direct_map)
5248 		gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5249 
5250 	kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5251 
5252 	return true;
5253 }
5254 
5255 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5256 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5257 
5258 static void kvm_smm_changed(struct kvm_vcpu *vcpu)
5259 {
5260 	if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
5261 		/* This is a good place to trace that we are exiting SMM.  */
5262 		trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5263 
5264 		if (unlikely(vcpu->arch.smi_pending)) {
5265 			kvm_make_request(KVM_REQ_SMI, vcpu);
5266 			vcpu->arch.smi_pending = 0;
5267 		} else {
5268 			/* Process a latched INIT, if any.  */
5269 			kvm_make_request(KVM_REQ_EVENT, vcpu);
5270 		}
5271 	}
5272 
5273 	kvm_mmu_reset_context(vcpu);
5274 }
5275 
5276 static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5277 {
5278 	unsigned changed = vcpu->arch.hflags ^ emul_flags;
5279 
5280 	vcpu->arch.hflags = emul_flags;
5281 
5282 	if (changed & HF_SMM_MASK)
5283 		kvm_smm_changed(vcpu);
5284 }
5285 
5286 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5287 				unsigned long *db)
5288 {
5289 	u32 dr6 = 0;
5290 	int i;
5291 	u32 enable, rwlen;
5292 
5293 	enable = dr7;
5294 	rwlen = dr7 >> 16;
5295 	for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5296 		if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5297 			dr6 |= (1 << i);
5298 	return dr6;
5299 }
5300 
5301 static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r)
5302 {
5303 	struct kvm_run *kvm_run = vcpu->run;
5304 
5305 	/*
5306 	 * rflags is the old, "raw" value of the flags.  The new value has
5307 	 * not been saved yet.
5308 	 *
5309 	 * This is correct even for TF set by the guest, because "the
5310 	 * processor will not generate this exception after the instruction
5311 	 * that sets the TF flag".
5312 	 */
5313 	if (unlikely(rflags & X86_EFLAGS_TF)) {
5314 		if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5315 			kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 |
5316 						  DR6_RTM;
5317 			kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5318 			kvm_run->debug.arch.exception = DB_VECTOR;
5319 			kvm_run->exit_reason = KVM_EXIT_DEBUG;
5320 			*r = EMULATE_USER_EXIT;
5321 		} else {
5322 			vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5323 			/*
5324 			 * "Certain debug exceptions may clear bit 0-3.  The
5325 			 * remaining contents of the DR6 register are never
5326 			 * cleared by the processor".
5327 			 */
5328 			vcpu->arch.dr6 &= ~15;
5329 			vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
5330 			kvm_queue_exception(vcpu, DB_VECTOR);
5331 		}
5332 	}
5333 }
5334 
5335 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5336 {
5337 	if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5338 	    (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
5339 		struct kvm_run *kvm_run = vcpu->run;
5340 		unsigned long eip = kvm_get_linear_rip(vcpu);
5341 		u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5342 					   vcpu->arch.guest_debug_dr7,
5343 					   vcpu->arch.eff_db);
5344 
5345 		if (dr6 != 0) {
5346 			kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
5347 			kvm_run->debug.arch.pc = eip;
5348 			kvm_run->debug.arch.exception = DB_VECTOR;
5349 			kvm_run->exit_reason = KVM_EXIT_DEBUG;
5350 			*r = EMULATE_USER_EXIT;
5351 			return true;
5352 		}
5353 	}
5354 
5355 	if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5356 	    !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
5357 		unsigned long eip = kvm_get_linear_rip(vcpu);
5358 		u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5359 					   vcpu->arch.dr7,
5360 					   vcpu->arch.db);
5361 
5362 		if (dr6 != 0) {
5363 			vcpu->arch.dr6 &= ~15;
5364 			vcpu->arch.dr6 |= dr6 | DR6_RTM;
5365 			kvm_queue_exception(vcpu, DB_VECTOR);
5366 			*r = EMULATE_DONE;
5367 			return true;
5368 		}
5369 	}
5370 
5371 	return false;
5372 }
5373 
5374 int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5375 			    unsigned long cr2,
5376 			    int emulation_type,
5377 			    void *insn,
5378 			    int insn_len)
5379 {
5380 	int r;
5381 	struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5382 	bool writeback = true;
5383 	bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
5384 
5385 	/*
5386 	 * Clear write_fault_to_shadow_pgtable here to ensure it is
5387 	 * never reused.
5388 	 */
5389 	vcpu->arch.write_fault_to_shadow_pgtable = false;
5390 	kvm_clear_exception_queue(vcpu);
5391 
5392 	if (!(emulation_type & EMULTYPE_NO_DECODE)) {
5393 		init_emulate_ctxt(vcpu);
5394 
5395 		/*
5396 		 * We will reenter on the same instruction since
5397 		 * we do not set complete_userspace_io.  This does not
5398 		 * handle watchpoints yet, those would be handled in
5399 		 * the emulate_ops.
5400 		 */
5401 		if (kvm_vcpu_check_breakpoint(vcpu, &r))
5402 			return r;
5403 
5404 		ctxt->interruptibility = 0;
5405 		ctxt->have_exception = false;
5406 		ctxt->exception.vector = -1;
5407 		ctxt->perm_ok = false;
5408 
5409 		ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
5410 
5411 		r = x86_decode_insn(ctxt, insn, insn_len);
5412 
5413 		trace_kvm_emulate_insn_start(vcpu);
5414 		++vcpu->stat.insn_emulation;
5415 		if (r != EMULATION_OK)  {
5416 			if (emulation_type & EMULTYPE_TRAP_UD)
5417 				return EMULATE_FAIL;
5418 			if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5419 						emulation_type))
5420 				return EMULATE_DONE;
5421 			if (emulation_type & EMULTYPE_SKIP)
5422 				return EMULATE_FAIL;
5423 			return handle_emulation_failure(vcpu);
5424 		}
5425 	}
5426 
5427 	if (emulation_type & EMULTYPE_SKIP) {
5428 		kvm_rip_write(vcpu, ctxt->_eip);
5429 		if (ctxt->eflags & X86_EFLAGS_RF)
5430 			kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
5431 		return EMULATE_DONE;
5432 	}
5433 
5434 	if (retry_instruction(ctxt, cr2, emulation_type))
5435 		return EMULATE_DONE;
5436 
5437 	/* this is needed for vmware backdoor interface to work since it
5438 	   changes registers values  during IO operation */
5439 	if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5440 		vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
5441 		emulator_invalidate_register_cache(ctxt);
5442 	}
5443 
5444 restart:
5445 	r = x86_emulate_insn(ctxt);
5446 
5447 	if (r == EMULATION_INTERCEPTED)
5448 		return EMULATE_DONE;
5449 
5450 	if (r == EMULATION_FAILED) {
5451 		if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5452 					emulation_type))
5453 			return EMULATE_DONE;
5454 
5455 		return handle_emulation_failure(vcpu);
5456 	}
5457 
5458 	if (ctxt->have_exception) {
5459 		r = EMULATE_DONE;
5460 		if (inject_emulated_exception(vcpu))
5461 			return r;
5462 	} else if (vcpu->arch.pio.count) {
5463 		if (!vcpu->arch.pio.in) {
5464 			/* FIXME: return into emulator if single-stepping.  */
5465 			vcpu->arch.pio.count = 0;
5466 		} else {
5467 			writeback = false;
5468 			vcpu->arch.complete_userspace_io = complete_emulated_pio;
5469 		}
5470 		r = EMULATE_USER_EXIT;
5471 	} else if (vcpu->mmio_needed) {
5472 		if (!vcpu->mmio_is_write)
5473 			writeback = false;
5474 		r = EMULATE_USER_EXIT;
5475 		vcpu->arch.complete_userspace_io = complete_emulated_mmio;
5476 	} else if (r == EMULATION_RESTART)
5477 		goto restart;
5478 	else
5479 		r = EMULATE_DONE;
5480 
5481 	if (writeback) {
5482 		unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5483 		toggle_interruptibility(vcpu, ctxt->interruptibility);
5484 		vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5485 		if (vcpu->arch.hflags != ctxt->emul_flags)
5486 			kvm_set_hflags(vcpu, ctxt->emul_flags);
5487 		kvm_rip_write(vcpu, ctxt->eip);
5488 		if (r == EMULATE_DONE)
5489 			kvm_vcpu_check_singlestep(vcpu, rflags, &r);
5490 		if (!ctxt->have_exception ||
5491 		    exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5492 			__kvm_set_rflags(vcpu, ctxt->eflags);
5493 
5494 		/*
5495 		 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5496 		 * do nothing, and it will be requested again as soon as
5497 		 * the shadow expires.  But we still need to check here,
5498 		 * because POPF has no interrupt shadow.
5499 		 */
5500 		if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5501 			kvm_make_request(KVM_REQ_EVENT, vcpu);
5502 	} else
5503 		vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
5504 
5505 	return r;
5506 }
5507 EXPORT_SYMBOL_GPL(x86_emulate_instruction);
5508 
5509 int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
5510 {
5511 	unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
5512 	int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5513 					    size, port, &val, 1);
5514 	/* do not return to emulator after return from userspace */
5515 	vcpu->arch.pio.count = 0;
5516 	return ret;
5517 }
5518 EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
5519 
5520 static void tsc_bad(void *info)
5521 {
5522 	__this_cpu_write(cpu_tsc_khz, 0);
5523 }
5524 
5525 static void tsc_khz_changed(void *data)
5526 {
5527 	struct cpufreq_freqs *freq = data;
5528 	unsigned long khz = 0;
5529 
5530 	if (data)
5531 		khz = freq->new;
5532 	else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5533 		khz = cpufreq_quick_get(raw_smp_processor_id());
5534 	if (!khz)
5535 		khz = tsc_khz;
5536 	__this_cpu_write(cpu_tsc_khz, khz);
5537 }
5538 
5539 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5540 				     void *data)
5541 {
5542 	struct cpufreq_freqs *freq = data;
5543 	struct kvm *kvm;
5544 	struct kvm_vcpu *vcpu;
5545 	int i, send_ipi = 0;
5546 
5547 	/*
5548 	 * We allow guests to temporarily run on slowing clocks,
5549 	 * provided we notify them after, or to run on accelerating
5550 	 * clocks, provided we notify them before.  Thus time never
5551 	 * goes backwards.
5552 	 *
5553 	 * However, we have a problem.  We can't atomically update
5554 	 * the frequency of a given CPU from this function; it is
5555 	 * merely a notifier, which can be called from any CPU.
5556 	 * Changing the TSC frequency at arbitrary points in time
5557 	 * requires a recomputation of local variables related to
5558 	 * the TSC for each VCPU.  We must flag these local variables
5559 	 * to be updated and be sure the update takes place with the
5560 	 * new frequency before any guests proceed.
5561 	 *
5562 	 * Unfortunately, the combination of hotplug CPU and frequency
5563 	 * change creates an intractable locking scenario; the order
5564 	 * of when these callouts happen is undefined with respect to
5565 	 * CPU hotplug, and they can race with each other.  As such,
5566 	 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5567 	 * undefined; you can actually have a CPU frequency change take
5568 	 * place in between the computation of X and the setting of the
5569 	 * variable.  To protect against this problem, all updates of
5570 	 * the per_cpu tsc_khz variable are done in an interrupt
5571 	 * protected IPI, and all callers wishing to update the value
5572 	 * must wait for a synchronous IPI to complete (which is trivial
5573 	 * if the caller is on the CPU already).  This establishes the
5574 	 * necessary total order on variable updates.
5575 	 *
5576 	 * Note that because a guest time update may take place
5577 	 * anytime after the setting of the VCPU's request bit, the
5578 	 * correct TSC value must be set before the request.  However,
5579 	 * to ensure the update actually makes it to any guest which
5580 	 * starts running in hardware virtualization between the set
5581 	 * and the acquisition of the spinlock, we must also ping the
5582 	 * CPU after setting the request bit.
5583 	 *
5584 	 */
5585 
5586 	if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5587 		return 0;
5588 	if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5589 		return 0;
5590 
5591 	smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5592 
5593 	spin_lock(&kvm_lock);
5594 	list_for_each_entry(kvm, &vm_list, vm_list) {
5595 		kvm_for_each_vcpu(i, vcpu, kvm) {
5596 			if (vcpu->cpu != freq->cpu)
5597 				continue;
5598 			kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
5599 			if (vcpu->cpu != smp_processor_id())
5600 				send_ipi = 1;
5601 		}
5602 	}
5603 	spin_unlock(&kvm_lock);
5604 
5605 	if (freq->old < freq->new && send_ipi) {
5606 		/*
5607 		 * We upscale the frequency.  Must make the guest
5608 		 * doesn't see old kvmclock values while running with
5609 		 * the new frequency, otherwise we risk the guest sees
5610 		 * time go backwards.
5611 		 *
5612 		 * In case we update the frequency for another cpu
5613 		 * (which might be in guest context) send an interrupt
5614 		 * to kick the cpu out of guest context.  Next time
5615 		 * guest context is entered kvmclock will be updated,
5616 		 * so the guest will not see stale values.
5617 		 */
5618 		smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5619 	}
5620 	return 0;
5621 }
5622 
5623 static struct notifier_block kvmclock_cpufreq_notifier_block = {
5624 	.notifier_call  = kvmclock_cpufreq_notifier
5625 };
5626 
5627 static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5628 					unsigned long action, void *hcpu)
5629 {
5630 	unsigned int cpu = (unsigned long)hcpu;
5631 
5632 	switch (action) {
5633 		case CPU_ONLINE:
5634 		case CPU_DOWN_FAILED:
5635 			smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5636 			break;
5637 		case CPU_DOWN_PREPARE:
5638 			smp_call_function_single(cpu, tsc_bad, NULL, 1);
5639 			break;
5640 	}
5641 	return NOTIFY_OK;
5642 }
5643 
5644 static struct notifier_block kvmclock_cpu_notifier_block = {
5645 	.notifier_call  = kvmclock_cpu_notifier,
5646 	.priority = -INT_MAX
5647 };
5648 
5649 static void kvm_timer_init(void)
5650 {
5651 	int cpu;
5652 
5653 	max_tsc_khz = tsc_khz;
5654 
5655 	cpu_notifier_register_begin();
5656 	if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
5657 #ifdef CONFIG_CPU_FREQ
5658 		struct cpufreq_policy policy;
5659 		memset(&policy, 0, sizeof(policy));
5660 		cpu = get_cpu();
5661 		cpufreq_get_policy(&policy, cpu);
5662 		if (policy.cpuinfo.max_freq)
5663 			max_tsc_khz = policy.cpuinfo.max_freq;
5664 		put_cpu();
5665 #endif
5666 		cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5667 					  CPUFREQ_TRANSITION_NOTIFIER);
5668 	}
5669 	pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
5670 	for_each_online_cpu(cpu)
5671 		smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5672 
5673 	__register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5674 	cpu_notifier_register_done();
5675 
5676 }
5677 
5678 static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5679 
5680 int kvm_is_in_guest(void)
5681 {
5682 	return __this_cpu_read(current_vcpu) != NULL;
5683 }
5684 
5685 static int kvm_is_user_mode(void)
5686 {
5687 	int user_mode = 3;
5688 
5689 	if (__this_cpu_read(current_vcpu))
5690 		user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
5691 
5692 	return user_mode != 0;
5693 }
5694 
5695 static unsigned long kvm_get_guest_ip(void)
5696 {
5697 	unsigned long ip = 0;
5698 
5699 	if (__this_cpu_read(current_vcpu))
5700 		ip = kvm_rip_read(__this_cpu_read(current_vcpu));
5701 
5702 	return ip;
5703 }
5704 
5705 static struct perf_guest_info_callbacks kvm_guest_cbs = {
5706 	.is_in_guest		= kvm_is_in_guest,
5707 	.is_user_mode		= kvm_is_user_mode,
5708 	.get_guest_ip		= kvm_get_guest_ip,
5709 };
5710 
5711 void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5712 {
5713 	__this_cpu_write(current_vcpu, vcpu);
5714 }
5715 EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5716 
5717 void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5718 {
5719 	__this_cpu_write(current_vcpu, NULL);
5720 }
5721 EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5722 
5723 static void kvm_set_mmio_spte_mask(void)
5724 {
5725 	u64 mask;
5726 	int maxphyaddr = boot_cpu_data.x86_phys_bits;
5727 
5728 	/*
5729 	 * Set the reserved bits and the present bit of an paging-structure
5730 	 * entry to generate page fault with PFER.RSV = 1.
5731 	 */
5732 	 /* Mask the reserved physical address bits. */
5733 	mask = rsvd_bits(maxphyaddr, 51);
5734 
5735 	/* Bit 62 is always reserved for 32bit host. */
5736 	mask |= 0x3ull << 62;
5737 
5738 	/* Set the present bit. */
5739 	mask |= 1ull;
5740 
5741 #ifdef CONFIG_X86_64
5742 	/*
5743 	 * If reserved bit is not supported, clear the present bit to disable
5744 	 * mmio page fault.
5745 	 */
5746 	if (maxphyaddr == 52)
5747 		mask &= ~1ull;
5748 #endif
5749 
5750 	kvm_mmu_set_mmio_spte_mask(mask);
5751 }
5752 
5753 #ifdef CONFIG_X86_64
5754 static void pvclock_gtod_update_fn(struct work_struct *work)
5755 {
5756 	struct kvm *kvm;
5757 
5758 	struct kvm_vcpu *vcpu;
5759 	int i;
5760 
5761 	spin_lock(&kvm_lock);
5762 	list_for_each_entry(kvm, &vm_list, vm_list)
5763 		kvm_for_each_vcpu(i, vcpu, kvm)
5764 			kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
5765 	atomic_set(&kvm_guest_has_master_clock, 0);
5766 	spin_unlock(&kvm_lock);
5767 }
5768 
5769 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5770 
5771 /*
5772  * Notification about pvclock gtod data update.
5773  */
5774 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5775 			       void *priv)
5776 {
5777 	struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5778 	struct timekeeper *tk = priv;
5779 
5780 	update_pvclock_gtod(tk);
5781 
5782 	/* disable master clock if host does not trust, or does not
5783 	 * use, TSC clocksource
5784 	 */
5785 	if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5786 	    atomic_read(&kvm_guest_has_master_clock) != 0)
5787 		queue_work(system_long_wq, &pvclock_gtod_work);
5788 
5789 	return 0;
5790 }
5791 
5792 static struct notifier_block pvclock_gtod_notifier = {
5793 	.notifier_call = pvclock_gtod_notify,
5794 };
5795 #endif
5796 
5797 int kvm_arch_init(void *opaque)
5798 {
5799 	int r;
5800 	struct kvm_x86_ops *ops = opaque;
5801 
5802 	if (kvm_x86_ops) {
5803 		printk(KERN_ERR "kvm: already loaded the other module\n");
5804 		r = -EEXIST;
5805 		goto out;
5806 	}
5807 
5808 	if (!ops->cpu_has_kvm_support()) {
5809 		printk(KERN_ERR "kvm: no hardware support\n");
5810 		r = -EOPNOTSUPP;
5811 		goto out;
5812 	}
5813 	if (ops->disabled_by_bios()) {
5814 		printk(KERN_ERR "kvm: disabled by bios\n");
5815 		r = -EOPNOTSUPP;
5816 		goto out;
5817 	}
5818 
5819 	r = -ENOMEM;
5820 	shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5821 	if (!shared_msrs) {
5822 		printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5823 		goto out;
5824 	}
5825 
5826 	r = kvm_mmu_module_init();
5827 	if (r)
5828 		goto out_free_percpu;
5829 
5830 	kvm_set_mmio_spte_mask();
5831 
5832 	kvm_x86_ops = ops;
5833 
5834 	kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
5835 			PT_DIRTY_MASK, PT64_NX_MASK, 0);
5836 
5837 	kvm_timer_init();
5838 
5839 	perf_register_guest_info_callbacks(&kvm_guest_cbs);
5840 
5841 	if (cpu_has_xsave)
5842 		host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5843 
5844 	kvm_lapic_init();
5845 #ifdef CONFIG_X86_64
5846 	pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5847 #endif
5848 
5849 	return 0;
5850 
5851 out_free_percpu:
5852 	free_percpu(shared_msrs);
5853 out:
5854 	return r;
5855 }
5856 
5857 void kvm_arch_exit(void)
5858 {
5859 	perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5860 
5861 	if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5862 		cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5863 					    CPUFREQ_TRANSITION_NOTIFIER);
5864 	unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5865 #ifdef CONFIG_X86_64
5866 	pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5867 #endif
5868 	kvm_x86_ops = NULL;
5869 	kvm_mmu_module_exit();
5870 	free_percpu(shared_msrs);
5871 }
5872 
5873 int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
5874 {
5875 	++vcpu->stat.halt_exits;
5876 	if (lapic_in_kernel(vcpu)) {
5877 		vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
5878 		return 1;
5879 	} else {
5880 		vcpu->run->exit_reason = KVM_EXIT_HLT;
5881 		return 0;
5882 	}
5883 }
5884 EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
5885 
5886 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5887 {
5888 	kvm_x86_ops->skip_emulated_instruction(vcpu);
5889 	return kvm_vcpu_halt(vcpu);
5890 }
5891 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5892 
5893 /*
5894  * kvm_pv_kick_cpu_op:  Kick a vcpu.
5895  *
5896  * @apicid - apicid of vcpu to be kicked.
5897  */
5898 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5899 {
5900 	struct kvm_lapic_irq lapic_irq;
5901 
5902 	lapic_irq.shorthand = 0;
5903 	lapic_irq.dest_mode = 0;
5904 	lapic_irq.dest_id = apicid;
5905 	lapic_irq.msi_redir_hint = false;
5906 
5907 	lapic_irq.delivery_mode = APIC_DM_REMRD;
5908 	kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
5909 }
5910 
5911 void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
5912 {
5913 	vcpu->arch.apicv_active = false;
5914 	kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
5915 }
5916 
5917 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5918 {
5919 	unsigned long nr, a0, a1, a2, a3, ret;
5920 	int op_64_bit, r = 1;
5921 
5922 	kvm_x86_ops->skip_emulated_instruction(vcpu);
5923 
5924 	if (kvm_hv_hypercall_enabled(vcpu->kvm))
5925 		return kvm_hv_hypercall(vcpu);
5926 
5927 	nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5928 	a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5929 	a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5930 	a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5931 	a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
5932 
5933 	trace_kvm_hypercall(nr, a0, a1, a2, a3);
5934 
5935 	op_64_bit = is_64_bit_mode(vcpu);
5936 	if (!op_64_bit) {
5937 		nr &= 0xFFFFFFFF;
5938 		a0 &= 0xFFFFFFFF;
5939 		a1 &= 0xFFFFFFFF;
5940 		a2 &= 0xFFFFFFFF;
5941 		a3 &= 0xFFFFFFFF;
5942 	}
5943 
5944 	if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5945 		ret = -KVM_EPERM;
5946 		goto out;
5947 	}
5948 
5949 	switch (nr) {
5950 	case KVM_HC_VAPIC_POLL_IRQ:
5951 		ret = 0;
5952 		break;
5953 	case KVM_HC_KICK_CPU:
5954 		kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
5955 		ret = 0;
5956 		break;
5957 	default:
5958 		ret = -KVM_ENOSYS;
5959 		break;
5960 	}
5961 out:
5962 	if (!op_64_bit)
5963 		ret = (u32)ret;
5964 	kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5965 	++vcpu->stat.hypercalls;
5966 	return r;
5967 }
5968 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5969 
5970 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
5971 {
5972 	struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5973 	char instruction[3];
5974 	unsigned long rip = kvm_rip_read(vcpu);
5975 
5976 	kvm_x86_ops->patch_hypercall(vcpu, instruction);
5977 
5978 	return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
5979 }
5980 
5981 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
5982 {
5983 	return vcpu->run->request_interrupt_window &&
5984 		likely(!pic_in_kernel(vcpu->kvm));
5985 }
5986 
5987 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
5988 {
5989 	struct kvm_run *kvm_run = vcpu->run;
5990 
5991 	kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
5992 	kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
5993 	kvm_run->cr8 = kvm_get_cr8(vcpu);
5994 	kvm_run->apic_base = kvm_get_apic_base(vcpu);
5995 	kvm_run->ready_for_interrupt_injection =
5996 		pic_in_kernel(vcpu->kvm) ||
5997 		kvm_vcpu_ready_for_interrupt_injection(vcpu);
5998 }
5999 
6000 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6001 {
6002 	int max_irr, tpr;
6003 
6004 	if (!kvm_x86_ops->update_cr8_intercept)
6005 		return;
6006 
6007 	if (!vcpu->arch.apic)
6008 		return;
6009 
6010 	if (vcpu->arch.apicv_active)
6011 		return;
6012 
6013 	if (!vcpu->arch.apic->vapic_addr)
6014 		max_irr = kvm_lapic_find_highest_irr(vcpu);
6015 	else
6016 		max_irr = -1;
6017 
6018 	if (max_irr != -1)
6019 		max_irr >>= 4;
6020 
6021 	tpr = kvm_lapic_get_cr8(vcpu);
6022 
6023 	kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6024 }
6025 
6026 static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
6027 {
6028 	int r;
6029 
6030 	/* try to reinject previous events if any */
6031 	if (vcpu->arch.exception.pending) {
6032 		trace_kvm_inj_exception(vcpu->arch.exception.nr,
6033 					vcpu->arch.exception.has_error_code,
6034 					vcpu->arch.exception.error_code);
6035 
6036 		if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6037 			__kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6038 					     X86_EFLAGS_RF);
6039 
6040 		if (vcpu->arch.exception.nr == DB_VECTOR &&
6041 		    (vcpu->arch.dr7 & DR7_GD)) {
6042 			vcpu->arch.dr7 &= ~DR7_GD;
6043 			kvm_update_dr7(vcpu);
6044 		}
6045 
6046 		kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
6047 					  vcpu->arch.exception.has_error_code,
6048 					  vcpu->arch.exception.error_code,
6049 					  vcpu->arch.exception.reinject);
6050 		return 0;
6051 	}
6052 
6053 	if (vcpu->arch.nmi_injected) {
6054 		kvm_x86_ops->set_nmi(vcpu);
6055 		return 0;
6056 	}
6057 
6058 	if (vcpu->arch.interrupt.pending) {
6059 		kvm_x86_ops->set_irq(vcpu);
6060 		return 0;
6061 	}
6062 
6063 	if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6064 		r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6065 		if (r != 0)
6066 			return r;
6067 	}
6068 
6069 	/* try to inject new event if pending */
6070 	if (vcpu->arch.nmi_pending) {
6071 		if (kvm_x86_ops->nmi_allowed(vcpu)) {
6072 			--vcpu->arch.nmi_pending;
6073 			vcpu->arch.nmi_injected = true;
6074 			kvm_x86_ops->set_nmi(vcpu);
6075 		}
6076 	} else if (kvm_cpu_has_injectable_intr(vcpu)) {
6077 		/*
6078 		 * Because interrupts can be injected asynchronously, we are
6079 		 * calling check_nested_events again here to avoid a race condition.
6080 		 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6081 		 * proposal and current concerns.  Perhaps we should be setting
6082 		 * KVM_REQ_EVENT only on certain events and not unconditionally?
6083 		 */
6084 		if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6085 			r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6086 			if (r != 0)
6087 				return r;
6088 		}
6089 		if (kvm_x86_ops->interrupt_allowed(vcpu)) {
6090 			kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6091 					    false);
6092 			kvm_x86_ops->set_irq(vcpu);
6093 		}
6094 	}
6095 	return 0;
6096 }
6097 
6098 static void process_nmi(struct kvm_vcpu *vcpu)
6099 {
6100 	unsigned limit = 2;
6101 
6102 	/*
6103 	 * x86 is limited to one NMI running, and one NMI pending after it.
6104 	 * If an NMI is already in progress, limit further NMIs to just one.
6105 	 * Otherwise, allow two (and we'll inject the first one immediately).
6106 	 */
6107 	if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6108 		limit = 1;
6109 
6110 	vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6111 	vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6112 	kvm_make_request(KVM_REQ_EVENT, vcpu);
6113 }
6114 
6115 #define put_smstate(type, buf, offset, val)			  \
6116 	*(type *)((buf) + (offset) - 0x7e00) = val
6117 
6118 static u32 process_smi_get_segment_flags(struct kvm_segment *seg)
6119 {
6120 	u32 flags = 0;
6121 	flags |= seg->g       << 23;
6122 	flags |= seg->db      << 22;
6123 	flags |= seg->l       << 21;
6124 	flags |= seg->avl     << 20;
6125 	flags |= seg->present << 15;
6126 	flags |= seg->dpl     << 13;
6127 	flags |= seg->s       << 12;
6128 	flags |= seg->type    << 8;
6129 	return flags;
6130 }
6131 
6132 static void process_smi_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
6133 {
6134 	struct kvm_segment seg;
6135 	int offset;
6136 
6137 	kvm_get_segment(vcpu, &seg, n);
6138 	put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
6139 
6140 	if (n < 3)
6141 		offset = 0x7f84 + n * 12;
6142 	else
6143 		offset = 0x7f2c + (n - 3) * 12;
6144 
6145 	put_smstate(u32, buf, offset + 8, seg.base);
6146 	put_smstate(u32, buf, offset + 4, seg.limit);
6147 	put_smstate(u32, buf, offset, process_smi_get_segment_flags(&seg));
6148 }
6149 
6150 #ifdef CONFIG_X86_64
6151 static void process_smi_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
6152 {
6153 	struct kvm_segment seg;
6154 	int offset;
6155 	u16 flags;
6156 
6157 	kvm_get_segment(vcpu, &seg, n);
6158 	offset = 0x7e00 + n * 16;
6159 
6160 	flags = process_smi_get_segment_flags(&seg) >> 8;
6161 	put_smstate(u16, buf, offset, seg.selector);
6162 	put_smstate(u16, buf, offset + 2, flags);
6163 	put_smstate(u32, buf, offset + 4, seg.limit);
6164 	put_smstate(u64, buf, offset + 8, seg.base);
6165 }
6166 #endif
6167 
6168 static void process_smi_save_state_32(struct kvm_vcpu *vcpu, char *buf)
6169 {
6170 	struct desc_ptr dt;
6171 	struct kvm_segment seg;
6172 	unsigned long val;
6173 	int i;
6174 
6175 	put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6176 	put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6177 	put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6178 	put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6179 
6180 	for (i = 0; i < 8; i++)
6181 		put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6182 
6183 	kvm_get_dr(vcpu, 6, &val);
6184 	put_smstate(u32, buf, 0x7fcc, (u32)val);
6185 	kvm_get_dr(vcpu, 7, &val);
6186 	put_smstate(u32, buf, 0x7fc8, (u32)val);
6187 
6188 	kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6189 	put_smstate(u32, buf, 0x7fc4, seg.selector);
6190 	put_smstate(u32, buf, 0x7f64, seg.base);
6191 	put_smstate(u32, buf, 0x7f60, seg.limit);
6192 	put_smstate(u32, buf, 0x7f5c, process_smi_get_segment_flags(&seg));
6193 
6194 	kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6195 	put_smstate(u32, buf, 0x7fc0, seg.selector);
6196 	put_smstate(u32, buf, 0x7f80, seg.base);
6197 	put_smstate(u32, buf, 0x7f7c, seg.limit);
6198 	put_smstate(u32, buf, 0x7f78, process_smi_get_segment_flags(&seg));
6199 
6200 	kvm_x86_ops->get_gdt(vcpu, &dt);
6201 	put_smstate(u32, buf, 0x7f74, dt.address);
6202 	put_smstate(u32, buf, 0x7f70, dt.size);
6203 
6204 	kvm_x86_ops->get_idt(vcpu, &dt);
6205 	put_smstate(u32, buf, 0x7f58, dt.address);
6206 	put_smstate(u32, buf, 0x7f54, dt.size);
6207 
6208 	for (i = 0; i < 6; i++)
6209 		process_smi_save_seg_32(vcpu, buf, i);
6210 
6211 	put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6212 
6213 	/* revision id */
6214 	put_smstate(u32, buf, 0x7efc, 0x00020000);
6215 	put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6216 }
6217 
6218 static void process_smi_save_state_64(struct kvm_vcpu *vcpu, char *buf)
6219 {
6220 #ifdef CONFIG_X86_64
6221 	struct desc_ptr dt;
6222 	struct kvm_segment seg;
6223 	unsigned long val;
6224 	int i;
6225 
6226 	for (i = 0; i < 16; i++)
6227 		put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
6228 
6229 	put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
6230 	put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
6231 
6232 	kvm_get_dr(vcpu, 6, &val);
6233 	put_smstate(u64, buf, 0x7f68, val);
6234 	kvm_get_dr(vcpu, 7, &val);
6235 	put_smstate(u64, buf, 0x7f60, val);
6236 
6237 	put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
6238 	put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
6239 	put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
6240 
6241 	put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
6242 
6243 	/* revision id */
6244 	put_smstate(u32, buf, 0x7efc, 0x00020064);
6245 
6246 	put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
6247 
6248 	kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6249 	put_smstate(u16, buf, 0x7e90, seg.selector);
6250 	put_smstate(u16, buf, 0x7e92, process_smi_get_segment_flags(&seg) >> 8);
6251 	put_smstate(u32, buf, 0x7e94, seg.limit);
6252 	put_smstate(u64, buf, 0x7e98, seg.base);
6253 
6254 	kvm_x86_ops->get_idt(vcpu, &dt);
6255 	put_smstate(u32, buf, 0x7e84, dt.size);
6256 	put_smstate(u64, buf, 0x7e88, dt.address);
6257 
6258 	kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6259 	put_smstate(u16, buf, 0x7e70, seg.selector);
6260 	put_smstate(u16, buf, 0x7e72, process_smi_get_segment_flags(&seg) >> 8);
6261 	put_smstate(u32, buf, 0x7e74, seg.limit);
6262 	put_smstate(u64, buf, 0x7e78, seg.base);
6263 
6264 	kvm_x86_ops->get_gdt(vcpu, &dt);
6265 	put_smstate(u32, buf, 0x7e64, dt.size);
6266 	put_smstate(u64, buf, 0x7e68, dt.address);
6267 
6268 	for (i = 0; i < 6; i++)
6269 		process_smi_save_seg_64(vcpu, buf, i);
6270 #else
6271 	WARN_ON_ONCE(1);
6272 #endif
6273 }
6274 
6275 static void process_smi(struct kvm_vcpu *vcpu)
6276 {
6277 	struct kvm_segment cs, ds;
6278 	struct desc_ptr dt;
6279 	char buf[512];
6280 	u32 cr0;
6281 
6282 	if (is_smm(vcpu)) {
6283 		vcpu->arch.smi_pending = true;
6284 		return;
6285 	}
6286 
6287 	trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
6288 	vcpu->arch.hflags |= HF_SMM_MASK;
6289 	memset(buf, 0, 512);
6290 	if (guest_cpuid_has_longmode(vcpu))
6291 		process_smi_save_state_64(vcpu, buf);
6292 	else
6293 		process_smi_save_state_32(vcpu, buf);
6294 
6295 	kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
6296 
6297 	if (kvm_x86_ops->get_nmi_mask(vcpu))
6298 		vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
6299 	else
6300 		kvm_x86_ops->set_nmi_mask(vcpu, true);
6301 
6302 	kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6303 	kvm_rip_write(vcpu, 0x8000);
6304 
6305 	cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
6306 	kvm_x86_ops->set_cr0(vcpu, cr0);
6307 	vcpu->arch.cr0 = cr0;
6308 
6309 	kvm_x86_ops->set_cr4(vcpu, 0);
6310 
6311 	/* Undocumented: IDT limit is set to zero on entry to SMM.  */
6312 	dt.address = dt.size = 0;
6313 	kvm_x86_ops->set_idt(vcpu, &dt);
6314 
6315 	__kvm_set_dr(vcpu, 7, DR7_FIXED_1);
6316 
6317 	cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
6318 	cs.base = vcpu->arch.smbase;
6319 
6320 	ds.selector = 0;
6321 	ds.base = 0;
6322 
6323 	cs.limit    = ds.limit = 0xffffffff;
6324 	cs.type     = ds.type = 0x3;
6325 	cs.dpl      = ds.dpl = 0;
6326 	cs.db       = ds.db = 0;
6327 	cs.s        = ds.s = 1;
6328 	cs.l        = ds.l = 0;
6329 	cs.g        = ds.g = 1;
6330 	cs.avl      = ds.avl = 0;
6331 	cs.present  = ds.present = 1;
6332 	cs.unusable = ds.unusable = 0;
6333 	cs.padding  = ds.padding = 0;
6334 
6335 	kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6336 	kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
6337 	kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
6338 	kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
6339 	kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
6340 	kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
6341 
6342 	if (guest_cpuid_has_longmode(vcpu))
6343 		kvm_x86_ops->set_efer(vcpu, 0);
6344 
6345 	kvm_update_cpuid(vcpu);
6346 	kvm_mmu_reset_context(vcpu);
6347 }
6348 
6349 void kvm_make_scan_ioapic_request(struct kvm *kvm)
6350 {
6351 	kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
6352 }
6353 
6354 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
6355 {
6356 	u64 eoi_exit_bitmap[4];
6357 
6358 	if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6359 		return;
6360 
6361 	bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
6362 
6363 	if (irqchip_split(vcpu->kvm))
6364 		kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
6365 	else {
6366 		if (vcpu->arch.apicv_active)
6367 			kvm_x86_ops->sync_pir_to_irr(vcpu);
6368 		kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
6369 	}
6370 	bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
6371 		  vcpu_to_synic(vcpu)->vec_bitmap, 256);
6372 	kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
6373 }
6374 
6375 static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6376 {
6377 	++vcpu->stat.tlb_flush;
6378 	kvm_x86_ops->tlb_flush(vcpu);
6379 }
6380 
6381 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6382 {
6383 	struct page *page = NULL;
6384 
6385 	if (!lapic_in_kernel(vcpu))
6386 		return;
6387 
6388 	if (!kvm_x86_ops->set_apic_access_page_addr)
6389 		return;
6390 
6391 	page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
6392 	if (is_error_page(page))
6393 		return;
6394 	kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6395 
6396 	/*
6397 	 * Do not pin apic access page in memory, the MMU notifier
6398 	 * will call us again if it is migrated or swapped out.
6399 	 */
6400 	put_page(page);
6401 }
6402 EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6403 
6404 void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
6405 					   unsigned long address)
6406 {
6407 	/*
6408 	 * The physical address of apic access page is stored in the VMCS.
6409 	 * Update it when it becomes invalid.
6410 	 */
6411 	if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT))
6412 		kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
6413 }
6414 
6415 /*
6416  * Returns 1 to let vcpu_run() continue the guest execution loop without
6417  * exiting to the userspace.  Otherwise, the value will be returned to the
6418  * userspace.
6419  */
6420 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
6421 {
6422 	int r;
6423 	bool req_int_win =
6424 		dm_request_for_irq_injection(vcpu) &&
6425 		kvm_cpu_accept_dm_intr(vcpu);
6426 
6427 	bool req_immediate_exit = false;
6428 
6429 	if (vcpu->requests) {
6430 		if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
6431 			kvm_mmu_unload(vcpu);
6432 		if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
6433 			__kvm_migrate_timers(vcpu);
6434 		if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6435 			kvm_gen_update_masterclock(vcpu->kvm);
6436 		if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6437 			kvm_gen_kvmclock_update(vcpu);
6438 		if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6439 			r = kvm_guest_time_update(vcpu);
6440 			if (unlikely(r))
6441 				goto out;
6442 		}
6443 		if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
6444 			kvm_mmu_sync_roots(vcpu);
6445 		if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
6446 			kvm_vcpu_flush_tlb(vcpu);
6447 		if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
6448 			vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
6449 			r = 0;
6450 			goto out;
6451 		}
6452 		if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
6453 			vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
6454 			r = 0;
6455 			goto out;
6456 		}
6457 		if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
6458 			vcpu->fpu_active = 0;
6459 			kvm_x86_ops->fpu_deactivate(vcpu);
6460 		}
6461 		if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6462 			/* Page is swapped out. Do synthetic halt */
6463 			vcpu->arch.apf.halted = true;
6464 			r = 1;
6465 			goto out;
6466 		}
6467 		if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6468 			record_steal_time(vcpu);
6469 		if (kvm_check_request(KVM_REQ_SMI, vcpu))
6470 			process_smi(vcpu);
6471 		if (kvm_check_request(KVM_REQ_NMI, vcpu))
6472 			process_nmi(vcpu);
6473 		if (kvm_check_request(KVM_REQ_PMU, vcpu))
6474 			kvm_pmu_handle_event(vcpu);
6475 		if (kvm_check_request(KVM_REQ_PMI, vcpu))
6476 			kvm_pmu_deliver_pmi(vcpu);
6477 		if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
6478 			BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
6479 			if (test_bit(vcpu->arch.pending_ioapic_eoi,
6480 				     vcpu->arch.ioapic_handled_vectors)) {
6481 				vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
6482 				vcpu->run->eoi.vector =
6483 						vcpu->arch.pending_ioapic_eoi;
6484 				r = 0;
6485 				goto out;
6486 			}
6487 		}
6488 		if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6489 			vcpu_scan_ioapic(vcpu);
6490 		if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6491 			kvm_vcpu_reload_apic_access_page(vcpu);
6492 		if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
6493 			vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6494 			vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
6495 			r = 0;
6496 			goto out;
6497 		}
6498 		if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
6499 			vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6500 			vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
6501 			r = 0;
6502 			goto out;
6503 		}
6504 		if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
6505 			vcpu->run->exit_reason = KVM_EXIT_HYPERV;
6506 			vcpu->run->hyperv = vcpu->arch.hyperv.exit;
6507 			r = 0;
6508 			goto out;
6509 		}
6510 
6511 		/*
6512 		 * KVM_REQ_HV_STIMER has to be processed after
6513 		 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
6514 		 * depend on the guest clock being up-to-date
6515 		 */
6516 		if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
6517 			kvm_hv_process_stimers(vcpu);
6518 	}
6519 
6520 	/*
6521 	 * KVM_REQ_EVENT is not set when posted interrupts are set by
6522 	 * VT-d hardware, so we have to update RVI unconditionally.
6523 	 */
6524 	if (kvm_lapic_enabled(vcpu)) {
6525 		/*
6526 		 * Update architecture specific hints for APIC
6527 		 * virtual interrupt delivery.
6528 		 */
6529 		if (vcpu->arch.apicv_active)
6530 			kvm_x86_ops->hwapic_irr_update(vcpu,
6531 				kvm_lapic_find_highest_irr(vcpu));
6532 	}
6533 
6534 	if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
6535 		kvm_apic_accept_events(vcpu);
6536 		if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6537 			r = 1;
6538 			goto out;
6539 		}
6540 
6541 		if (inject_pending_event(vcpu, req_int_win) != 0)
6542 			req_immediate_exit = true;
6543 		/* enable NMI/IRQ window open exits if needed */
6544 		else if (vcpu->arch.nmi_pending)
6545 			kvm_x86_ops->enable_nmi_window(vcpu);
6546 		else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
6547 			kvm_x86_ops->enable_irq_window(vcpu);
6548 
6549 		if (kvm_lapic_enabled(vcpu)) {
6550 			update_cr8_intercept(vcpu);
6551 			kvm_lapic_sync_to_vapic(vcpu);
6552 		}
6553 	}
6554 
6555 	r = kvm_mmu_reload(vcpu);
6556 	if (unlikely(r)) {
6557 		goto cancel_injection;
6558 	}
6559 
6560 	preempt_disable();
6561 
6562 	kvm_x86_ops->prepare_guest_switch(vcpu);
6563 	if (vcpu->fpu_active)
6564 		kvm_load_guest_fpu(vcpu);
6565 	kvm_load_guest_xcr0(vcpu);
6566 
6567 	vcpu->mode = IN_GUEST_MODE;
6568 
6569 	srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6570 
6571 	/* We should set ->mode before check ->requests,
6572 	 * see the comment in make_all_cpus_request.
6573 	 */
6574 	smp_mb__after_srcu_read_unlock();
6575 
6576 	local_irq_disable();
6577 
6578 	if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
6579 	    || need_resched() || signal_pending(current)) {
6580 		vcpu->mode = OUTSIDE_GUEST_MODE;
6581 		smp_wmb();
6582 		local_irq_enable();
6583 		preempt_enable();
6584 		vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6585 		r = 1;
6586 		goto cancel_injection;
6587 	}
6588 
6589 	if (req_immediate_exit)
6590 		smp_send_reschedule(vcpu->cpu);
6591 
6592 	trace_kvm_entry(vcpu->vcpu_id);
6593 	wait_lapic_expire(vcpu);
6594 	__kvm_guest_enter();
6595 
6596 	if (unlikely(vcpu->arch.switch_db_regs)) {
6597 		set_debugreg(0, 7);
6598 		set_debugreg(vcpu->arch.eff_db[0], 0);
6599 		set_debugreg(vcpu->arch.eff_db[1], 1);
6600 		set_debugreg(vcpu->arch.eff_db[2], 2);
6601 		set_debugreg(vcpu->arch.eff_db[3], 3);
6602 		set_debugreg(vcpu->arch.dr6, 6);
6603 		vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
6604 	}
6605 
6606 	kvm_x86_ops->run(vcpu);
6607 
6608 	/*
6609 	 * Do this here before restoring debug registers on the host.  And
6610 	 * since we do this before handling the vmexit, a DR access vmexit
6611 	 * can (a) read the correct value of the debug registers, (b) set
6612 	 * KVM_DEBUGREG_WONT_EXIT again.
6613 	 */
6614 	if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
6615 		int i;
6616 
6617 		WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6618 		kvm_x86_ops->sync_dirty_debug_regs(vcpu);
6619 		for (i = 0; i < KVM_NR_DB_REGS; i++)
6620 			vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6621 	}
6622 
6623 	/*
6624 	 * If the guest has used debug registers, at least dr7
6625 	 * will be disabled while returning to the host.
6626 	 * If we don't have active breakpoints in the host, we don't
6627 	 * care about the messed up debug address registers. But if
6628 	 * we have some of them active, restore the old state.
6629 	 */
6630 	if (hw_breakpoint_active())
6631 		hw_breakpoint_restore();
6632 
6633 	vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
6634 
6635 	vcpu->mode = OUTSIDE_GUEST_MODE;
6636 	smp_wmb();
6637 
6638 	/* Interrupt is enabled by handle_external_intr() */
6639 	kvm_x86_ops->handle_external_intr(vcpu);
6640 
6641 	++vcpu->stat.exits;
6642 
6643 	/*
6644 	 * We must have an instruction between local_irq_enable() and
6645 	 * kvm_guest_exit(), so the timer interrupt isn't delayed by
6646 	 * the interrupt shadow.  The stat.exits increment will do nicely.
6647 	 * But we need to prevent reordering, hence this barrier():
6648 	 */
6649 	barrier();
6650 
6651 	kvm_guest_exit();
6652 
6653 	preempt_enable();
6654 
6655 	vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6656 
6657 	/*
6658 	 * Profile KVM exit RIPs:
6659 	 */
6660 	if (unlikely(prof_on == KVM_PROFILING)) {
6661 		unsigned long rip = kvm_rip_read(vcpu);
6662 		profile_hit(KVM_PROFILING, (void *)rip);
6663 	}
6664 
6665 	if (unlikely(vcpu->arch.tsc_always_catchup))
6666 		kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6667 
6668 	if (vcpu->arch.apic_attention)
6669 		kvm_lapic_sync_from_vapic(vcpu);
6670 
6671 	r = kvm_x86_ops->handle_exit(vcpu);
6672 	return r;
6673 
6674 cancel_injection:
6675 	kvm_x86_ops->cancel_injection(vcpu);
6676 	if (unlikely(vcpu->arch.apic_attention))
6677 		kvm_lapic_sync_from_vapic(vcpu);
6678 out:
6679 	return r;
6680 }
6681 
6682 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
6683 {
6684 	if (!kvm_arch_vcpu_runnable(vcpu) &&
6685 	    (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
6686 		srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6687 		kvm_vcpu_block(vcpu);
6688 		vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6689 
6690 		if (kvm_x86_ops->post_block)
6691 			kvm_x86_ops->post_block(vcpu);
6692 
6693 		if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
6694 			return 1;
6695 	}
6696 
6697 	kvm_apic_accept_events(vcpu);
6698 	switch(vcpu->arch.mp_state) {
6699 	case KVM_MP_STATE_HALTED:
6700 		vcpu->arch.pv.pv_unhalted = false;
6701 		vcpu->arch.mp_state =
6702 			KVM_MP_STATE_RUNNABLE;
6703 	case KVM_MP_STATE_RUNNABLE:
6704 		vcpu->arch.apf.halted = false;
6705 		break;
6706 	case KVM_MP_STATE_INIT_RECEIVED:
6707 		break;
6708 	default:
6709 		return -EINTR;
6710 		break;
6711 	}
6712 	return 1;
6713 }
6714 
6715 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
6716 {
6717 	return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6718 		!vcpu->arch.apf.halted);
6719 }
6720 
6721 static int vcpu_run(struct kvm_vcpu *vcpu)
6722 {
6723 	int r;
6724 	struct kvm *kvm = vcpu->kvm;
6725 
6726 	vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6727 
6728 	for (;;) {
6729 		if (kvm_vcpu_running(vcpu)) {
6730 			r = vcpu_enter_guest(vcpu);
6731 		} else {
6732 			r = vcpu_block(kvm, vcpu);
6733 		}
6734 
6735 		if (r <= 0)
6736 			break;
6737 
6738 		clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6739 		if (kvm_cpu_has_pending_timer(vcpu))
6740 			kvm_inject_pending_timer_irqs(vcpu);
6741 
6742 		if (dm_request_for_irq_injection(vcpu) &&
6743 			kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
6744 			r = 0;
6745 			vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
6746 			++vcpu->stat.request_irq_exits;
6747 			break;
6748 		}
6749 
6750 		kvm_check_async_pf_completion(vcpu);
6751 
6752 		if (signal_pending(current)) {
6753 			r = -EINTR;
6754 			vcpu->run->exit_reason = KVM_EXIT_INTR;
6755 			++vcpu->stat.signal_exits;
6756 			break;
6757 		}
6758 		if (need_resched()) {
6759 			srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6760 			cond_resched();
6761 			vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6762 		}
6763 	}
6764 
6765 	srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6766 
6767 	return r;
6768 }
6769 
6770 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6771 {
6772 	int r;
6773 	vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6774 	r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6775 	srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6776 	if (r != EMULATE_DONE)
6777 		return 0;
6778 	return 1;
6779 }
6780 
6781 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6782 {
6783 	BUG_ON(!vcpu->arch.pio.count);
6784 
6785 	return complete_emulated_io(vcpu);
6786 }
6787 
6788 /*
6789  * Implements the following, as a state machine:
6790  *
6791  * read:
6792  *   for each fragment
6793  *     for each mmio piece in the fragment
6794  *       write gpa, len
6795  *       exit
6796  *       copy data
6797  *   execute insn
6798  *
6799  * write:
6800  *   for each fragment
6801  *     for each mmio piece in the fragment
6802  *       write gpa, len
6803  *       copy data
6804  *       exit
6805  */
6806 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
6807 {
6808 	struct kvm_run *run = vcpu->run;
6809 	struct kvm_mmio_fragment *frag;
6810 	unsigned len;
6811 
6812 	BUG_ON(!vcpu->mmio_needed);
6813 
6814 	/* Complete previous fragment */
6815 	frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6816 	len = min(8u, frag->len);
6817 	if (!vcpu->mmio_is_write)
6818 		memcpy(frag->data, run->mmio.data, len);
6819 
6820 	if (frag->len <= 8) {
6821 		/* Switch to the next fragment. */
6822 		frag++;
6823 		vcpu->mmio_cur_fragment++;
6824 	} else {
6825 		/* Go forward to the next mmio piece. */
6826 		frag->data += len;
6827 		frag->gpa += len;
6828 		frag->len -= len;
6829 	}
6830 
6831 	if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
6832 		vcpu->mmio_needed = 0;
6833 
6834 		/* FIXME: return into emulator if single-stepping.  */
6835 		if (vcpu->mmio_is_write)
6836 			return 1;
6837 		vcpu->mmio_read_completed = 1;
6838 		return complete_emulated_io(vcpu);
6839 	}
6840 
6841 	run->exit_reason = KVM_EXIT_MMIO;
6842 	run->mmio.phys_addr = frag->gpa;
6843 	if (vcpu->mmio_is_write)
6844 		memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6845 	run->mmio.len = min(8u, frag->len);
6846 	run->mmio.is_write = vcpu->mmio_is_write;
6847 	vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6848 	return 0;
6849 }
6850 
6851 
6852 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6853 {
6854 	struct fpu *fpu = &current->thread.fpu;
6855 	int r;
6856 	sigset_t sigsaved;
6857 
6858 	fpu__activate_curr(fpu);
6859 
6860 	if (vcpu->sigset_active)
6861 		sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6862 
6863 	if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
6864 		kvm_vcpu_block(vcpu);
6865 		kvm_apic_accept_events(vcpu);
6866 		clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
6867 		r = -EAGAIN;
6868 		goto out;
6869 	}
6870 
6871 	/* re-sync apic's tpr */
6872 	if (!lapic_in_kernel(vcpu)) {
6873 		if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6874 			r = -EINVAL;
6875 			goto out;
6876 		}
6877 	}
6878 
6879 	if (unlikely(vcpu->arch.complete_userspace_io)) {
6880 		int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6881 		vcpu->arch.complete_userspace_io = NULL;
6882 		r = cui(vcpu);
6883 		if (r <= 0)
6884 			goto out;
6885 	} else
6886 		WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
6887 
6888 	r = vcpu_run(vcpu);
6889 
6890 out:
6891 	post_kvm_run_save(vcpu);
6892 	if (vcpu->sigset_active)
6893 		sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6894 
6895 	return r;
6896 }
6897 
6898 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6899 {
6900 	if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6901 		/*
6902 		 * We are here if userspace calls get_regs() in the middle of
6903 		 * instruction emulation. Registers state needs to be copied
6904 		 * back from emulation context to vcpu. Userspace shouldn't do
6905 		 * that usually, but some bad designed PV devices (vmware
6906 		 * backdoor interface) need this to work
6907 		 */
6908 		emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
6909 		vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6910 	}
6911 	regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6912 	regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6913 	regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6914 	regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6915 	regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6916 	regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6917 	regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6918 	regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
6919 #ifdef CONFIG_X86_64
6920 	regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6921 	regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6922 	regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6923 	regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6924 	regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6925 	regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6926 	regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6927 	regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
6928 #endif
6929 
6930 	regs->rip = kvm_rip_read(vcpu);
6931 	regs->rflags = kvm_get_rflags(vcpu);
6932 
6933 	return 0;
6934 }
6935 
6936 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6937 {
6938 	vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6939 	vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6940 
6941 	kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6942 	kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6943 	kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6944 	kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6945 	kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6946 	kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6947 	kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6948 	kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
6949 #ifdef CONFIG_X86_64
6950 	kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6951 	kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6952 	kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6953 	kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6954 	kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6955 	kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6956 	kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6957 	kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
6958 #endif
6959 
6960 	kvm_rip_write(vcpu, regs->rip);
6961 	kvm_set_rflags(vcpu, regs->rflags);
6962 
6963 	vcpu->arch.exception.pending = false;
6964 
6965 	kvm_make_request(KVM_REQ_EVENT, vcpu);
6966 
6967 	return 0;
6968 }
6969 
6970 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6971 {
6972 	struct kvm_segment cs;
6973 
6974 	kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
6975 	*db = cs.db;
6976 	*l = cs.l;
6977 }
6978 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6979 
6980 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6981 				  struct kvm_sregs *sregs)
6982 {
6983 	struct desc_ptr dt;
6984 
6985 	kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6986 	kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6987 	kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6988 	kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6989 	kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6990 	kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
6991 
6992 	kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6993 	kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
6994 
6995 	kvm_x86_ops->get_idt(vcpu, &dt);
6996 	sregs->idt.limit = dt.size;
6997 	sregs->idt.base = dt.address;
6998 	kvm_x86_ops->get_gdt(vcpu, &dt);
6999 	sregs->gdt.limit = dt.size;
7000 	sregs->gdt.base = dt.address;
7001 
7002 	sregs->cr0 = kvm_read_cr0(vcpu);
7003 	sregs->cr2 = vcpu->arch.cr2;
7004 	sregs->cr3 = kvm_read_cr3(vcpu);
7005 	sregs->cr4 = kvm_read_cr4(vcpu);
7006 	sregs->cr8 = kvm_get_cr8(vcpu);
7007 	sregs->efer = vcpu->arch.efer;
7008 	sregs->apic_base = kvm_get_apic_base(vcpu);
7009 
7010 	memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
7011 
7012 	if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
7013 		set_bit(vcpu->arch.interrupt.nr,
7014 			(unsigned long *)sregs->interrupt_bitmap);
7015 
7016 	return 0;
7017 }
7018 
7019 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
7020 				    struct kvm_mp_state *mp_state)
7021 {
7022 	kvm_apic_accept_events(vcpu);
7023 	if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
7024 					vcpu->arch.pv.pv_unhalted)
7025 		mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
7026 	else
7027 		mp_state->mp_state = vcpu->arch.mp_state;
7028 
7029 	return 0;
7030 }
7031 
7032 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
7033 				    struct kvm_mp_state *mp_state)
7034 {
7035 	if (!kvm_vcpu_has_lapic(vcpu) &&
7036 	    mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
7037 		return -EINVAL;
7038 
7039 	if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
7040 		vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
7041 		set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
7042 	} else
7043 		vcpu->arch.mp_state = mp_state->mp_state;
7044 	kvm_make_request(KVM_REQ_EVENT, vcpu);
7045 	return 0;
7046 }
7047 
7048 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
7049 		    int reason, bool has_error_code, u32 error_code)
7050 {
7051 	struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7052 	int ret;
7053 
7054 	init_emulate_ctxt(vcpu);
7055 
7056 	ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
7057 				   has_error_code, error_code);
7058 
7059 	if (ret)
7060 		return EMULATE_FAIL;
7061 
7062 	kvm_rip_write(vcpu, ctxt->eip);
7063 	kvm_set_rflags(vcpu, ctxt->eflags);
7064 	kvm_make_request(KVM_REQ_EVENT, vcpu);
7065 	return EMULATE_DONE;
7066 }
7067 EXPORT_SYMBOL_GPL(kvm_task_switch);
7068 
7069 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
7070 				  struct kvm_sregs *sregs)
7071 {
7072 	struct msr_data apic_base_msr;
7073 	int mmu_reset_needed = 0;
7074 	int pending_vec, max_bits, idx;
7075 	struct desc_ptr dt;
7076 
7077 	if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
7078 		return -EINVAL;
7079 
7080 	dt.size = sregs->idt.limit;
7081 	dt.address = sregs->idt.base;
7082 	kvm_x86_ops->set_idt(vcpu, &dt);
7083 	dt.size = sregs->gdt.limit;
7084 	dt.address = sregs->gdt.base;
7085 	kvm_x86_ops->set_gdt(vcpu, &dt);
7086 
7087 	vcpu->arch.cr2 = sregs->cr2;
7088 	mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
7089 	vcpu->arch.cr3 = sregs->cr3;
7090 	__set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
7091 
7092 	kvm_set_cr8(vcpu, sregs->cr8);
7093 
7094 	mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
7095 	kvm_x86_ops->set_efer(vcpu, sregs->efer);
7096 	apic_base_msr.data = sregs->apic_base;
7097 	apic_base_msr.host_initiated = true;
7098 	kvm_set_apic_base(vcpu, &apic_base_msr);
7099 
7100 	mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
7101 	kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
7102 	vcpu->arch.cr0 = sregs->cr0;
7103 
7104 	mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
7105 	kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
7106 	if (sregs->cr4 & X86_CR4_OSXSAVE)
7107 		kvm_update_cpuid(vcpu);
7108 
7109 	idx = srcu_read_lock(&vcpu->kvm->srcu);
7110 	if (!is_long_mode(vcpu) && is_pae(vcpu)) {
7111 		load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7112 		mmu_reset_needed = 1;
7113 	}
7114 	srcu_read_unlock(&vcpu->kvm->srcu, idx);
7115 
7116 	if (mmu_reset_needed)
7117 		kvm_mmu_reset_context(vcpu);
7118 
7119 	max_bits = KVM_NR_INTERRUPTS;
7120 	pending_vec = find_first_bit(
7121 		(const unsigned long *)sregs->interrupt_bitmap, max_bits);
7122 	if (pending_vec < max_bits) {
7123 		kvm_queue_interrupt(vcpu, pending_vec, false);
7124 		pr_debug("Set back pending irq %d\n", pending_vec);
7125 	}
7126 
7127 	kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7128 	kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7129 	kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7130 	kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7131 	kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7132 	kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
7133 
7134 	kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7135 	kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
7136 
7137 	update_cr8_intercept(vcpu);
7138 
7139 	/* Older userspace won't unhalt the vcpu on reset. */
7140 	if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
7141 	    sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
7142 	    !is_protmode(vcpu))
7143 		vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7144 
7145 	kvm_make_request(KVM_REQ_EVENT, vcpu);
7146 
7147 	return 0;
7148 }
7149 
7150 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
7151 					struct kvm_guest_debug *dbg)
7152 {
7153 	unsigned long rflags;
7154 	int i, r;
7155 
7156 	if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
7157 		r = -EBUSY;
7158 		if (vcpu->arch.exception.pending)
7159 			goto out;
7160 		if (dbg->control & KVM_GUESTDBG_INJECT_DB)
7161 			kvm_queue_exception(vcpu, DB_VECTOR);
7162 		else
7163 			kvm_queue_exception(vcpu, BP_VECTOR);
7164 	}
7165 
7166 	/*
7167 	 * Read rflags as long as potentially injected trace flags are still
7168 	 * filtered out.
7169 	 */
7170 	rflags = kvm_get_rflags(vcpu);
7171 
7172 	vcpu->guest_debug = dbg->control;
7173 	if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
7174 		vcpu->guest_debug = 0;
7175 
7176 	if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
7177 		for (i = 0; i < KVM_NR_DB_REGS; ++i)
7178 			vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
7179 		vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
7180 	} else {
7181 		for (i = 0; i < KVM_NR_DB_REGS; i++)
7182 			vcpu->arch.eff_db[i] = vcpu->arch.db[i];
7183 	}
7184 	kvm_update_dr7(vcpu);
7185 
7186 	if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7187 		vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
7188 			get_segment_base(vcpu, VCPU_SREG_CS);
7189 
7190 	/*
7191 	 * Trigger an rflags update that will inject or remove the trace
7192 	 * flags.
7193 	 */
7194 	kvm_set_rflags(vcpu, rflags);
7195 
7196 	kvm_x86_ops->update_bp_intercept(vcpu);
7197 
7198 	r = 0;
7199 
7200 out:
7201 
7202 	return r;
7203 }
7204 
7205 /*
7206  * Translate a guest virtual address to a guest physical address.
7207  */
7208 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
7209 				    struct kvm_translation *tr)
7210 {
7211 	unsigned long vaddr = tr->linear_address;
7212 	gpa_t gpa;
7213 	int idx;
7214 
7215 	idx = srcu_read_lock(&vcpu->kvm->srcu);
7216 	gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
7217 	srcu_read_unlock(&vcpu->kvm->srcu, idx);
7218 	tr->physical_address = gpa;
7219 	tr->valid = gpa != UNMAPPED_GVA;
7220 	tr->writeable = 1;
7221 	tr->usermode = 0;
7222 
7223 	return 0;
7224 }
7225 
7226 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7227 {
7228 	struct fxregs_state *fxsave =
7229 			&vcpu->arch.guest_fpu.state.fxsave;
7230 
7231 	memcpy(fpu->fpr, fxsave->st_space, 128);
7232 	fpu->fcw = fxsave->cwd;
7233 	fpu->fsw = fxsave->swd;
7234 	fpu->ftwx = fxsave->twd;
7235 	fpu->last_opcode = fxsave->fop;
7236 	fpu->last_ip = fxsave->rip;
7237 	fpu->last_dp = fxsave->rdp;
7238 	memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
7239 
7240 	return 0;
7241 }
7242 
7243 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7244 {
7245 	struct fxregs_state *fxsave =
7246 			&vcpu->arch.guest_fpu.state.fxsave;
7247 
7248 	memcpy(fxsave->st_space, fpu->fpr, 128);
7249 	fxsave->cwd = fpu->fcw;
7250 	fxsave->swd = fpu->fsw;
7251 	fxsave->twd = fpu->ftwx;
7252 	fxsave->fop = fpu->last_opcode;
7253 	fxsave->rip = fpu->last_ip;
7254 	fxsave->rdp = fpu->last_dp;
7255 	memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
7256 
7257 	return 0;
7258 }
7259 
7260 static void fx_init(struct kvm_vcpu *vcpu)
7261 {
7262 	fpstate_init(&vcpu->arch.guest_fpu.state);
7263 	if (cpu_has_xsaves)
7264 		vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
7265 			host_xcr0 | XSTATE_COMPACTION_ENABLED;
7266 
7267 	/*
7268 	 * Ensure guest xcr0 is valid for loading
7269 	 */
7270 	vcpu->arch.xcr0 = XFEATURE_MASK_FP;
7271 
7272 	vcpu->arch.cr0 |= X86_CR0_ET;
7273 }
7274 
7275 void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7276 {
7277 	if (vcpu->guest_fpu_loaded)
7278 		return;
7279 
7280 	/*
7281 	 * Restore all possible states in the guest,
7282 	 * and assume host would use all available bits.
7283 	 * Guest xcr0 would be loaded later.
7284 	 */
7285 	kvm_put_guest_xcr0(vcpu);
7286 	vcpu->guest_fpu_loaded = 1;
7287 	__kernel_fpu_begin();
7288 	__copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state);
7289 	trace_kvm_fpu(1);
7290 }
7291 
7292 void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7293 {
7294 	kvm_put_guest_xcr0(vcpu);
7295 
7296 	if (!vcpu->guest_fpu_loaded) {
7297 		vcpu->fpu_counter = 0;
7298 		return;
7299 	}
7300 
7301 	vcpu->guest_fpu_loaded = 0;
7302 	copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
7303 	__kernel_fpu_end();
7304 	++vcpu->stat.fpu_reload;
7305 	/*
7306 	 * If using eager FPU mode, or if the guest is a frequent user
7307 	 * of the FPU, just leave the FPU active for next time.
7308 	 * Every 255 times fpu_counter rolls over to 0; a guest that uses
7309 	 * the FPU in bursts will revert to loading it on demand.
7310 	 */
7311 	if (!vcpu->arch.eager_fpu) {
7312 		if (++vcpu->fpu_counter < 5)
7313 			kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
7314 	}
7315 	trace_kvm_fpu(0);
7316 }
7317 
7318 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7319 {
7320 	kvmclock_reset(vcpu);
7321 
7322 	free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
7323 	kvm_x86_ops->vcpu_free(vcpu);
7324 }
7325 
7326 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7327 						unsigned int id)
7328 {
7329 	struct kvm_vcpu *vcpu;
7330 
7331 	if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7332 		printk_once(KERN_WARNING
7333 		"kvm: SMP vm created on host with unstable TSC; "
7334 		"guest TSC will not be reliable\n");
7335 
7336 	vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7337 
7338 	return vcpu;
7339 }
7340 
7341 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7342 {
7343 	int r;
7344 
7345 	kvm_vcpu_mtrr_init(vcpu);
7346 	r = vcpu_load(vcpu);
7347 	if (r)
7348 		return r;
7349 	kvm_vcpu_reset(vcpu, false);
7350 	kvm_mmu_setup(vcpu);
7351 	vcpu_put(vcpu);
7352 	return r;
7353 }
7354 
7355 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
7356 {
7357 	struct msr_data msr;
7358 	struct kvm *kvm = vcpu->kvm;
7359 
7360 	if (vcpu_load(vcpu))
7361 		return;
7362 	msr.data = 0x0;
7363 	msr.index = MSR_IA32_TSC;
7364 	msr.host_initiated = true;
7365 	kvm_write_tsc(vcpu, &msr);
7366 	vcpu_put(vcpu);
7367 
7368 	if (!kvmclock_periodic_sync)
7369 		return;
7370 
7371 	schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7372 					KVMCLOCK_SYNC_PERIOD);
7373 }
7374 
7375 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
7376 {
7377 	int r;
7378 	vcpu->arch.apf.msr_val = 0;
7379 
7380 	r = vcpu_load(vcpu);
7381 	BUG_ON(r);
7382 	kvm_mmu_unload(vcpu);
7383 	vcpu_put(vcpu);
7384 
7385 	kvm_x86_ops->vcpu_free(vcpu);
7386 }
7387 
7388 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
7389 {
7390 	vcpu->arch.hflags = 0;
7391 
7392 	atomic_set(&vcpu->arch.nmi_queued, 0);
7393 	vcpu->arch.nmi_pending = 0;
7394 	vcpu->arch.nmi_injected = false;
7395 	kvm_clear_interrupt_queue(vcpu);
7396 	kvm_clear_exception_queue(vcpu);
7397 
7398 	memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
7399 	kvm_update_dr0123(vcpu);
7400 	vcpu->arch.dr6 = DR6_INIT;
7401 	kvm_update_dr6(vcpu);
7402 	vcpu->arch.dr7 = DR7_FIXED_1;
7403 	kvm_update_dr7(vcpu);
7404 
7405 	vcpu->arch.cr2 = 0;
7406 
7407 	kvm_make_request(KVM_REQ_EVENT, vcpu);
7408 	vcpu->arch.apf.msr_val = 0;
7409 	vcpu->arch.st.msr_val = 0;
7410 
7411 	kvmclock_reset(vcpu);
7412 
7413 	kvm_clear_async_pf_completion_queue(vcpu);
7414 	kvm_async_pf_hash_reset(vcpu);
7415 	vcpu->arch.apf.halted = false;
7416 
7417 	if (!init_event) {
7418 		kvm_pmu_reset(vcpu);
7419 		vcpu->arch.smbase = 0x30000;
7420 	}
7421 
7422 	memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7423 	vcpu->arch.regs_avail = ~0;
7424 	vcpu->arch.regs_dirty = ~0;
7425 
7426 	kvm_x86_ops->vcpu_reset(vcpu, init_event);
7427 }
7428 
7429 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
7430 {
7431 	struct kvm_segment cs;
7432 
7433 	kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7434 	cs.selector = vector << 8;
7435 	cs.base = vector << 12;
7436 	kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7437 	kvm_rip_write(vcpu, 0);
7438 }
7439 
7440 int kvm_arch_hardware_enable(void)
7441 {
7442 	struct kvm *kvm;
7443 	struct kvm_vcpu *vcpu;
7444 	int i;
7445 	int ret;
7446 	u64 local_tsc;
7447 	u64 max_tsc = 0;
7448 	bool stable, backwards_tsc = false;
7449 
7450 	kvm_shared_msr_cpu_online();
7451 	ret = kvm_x86_ops->hardware_enable();
7452 	if (ret != 0)
7453 		return ret;
7454 
7455 	local_tsc = rdtsc();
7456 	stable = !check_tsc_unstable();
7457 	list_for_each_entry(kvm, &vm_list, vm_list) {
7458 		kvm_for_each_vcpu(i, vcpu, kvm) {
7459 			if (!stable && vcpu->cpu == smp_processor_id())
7460 				kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
7461 			if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7462 				backwards_tsc = true;
7463 				if (vcpu->arch.last_host_tsc > max_tsc)
7464 					max_tsc = vcpu->arch.last_host_tsc;
7465 			}
7466 		}
7467 	}
7468 
7469 	/*
7470 	 * Sometimes, even reliable TSCs go backwards.  This happens on
7471 	 * platforms that reset TSC during suspend or hibernate actions, but
7472 	 * maintain synchronization.  We must compensate.  Fortunately, we can
7473 	 * detect that condition here, which happens early in CPU bringup,
7474 	 * before any KVM threads can be running.  Unfortunately, we can't
7475 	 * bring the TSCs fully up to date with real time, as we aren't yet far
7476 	 * enough into CPU bringup that we know how much real time has actually
7477 	 * elapsed; our helper function, get_kernel_ns() will be using boot
7478 	 * variables that haven't been updated yet.
7479 	 *
7480 	 * So we simply find the maximum observed TSC above, then record the
7481 	 * adjustment to TSC in each VCPU.  When the VCPU later gets loaded,
7482 	 * the adjustment will be applied.  Note that we accumulate
7483 	 * adjustments, in case multiple suspend cycles happen before some VCPU
7484 	 * gets a chance to run again.  In the event that no KVM threads get a
7485 	 * chance to run, we will miss the entire elapsed period, as we'll have
7486 	 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7487 	 * loose cycle time.  This isn't too big a deal, since the loss will be
7488 	 * uniform across all VCPUs (not to mention the scenario is extremely
7489 	 * unlikely). It is possible that a second hibernate recovery happens
7490 	 * much faster than a first, causing the observed TSC here to be
7491 	 * smaller; this would require additional padding adjustment, which is
7492 	 * why we set last_host_tsc to the local tsc observed here.
7493 	 *
7494 	 * N.B. - this code below runs only on platforms with reliable TSC,
7495 	 * as that is the only way backwards_tsc is set above.  Also note
7496 	 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7497 	 * have the same delta_cyc adjustment applied if backwards_tsc
7498 	 * is detected.  Note further, this adjustment is only done once,
7499 	 * as we reset last_host_tsc on all VCPUs to stop this from being
7500 	 * called multiple times (one for each physical CPU bringup).
7501 	 *
7502 	 * Platforms with unreliable TSCs don't have to deal with this, they
7503 	 * will be compensated by the logic in vcpu_load, which sets the TSC to
7504 	 * catchup mode.  This will catchup all VCPUs to real time, but cannot
7505 	 * guarantee that they stay in perfect synchronization.
7506 	 */
7507 	if (backwards_tsc) {
7508 		u64 delta_cyc = max_tsc - local_tsc;
7509 		backwards_tsc_observed = true;
7510 		list_for_each_entry(kvm, &vm_list, vm_list) {
7511 			kvm_for_each_vcpu(i, vcpu, kvm) {
7512 				vcpu->arch.tsc_offset_adjustment += delta_cyc;
7513 				vcpu->arch.last_host_tsc = local_tsc;
7514 				kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
7515 			}
7516 
7517 			/*
7518 			 * We have to disable TSC offset matching.. if you were
7519 			 * booting a VM while issuing an S4 host suspend....
7520 			 * you may have some problem.  Solving this issue is
7521 			 * left as an exercise to the reader.
7522 			 */
7523 			kvm->arch.last_tsc_nsec = 0;
7524 			kvm->arch.last_tsc_write = 0;
7525 		}
7526 
7527 	}
7528 	return 0;
7529 }
7530 
7531 void kvm_arch_hardware_disable(void)
7532 {
7533 	kvm_x86_ops->hardware_disable();
7534 	drop_user_return_notifiers();
7535 }
7536 
7537 int kvm_arch_hardware_setup(void)
7538 {
7539 	int r;
7540 
7541 	r = kvm_x86_ops->hardware_setup();
7542 	if (r != 0)
7543 		return r;
7544 
7545 	if (kvm_has_tsc_control) {
7546 		/*
7547 		 * Make sure the user can only configure tsc_khz values that
7548 		 * fit into a signed integer.
7549 		 * A min value is not calculated needed because it will always
7550 		 * be 1 on all machines.
7551 		 */
7552 		u64 max = min(0x7fffffffULL,
7553 			      __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
7554 		kvm_max_guest_tsc_khz = max;
7555 
7556 		kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
7557 	}
7558 
7559 	kvm_init_msr_list();
7560 	return 0;
7561 }
7562 
7563 void kvm_arch_hardware_unsetup(void)
7564 {
7565 	kvm_x86_ops->hardware_unsetup();
7566 }
7567 
7568 void kvm_arch_check_processor_compat(void *rtn)
7569 {
7570 	kvm_x86_ops->check_processor_compatibility(rtn);
7571 }
7572 
7573 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
7574 {
7575 	return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
7576 }
7577 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
7578 
7579 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
7580 {
7581 	return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
7582 }
7583 
7584 bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
7585 {
7586 	return irqchip_in_kernel(vcpu->kvm) == lapic_in_kernel(vcpu);
7587 }
7588 
7589 struct static_key kvm_no_apic_vcpu __read_mostly;
7590 
7591 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7592 {
7593 	struct page *page;
7594 	struct kvm *kvm;
7595 	int r;
7596 
7597 	BUG_ON(vcpu->kvm == NULL);
7598 	kvm = vcpu->kvm;
7599 
7600 	vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv();
7601 	vcpu->arch.pv.pv_unhalted = false;
7602 	vcpu->arch.emulate_ctxt.ops = &emulate_ops;
7603 	if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu))
7604 		vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7605 	else
7606 		vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
7607 
7608 	page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7609 	if (!page) {
7610 		r = -ENOMEM;
7611 		goto fail;
7612 	}
7613 	vcpu->arch.pio_data = page_address(page);
7614 
7615 	kvm_set_tsc_khz(vcpu, max_tsc_khz);
7616 
7617 	r = kvm_mmu_create(vcpu);
7618 	if (r < 0)
7619 		goto fail_free_pio_data;
7620 
7621 	if (irqchip_in_kernel(kvm)) {
7622 		r = kvm_create_lapic(vcpu);
7623 		if (r < 0)
7624 			goto fail_mmu_destroy;
7625 	} else
7626 		static_key_slow_inc(&kvm_no_apic_vcpu);
7627 
7628 	vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7629 				       GFP_KERNEL);
7630 	if (!vcpu->arch.mce_banks) {
7631 		r = -ENOMEM;
7632 		goto fail_free_lapic;
7633 	}
7634 	vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7635 
7636 	if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7637 		r = -ENOMEM;
7638 		goto fail_free_mce_banks;
7639 	}
7640 
7641 	fx_init(vcpu);
7642 
7643 	vcpu->arch.ia32_tsc_adjust_msr = 0x0;
7644 	vcpu->arch.pv_time_enabled = false;
7645 
7646 	vcpu->arch.guest_supported_xcr0 = 0;
7647 	vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
7648 
7649 	vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
7650 
7651 	vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
7652 
7653 	kvm_async_pf_hash_reset(vcpu);
7654 	kvm_pmu_init(vcpu);
7655 
7656 	vcpu->arch.pending_external_vector = -1;
7657 
7658 	kvm_hv_vcpu_init(vcpu);
7659 
7660 	return 0;
7661 
7662 fail_free_mce_banks:
7663 	kfree(vcpu->arch.mce_banks);
7664 fail_free_lapic:
7665 	kvm_free_lapic(vcpu);
7666 fail_mmu_destroy:
7667 	kvm_mmu_destroy(vcpu);
7668 fail_free_pio_data:
7669 	free_page((unsigned long)vcpu->arch.pio_data);
7670 fail:
7671 	return r;
7672 }
7673 
7674 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7675 {
7676 	int idx;
7677 
7678 	kvm_hv_vcpu_uninit(vcpu);
7679 	kvm_pmu_destroy(vcpu);
7680 	kfree(vcpu->arch.mce_banks);
7681 	kvm_free_lapic(vcpu);
7682 	idx = srcu_read_lock(&vcpu->kvm->srcu);
7683 	kvm_mmu_destroy(vcpu);
7684 	srcu_read_unlock(&vcpu->kvm->srcu, idx);
7685 	free_page((unsigned long)vcpu->arch.pio_data);
7686 	if (!lapic_in_kernel(vcpu))
7687 		static_key_slow_dec(&kvm_no_apic_vcpu);
7688 }
7689 
7690 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
7691 {
7692 	kvm_x86_ops->sched_in(vcpu, cpu);
7693 }
7694 
7695 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
7696 {
7697 	if (type)
7698 		return -EINVAL;
7699 
7700 	INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
7701 	INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
7702 	INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
7703 	INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
7704 	atomic_set(&kvm->arch.noncoherent_dma_count, 0);
7705 
7706 	/* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7707 	set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7708 	/* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7709 	set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7710 		&kvm->arch.irq_sources_bitmap);
7711 
7712 	raw_spin_lock_init(&kvm->arch.tsc_write_lock);
7713 	mutex_init(&kvm->arch.apic_map_lock);
7714 	spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7715 
7716 	pvclock_update_vm_gtod_copy(kvm);
7717 
7718 	INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
7719 	INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7720 
7721 	return 0;
7722 }
7723 
7724 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7725 {
7726 	int r;
7727 	r = vcpu_load(vcpu);
7728 	BUG_ON(r);
7729 	kvm_mmu_unload(vcpu);
7730 	vcpu_put(vcpu);
7731 }
7732 
7733 static void kvm_free_vcpus(struct kvm *kvm)
7734 {
7735 	unsigned int i;
7736 	struct kvm_vcpu *vcpu;
7737 
7738 	/*
7739 	 * Unpin any mmu pages first.
7740 	 */
7741 	kvm_for_each_vcpu(i, vcpu, kvm) {
7742 		kvm_clear_async_pf_completion_queue(vcpu);
7743 		kvm_unload_vcpu_mmu(vcpu);
7744 	}
7745 	kvm_for_each_vcpu(i, vcpu, kvm)
7746 		kvm_arch_vcpu_free(vcpu);
7747 
7748 	mutex_lock(&kvm->lock);
7749 	for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7750 		kvm->vcpus[i] = NULL;
7751 
7752 	atomic_set(&kvm->online_vcpus, 0);
7753 	mutex_unlock(&kvm->lock);
7754 }
7755 
7756 void kvm_arch_sync_events(struct kvm *kvm)
7757 {
7758 	cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7759 	cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
7760 	kvm_free_all_assigned_devices(kvm);
7761 	kvm_free_pit(kvm);
7762 }
7763 
7764 int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
7765 {
7766 	int i, r;
7767 	unsigned long hva;
7768 	struct kvm_memslots *slots = kvm_memslots(kvm);
7769 	struct kvm_memory_slot *slot, old;
7770 
7771 	/* Called with kvm->slots_lock held.  */
7772 	if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
7773 		return -EINVAL;
7774 
7775 	slot = id_to_memslot(slots, id);
7776 	if (size) {
7777 		if (WARN_ON(slot->npages))
7778 			return -EEXIST;
7779 
7780 		/*
7781 		 * MAP_SHARED to prevent internal slot pages from being moved
7782 		 * by fork()/COW.
7783 		 */
7784 		hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
7785 			      MAP_SHARED | MAP_ANONYMOUS, 0);
7786 		if (IS_ERR((void *)hva))
7787 			return PTR_ERR((void *)hva);
7788 	} else {
7789 		if (!slot->npages)
7790 			return 0;
7791 
7792 		hva = 0;
7793 	}
7794 
7795 	old = *slot;
7796 	for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
7797 		struct kvm_userspace_memory_region m;
7798 
7799 		m.slot = id | (i << 16);
7800 		m.flags = 0;
7801 		m.guest_phys_addr = gpa;
7802 		m.userspace_addr = hva;
7803 		m.memory_size = size;
7804 		r = __kvm_set_memory_region(kvm, &m);
7805 		if (r < 0)
7806 			return r;
7807 	}
7808 
7809 	if (!size) {
7810 		r = vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
7811 		WARN_ON(r < 0);
7812 	}
7813 
7814 	return 0;
7815 }
7816 EXPORT_SYMBOL_GPL(__x86_set_memory_region);
7817 
7818 int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
7819 {
7820 	int r;
7821 
7822 	mutex_lock(&kvm->slots_lock);
7823 	r = __x86_set_memory_region(kvm, id, gpa, size);
7824 	mutex_unlock(&kvm->slots_lock);
7825 
7826 	return r;
7827 }
7828 EXPORT_SYMBOL_GPL(x86_set_memory_region);
7829 
7830 void kvm_arch_destroy_vm(struct kvm *kvm)
7831 {
7832 	if (current->mm == kvm->mm) {
7833 		/*
7834 		 * Free memory regions allocated on behalf of userspace,
7835 		 * unless the the memory map has changed due to process exit
7836 		 * or fd copying.
7837 		 */
7838 		x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
7839 		x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
7840 		x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
7841 	}
7842 	kvm_iommu_unmap_guest(kvm);
7843 	kfree(kvm->arch.vpic);
7844 	kfree(kvm->arch.vioapic);
7845 	kvm_free_vcpus(kvm);
7846 	kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
7847 }
7848 
7849 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
7850 			   struct kvm_memory_slot *dont)
7851 {
7852 	int i;
7853 
7854 	for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7855 		if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
7856 			kvfree(free->arch.rmap[i]);
7857 			free->arch.rmap[i] = NULL;
7858 		}
7859 		if (i == 0)
7860 			continue;
7861 
7862 		if (!dont || free->arch.lpage_info[i - 1] !=
7863 			     dont->arch.lpage_info[i - 1]) {
7864 			kvfree(free->arch.lpage_info[i - 1]);
7865 			free->arch.lpage_info[i - 1] = NULL;
7866 		}
7867 	}
7868 }
7869 
7870 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7871 			    unsigned long npages)
7872 {
7873 	int i;
7874 
7875 	for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7876 		unsigned long ugfn;
7877 		int lpages;
7878 		int level = i + 1;
7879 
7880 		lpages = gfn_to_index(slot->base_gfn + npages - 1,
7881 				      slot->base_gfn, level) + 1;
7882 
7883 		slot->arch.rmap[i] =
7884 			kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7885 		if (!slot->arch.rmap[i])
7886 			goto out_free;
7887 		if (i == 0)
7888 			continue;
7889 
7890 		slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
7891 					sizeof(*slot->arch.lpage_info[i - 1]));
7892 		if (!slot->arch.lpage_info[i - 1])
7893 			goto out_free;
7894 
7895 		if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
7896 			slot->arch.lpage_info[i - 1][0].write_count = 1;
7897 		if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
7898 			slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
7899 		ugfn = slot->userspace_addr >> PAGE_SHIFT;
7900 		/*
7901 		 * If the gfn and userspace address are not aligned wrt each
7902 		 * other, or if explicitly asked to, disable large page
7903 		 * support for this slot
7904 		 */
7905 		if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7906 		    !kvm_largepages_enabled()) {
7907 			unsigned long j;
7908 
7909 			for (j = 0; j < lpages; ++j)
7910 				slot->arch.lpage_info[i - 1][j].write_count = 1;
7911 		}
7912 	}
7913 
7914 	return 0;
7915 
7916 out_free:
7917 	for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7918 		kvfree(slot->arch.rmap[i]);
7919 		slot->arch.rmap[i] = NULL;
7920 		if (i == 0)
7921 			continue;
7922 
7923 		kvfree(slot->arch.lpage_info[i - 1]);
7924 		slot->arch.lpage_info[i - 1] = NULL;
7925 	}
7926 	return -ENOMEM;
7927 }
7928 
7929 void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
7930 {
7931 	/*
7932 	 * memslots->generation has been incremented.
7933 	 * mmio generation may have reached its maximum value.
7934 	 */
7935 	kvm_mmu_invalidate_mmio_sptes(kvm, slots);
7936 }
7937 
7938 int kvm_arch_prepare_memory_region(struct kvm *kvm,
7939 				struct kvm_memory_slot *memslot,
7940 				const struct kvm_userspace_memory_region *mem,
7941 				enum kvm_mr_change change)
7942 {
7943 	return 0;
7944 }
7945 
7946 static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
7947 				     struct kvm_memory_slot *new)
7948 {
7949 	/* Still write protect RO slot */
7950 	if (new->flags & KVM_MEM_READONLY) {
7951 		kvm_mmu_slot_remove_write_access(kvm, new);
7952 		return;
7953 	}
7954 
7955 	/*
7956 	 * Call kvm_x86_ops dirty logging hooks when they are valid.
7957 	 *
7958 	 * kvm_x86_ops->slot_disable_log_dirty is called when:
7959 	 *
7960 	 *  - KVM_MR_CREATE with dirty logging is disabled
7961 	 *  - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
7962 	 *
7963 	 * The reason is, in case of PML, we need to set D-bit for any slots
7964 	 * with dirty logging disabled in order to eliminate unnecessary GPA
7965 	 * logging in PML buffer (and potential PML buffer full VMEXT). This
7966 	 * guarantees leaving PML enabled during guest's lifetime won't have
7967 	 * any additonal overhead from PML when guest is running with dirty
7968 	 * logging disabled for memory slots.
7969 	 *
7970 	 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
7971 	 * to dirty logging mode.
7972 	 *
7973 	 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
7974 	 *
7975 	 * In case of write protect:
7976 	 *
7977 	 * Write protect all pages for dirty logging.
7978 	 *
7979 	 * All the sptes including the large sptes which point to this
7980 	 * slot are set to readonly. We can not create any new large
7981 	 * spte on this slot until the end of the logging.
7982 	 *
7983 	 * See the comments in fast_page_fault().
7984 	 */
7985 	if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
7986 		if (kvm_x86_ops->slot_enable_log_dirty)
7987 			kvm_x86_ops->slot_enable_log_dirty(kvm, new);
7988 		else
7989 			kvm_mmu_slot_remove_write_access(kvm, new);
7990 	} else {
7991 		if (kvm_x86_ops->slot_disable_log_dirty)
7992 			kvm_x86_ops->slot_disable_log_dirty(kvm, new);
7993 	}
7994 }
7995 
7996 void kvm_arch_commit_memory_region(struct kvm *kvm,
7997 				const struct kvm_userspace_memory_region *mem,
7998 				const struct kvm_memory_slot *old,
7999 				const struct kvm_memory_slot *new,
8000 				enum kvm_mr_change change)
8001 {
8002 	int nr_mmu_pages = 0;
8003 
8004 	if (!kvm->arch.n_requested_mmu_pages)
8005 		nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
8006 
8007 	if (nr_mmu_pages)
8008 		kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
8009 
8010 	/*
8011 	 * Dirty logging tracks sptes in 4k granularity, meaning that large
8012 	 * sptes have to be split.  If live migration is successful, the guest
8013 	 * in the source machine will be destroyed and large sptes will be
8014 	 * created in the destination. However, if the guest continues to run
8015 	 * in the source machine (for example if live migration fails), small
8016 	 * sptes will remain around and cause bad performance.
8017 	 *
8018 	 * Scan sptes if dirty logging has been stopped, dropping those
8019 	 * which can be collapsed into a single large-page spte.  Later
8020 	 * page faults will create the large-page sptes.
8021 	 */
8022 	if ((change != KVM_MR_DELETE) &&
8023 		(old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
8024 		!(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
8025 		kvm_mmu_zap_collapsible_sptes(kvm, new);
8026 
8027 	/*
8028 	 * Set up write protection and/or dirty logging for the new slot.
8029 	 *
8030 	 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
8031 	 * been zapped so no dirty logging staff is needed for old slot. For
8032 	 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
8033 	 * new and it's also covered when dealing with the new slot.
8034 	 *
8035 	 * FIXME: const-ify all uses of struct kvm_memory_slot.
8036 	 */
8037 	if (change != KVM_MR_DELETE)
8038 		kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
8039 }
8040 
8041 void kvm_arch_flush_shadow_all(struct kvm *kvm)
8042 {
8043 	kvm_mmu_invalidate_zap_all_pages(kvm);
8044 }
8045 
8046 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
8047 				   struct kvm_memory_slot *slot)
8048 {
8049 	kvm_mmu_invalidate_zap_all_pages(kvm);
8050 }
8051 
8052 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
8053 {
8054 	if (!list_empty_careful(&vcpu->async_pf.done))
8055 		return true;
8056 
8057 	if (kvm_apic_has_events(vcpu))
8058 		return true;
8059 
8060 	if (vcpu->arch.pv.pv_unhalted)
8061 		return true;
8062 
8063 	if (atomic_read(&vcpu->arch.nmi_queued))
8064 		return true;
8065 
8066 	if (test_bit(KVM_REQ_SMI, &vcpu->requests))
8067 		return true;
8068 
8069 	if (kvm_arch_interrupt_allowed(vcpu) &&
8070 	    kvm_cpu_has_interrupt(vcpu))
8071 		return true;
8072 
8073 	if (kvm_hv_has_stimer_pending(vcpu))
8074 		return true;
8075 
8076 	return false;
8077 }
8078 
8079 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
8080 {
8081 	if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
8082 		kvm_x86_ops->check_nested_events(vcpu, false);
8083 
8084 	return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
8085 }
8086 
8087 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
8088 {
8089 	return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
8090 }
8091 
8092 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
8093 {
8094 	return kvm_x86_ops->interrupt_allowed(vcpu);
8095 }
8096 
8097 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
8098 {
8099 	if (is_64_bit_mode(vcpu))
8100 		return kvm_rip_read(vcpu);
8101 	return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
8102 		     kvm_rip_read(vcpu));
8103 }
8104 EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
8105 
8106 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
8107 {
8108 	return kvm_get_linear_rip(vcpu) == linear_rip;
8109 }
8110 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
8111 
8112 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
8113 {
8114 	unsigned long rflags;
8115 
8116 	rflags = kvm_x86_ops->get_rflags(vcpu);
8117 	if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8118 		rflags &= ~X86_EFLAGS_TF;
8119 	return rflags;
8120 }
8121 EXPORT_SYMBOL_GPL(kvm_get_rflags);
8122 
8123 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8124 {
8125 	if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
8126 	    kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
8127 		rflags |= X86_EFLAGS_TF;
8128 	kvm_x86_ops->set_rflags(vcpu, rflags);
8129 }
8130 
8131 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8132 {
8133 	__kvm_set_rflags(vcpu, rflags);
8134 	kvm_make_request(KVM_REQ_EVENT, vcpu);
8135 }
8136 EXPORT_SYMBOL_GPL(kvm_set_rflags);
8137 
8138 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
8139 {
8140 	int r;
8141 
8142 	if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
8143 	      work->wakeup_all)
8144 		return;
8145 
8146 	r = kvm_mmu_reload(vcpu);
8147 	if (unlikely(r))
8148 		return;
8149 
8150 	if (!vcpu->arch.mmu.direct_map &&
8151 	      work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
8152 		return;
8153 
8154 	vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
8155 }
8156 
8157 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
8158 {
8159 	return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
8160 }
8161 
8162 static inline u32 kvm_async_pf_next_probe(u32 key)
8163 {
8164 	return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
8165 }
8166 
8167 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8168 {
8169 	u32 key = kvm_async_pf_hash_fn(gfn);
8170 
8171 	while (vcpu->arch.apf.gfns[key] != ~0)
8172 		key = kvm_async_pf_next_probe(key);
8173 
8174 	vcpu->arch.apf.gfns[key] = gfn;
8175 }
8176 
8177 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
8178 {
8179 	int i;
8180 	u32 key = kvm_async_pf_hash_fn(gfn);
8181 
8182 	for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
8183 		     (vcpu->arch.apf.gfns[key] != gfn &&
8184 		      vcpu->arch.apf.gfns[key] != ~0); i++)
8185 		key = kvm_async_pf_next_probe(key);
8186 
8187 	return key;
8188 }
8189 
8190 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8191 {
8192 	return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
8193 }
8194 
8195 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8196 {
8197 	u32 i, j, k;
8198 
8199 	i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
8200 	while (true) {
8201 		vcpu->arch.apf.gfns[i] = ~0;
8202 		do {
8203 			j = kvm_async_pf_next_probe(j);
8204 			if (vcpu->arch.apf.gfns[j] == ~0)
8205 				return;
8206 			k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
8207 			/*
8208 			 * k lies cyclically in ]i,j]
8209 			 * |    i.k.j |
8210 			 * |....j i.k.| or  |.k..j i...|
8211 			 */
8212 		} while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
8213 		vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
8214 		i = j;
8215 	}
8216 }
8217 
8218 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
8219 {
8220 
8221 	return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
8222 				      sizeof(val));
8223 }
8224 
8225 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
8226 				     struct kvm_async_pf *work)
8227 {
8228 	struct x86_exception fault;
8229 
8230 	trace_kvm_async_pf_not_present(work->arch.token, work->gva);
8231 	kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
8232 
8233 	if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
8234 	    (vcpu->arch.apf.send_user_only &&
8235 	     kvm_x86_ops->get_cpl(vcpu) == 0))
8236 		kvm_make_request(KVM_REQ_APF_HALT, vcpu);
8237 	else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
8238 		fault.vector = PF_VECTOR;
8239 		fault.error_code_valid = true;
8240 		fault.error_code = 0;
8241 		fault.nested_page_fault = false;
8242 		fault.address = work->arch.token;
8243 		kvm_inject_page_fault(vcpu, &fault);
8244 	}
8245 }
8246 
8247 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
8248 				 struct kvm_async_pf *work)
8249 {
8250 	struct x86_exception fault;
8251 
8252 	trace_kvm_async_pf_ready(work->arch.token, work->gva);
8253 	if (work->wakeup_all)
8254 		work->arch.token = ~0; /* broadcast wakeup */
8255 	else
8256 		kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
8257 
8258 	if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
8259 	    !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
8260 		fault.vector = PF_VECTOR;
8261 		fault.error_code_valid = true;
8262 		fault.error_code = 0;
8263 		fault.nested_page_fault = false;
8264 		fault.address = work->arch.token;
8265 		kvm_inject_page_fault(vcpu, &fault);
8266 	}
8267 	vcpu->arch.apf.halted = false;
8268 	vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
8269 }
8270 
8271 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
8272 {
8273 	if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
8274 		return true;
8275 	else
8276 		return !kvm_event_needs_reinjection(vcpu) &&
8277 			kvm_x86_ops->interrupt_allowed(vcpu);
8278 }
8279 
8280 void kvm_arch_start_assignment(struct kvm *kvm)
8281 {
8282 	atomic_inc(&kvm->arch.assigned_device_count);
8283 }
8284 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
8285 
8286 void kvm_arch_end_assignment(struct kvm *kvm)
8287 {
8288 	atomic_dec(&kvm->arch.assigned_device_count);
8289 }
8290 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
8291 
8292 bool kvm_arch_has_assigned_device(struct kvm *kvm)
8293 {
8294 	return atomic_read(&kvm->arch.assigned_device_count);
8295 }
8296 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
8297 
8298 void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
8299 {
8300 	atomic_inc(&kvm->arch.noncoherent_dma_count);
8301 }
8302 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
8303 
8304 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
8305 {
8306 	atomic_dec(&kvm->arch.noncoherent_dma_count);
8307 }
8308 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
8309 
8310 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
8311 {
8312 	return atomic_read(&kvm->arch.noncoherent_dma_count);
8313 }
8314 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
8315 
8316 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
8317 				      struct irq_bypass_producer *prod)
8318 {
8319 	struct kvm_kernel_irqfd *irqfd =
8320 		container_of(cons, struct kvm_kernel_irqfd, consumer);
8321 
8322 	if (kvm_x86_ops->update_pi_irte) {
8323 		irqfd->producer = prod;
8324 		return kvm_x86_ops->update_pi_irte(irqfd->kvm,
8325 				prod->irq, irqfd->gsi, 1);
8326 	}
8327 
8328 	return -EINVAL;
8329 }
8330 
8331 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
8332 				      struct irq_bypass_producer *prod)
8333 {
8334 	int ret;
8335 	struct kvm_kernel_irqfd *irqfd =
8336 		container_of(cons, struct kvm_kernel_irqfd, consumer);
8337 
8338 	if (!kvm_x86_ops->update_pi_irte) {
8339 		WARN_ON(irqfd->producer != NULL);
8340 		return;
8341 	}
8342 
8343 	WARN_ON(irqfd->producer != prod);
8344 	irqfd->producer = NULL;
8345 
8346 	/*
8347 	 * When producer of consumer is unregistered, we change back to
8348 	 * remapped mode, so we can re-use the current implementation
8349 	 * when the irq is masked/disabed or the consumer side (KVM
8350 	 * int this case doesn't want to receive the interrupts.
8351 	*/
8352 	ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
8353 	if (ret)
8354 		printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
8355 		       " fails: %d\n", irqfd->consumer.token, ret);
8356 }
8357 
8358 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
8359 				   uint32_t guest_irq, bool set)
8360 {
8361 	if (!kvm_x86_ops->update_pi_irte)
8362 		return -EINVAL;
8363 
8364 	return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
8365 }
8366 
8367 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
8368 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
8369 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
8370 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
8371 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
8372 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
8373 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
8374 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
8375 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
8376 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
8377 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
8378 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
8379 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
8380 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
8381 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
8382 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
8383 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
8384